CN109327410B - Improved three-level CLOS routing method based on FPGA crossing - Google Patents

Abstract

The invention relates to an improved three-level CLOS routing algorithm based on FPGA (field programmable gate array) intersection, which is based on the internal intersection capacity of the FPGA, and aims to realize the input and output routing intersection function of optical fiber signals and realize the routing nesting algorithm of a two-layer three-level CLOS network, wherein the first layer three-level CLOS network is added with a design strategy of intermediate-level combination, and the number of the input and output stages and the switching stage is increased to 4 by 1 connecting channel of the traditional framework, so that the routing space is increased, the second layer CLOS network calculates the routing in an FPGA chip, a direct switching mode is realized in the scene of local board intersection, the switching stage resources are not occupied, and the routing space is increased, so that the FPGA chip routing algorithm has the advantage of greatly reducing the blocking rate in the scene of large-capacity intersection. The invention increases the routing space of the route through the improvement on the architecture and the algorithm, greatly reduces the blocking rate, and improves the performance advantage and the user experience of the equipment.

Description

Improved three-level CLOS routing method based on FPGA crossing

Technical Field

The invention relates to an improved three-level CLOS routing method based on FPGA crossing, which is used for carrying out time slot and channel crossing on optical fiber signals SDH and 10GE, calculating a routing table of each level of the three-level CLOS according to the input and output routing requirements of equipment by improving a nested three-level CLOS network routing algorithm, and configuring a routing result into an FPGA and a crossing chip to realize the function of optical fiber signal routing crossing.

Background

CLOS networks are classical strictly non-blocking multi-stage interconnect networks that are widely used in optical communication networks, and have the characteristics of scalability, fixed switching delay, freedom and order of data transmission. A classical CLOS network is a three-stage fully interconnected symmetrical network comprising three stages, input stage/intermediate stage/output stage, the input stage having r N x m crossbars, the intermediate stage having m r x r crossbars, the output stage having r m x N crossbars, the network having a total of N = N x r inputs and outputs, each intermediate stage switch having and only one connection link with each input stage switch and output stage switch. Since the proposal of CLOS, people carry out intensive research on the topological structure, the connection characteristics and the control routing algorithm of the CLOS, and also obtain a plurality of results, wherein, a plurality of research results are carried out on the routing strategy of how to reduce the blocking rate and optimize the routing algorithm, for example, the strategy of adopting the optimal path with the minimum calculation blocking probability in selecting the middle-level unit is realized. The traditional close routing algorithm establishes an algorithm model according to a three-level CLOS network architecture, an input-output cross pair required to be realized at the outer layer is used as an input parameter of the algorithm model, the algorithm adopts an optimal routing strategy to carry out three-level routing according to the resource occupation/idle condition of an input stage/an intermediate stage/an output stage, a routing finding result of an intermediate path is given, and the input-output routing cross is completed. Under the current trend that the whole IP network flow and scale are expanded continuously, a higher requirement is provided for the high-capacity cross-exchange capacity in optical communication, in order to realize the cross-exchange capacity with the capacity at the Tbits level, aiming at the requirements of high capacity, non-blocking rate and minimum used resources, only one connecting link between the traditional input/output stage and the middle stage cannot meet the high-capacity cross-exchange capacity, and aiming at 192-path input and output high-capacity cross of a three-stage CLOS framework (m =32, r =12 and n =16), the traditional framework still has the blocking probability for the time slot cross with small granularity.

Disclosure of Invention

In view of the state of the prior art, the invention aims at the 192-path input/output high-capacity cross application requirement of a three-level CLOS framework (m =32, r =12, n =16), in order to realize the functional requirement of time slot and channel cross of different optical fiber signals in the optical communication field, the blocking probability still exists for the high-capacity fine-granularity time slot cross in the traditional three-level CLOS network framework, in order to increase the selectable path resource of the connection link from the input/output level to the middle level, one connection link from the traditional input/output level to the middle level is changed into 4 connection links, the routing resource of the middle level is increased, the blocking rate is reduced, and in order to reduce the problem of resource shortage under the high-capacity cross scene of the middle level resource, a nested layer three-level CLOS network is designed, after the routing algorithm calculates the routing path of the first layer three-level CLOS network, calculates the routing path of the nested layer three-, when the input and the output are crossed on the three-level CLOS network on the nested layer, the calculation of the three-level CLOS routing algorithm of the first layer is not needed, the intermediate-level resource of the three-level CLOS network of the first layer is not used, the blocking probability under the crossing of large-capacity fine granularity is reduced, and meanwhile, the nested layer is directly crossed and switched, so that the signal cross transmission delay is reduced.

The technical scheme adopted by the invention is as follows: an improved three-stage CLOS routing method based on FPGA crossing is characterized in that a routing algorithm operation platform is a high-capacity TBits-stage crossing device and comprises 15 boards, wherein 12 boards are service boards, 2 boards are switching boards, 1 main control board runs a control scheduling program in the main control board and a three-stage CLOS routing algorithm of the structure, SOC chips zynq7030 and FPGA chips are arranged on the service boards, crossing chips are arranged on the switching boards, the FPGA on each service board has 48 x 48 input and output crossing capacity, the crossing capacity is divided into an input stage 16 x 32 crossing matrix and an output stage 32 x 16 crossing matrix in a three-stage CLOS network structure of a first layer, an intermediate stage is realized by two switching boards, each switching board has 4 crossing capacities of 48 x 48, the crossing capacity of each 48 x 48 is realized by a combination of 4 crossing chips, and each crossing chip has 12 x 12 crossing capacity, the 12 service boards are divided into a part of cross capability 16X 32 as an input stage and a part ofcross capability 32X 16 as an output stage, the middle stage is provided with 8 cross switches of 48X 48, the output stage is provided with 12 cross switches of32X 16, each unit of the input stage and the middle stage is provided with four connecting links, each unit of the output stage and the middle stage is also provided with four connecting links, so that 32 outputs in each unit of the input stage are respectively the product of 4 connecting links and 8 middle stage units, and 32 inputs of each unit of the output stage are also calculated;

when a three-level CLOS architecture with intermediate-level combination calculates a three-level routing path of an input/output 192 × 192 cross matrix, according to the input or output unit number designated by a user, namely which unit of 12 input or output levels, each unit selects which channel of 16 fiber channels, if the realized time slot cross is not the channel cross but needs to be realized, the user also needs to designate which time slots of 64 time slots in the channel need to be subjected to cross switching, and the selectable time slot granularity comprises VC-12/VC-4/VC-16c/VC-64 c;

the three-level CLOS routing algorithm calculates an input/output/middle-level routing table according to a network architecture through an input/output cross pair appointed by a user;

the new cross logic implementation flow of the first layer three-level CLOS routing algorithm is that when a user gives a cross list to be newly built, the algorithm firstly judges whether the currently-built cross and the existing cross have the repetition of an output port or a time slot, if so, the original cross pair is deleted, then, a new current cross list is established, whether the numbers of the input and output units are the same or not is judged firstly, if the numbers are different, firstly judging whether output stage copy exists or not, if the input signal to be newly established has a route and is output to the corresponding output unit, the route is multiplexed, and only one output-level route table is newly established at the output unit, so that all route information is updated; if the output level copy does not exist, judging whether the intermediate level copy exists, namely whether the input signal needing to be newly built has a route to be output to the selected intermediate level unit exists, if so, adding routing information of the intermediate level and the output level, if not, judging whether the intermediate level multiplex exists, namely whether a route which has already established the intermediate level exists but the channel of the route is not full, and the residual space can contain the size of the current established cross time slot, if so, updating the intermediate level and input level routing table, otherwise, calculating an idle route to be provided for the current cross use;

the deleting cross logic implementation flow of the first-layer three-level CLOS routing algorithm is that when a user provides a cross list needing to be deleted, the algorithm firstly judges whether the numbers of input and output units which are currently deleted and crossed are the same, if so, the input and output cross list is directly updated in the second-layer three-level CLOS routing algorithm to carry out middle routing calculation, if not, an output-level routing table is deleted firstly, then whether a middle-level route is used for multiple times is judged, if so, the middle-level route is not deleted, whether an input-level route is used for multiple times is judged, if so, the input-level route is not deleted, and the deleting operation of the cross is completed;

after the routing algorithm calculates the three-level routing table of the three-level CLOS network of the first layer, because the routes with the same input and output level unit numbers are actually crossed on the same service board, the routes with the same input and output levels are merged, when the routing table on the service board has 10GE cross routes, 10GE channel cross routes are extracted to be used as the input of the routing algorithm of the three-level CLOS network of the second layer, so as to calculate the three-level routing table of the three-level CLOS network on each service board, the architecture of the three-level CLOS network of the second layer, 12 cross switches with 4 x 8 in the input stage, 8 cross switches with 12 x 12 in the middle stage, 12 cross switches with 8 x 4 in the output stage, and only one connecting link is arranged in the output stage and the middle stage, the three-level CLOS network is the traditional three-level CLOS network, the routing table of the 10GE cross channels of the three-level CLOS network of the second layer is strictly without blocking, the algorithm needs to calculate the routing table of the 10GE cross channels of the three-level CLOS network of, configuring a cross configuration register provided by the FPGA according to the routing table to perform cross configuration;

the logic of the routing algorithm of the channel intersection of the second-layer three-level CLOS network is that the input and output routes on the same service board are used as the input of the algorithm, firstly, whether output level copy exists is judged, namely, the same established input intersection already has a routing path to reach an output level unit, the path is directly multiplexed at the moment, the new construction is finished only by establishing a routing table at the output level, if no output level copy exists, whether middle level copy exists is judged, namely, the same established input intersection already has a path to reach the middle level, the path is directly multiplexed at the moment, the new construction is finished only by establishing the routing table at the middle level and the output level, if no middle level copy exists, an idle routing path is calculated for the intersection, and meanwhile, the three-level routing table is updated, and the new construction is finished;

in the routing algorithm framework, the calculation of a first-layer three-level CLOS network routing path is realized by using python language, and the complex logic of the algorithm and the storage and query of data are realized by utilizing the matrix operation and data processing capability of numpy/pandas language of python;

the calculated routing data provides an acquisition interface for C + + calling, the calculation of the second-layer three-level CLOS network routing path is realized by C + + and is packaged into a C + + algorithm function module class for calling the service control flow codes.

The invention has the beneficial effects that: at present, a high-capacity cross exchange is designed by combining a three-level CLOS framework in the optical communication field with the channel and time slot cross capability of an FPGA, a plurality of connecting links are arranged between an input stage/output stage and an intermediate stage of the first-level three-level CLOS network design, the channel of the FPGA is crossed by using the first-level nested three-level CLOS framework, a scheme that intermediate-level resources are not used under the condition that the board is crossed is realized, and the design scheme is rarely adopted in the optical communication field at present. The invention improves the traditional three-level CLOS crossing network in the algorithm structure based on the time slot and channel crossing capability of FPGA, adopts the strategy of combining the intermediate level in the routing algorithm and using no intermediate level resource for the board crossing, and realizes the large-capacity crossing network by nesting two layers of CLOS crossing networks, thereby realizing the large-capacity routing crossing capability of optical fiber signals in the field of optical communication.

The invention firstly optimizes and improves the traditional three-level CLOS network architecture, realizes the cross capability of high-capacity TBits level by adopting a two-layer three-level CLOS network, can simultaneously process the time slot cross of 10GE channel cross SDH in the cross exchange of the processing of the accessed optical fiber signals, meets the high-capacity cross requirement of the current optical fiber signals, provides effective technical support of front-end wires for the analysis and the processing of the optical fiber signals, and effectively solves the requirement of customers on high-capacity cross.

The high-capacity TBits-level crossing equipment is already deployed and operated at a plurality of optical fiber connection places, the requirement of customers on high-capacity crossing is effectively met, certain sales profits are created for companies by the equipment, the equipment becomes representative products of the companies gradually, and market-level innovation awards are obtained on the equipment architecture design and the function realization.

Meanwhile, the device algorithm design framework is based on the cross capability realized by the FPGA, the flexibility of expansion and improvement of the three-level CLOS network is increased, a multilayer nested three-level CLOS network is constructed, the blocking probability of high-capacity cross is solved by adopting intermediate-level combination, the design is also the first innovation, the same input and output unit can be crossed without using intermediate-level routing resources, the problem of shortage of intermediate-level routing resources of the traditional three-level CLOS network is solved, the input stage, the output stage and the intermediate stage are improved to have 4 connecting channels by the traditional design that only one connecting link is arranged, and the routing space of the input and output stage and the intermediate stage is effectively increased.

The same output unit carries out crossing, and because the intermediate level routing resource is not used, the algorithm flow is shortened, the response speed of the newly-built crossing is obviously improved, and the problem of poor user experience of the newly-built crossing of the similar crossing equipment in the prior art is solved.

In conclusion, the invention improves the traditional three-level CLOS crossing network in the algorithm structure based on the time slot and channel crossing capability of FPGA, adopts the strategy of combining the intermediate level in the routing algorithm without using the intermediate level resource, and realizes the large-capacity crossing network by nesting two layers of CLOS crossing networks, thereby realizing the large-capacity routing crossing capability of optical fiber signals in the field of optical communication.

Drawings

FIG. 1 is a diagram of a hardware device according to the present invention;

FIG. 2 is a first level three level CLOS network cross matrix diagram of the present invention;

FIG. 3 is a new cross flow chart of the first layer three-level CLOS network routing algorithm of the present invention;

FIG. 4 is a cross-flow diagram for the first level three level CLOS network routing algorithm deletion of the present invention;

FIG. 5 is a second level three level CLOS network cross matrix diagram in accordance with the present invention;

fig. 6 is a flow chart of the new routing of the second layer three-level CLOS network routing algorithm of the present invention.

Detailed Description

The operation platform of the invention is a high-capacity TBits-level crossing device, the device needs to be fully inserted with 12 service board cards, 2 exchange boards and 1 main control board, after the device is powered on, a control program on each board card is started, the operation state lamp on each board card is displayed, the device controls the interconnection between a network manager and the device through a network cable or an exchanger, so that the two are in the same local area network and can carry out network communication, firstly, a B/S network manager establishes a device model, fills in relevant information of the device such as an ip address port number device id and the like, enters a control interface of the TBits-level device, checks the on-site condition of the board cards, clicks a service view, can carry out operations such as newly-built crossing/deleting crossing and the like in the service view, clicks the newly-built crossing, pops a crossing information input frame, selects an input/output board card number/input/, if the established intersection is an SDH intersection, selecting a high-low order time slot for input and output, clicking new construction after the selection is finished, popping up a new construction success and failure prompt box, if the new construction is successful, realizing the current route successfully constructed in the list, and if the new construction is failed, not displaying the current route; when new issuing, the equipment operation program receives a control instruction, a newly-established cross table is transmitted into an algorithm module, the algorithm module calculates and outputs a first-layer three-level CLOS network routing table and a second-layer three-level CLOS network routing table, a main control board obtains the routing table and issues information to a service board for register configuration, routing channel or time slot information of an FPGA is configured, cross chip routing information on a switching board is configured, after configuration is completed, a response is gradually returned to a B/S network management to display new success and failure and refresh the current routing table, an error code instrument is used for receiving an input optical fiber and an output optical fiber according to the input-output corresponding relation of the routing table, an input signal format is configured for emitting light, and whether a signal is received and no error code exists in the error code instrument is detected; if the user deletes the intersection, selecting a route to be deleted in the route list frame, clicking a delete intersection button, popping up a delete intersection success or failure result, when a delete intersection instruction is issued, transferring delete intersection contents to an algorithm by a main control, carrying out delete operation on the algorithm, updating the two-layer three-level CLOS network route list, issuing configuration information to a service board and a cross board, and carrying out register configuration on the FPGA and the cross chip; and testing and deleting the signal display obstruction of the input and output cross pair by using an error code meter.

The specific implementation method comprises the following steps:

as shown in fig. 1, the system includes 14 boards, wherein 12 boards are service boards, 2 boards are switch boards, and 1 main control board.

The main control board runs a control scheduling program and a three-level CLOS routing algorithm of the framework, the service board is provided with an SOC chip zynq7030 and an FPGA chip, and the exchange board is provided with a cross chip.

The FPGA on each service board has 48 × 48 input-output cross capability, the cross capability is divided into aninput stage 16 × 32 cross matrix and an output stage 32 × 16 cross matrix in a three-stage CLOS network architecture of a first layer, an intermediate stage is realized by two switching boards, each switching board has 4 cross capabilities of 48 × 48, and each cross capability of 48 × 48 is realized by a combination of 4 cross chips, because each cross chip has 12 cross capabilities. The 12 service boards are divided into a part ofcross capability 16 × 32 as an input stage, a part of cross capability 32 × 16 as an output stage, the middle stage is composed of 8 units of 48 × 48, and a network architecture block diagram of a three-stage CLOS architecture (m =32, r =12, n =16) is shown in fig. 2, wherein each unit of the input stage and the switching stage has four connecting links, each unit of the output stage and the switching stage has four connecting links, so that 32 outputs of each unit of the input stage are products of 4 connecting links and 8 units of the switching stage, and 32 inputs of each unit of the output stage are calculated similarly.

When the three-level CLOS architecture with intermediate-level combination calculates the three-level routing path of the input/output 192 × 192 cross matrix, the input/output unit number specified by a user is more, namely which unit of 12 input/output levels, which channel of 16 fiber channels is selected in each unit, if the channel cross is not realized and the time slot cross needs to be realized, the user also needs to specify which write time slot of 64 time slots in the channel needs to be cross-switched, and the selectable time slot granularity comprises VC-12/VC-4/VC-16c/VC-64 c. The three-level CLOS routing algorithm calculates the routing table of input/output/intermediate level according to the network architecture by the input/output cross-pairs designated by the user.

The new cross logic implementation flow of the first layer three-level CLOS routing algorithm is shown in FIG. 3, when a user gives a cross list to be newly created, the algorithm first judges whether the currently created cross has the repetition of an output port or a time slot with the existing cross, if so, the original cross pair is deleted, then, a new current cross list is established, whether the numbers of the input and output units are the same or not is judged firstly, if the same, the crossing is considered to be carried out on the same service board, the crossing is directly realized by the FPGA, the route of the second-layer CLOS network is directly calculated, the intermediate-level resource of the first-layer CLOS network is not used, if the serial numbers are different, firstly judging whether output stage duplication exists (namely, the newly-built input signal is required to have a route output to a corresponding output unit), multiplexing the route, and only building a route table of the output stage at the output unit to update all route information; if the output stage copy does not exist, judging whether the intermediate stage copy exists (namely the newly-built input signal is required to have a route to be output to the selected intermediate stage unit), if so, adding routing information of the intermediate stage and the output stage, if not, judging whether intermediate stage multiplexing exists (namely an intermediate stage route is established but the channel is not full, and the residual space can accommodate the size of the current established cross time slot), updating the intermediate stage and input stage routing table, otherwise, calculating an idle route to be provided for the current cross use.

The cross deletion logic implementation flow of the first-layer three-level CLOS routing algorithm is shown in FIG. 4, when a user provides a cross list to be deleted, the algorithm firstly judges whether the numbers of input and output units which are currently subjected to cross deletion are the same, if so, the input and output cross list is directly updated in the second-layer three-level CLOS routing algorithm to perform intermediate routing calculation, if not, an output-level routing table is firstly deleted, then whether the intermediate-level routing is used for multiple times is judged, if so, the intermediate-level routing is not deleted, whether the input-level routing is used for multiple times is judged, and if so, the input-level routing is not deleted. The delete operation of the intersection is completed.

After the routing algorithm calculates the three-level routing table of the three-level CLOS network of the first layer, because the routes with the same input and output level unit numbers are actually crossed on the same service board, the routes with the same input and output levels are merged, when the routing table on the service board has 10GE cross routes, 10GE channel cross routes are extracted to be used as the input of the routing algorithm of the three-level CLOS network of the second layer, so as to calculate the three-level routing table of the three-level CLOS network on each service board, the architecture of the three-level CLOS network of the second layer is shown in figure 5, the input level has 12 cross switches of 4 x 8, the middle level has 8 cross switches of 12 x 12, the output level has 12 cross switches of 8 x 4, and the input level output level and the middle level both have only one connecting link. The three-level CLOS network is a traditional three-level CLOS network and is strictly non-blocking, the algorithm needs to calculate a routing table of 10GE channels of the second-level three-level CLOS network, and cross configuration is carried out according to a cross configuration register provided by a routing table configuration FPGA.

The logic of the routing algorithm for channel crossing of the second-layer three-level CLOS network is shown in fig. 6, the input and output routes on the same service board are used as the input of the algorithm, firstly, whether output level duplication exists is judged, namely, the same established input crossing has a route path reaching an output level unit, the path is directly multiplexed at the moment, the new establishment is finished only by establishing a routing table at the output level, if no output level duplication exists, whether middle level duplication exists is judged, namely, the same established input crossing has a path reaching the middle level, the path is directly multiplexed at the moment, the new establishment is finished only by establishing the routing table at the middle level and the output level, if no middle level duplication exists, an idle routing path is calculated for the cross use of the path, and meanwhile, the three-level routing table is updated, and the new establishment is finished.

The routing algorithm framework is characterized in that the calculation of the routing path of the CLOS network with the first layer and the third layer is realized by using python language, and the complex logic of the algorithm and the storage and the query of data are realized by utilizing the matrix operation and the data processing capability of numpy/pandas and other languages of python. The calculated routing data provides an acquisition interface for C + + calling, the calculation of the second-layer three-level CLOS network routing path is realized by C + + and is packaged into a C + + algorithm function module class for calling the service control flow codes.

Claims (1)

1. An improved three-level CLOS routing method based on FPGA intersection is characterized in that a running platform of the routing method is a high-capacity TBits-level intersection device and comprises 15 boards, wherein 12 boards are service boards, 2 boards are exchange boards, 1 main control board runs a control scheduling program in the main control board and the three-level CLOS routing method of the routing method, SOC chips zynq7030 and FPGA chips are arranged on the service boards, intersection chips are arranged on the exchange boards, the FPGA on each service board has 48 × 48 input and output intersection capacity, the intersection capacity is divided into an input stage 16 × 32 intersection matrix and an output stage 32 × 16 intersection matrix in a three-level CLOS network architecture of a first layer, an intermediate stage is realized by two exchange boards, each exchange board has 4 intersection capacities of 48 × 48, each 48 × 48 intersection capacity is realized by a combination of 4 intersection chips, and each intersection chip has 12 × 12 intersection capacity, the 12 business boards are divided into a part of cross capability 16X 32 as an input stage, a part of cross capability 32X 16 as an output stage, and the middle stage is composed of 8 units of 48X 48, so that the input stage of the first three-stage CLOS network architecture is provided with 12 cross switches of 16X 32, the middle stage is provided with 8 cross switches of 48X 48, and the output stage is provided with 12 cross switches of 32X 16, wherein each unit of the input stage and the middle stage is provided with four connecting links, each unit of the output stage and the middle stage is also provided with four connecting links, so that 32 outputs in each unit of the input stage are respectively the product of 4 connecting links and 8 middle stage units, and 32 inputs of each unit of the output stage are also calculated;

when a three-level CLOS architecture with intermediate-level combination calculates a three-level routing path of an input/output 192 × 192 cross matrix, according to the input or output unit number designated by a user, namely which unit of 12 input or output levels, each unit selects which channel of 16 fiber channels, if the realized time slot cross is not the channel cross but needs to be realized, the user also needs to designate which time slots of 64 time slots in the channel need to be subjected to cross switching, and the selectable time slot granularity comprises VC-12/VC-4/VC-16c/VC-64 c;

the three-level CLOS routing method calculates the routing table of input/output/middle level according to the network architecture by the input/output cross pair appointed by the user;

the new cross logic implementation process of the first layer three-level CLOS routing method is that when a user gives a cross list to be newly built, the method firstly judges whether the currently newly built cross has the repetition of an output port or a time slot with the existing cross, if so, deletes the original cross pair, then, a new current cross list is established, whether the numbers of the input and output units are the same or not is judged firstly, if the numbers are different, firstly judging whether output stage copy exists or not, if the input signal to be newly established has a route and is output to the corresponding output unit, the route is multiplexed, and only one output-level route table is newly established at the output unit, so that all route information is updated; if the output level copy does not exist, judging whether the intermediate level copy exists, namely whether the input signal needing to be newly built has a route to be output to the selected intermediate level unit exists, if so, adding routing information of the intermediate level and the output level, if not, judging whether the intermediate level multiplex exists, namely whether a route which has already established the intermediate level exists but the channel of the route is not full, and the residual space can contain the size of the current established cross time slot, if so, updating the intermediate level and input level routing table, otherwise, calculating an idle route to be provided for the current cross use;

the method comprises the steps of firstly judging whether the numbers of input and output units which are deleted at present are the same, if so, directly updating the input and output cross lists in the second-layer three-level CLOS routing method to carry out intermediate routing calculation, if not, deleting an output-level routing list, then judging whether an intermediate-level route is used for multiple times, if so, not deleting the intermediate-level route, judging whether an input-level route is used for multiple times, if not, not deleting the input-level route, and finishing the deleting operation of the cross;

after the routing method calculates the three-level routing table of the three-level CLOS network of the first layer, because the routes with the same input and output level unit numbers are actually crossed on the same service board, the routes with the same input and output levels are merged, when the routing table on the service board has 10GE cross routes, 10GE channel cross routes are extracted to be used as the input of the routing method of the three-level CLOS network of the second layer, so as to calculate the three-level routing table of the three-level CLOS network on each service board, the architecture of the three-level CLOS network of the second layer, 12 cross switches with 4 x 8 in the input stage, 8 cross switches with 12 x 12 in the middle stage, 12 cross switches with 8 x 4 in the output stage, and only one connecting link is arranged in the output stage and the middle stage, the three-level CLOS network is the traditional three-level CLOS network, and the method has no blocking strictly, and the routing table of the 10GE cross channels of the three-level CLOS network of the second layer is calculated, configuring a cross configuration register provided by the FPGA according to the routing table to perform cross configuration;

the logic of the routing method of the channel intersection of the second-layer three-level CLOS network is to take the input and output routes on the same service board as the input of the method, firstly, judge whether output level copy exists or not, namely, the same established input intersection already has a routing path to reach an output level unit, at the moment, the path is directly multiplexed, the new establishment is finished only by establishing a routing table at the output level, if output level copy does not exist, whether intermediate level copy exists or not is judged, namely, the same established input intersection already has a path to reach the intermediate level, at the moment, the path is directly multiplexed, the new establishment is finished only by establishing the routing table at the intermediate level and the output level, if intermediate level copy does not exist, an idle routing path is calculated for the intersection, and meanwhile, the three-level routing table is updated, and the new establishment is finished;

in the routing method framework, the calculation of a first-layer three-level CLOS network routing path is realized by using python language, and the complex logic of the method and the storage and query of data are realized by utilizing the matrix operation and data processing capacity of numpy/pandas language of python;

the calculated routing data provides an acquisition interface for C + + calling, the calculation of the second-layer three-level CLOS network routing path is realized by C + + and is packaged into a C + + algorithm function module class for calling the service control flow codes.

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