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CN109308996A - One-time negative pressure diffusion process for silicon wafer - Google Patents

One-time negative pressure diffusion process for silicon wafer
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Publication number
CN109308996A
CN109308996ACN201710615675.0ACN201710615675ACN109308996ACN 109308996 ACN109308996 ACN 109308996ACN 201710615675 ACN201710615675 ACN 201710615675ACN 109308996 ACN109308996 ACN 109308996A
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diffusion
silicon wafer
source
negative pressure
silicon
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CN201710615675.0A
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CN109308996B (en
Inventor
李亚哲
王彦君
孙晨光
徐长坡
陈澄
武卫
梁效峰
黄志焕
杨玉聪
李丽娟
朱建佶
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Tcl Huanxin Semiconductor Tianjin Co ltd
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Tianjin Huanxin Technology & Development Co ltd
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Abstract

The invention provides a silicon wafer one-time negative pressure diffusion process, which comprises the following steps: after thinning the two sides, placing the silicon wafer into a diffusion pretreatment, printing a diffusion source on the treated silicon wafer, printing a phosphorus diffusion source on one side of the treated silicon wafer by adopting a screen printing process, and printing a boron diffusion source or a boron-aluminum diffusion source on the other side of the treated silicon wafer; stacking the surfaces of the silicon wafers with the same diffusion source oppositely for loading into a boat; low-pressure diffusion is carried out in a diffusion furnace and diffusion post-treatment is carried out. The invention has the advantages that the phosphorus diffusion source, the boron diffusion source or the boron-aluminum diffusion source are respectively printed on the two sides of the silicon wafer by adopting the screen printing process, so that the coating flow of the liquid source of the silicon wafer is simplified, and the processing period is shortened; a one-time negative pressure diffusion process is adopted after the liquid source is coated, so that the source return condition of the edge of the silicon wafer is reduced, the diffusion process steps are simplified, and the diffusion efficiency is improved; the process method is adopted to carry out the primary diffusion of the liquid source of the silicon chip, so that the manufactured PN junction is uniform, and the processing cost of the silicon chip is reduced.

Description

A kind of negative pressure diffusion technique of silicon wafer
Technical field
The invention belongs to the manufacturing process areas of silicon wafer, more particularly, to a kind of negative pressure diffusion technique of silicon wafer.
Background technique
With the development of semiconductor technology, the requirement to semiconductor surface passivation is higher and higher, as passivating material, should haveStandby good electric property, reliability, good chemical stability, operability and economy.According to above-mentioned requirements, partly leadBody is passivated special glass and starts to apply in semicon industry as a kind of ideal semiconductor passivation material.Using partly leadingThe chip of body passivation special glass production is known as glassivation chip (Glass passivation process Chip), i.e.,GPP chip.
Currently, the production of silicon wafer can use diffusion technique formation PN junction, diffusion work commonly used in the trade at present mostly in industrySkill is generally used phosphorus paper source, a boron paper source perfect diffusion or is spread twice using phosphorus, boron, and there is can not for these diffusion waysThe defect avoided: 1) due to paper source after sintering silicon wafer between gap increase, cause volatilization phosphorus source to diffuse to boron face and cause to return source;2)The mode technique production spread twice is cumbersome, and after one side phosphorus diffusion, another side needs sandblasting or chemical reduction to remove anti-sourceAmount, then boron diffusion is carried out, at high cost, diffuser efficiency is low, and be easy to cause fragment.
Summary of the invention
In view of the above problems, the problem to be solved in the present invention is to provide a kind of negative pressure diffusion techniques of silicon wafer, using silkWire mark brush phosphorous diffusion source, boron diffusion source or boron aluminum extension dissipate source, and use a negative pressure diffusion technique, make uniform PN junction, mitigateSource situation is returned, diffuser efficiency is improved.
In order to solve the above technical problems, the technical solution adopted by the present invention is that: a kind of negative pressure diffusion technique of silicon wafer, packetInclude following steps:
1) low pressure is spread: the silicon wafer behind coating diffusion source is carried out low pressure diffusion in diffusion furnace.
Further, the low pressure in step 1) spreads specific steps are as follows:
A. the silicon wafer behind coating diffusion source is placed in diffusion furnace, and air pressure in diffusion furnace is evacuated to negative pressure.
Further, further comprising the steps of after step a:
B. diffusion furnace temperature is risen into 1250 DEG C of -1300 DEG C of progress constant temperature diffusions, constant temperature time 10-30h;
C. after spreading, diffusion furnace temperature is down to 550 DEG C -650 DEG C and is come out of the stove.
It further, further include printing diffusion source before step 1) negative pressure diffusing step.
Further, printing diffusion source uses screen printing technique, specifically includes the following steps:
A. in the silicon wafer one side printing phosphorous diffusion source by being handled before spreading: phosphorous diffusion source being sprayed on halftone, silicon waferIt is placed in below the halftone, is printed phosphorous diffusion source to silicon chip surface with scraper;
B. the silicon wafer for printing phosphorous diffusion source is placed in baking oven, phosphorous diffusion source is dried;
C. boron diffusion source or boron aluminum extension are dissipated source by the technique of step B, step C to print to silicon wafer another side, and is driedIt is roasting;
D. upper Al is sprayed on silicon wafer two sides2O3Powder or silicon powder.
Further, the drying time in step B is determined according to the number to be printed in diffusion source.
It further, further include lamination dress boat behind printing diffusion source.
Further, the step of lamination dress boat are as follows: by silicon wafer boron source face or boron silicon source face and boron source face or boron silicon source face phaseIt is right, phosphorus source face progress lamination opposite with phosphorus source face is filled into boat.
Further, further include diffusion post-processing after diffusion, specially the silicon wafer after diffusion is placed in acid and is diffusedPost-processing.
Further, the acid in diffusion post-processing is hydrofluoric acid.
The advantages and positive effects of the present invention are: due to the adoption of the above technical scheme, being existed using silk-screen printing techniqueSilicon wafer two sides prints phosphorous diffusion source, boron diffusion source or boron aluminum extension respectively and dissipates source, so that the coating process of silicon wafer liquid source obtains letterChange, and the process-cycle is reduced;A negative pressure diffusion technique is used after liquid source coating, mitigates silicon chip edge and returns source situation,And the diffusion process steps simplify, and improve diffuser efficiency;Silicon wafer liquid source One Diffusion Process is carried out using the process, so thatThe PN junction of production is uniform, so that the processing cost of silicon wafer reduces.
Detailed description of the invention
Fig. 1 is flow chart of the invention.
Specific embodiment
The present invention is described further in the following with reference to the drawings and specific embodiments.
As shown in Figure 1, including the following steps: the present invention relates to a kind of negative pressure diffusion technique of silicon wafer
1) silicon wafer is two-sided is thinned: two-sided corrosion is carried out to silicon wafer using corrosive liquid, removes surface damage layer, specifically include asLower step:
A. thermometer measure corrosive liquid temperature is used, which is generally 0-15 DEG C, and sets silicon wafer according to corrosive liquid temperatureEtching time, the etching time are generally 9-50s, determine etching time according to corrosive liquid temperature, silicon wafer is placed in corrosive liquidMiddle carry out corrosion thinning, the thickness of silicon wafer thinning single surface is determined according to corrosive liquid temperature, which is generally 10-20 μm;
B. after corroding, silicon wafer is cleaned, is to be put into silicon wafer in pure water rinse bath to clean here, cleanedFall the corrosive liquid during corrosion thinning, the time of cleaning is 10-20min;
C. measure silicon wafer subduction amount: whether the subduction amount that Wafer Cleaning completely measures silicon wafer afterwards complies with standard, inner to useMeasuring instrument is spiral micrometer, can also be the instrument of other measurement thickness, that is, the measurement two-sided thinned thickness of silicon wafer, it shouldThickness is generally 10-20 μm;
D. spilling water cleaning is carried out to silicon wafer after measuring and is dried, the purpose of spilling water cleaning is silicon after removal is thinned
The impurity on piece surface.
Wherein, above-mentioned corrosive liquid is the nitric acid being mixed in a certain ratio, hydrofluoric acid, glacial acetic acid and pure water, the corrosive liquidIt can be good at carrying out corrosion thinning to silicon wafer, mixed proportion here is that example is mixed by volume, according to volume ratioIt is mixed for the ratio of 10-20:5-10:1-10:1-10.
2) it spreads pre-treatment: alkali process successively being carried out to the silicon wafer after being thinned, spilling water cleaning, acid cleaning, spilling water cleaning, is got rid ofIt is dry, it is therefore an objective to which that the surface mechanical damage for removing silicon wafer removes the impurity such as metal ion and the organic solvent of silicon chip surface, that is,
A. the silicon wafer after being thinned is placed in lye and handles, which is potassium hydroxide solution, and the hydroxideThe temperature of potassium solution is 40-80 DEG C, and the alkali process time is in 5-20min, and alkali process here is level-one alkali process, it is,Carry out an alkali process;
B. silicon wafer is put into progress spilling water cleaning in pure water after the completion of alkali process, removes the lye of silicon chip surface, hereCleaning includes three steps, is first cleaned using spilling water, and spilling water cleaning here is cleaned using two-stage spilling water, that is, carries out spilling water twiceCleaning, using ultrasonic spilling water cleaning after the cleaning of two-stage spilling water, ultrasonic spilling water cleaning is using primary ultrasonic spilling water cleaning, ultrasonic spilling waterIt is cleaned after cleaning using spilling water, is cleaned here using two-stage spilling water, the time of every step cleaning is in 5-20min, here hereThe cleaning of two-stage spilling water refer to that silicon wafer carries out water twice and cleans, sufficiently remove other solution impurities of silicon chip surface, level-one is superThe cleaning of sound spilling water refers to carrying out primary ultrasonic spilling water cleaning;
C. the silicon wafer cleaned up is placed in acid solution and carries out sour processing, acid solution used is nitric acid solution, temperature oneAs be 60-100 DEG C, acid processing the time be 5-20min in, here acid processing be three-level acid handle, it is, carry out three hypo acidsThe time of processing, every hypo acid processing is all identical;
D. after the completion of acid processing, silicon wafer is put into pure water and carries out spilling water cleaning and dries, removes the acid solution of silicon chip surface,Here spilling water scavenging period is in 5-20min, and spilling water cleaning here is that level Four spilling water cleans, and is overflow it is, carrying out four timesThe time of water cleaning, each spilling water cleaning is identical;
E. the silicon wafer cleaned up is dried, so that there is no the impurity such as water for silicon chip surface.
3) print diffusion source: using silk-screen printing technique, to treated, silicon wafer one side prints phosphorous diffusion source, another side printBrush boron diffusion source or boron aluminum extension dissipate source, specifically includes the following steps:
A. in silicon wafer one side printing phosphorous diffusion source: phosphorous diffusion source being sprayed on halftone, which is woven by engineering plasticsIt forms, silicon wafer is placed in below halftone, applies pressure at a certain angle above halftone with scraper, phosphorous diffusion source is printed to siliconPiece surface, the angle of scraper here are 45 ° -75 °, printing pressure 30N-120N, and version spacing is 1-3mm, and print speed printing speed is50-300mm/S, scraper height are 1-3mm, and scraper hardness is 40-80HRC;
B. the silicon wafer for printing phosphorous diffusion source is placed in baking oven, phosphorous diffusion source is dried, the drying time according toThe number to be printed of phosphorous diffusion source determines that time for generally toasting is 5-25min, and temperature is 90-180 DEG C;
C. boron diffusion source or boron aluminum extension are dissipated source by the processing step of step B, step C to print to silicon wafer another side, is gone forward side by sideRow baking, temperature are 90-180 DEG C, baking time 5-15min;
D. after the completion of toasting, upper Al is sprayed on silicon wafer two sides2O3Powder or silicon powder.
4) lamination fills boat: by silicon wafer, opposite lamination fills boat two-by-two, i.e., by silicon wafer boron source face or boron silicon source face and boron source face orBoron silicon source face is opposite, carries out lamination for phosphorus source face is opposite with phosphorus source face, is put into silicon carbide boat after lamination, and before and after being carbonized boatBaffle is placed in position, and silicon wafer is compressed, and can make full use of the space in diffusion furnace after carrying out low pressure diffusion in this way, and workIt is high-efficient, multiple batches of silicon wafer can be once diffused;
5) low pressure is spread: will be carried out low pressure diffusion in diffusion furnace mounted in the silicon wafer of carbonization boat, is made uniform PN junction;ItsIn, the step mesolow diffusion the specific steps are;
A. the carbonization boat equipped with silicon wafer is placed in diffusion furnace, is placed in the flat-temperature zone of the diffusion furnace, used after closing fire doorAir pressure in diffusion furnace is evacuated to negative pressure, generally 10-101Kpa by vacuum pump;
B. diffusion furnace temperature is risen into 1250 DEG C of -1300 DEG C of progress constant temperature diffusions by 550 DEG C -650 DEG C, constant temperature time is10-30h;
C. after spreading, diffusion furnace temperature is down to 550 DEG C -650 DEG C, and the carbonization boat of containing silicon slice is pulled out diffusion furnace.
6) diffusion post-processing: the silicon wafer after diffusion being placed in acid and is diffused post-processing, and silicon wafer is washed by water and made after separatingWith nitration mixture clean the surface, silicon chip surface phosphorus, Pyrex after diffusion are removed.The acid for being used as diffusion post-processing in the step is hydrogenFluorspar acid solution is the nitric acid, hydrofluoric acid and glacial acetic acid being mixed in a certain ratio to the nitration mixture that silicon chip surface carries out cleaning, hereOne be set to according to volume ratio be 6-15:10-20:30-40 ratio mixed.
Negative pressure diffusion technique of silicon wafer is that the techniques such as subsequent silicon wafer glass is blunt are prepared.
Using the PN junction result of an above-mentioned negative pressure diffusion technique are as follows: 40-60 μm of boron knot, 90-120 μm of aluminium knot, phosphorus knot40-60μm.Make the resistance to electric discharge result of sample are as follows: 800-1500V.
Experiment proves that result it is found that using a negative pressure diffusion technique make silicon wafer, PN junction is uniform, and consistency is good,Negative-pressure operation is carried out in the warming-up section of phosphorus source volatilization, the phosphorus source volatilized is discharged, which as early as possible, reduces the effect that phosphorus source returns source, silicon waferIt is small that edge returns source amount.
The advantages and positive effects of the present invention are: due to the adoption of the above technical scheme, being existed using silk-screen printing techniqueSilicon wafer two sides prints phosphorous diffusion source, boron diffusion source or boron aluminum extension respectively and dissipates source, so that the coating process of silicon wafer liquid source obtains letterChange, and the process-cycle is reduced;A negative pressure diffusion technique is used after liquid source coating, mitigates silicon chip edge and returns source situation,And the diffusion process steps simplify, and improve diffuser efficiency;Silicon wafer liquid source One Diffusion Process is carried out using the process, so thatThe PN junction of production is uniform, so that the processing cost of silicon wafer reduces.
One embodiment of the present invention has been described in detail above, but the content is only preferable implementation of the inventionExample, should not be considered as limiting the scope of the invention.It is all according to all the changes and improvements made by the present patent application rangeDeng should still be within the scope of the patent of the present invention.

Claims (10)

CN201710615675.0A2017-07-262017-07-26One-time negative pressure diffusion process for silicon waferActiveCN109308996B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN111710597A (en)*2020-06-302020-09-25山东宝乘电子有限公司Method for manufacturing silicon rectifying chip substrate by utilizing boron-phosphorus one-step diffusion

Citations (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN101944554A (en)*2010-09-162011-01-12浙江大学Boron-aluminum common gettering method for silicon slice
CN104091857A (en)*2014-06-302014-10-08欧贝黎新能源科技股份有限公司Low-pressure variable-temperature diffusion method of nanometer textured polycrystalline silicon solar cell
CN105261670A (en)*2015-08-312016-01-20湖南红太阳光电科技有限公司Low-pressure diffusion technology for crystalline silicon cell
CN205347629U (en)*2015-12-072016-06-29广东爱康太阳能科技有限公司Low pressure high temperature diffusion stove

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN101944554A (en)*2010-09-162011-01-12浙江大学Boron-aluminum common gettering method for silicon slice
CN104091857A (en)*2014-06-302014-10-08欧贝黎新能源科技股份有限公司Low-pressure variable-temperature diffusion method of nanometer textured polycrystalline silicon solar cell
CN105261670A (en)*2015-08-312016-01-20湖南红太阳光电科技有限公司Low-pressure diffusion technology for crystalline silicon cell
CN205347629U (en)*2015-12-072016-06-29广东爱康太阳能科技有限公司Low pressure high temperature diffusion stove

Cited By (1)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN111710597A (en)*2020-06-302020-09-25山东宝乘电子有限公司Method for manufacturing silicon rectifying chip substrate by utilizing boron-phosphorus one-step diffusion

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Address after:300380 2nd floor, block a, No.12 Haitai East Road, Huayuan Industrial Zone, Xiqing District, Tianjin

Patentee after:TCL Huanxin Semiconductor (Tianjin) Co.,Ltd.

Address before:300380 2nd floor, block a, No.12 Haitai East Road, Huayuan Industrial Zone, Xiqing District, Tianjin

Patentee before:TIANJIN HUANXIN TECHNOLOGY & DEVELOPMENT Co.,Ltd.


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