CN109213710B - High-speed serial interface device and data transmission method thereof - Google Patents

Abstract

A high-speed serial interface device and a data transmission method thereof. The information processing circuit generates first configuration information in response to a data transmission task for accessing a storage unit of another high-speed serial interface device. The encoding circuit performs encoding processing on the first configuration information to generate a first encoding configuration command. An encoding circuit. The high-speed serial interface circuit is coupled with the encoding circuit and embeds the first encoding configuration command into the control bits of the plurality of first data samples based on a high-speed serial interface protocol. The high-speed serial interface circuit transmits a plurality of first frames formed by the plurality of first data samples to another high-speed serial interface device so as to carry out the data transmission task by transmitting a first encoding configuration command to the another high-speed serial interface device.

Description

High-speed serial interface device and data transmission method thereof

[ technical field ] A method for producing a semiconductor device

The present invention relates to data transmission between chips, and more particularly, to a high-speed serial interface device and a data transmission method thereof.

[ background of the invention ]

As the demand for data volume increases, a new challenge is presented to the transmission speed of the chip internal interface. Conventional parallel interfaces have gradually shown deficiencies. Compared with the traditional parallel interface, the emerging JESD204B interface has significant advantages in terms of power consumption and pin count. In addition, the JESD204B interface can provide more efficient transmission and is therefore suitable as a transmission interface for an analog-to-digital converter or a digital-to-analog converter. Based on the advantages, the JESD204B interface is gradually becoming a new mainstream interface standard.

Generally, the JESD204B interface is used for high-speed mass data transfer, but is not used for transferring control information between chips or for allowing both chips to exchange status information of internal registers. Therefore, a chip configured with the JESD204B interface is usually configured with another low-speed transmission interface to transmit some control information or status information of the internal registers of the chip between chips. The low-speed transmission Interface is, for example, an Inter-Integrated Circuit (I2C) Interface or a Serial Peripheral Interface (SPI) Interface. However, the number of pins of the chip will increase due to the need to additionally configure various transmission interfaces in the chip. The number of leads of the chip directly affects the area and manufacturing cost of the chip, and therefore how to effectively reduce the number of leads of the crystal plane is one of the issues of concern to those skilled in the art.

[ summary of the invention ]

In view of the above, the present invention provides a high-speed serial interface device and a data transmission method thereof, which can reduce chip pins and reduce the overall chip area.

An embodiment of the invention provides a high-speed serial interface device, which comprises an information processing circuit, an encoding circuit and a high-speed serial interface circuit. The information processing circuit generates first configuration information in response to a data transmission task for accessing a storage unit of another high-speed serial interface device. The encoding circuit is coupled to the information processing circuit and performs encoding processing on the first configuration information to generate a first encoding configuration command. The high-speed serial interface circuit is coupled with the coding circuit, embeds a first coding configuration command into control bits of a plurality of first data samples based on a high-speed serial interface protocol, and transmits a plurality of first frames formed by the plurality of first data samples to another high-speed serial interface device so as to carry out the data transmission task by transmitting the first coding configuration command to the other high-speed serial interface device.

In an embodiment of the invention, the first encoding configuration command includes a preamble, a start bit, an operation command, a target address, and specific data.

In an embodiment of the invention, when the operation command is a read command, the specific data of the first code allocation command is a read sequence number. When the operation command is a write-back data command, the specific data of the first encoding configuration command is write-back read data. When the operation command is a write command, the specific data of the first encoding configuration command is write data.

In an embodiment of the invention, the preamble includes a plurality of preamble bits, and each of the preamble bits is a first bit value. The start bit is a second bit value, and the first bit value is different from the second bit value.

In an embodiment of the invention, the operation command includes a plurality of command bits, and the target address includes a plurality of address bits. The specific data includes a plurality of specific data bits, and the number of preamble bits is greater than the sum of the number of start bits, the number of operation bits, the number of address bits, and the number of specific data bits.

In an embodiment of the invention, the high-speed serial interface circuit receives a plurality of second data samples constituting a plurality of second frames from another high-speed serial interface device, and the high-speed serial interface device further includes a decoding circuit. The decoding circuit is coupled between the information processing unit and the high-speed serial interface circuit, acquires the control bit of each second data sample through the high-speed serial interface circuit to acquire a second encoding configuration command, and decodes the second encoding configuration command to extract second configuration information. The information processing circuit executes an operation according to the second configuration information to perform a data transmission task initiated by the high-speed serial interface device or perform another data transmission task initiated by another high-speed serial interface device.

In an embodiment of the invention, the operation includes obtaining write-back read data from the second configuration information, storing the write-back read data in the storage unit of the high-speed serial interface device, or obtaining the write-back read data from the storage unit of the high-speed serial interface device according to the target address in the second configuration information.

In an embodiment of the invention, if the data transmission task is to transmit write data to another high-speed serial interface device, the operation command of the first code allocation command is a write command. If the data transmission task is reading data from another high-speed serial interface device, the operation command of the first encoding configuration command is a read command, the operation command of the second encoding configuration command is a write-back data command, and the operation is acquiring write-back read data from the second configuration information.

In an embodiment of the invention, the high-speed serial interface circuit includes an interface transmitter and an interface receiver. The interface transmitter is coupled to the encoding circuit, and the interface receiver is coupled to the decoding circuit.

In an embodiment of the invention, the high-speed serial interface protocol includes JESD204b protocol.

From another perspective, the present invention provides a data transmission method based on a high-speed serial interface, which includes the following steps. The first configuration information is generated in response to a data transfer task for accessing a storage unit of another high speed serial interface device. The first configuration information is encoded to generate a first encoded configuration command. The first encoded configuration command is embedded into control bits of a plurality of first data samples based on a high speed serial interface protocol. The method includes transmitting a plurality of first frames of first data samples to another high-speed serial interface device according to a high-speed serial interface protocol to perform the data transmission task by transmitting a first encoded configuration command to the another high-speed serial interface device.

In view of the above, in an embodiment of the present invention, when the high-speed serial interface device attempts to access the storage unit of another high-speed serial interface device, the high-speed serial interface device encodes the configuration information and embeds the encoded configuration information into the control bits of the plurality of data samples specified by the high-speed serial interface protocol, so that the another high-speed serial interface device can decode the configuration information in response to receiving the plurality of frames formed by the plurality of data samples. Thus, another high-speed serial interface can store the write data according to the configuration information. Or, the other high-speed serial interface can read the write-back read data in the storage unit according to the configuration information and transmit the write-back read data back to the high-speed serial interface device generating the configuration information. In this way, the configuration of another transmission interface for transmitting the configuration information can be omitted. By omitting the configuration of the transmission interface into the chip, the pin count of the chip can be reduced, and thus the chip area can be reduced.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

[ description of the drawings ]

FIG. 1 is a block diagram of a high-speed serial interface device according to an embodiment of the present invention.

Fig. 2 is a diagram illustrating a frame according to an embodiment of the invention.

Fig. 3 is a schematic diagram illustrating an encoding configuration command according to an embodiment of the invention.

Fig. 4A is a schematic diagram of data transmission according to an embodiment of the invention.

Fig. 4B is a schematic diagram of data transmission according to an embodiment of the invention.

Fig. 5A is a flowchart illustrating a data transmission method according to an embodiment of the invention.

Fig. 5B is a flowchart illustrating a data transmission method according to an embodiment of the invention.

[ notation ] to show

100. 200: high-speed serial interface device

110. 210: information processing circuit

130. 250: encoding circuit

140. 240: high-speed serial interface circuit

150. 230: decoding circuit

120. 220, and (2) a step of: storage unit

141. 242: interface transmitter

241. 142: interface receiver

M1: first configuration information

M2: second configuration information

F1_1 to F1_ N: first frame

F2_1 to F2_ N: second frame

S1-S8: data samples

CS: control bit

F1: frame

31: preamble symbol

32: start bit

33: operating commands

34: target address

35: specific data

cmd1, X1: a first encoded configuration command

X2: second encoding configuration command

41: read command

42. 44, 48: target address

43: write back data command

45: write back read data

47: write command

49: writing data

S501 to S508: step (ii) of

[ detailed description ] embodiments

Reference will now be made in detail to the present exemplary embodiments, examples of which are illustrated in the accompanying drawings. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

In the following embodiments, the JESD204B interface will be described as the high-speed serial interface of the present invention. However, the present invention is not so limited and the same concepts presented in the present invention can be applied by those skilled in the art in any other high speed serial interface.

FIG. 1 is a block diagram of a high-speed serial interface device according to an embodiment of the present invention. Referring to FIG. 1, a high speedserial interface device 100 and another high speedserial interface device 200 are shown. The high-speedserial interface device 200 may be, for example, a system chip with an analog-to-digital converter, but the invention is not limited thereto. The high-speedserial interface device 100 includes aninformation processing circuit 110, astorage unit 120, anencoding circuit 130, adecoding circuit 150, and a high-speedserial interface circuit 140. Similarly, the high-speedserial interface device 200 includes aninformation processing circuit 210, astorage unit 220, anencoding circuit 250, adecoding circuit 230, and a high-speedserial interface circuit 240.

When the high-speedserial interface device 100 performs a data transmission task and needs to access thestorage unit 220 of the high-speedserial interface device 200, theinformation processing circuit 110 of the high-speedserial interface device 100 may generate the first configuration information M1 in response to the data transmission task. Thestorage unit 220 of the high-speedserial interface device 200 is, for example, a register or a memory.

Theencoding circuit 130 is coupled to theinformation processing circuit 110, receives the first configuration information M1, and encodes the first configuration information M1 to generate a first encoded configuration command X1. Then, theencoding circuit 130 may transmit the first encoded configuration command X1 to the high-speedserial interface circuit 140 supporting the high-speed serial interface protocol, so that the high-speedserial interface circuit 140 embeds the first encoded configuration command X1 into the control bits of the plurality of first data samples based on the high-speed serial interface protocol. The high-speedserial interface circuit 140 is coupled to theencoding circuit 130 and supports a high-speed serial interface protocol, and includes aninterface transmitter 141 and aninterface receiver 142. Theinterface transmitter 141 is coupled to theencoding circuit 130, and theinterface receiver 142 is coupled to thedecoding circuit 150. Similarly, the high-speedserial interface circuit 240 of the high-speedserial interface device 200 also includes aninterface transmitter 242 and aninterface receiver 241. As shown in FIG. 1, theinterface transmitter 141 of the high-speedserial interface circuit 140 is connected to theinterface receiver 241 of the high-speedserial interface circuit 240, and theinterface receiver 142 of the high-speedserial interface circuit 140 is connected to theinterface transmitter 242 of the high-speedserial interface circuit 240.

In detail, based on the specification of the high speed serial interface protocol, the data to be transmitted is framed into a plurality of frames, each of the frames is composed of a plurality of data samples, and each of the data samples has at least one control bit for flexible use. In the embodiment, the high-speedserial interface circuit 140 coupled to theencoding circuit 130 may generate a plurality of first frames F1_ 1-F1 _ N based on the high-speed serial interface protocol. As previously described, each frame includes a plurality of first data samples, and each first data sample includes at least one control bit. Theinterface transmitter 141 of the high-speedserial interface circuit 140 may embed the first encoded configuration command X1 in control bits within the plurality of first frames F1_ 1-F1 _ N.

In one embodiment, the high speedserial interface circuit 140 transmits a plurality of first frames F1_ 1-F1 _ N comprising the plurality of first data samples to another high speedserial interface device 200. Furthermore, the first encoding configuration command X1 can be transmitted to another high-speedserial interface device 200 to perform the data transmission task by embedding the first encoding configuration command X1 in the control bits of the first data sample. In detail, theinterface transmitter 141 may include a serializer (serializer) to serially output the plurality of first frames F1_1 to F1_ N to theinterface receiver 241 via at least one transmission lane. Since the first encoding configuration command X1 is embedded in the control bits of the first frames F1_ 1-F1 _ N, the first encoding configuration command X1 can be received by theinterface receiver 241 of the high-speedserial interface device 200 based on the transmission of the first frames F1_ 1-F1 _ N.

Theinterface receiver 241 receives the first frames F1_ 1-F1 _ N, and unframes the first frames F1_ 1-F1 _ N based on the high speed serial interface protocol to extract the first code allocation command X1 from the control bits of the first frames F1_ 1-F1 _ N. Then, theinterface receiver 241 outputs the first encoded configuration command X1 to thedecoding circuit 230, and thedecoding circuit 230 decodes the first encoded configuration command X1 to restore the first configuration information M1 and outputs the first configuration information M1 to theinformation processing circuit 210.

In this way, theinformation processing circuit 210 can write the data from the high speedserial interface device 100 into thestorage unit 220 according to the content of the first configuration information M1. Alternatively, theinformation processing circuit 210 may perform other subsequent corresponding operations according to the data from the high-speedserial interface device 100 according to the content of the first configuration information M1. Alternatively, theinformation processing circuit 210 may obtain the write-back read data from thestorage unit 220 according to the content of the first configuration information M1, and transmit the write-back read data back to the high-speedserial interface device 100. Accordingly, the data transmission task of accessing thestorage unit 220 of another high speedserial interface device 200 can be completed through the high speed serial interface. It should be noted that, since the data of the data transmission task is transmitted through the control bits of the first frames F1_ 1-F1 _ N, the high speedserial interface device 100 and the other high speedserial interface device 200 can simultaneously perform high-speed mass data transmission through the first data samples of the first frames F1_ 1-F1 _ N.

Similarly, when the high-speedserial interface device 200 performs another data transmission task and needs to access the high-speedserial interface device 100, theinformation processing circuit 210 of the high-speedserial interface device 200 may generate the second configuration information M2 in response to the data transmission task. The embodiments are as described above and will not be described again.

It is noted that, when the data transmission task initiated by the high-speedserial interface device 100 is to read data in thestorage unit 220 of the high-speedserial interface device 200, in order to return write-back read data to the high-speedserial interface device 100, theinformation processing circuit 210 may read corresponding data in thestorage unit 220 according to the analyzed result after analyzing the first configuration information M1. Then, theinformation processing circuit 210 generates the second configuration information M2 to transmit the data to be read in the first configuration information M1 to the high speedserial interface device 100.

Theencoding circuit 250 may perform operations and principles similar to those of theencoding circuit 130 to generate a second encoded configuration command X2 based on the second configuration information M2. After theinterface transmitter 242 frames the data to be transmitted into the second frames F2_ 1-F2 _ N, the second encoding configuration command X2 is embedded in the control bits of the second frames F2_ 1-F2 _ N, and the second frames F2_ 1-F2 _ N embedded with the second encoding configuration command X2 are transmitted to the high-speedserial interface device 100. Further, the high-speedserial interface circuit 140 may receive a plurality of second data samples constituting a plurality of second frames F2_ 1-F2 _ N from another high-speedserial interface device 200. Then, thedecoding circuit 150 may obtain the second encoded configuration command X2 by obtaining the control bit of each second data sample through the high-speedserial interface circuit 140, and extract the second configuration information M2 by decoding the second encoded configuration command X2. Theinformation processing circuit 110 may correspondingly perform operations according to the second configuration information M2.

In summary, when the high-speedserial interface device 100 is to read data from thestorage unit 220 of the high-speedserial interface device 200, the first configuration information M1 of the data to be read can be transmitted to the high-speedserial interface device 200 in the above-mentioned manner. After receiving the first configuration information M1, the high-speedserial interface device 200 first reads the corresponding read data from thestorage unit 220, and transmits the second configuration information M2 with the read data back to the high-speedserial interface device 100 to complete the task of reading the data. When the high speedserial interface device 100 is about to write the write data into thestorage unit 220 of the high speedserial interface device 200, the first configuration information M1 with the write data can be transmitted to the high speedserial interface device 200 in the above manner. After the high-speedserial interface device 200 receives and restores the first configuration information M1, it can be written into the program.

Taking the JESD204b as an example of the high-speed serial interface protocol, the high-speedserial interface circuits 140 and 240 include circuits required for specifically executing the JESD204b protocol, such as a transport layer circuit, a Physical layer circuit, and a Link layer circuit of the JESD204b protocol.

Examples of embedding the first encoding configuration command into the first/second frame are further described below. Taking the JESD204b protocol as an example of the high speed serial interface protocol, data to be transmitted is mapped into a plurality of 8-bit bytes (octets) corresponding to a transport channel, and the plurality of 8-bit bytes form a frame (i.e., the first frame F1_ 1-F1 _ N and the second frame F2_ 1-F2 _ N shown in fig. 1). In addition, one frame may include at least one data sample (i.e., a first data sample and a second data sample constituting the first frame F1_ 1-F1 _ N and the second frame F2_ 1-F2 _ N), and each data sample may carry 1 to 3 control bits. It should be noted that the total number of bits of a single data sample, the number of control bits in a single data sample, and the number of data samples in a single frame can be adjusted according to actual requirements, which is not limited in the present invention.

Fig. 2 is a diagram illustrating a frame according to an embodiment of the invention. Referring to the example of FIG. 2, frame F1 may be comprised of 13 8-bit bytes. In addition, the frame F1 may include multipledata samples S1S 8, and eachdata sample S1S 8 may carry 1 control bit and 12 sample bits. That is, the total number of bits per data sample S1-S8 is 13 bits, and the frame F1 may carry 8 control bits CS. The 8 control bits CS can be used to transmit the encoded configuration command of the present invention (i.e. the first encoded configuration command X1 and the second encoded configuration command X2 generated by encoding the first configuration information M1 and the second configuration information M2). It can be appreciated that in the example of fig. 2, when the number of bits of the coded configuration command is greater than 8, the coded configuration command needs to be transmitted over multiple frames.

In the example of FIG. 2, the control bits CS of the data samples S1-S8 are centrally located at the end of the frame F1, but the invention is not limited thereto. In other embodiments, the control bits of the data samples S1-S8 may be arranged centrally at the beginning of the frame F1 or scattered at the end of each data sample S1-S8. However, the transport layer standard of the JESD204B protocol gives very flexible frame formats, and fig. 2 is only an exemplary illustration and is not intended to limit the invention.

An example of encoding the first configuration information to generate the first configuration instruction is further described below. Fig. 3 is a schematic diagram illustrating a first encoding configuration command according to an embodiment of the invention. Referring to FIG. 3, a first coded allocate command cmd1 is an example of the first coded allocate command X1 shown in FIG. 1, and the first coded allocate command cmd1 includes apreamble 31, astart bit 32, anoperation command 33, atarget address 34, andspecific data 35. In one embodiment, when theoperation command 33 is a read command, thespecific data 35 of the first encoded configuration command cmd1 is a read sequence number. When theoperation command 33 is a write-back data command, thespecific data 35 of the first encoded configuration command cmd1 is write-back read data. When theoperation command 33 is a write command, thespecific data 35 of the first encoded configuration command cmd1 is write data.

In the example of FIG. 3, thepreamble 31 includes 28 preamble bits, and the preamble bits are all the first bit value '1'. The start bit is a second bit value '0' different from the first bit value '1'. Theoperation command 33 includes 2 command bits, and thetarget address 34 includes 8 address bits. Thespecific data 35 includes 16 specific data bits. Based on the above configuration, when the high speedserial interface device 100 transmits a plurality of first frames F1_ 1-F1 _ N with the first encoded configuration command cmd1 to the high speedserial interface device 200, thepreamble 31, thestart bit 32, theoperation command 33, thetarget address 34, and thespecific data 35 in the first encoded configuration command cmd1 can be received by the high speedserial interface device 200 in sequence.

Specifically, in one embodiment, in order for the receiver receiving the first coded configuration command cmd1 to recognize the start of the first coded configuration command cmd1 for proper decoding, thepreamble 31 may be formed by a plurality of preamble bytes that are all first bit values, and thestart bit 32 may be formed by at least one start byte that is all second bit values. Also, the number of leading bits will be greater than the sum of the number of start bits, the number of operation bits, the number of address bits, and the number of specific data bits. As shown in the example of fig. 3, the sum of the number of start bits, the number of operation bits, the number of address bits, and the number of specific data bits is equal to 27 bits (1+2+8+16 is 27), so the number of preamble bits is configured to be at least equal to 28 bits. However, fig. 3 is only an exemplary illustration and is not intended to limit the present invention, and the number of the leading bits and the start bits may not be limited in the present invention. The number of command bits, destination address bits, and specific data bits may also be configured as desired.

It should be noted that, in one embodiment, the encoded configuration command with the operation command, the target address and the specific data may be transmitted in N frames. Taking the frame format of FIG. 2 and the first command encoding scheme of FIG. 3 as examples, since the first command encoding scheme cmd1 has a data size of 55 bits and each frame can only transmit a data size of 8 bits, the first command encoding scheme cmd1 needs to be transmitted through at least 7 frames as shown in FIG. 2.

Fig. 4A is a schematic diagram of data transmission according to an embodiment of the invention. Referring to FIG. 4A, if the data transfer task initiated by the high speedserial interface device 100 is to read data from another high speedserial interface device 200, the operation command of the first code allocation command X1 is a read command. Thedecoding circuit 230 decodes the first encoded configuration command X1 and outputs the first configuration information M1 to theinformation processing circuit 210, wherein the first configuration information M1 includes the readcommand 41 and the target address 'A' 42. Therefore, thedata processing circuit 210 can obtain the data 'A' at the target address 'A' in thestorage unit 220 according to the readcommand 41 and the target address 'A' 42. Thereafter, theinformation processing circuit 210 may output the second configuration information M2 including the write-back data command 43, the target address 'a' 44, and the write-back read data 'a' 45. Theencoding circuit 250 encodes the second configuration information M2 to generate a second encoded configuration command X2, and embeds the second encoded configuration command X2 into control bits within a plurality of second frames, such that the second encoded configuration command X2 can be transmitted back to the high speedserial interface device 100 via the plurality of second frames. As such, theinformation processing circuit 120 of the high-speedserial interface device 100 can obtain the write-back read data 'A' 45 from the second configuration information M2 by receiving the second encoded configuration command X2.

Fig. 4B is a schematic diagram of data transmission according to an embodiment of the invention. Referring to FIG. 4B, if the data transfer task initiated by the high speedserial interface device 100 is to transfer write data to another high speedserial interface device 200, the operation command of the first code allocation command X1 is a write command. Further, thedecoding circuit 230 decodes the first encoding configuration command X1 and outputs the first configuration information M1 to theinformation processing circuit 210, wherein the first configuration information M1 includes thewrite command 47, the target address 'B' 48, and the write data 'B' 49. Therefore, theinformation processing circuit 210 can write the write data 'B' 49 into the storage space indicated by the target address 'B' in thestorage unit 220 according to thewrite command 47 and the target address 'B' 48.

Based on the above, the operations performed by theinformation processing circuit 210 in response to receiving the first configuration information M1 in response to different types of data transmission tasks include: the write-back read data is obtained from the first configuration information M1, the write data in the first configuration information M1 is stored in thestorage unit 220 of the high speedserial interface device 200, or the write-back read data is obtained from theown storage unit 220 according to the target address in the first configuration information M1. Based on the same principle, the operations that theinformation processing circuit 110 may perform in response to receiving the second configuration information M2 include: the write-back read data is obtained from the second configuration information M2, the write data in the second configuration information M2 is stored in thestorage unit 120 of the high speedserial interface device 100, or the write-back read data is obtained from theown storage unit 120 according to the target address in the second configuration information M2.

It should be noted that, no matter the data reading task of fig. 4A or the data writing task of fig. 4B, the data is transmitted in a unidirectional manner during the transmission process, and a Handshake (Handshake) procedure requiring a return response is not used. Thereby increasing the bandwidth utilization between the two high speedserial interface devices 100, 200.

Fig. 5A and 5B are flow charts of a data transmission method according to an embodiment of the invention. The details of the data transmission method and the features of the related apparatus of the present embodiment can be obtained from the above description of the embodiments of fig. 1 to 4B, and are not repeated herein.

Referring to fig. 5A, in step S501, first configuration information is generated in response to initiating a data transmission task. In step S502, the first configuration information is encoded to generate a first encoded configuration command. In step S503, a first encoding configuration command is embedded into control bits of a plurality of first data samples based on a high speed serial interface protocol. In step S504, a plurality of first frames comprising the first data samples are transmitted to another high-speed serial interface device according to the high-speed serial interface protocol, so as to perform a data transmission task by transmitting the first code allocation command to the another high-speed serial interface device.

Referring to fig. 5B, in step S505, a plurality of second data samples forming a plurality of second frames are received from another high-speed serial interface device. In step S506, a second code allocation command is obtained by obtaining the control bit of each second data sample through the high-speed serial interface circuit. In step S507, the second encoding configuration command is decoded to extract the second configuration information. In step S508, an operation is performed to perform a data transmission task or another data transmission task initiated by another high-speed serial interface device according to the second configuration information.

In summary, in the embodiments of the invention, the high-speed serial interface originally used for only high-speed data transmission can also be used for performing the data transmission task originally responsible for the other transmission interface, and the configuration of the other transmission interface can be omitted accordingly. By omitting the configuration of the transmission interface into the chip, the number of pins of the chip can be reduced, and thus the manufacturing cost and the chip area can be reduced. In addition, by flexibly configuring the number and the position of the control bits, the invention can adjust the transmission rate for performing the data transmission task, and can simultaneously perform high-rate mass data transmission through the data samples in the frame, thereby improving the efficiency of interface transmission.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (19)

1. A high-speed serial interface apparatus, comprising:

the information processing circuit is used for responding to a data transmission task to generate first configuration information, wherein the data transmission task is used for accessing a storage unit of another high-speed serial interface device;

the coding circuit is coupled with the information processing circuit and used for coding the first configuration information to generate a first coding configuration command; and

a high-speed serial interface circuit, coupled to the encoding circuit, for embedding the first encoding configuration command into control bits of a plurality of first data samples based on a high-speed serial interface protocol, and transmitting a plurality of first frames composed of the plurality of first data samples to the other high-speed serial interface device to perform the data transmission task by transmitting the first encoding configuration command to the other high-speed serial interface device, wherein the high-speed serial interface circuit generates the plurality of first frames based on the high-speed serial interface protocol, each of the first frames includes the plurality of first data samples, and each of the first data samples has at least one control bit for flexible use.

2. The high speed serial interface device of claim 1, wherein the first encoded configuration command includes a preamble, a start bit, an operation command, a target address, and specific data.

3. The high speed serial interface device of claim 2, wherein when the operation command is a read command, the specific data of the first encoded configuration command is a read sequence number; when the operation command is a write-back data command, the specific data of the first encoding configuration command is write-back read data; and when the operation command is a write command, the specific data of the first encoding configuration command is write data.

4. The apparatus of claim 2, wherein the preamble comprises a plurality of preamble bits, each of the plurality of preamble bits is a first bit value, the start bit is a second bit value, and the first bit value is different from the second bit value.

5. The high speed serial interface device of claim 4, wherein the operation command includes a plurality of command bits, the target address includes a plurality of address bits, the specific data includes a plurality of specific data bits, and the number of the plurality of preamble bits is greater than the sum of the number of the start bits, the number of the operation bits, the number of the address bits, and the number of the specific data bits.

6. The high-speed serial interface device of claim 1 wherein said high-speed serial interface circuit receives a plurality of second data samples constituting a plurality of second frames from said another high-speed serial interface device, and said high-speed serial interface device further comprises:

a decoding circuit coupled between the information processing unit and the high-speed serial interface circuit for obtaining a second encoding configuration command by obtaining the control bits of each of the plurality of second data samples through the high-speed serial interface circuit and decoding the second encoding configuration command to extract second configuration information,

the information processing circuit executes operation according to the second configuration information to perform the data transmission task initiated by the high-speed serial interface device or perform another data transmission task initiated by the other high-speed serial interface device.

7. The device of claim 6, wherein the operation comprises retrieving first write-back read data from the second configuration information, storing write data into the storage unit of the device, or retrieving a second write-back read data from the storage unit of the device according to the target address in the second configuration information.

8. The high-speed serial interface device according to claim 6, wherein if the data transfer task is to transfer write data to the other high-speed serial interface device, the operation command of the first encoded configuration command is a write command,

if the data transmission task is reading data from the other high-speed serial interface device, the operation command of the first encoding configuration command is a read command, the operation command of the second encoding configuration command is a write-back data command, and the operation is acquiring write-back read data from the second configuration information.

9. The high-speed serial interface device of claim 6, wherein said high-speed serial interface circuit comprises an interface transmitter and an interface receiver, said interface transmitter is coupled to said encoding circuit, and said interface receiver is coupled to said decoding circuit.

10. The high-speed serial interface device according to claim 1, wherein said high-speed serial interface protocol comprises JESD204b protocol.

11. A data transmission method based on a high-speed serial interface is characterized by comprising the following steps:

generating first configuration information in response to a data transfer task for accessing a storage unit of another high-speed serial interface device;

coding the first configuration information to generate a first coding configuration command;

embedding the first encoded configuration command into control bits of a plurality of first data samples based on a high speed serial interface protocol; and

transmitting a plurality of first frames composed of the plurality of first data samples to the other high-speed serial interface device according to the high-speed serial interface protocol so as to carry out the data transmission task by transmitting the first encoding configuration command to the other high-speed serial interface device, wherein the high-speed serial interface circuit generates the plurality of first frames based on the high-speed serial interface protocol, each first frame comprises the plurality of first data samples, and each first data sample has at least one control bit for flexible use.

12. The high-speed serial interface based data transmission method of claim 11, wherein the first encoding configuration command includes a preamble, a start bit, an operation command, a target address, and specific data.

13. The data transmission method according to claim 12, wherein when the operation command is a read command, the specific data is a read sequence number; when the operation command is a write-back data command, the specific data is write-back read data; and when the operation command is a write command, the specific data is write data.

14. The method of claim 12, wherein the preamble comprises a plurality of preamble bits, each of the plurality of preamble bits is a first bit value, the start bit is a second bit value, and the first bit value is different from the second bit value.

15. The method of claim 14, wherein the operation command comprises a plurality of command bits, the target address comprises a plurality of address bits, the specific data comprises a plurality of specific data bits, and the number of the plurality of preamble bits is greater than the sum of the number of start bits, the number of operation bits, the number of address bits, and the number of specific data bits.

16. The method of claim 12, further comprising:

receiving a plurality of second data samples constituting a plurality of second frames from the other high-speed serial interface device;

obtaining a second encoding configuration command by obtaining a control bit of each of the plurality of second data samples through the high-speed serial interface circuit; and

decoding the second coding configuration command to extract second configuration information; and

and executing operation according to the second configuration information to perform the data transmission task initiated by the high-speed serial interface device or perform another data transmission task initiated by the other high-speed serial interface device.

17. The method as claimed in claim 16, wherein the operation includes obtaining first write-back read data from the second configuration information, storing write data in a storage unit of the high speed serial interface device, or obtaining second write-back read data from the storage unit of the high speed serial interface device according to a target address in the second configuration information.

18. The method as claimed in claim 16, wherein if the data transmission task is to transmit write data to the other high-speed serial interface device, the operation command of the first encoded configuration command is a write command,

if the data transmission task is reading data from the other high-speed serial interface device, the operation command of the first encoding configuration command is a read command, the operation command of the second encoding configuration command is a write-back data command, and the operation is acquiring write-back read data from the second configuration information.

19. The data transmission method based on the high-speed serial interface as claimed in claim 11, wherein the high-speed serial interface protocol includes JESD204b protocol.

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