[summary of the invention]
In view of this, the present invention provides a kind of HSSI High-Speed Serial Interface device and its data transmission method, chip can be reducedPin simultaneously reduces chip entire area.
One embodiment of the invention provides a kind of HSSI High-Speed Serial Interface device comprising information-processing circuit, coding circuit,And high-speed serial interface circuit.Information-processing circuit generates the first configuration information in response to a data transfer task, above-mentionedStorage element of the data transfer task to access another HSSI High-Speed Serial Interface device.Coding circuit couples information processing electricityRoad carries out coded treatment to the first configuration information and generates the first coding configuration order.High-speed serial interface circuit coupling codingCircuit, based on HSSI High-Speed Serial Interface agreement by first coding configuration order be embedded in multiple first data samples control bit itIn, and multiple first frames composed by multiple first data sample are transmitted to another HSSI High-Speed Serial Interface device, it is passed with passing throughThe first coding configuration order is sent to carry out above-mentioned data transfer task to another HSSI High-Speed Serial Interface device.
In one embodiment of the invention, it is above-mentioned first coding configuration order include leading character, start bit, operational order,Destination address and specific data.
In one embodiment of the invention, when aforesaid operations order is reading order, the spy of the first coding configuration orderFixed number evidence is reading serial number.When aforesaid operations order is write back data order, the specific data of the first coding configuration order isWrite back read data.When aforesaid operations order is writing commands, the specific data of the first coding configuration order is write-in data.
In one embodiment of the invention, above-mentioned leading character includes multiple leading character positions, and each leading character position is firstValue.Above-mentioned start bit is the second place value, and the first place value is different from the second place value.
In one embodiment of the invention, aforesaid operations order includes multiple command bits, and above-mentioned destination address includesMore address bits.Above-mentioned specific data includes multiple specific data positions, and the quantity of above-mentioned leading character position is greater than start bitQuantity, the quantity of operative position, the summation of the quantity of address bit and the quantity of specific data position.
In one embodiment of the invention, above-mentioned high-speed serial interface circuit is from another HSSI High-Speed Serial Interface device reception groupAt multiple second data samples of multiple second frames, and HSSI High-Speed Serial Interface device further includes decoding circuit.Decoding circuit couplingBetween information process unit and high-speed serial interface circuit, each second data sample is obtained by high-speed serial interface circuitControl bit and obtain the second coding configuration order, and decoding processing is carried out to the second coding configuration order and extracts second with confidenceBreath.Information-processing circuit executes an operation according to the second configuration information, is passed with carrying out the data of HSSI High-Speed Serial Interface device initiationDefeated task carries out another data transfer task that another HSSI High-Speed Serial Interface device is initiated.
In one embodiment of the invention, aforesaid operations include writing back read data from the acquisition of the second configuration information, being writtenAmong data storage to the storage element of high speed serial interface device, or according to the destination address in the second configuration information from heightBack read data is write in the storage element acquisition of fast serial interface device.
In one embodiment of the invention, if above-mentioned data transfer task is that data will be written to be transmitted to another high speed serializationThe operational order of interface arrangement, the first coding configuration order is writing commands.If above-mentioned data transfer task is from another high speedWhen serial interface device reads data, the operational order of the first coding configuration order is reading order, the second coding configuration orderOperational order be write back data order, and aforesaid operations be from the second configuration information acquisition write back read data.
In one embodiment of the invention, above-mentioned high-speed serial interface circuit includes interface transmitter and interface receiver.Interface transmitter couples coding circuit, and interface receiver couples decoding circuit.
In one embodiment of the invention, above-mentioned HSSI High-Speed Serial Interface agreement includes JESD204b agreement.
From another point of view, the present invention proposes a kind of data transmission method based on HSSI High-Speed Serial Interface, the methodInclude the following steps.The first configuration information is generated in response to a data transfer task, data transfer task is another to accessThe storage element of HSSI High-Speed Serial Interface device.Coded treatment is carried out to the first configuration information and generates the first coding configuration order.Based on a HSSI High-Speed Serial Interface agreement, the first coding configuration order is embedded among the control bit of multiple first data samples.Multiple first frames composed by the first data sample are transmitted to another HSSI High-Speed Serial Interface device according to HSSI High-Speed Serial Interface agreement,To carry out the data transfer task by transmission the first coding configuration order to another HSSI High-Speed Serial Interface device.
Based on above-mentioned, in one embodiment of this invention, when HSSI High-Speed Serial Interface device attempts to access another high speed serializationWhen the storage element of interface arrangement, HSSI High-Speed Serial Interface device is embedded in HSSI High-Speed Serial Interface agreement after can encoding configuration informationAmong the control bit of the multiple data samples standardized, cause another HSSI High-Speed Serial Interface device in response to receiving multiple dataMultiple frames composed by sample and configuration information can be decoded out.Then, another HSSI High-Speed Serial Interface can according to configuration information andStorage write-in data.Alternatively, another HSSI High-Speed Serial Interface can read the back read data of writing in storage element according to configuration information,And by write back read data return to generate configuration information HSSI High-Speed Serial Interface device.In this way, originally above-mentioned to transmitThe configuration of another coffret of configuration information can omit.By omitting in configuration coffret to chip, the number of pins of chipAmount can be reduced, and therefore reduce chip area.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate institute's accompanying drawingsIt is described in detail below.
[Detailed description of the invention]
Fig. 1 is the schematic diagram of HSSI High-Speed Serial Interface device depicted in an embodiment according to the present invention.
Fig. 2 is the schematic diagram of a frame depicted in an embodiment according to the present invention.
Fig. 3 is the schematic diagram of coding configuration order depicted in an embodiment according to the present invention.
Fig. 4 A is the schematic diagram of the transmission of data depicted in an embodiment according to the present invention.
Fig. 4 B is the schematic diagram of the transmission of data depicted in an embodiment according to the present invention.
Fig. 5 A is the flow chart of data transmission method depicted in an embodiment according to the present invention.
Fig. 5 B is the flow chart of data transmission method depicted in an embodiment according to the present invention.
[symbol description]
100,200: HSSI High-Speed Serial Interface device
110,210: information-processing circuit
130,250: coding circuit
140,240: high-speed serial interface circuit
150,230: decoding circuit
120,220: storage element
141,242: interface transmitter
241,142: interface receiver
M1: the first configuration information
M2: the second configuration information
F1_1~F1_N: first frame
F2_1~F2_N: the second frame
S1~S8: data sample
CS: control bit
F1: frame
31: leading character
32: start bit
33: operational order
34: destination address
35: specific data
Cmd1, X1: the first coding configuration order
X2: the second coding configuration order
41: reading order
42,44,48: destination address
43: write back data order
45: writing back read data
47: writing commands
49: write-in data
S501~S508: step
[specific embodiment]
With detailed reference to this exemplary embodiment, illustrate the example of the exemplary embodiment in the accompanying drawings.In addition, allPossible place, represents same or like part using component/component of identical label in schema and embodiment.
First illustrate, below in an example by using JESD204B interface as HSSI High-Speed Serial Interface of the invention intoRow explanation.However, the present invention is not restricted to this, the same concept presented in the present invention can be answered by those skilled in the artFor in any other high speed serialization interface.
Fig. 1 is the schematic diagram of HSSI High-Speed Serial Interface device depicted in an embodiment according to the present invention.Fig. 1 is please referred to,HSSI High-Speed Serial Interface device 100 and another HSSI High-Speed Serial Interface device 200.HSSI High-Speed Serial Interface device 200, which can be for example, to be hadThe System on Chip/SoC of analog-digital converter, but the present invention is not restricted to this.HSSI High-Speed Serial Interface device 100 includes information processingCircuit 110, storage element 120, coding circuit 130, decoding circuit 150 and high-speed serial interface circuit 140.It is similar, it is highFast serial interface device 200 includes information-processing circuit 210, storage element 220, coding circuit 250, decoding circuit 230, andHigh-speed serial interface circuit 240.
Need to access HSSI High-Speed Serial Interface device 200 when HSSI High-Speed Serial Interface device 100 executes a data transfer taskStorage element 220 when, the information-processing circuit 110 of HSSI High-Speed Serial Interface device 100 may be in response to this data transfer task andGenerate the first configuration information M1.The storage element 220 of above-mentioned HSSI High-Speed Serial Interface device 200 is, for example, register or memory.
Coding circuit 130 couples information-processing circuit 110, receives above-mentioned first configuration information M1, and match confidence to firstBreath M1 carries out coded treatment and generates the first coding configuration order X1.Then, coding circuit 130 can be by this first coding configuration lifeIt enables X1 be sent to the high-speed serial interface circuit 140 for supporting HSSI High-Speed Serial Interface agreement, is based on high-speed serial interface circuit 140First coding configuration order X1 is embedded among the control bit of multiple first data samples by HSSI High-Speed Serial Interface agreement.High speed is gone here and thereLine interface circuit 140 couples coding circuit 130 and supports HSSI High-Speed Serial Interface agreement, and including interface transmitter 141 and interfaceReceiver 142.Interface transmitter 141 couples coding circuit 130, and interface receiver 142 couples decoding circuit 150.It is similar,The high-speed serial interface circuit 240 of HSSI High-Speed Serial Interface device 200 also includes interface transmitter 242 and interface receiver 241.Such asShown in Fig. 1, the interface transmitter 141 of high-speed serial interface circuit 140 connects the interface receiver of high-speed serial interface circuit 240241, and the interface receiver 142 of high-speed serial interface circuit 140 connects the interface transmitter of high-speed serial interface circuit 240242。
Specifically, the specification based on HSSI High-Speed Serial Interface agreement, data to be sent will be turned to multiple frames by frame, shouldMultiple frames are made of multiple data samples respectively, and each data sample all has at least one control for Flexible usePosition.In this present embodiment, couple coding circuit 130 high-speed serial interface circuit 140 can based on HSSI High-Speed Serial Interface agreement andGenerate multiple first frame F1_1~F1_N.As previously mentioned, each frame includes multiple first data samples, and each first data sampleThis includes at least one control bit.The interface transmitter 141 of high-speed serial interface circuit 140 can encode configuration order X1 for firstThe control bit being embedded in multiple first frame F1_1~F1_N.
In one embodiment, high-speed serial interface circuit 140 can be by composed by multiple first data sample multipleOne frame F1_1~F1_N is sent to another HSSI High-Speed Serial Interface device 200.Also, by the way that the first coding configuration order X1 is embedded inThe mode of the control bit of first data sample, the first coding configuration order X1 can be transferred into another HSSI High-Speed Serial Interface device200 and carry out above-mentioned data transfer task.Specifically, interface transmitter 141 may include serializer (serializer), withVia at least one transmission channel (transmission lane) by multiple first frame F1_1~F1_N Serial output to interfaceReceiver 241.Since the first coding configuration order X1 has been embedded among the control bit of multiple first frame F1_1~F1_N,Therefore the first coding configuration order X1 can the transmission based on first frame F1_1~F1_N and connecing by HSSI High-Speed Serial Interface device 200Mouth receiver 241 is received.
Interface receiver 241 receives first frame F1_1~F1_N, and is solved based on HSSI High-Speed Serial Interface agreement skeletonisationFirst frame F1_1~F1_N and the first coding configuration order X1 is extracted out of first frame F1_1~F1_N control bit.Then,To decoding circuit 230,230 decodable code first of decoding circuit encodes matches first coding configuration order X1 of the output of interface receiver 241It sets order X1 and restores the first configuration information M1, and the first configuration information M1 is exported to information-processing circuit 210.
In this way, information-processing circuit 210 can according to the first configuration information M1 content and will be connect from high speed serializationStorage element 220 is written in the data of mouth device 100.Alternatively, information-processing circuit 210 can be according to the content of the first configuration information M1And other subsequent respective operations are executed according to the data from HSSI High-Speed Serial Interface device 100.Or information-processing circuit210 can according to the first configuration information M1 content and out of storage element 220 obtain write back read data, and will write back read data returnIt is transmitted to HSSI High-Speed Serial Interface device 100.Base this, access the storage element 220 of another HSSI High-Speed Serial Interface device 200 data passDefeated task can be completed by HSSI High-Speed Serial Interface.It is noted that since the data of above-mentioned data transfer task are all logicalThe control bit of first frame F1_1~F1_N is crossed to transmit, therefore HSSI High-Speed Serial Interface device 100 and another HSSI High-Speed Serial Interface fillThe mass data transmission of high-speed can be carried out by the first data sample of first frame F1_1~F1_N simultaneously by setting 200.
It is similar, it needs to access high speed serialization when HSSI High-Speed Serial Interface device 200 executes another data transfer task and connectsWhen mouthful device 100, the information-processing circuit 210 of HSSI High-Speed Serial Interface device 200 may be in response to data transfer task and generate theTwo configuration information M2.Specific embodiment is as previously mentioned, just no longer illustrate.
It is worth noting that, when the data transfer task that HSSI High-Speed Serial Interface device 100 is initiated is to read high speed serialization to connectWhen data in the storage element 220 of mouthful device 200, HSSI High-Speed Serial Interface device 100 is returned in order to which back read data will be write, is believedAfter ceasing first configuration information M1 of the parsing of processing circuit 210, corresponding number in storage element 220 can be read according to the result of parsingAccording to.Then, information-processing circuit 210 generates the second configuration information M2, and the data to be read in the first configuration information M1 are passedIt send to high speed serial interface device 100.
Operation similar with coding circuit 130 and principle can be performed in coding circuit 250, is generated according to the second configuration information M2Second coding configuration order X2.And interface transmitter 242 be intended to transmission data framework turn to second frame F2_1~F2_N after, willSecond coding configuration order X2 is embedded on the control bit of multiple second frame F2_1~F2_N, and can be embedded into second for multipleSecond frame F2_1~F2_N of coding configuration order X2 is sent to HSSI High-Speed Serial Interface device 100.Furthermore, it is understood that high speed serializationInterface circuit 140 can receive from another HSSI High-Speed Serial Interface device 200 and form multiple the second of multiple second frame F2_1~F2_NData sample.Then, decoding circuit 150 can obtain the control bit of each second data sample by high-speed serial interface circuit 140And the second coding configuration order X2 is obtained, and decoding processing is carried out to the second coding configuration order X2 and extracts second with confidenceCease M2.Information-processing circuit 110 can correspond to according to the second configuration information M2 and execute operation.
In conclusion working as the storage element 220 of the HSSI High-Speed Serial Interface device 200 to be read of HSSI High-Speed Serial Interface device 100Data when, can be intended to read data the first configuration information M1 be sent to HSSI High-Speed Serial Interface device 200 through the above way.After HSSI High-Speed Serial Interface device 200 receives the first configuration information M1, corresponding reading data first are read to storage element 220,And the second configuration information M2 for reading data with this is sent back into HSSI High-Speed Serial Interface device 100, to complete to read dataTask.It is written when HSSI High-Speed Serial Interface device 100 is intended to data will be written to the storage element 220 of high speed serial interface device 200When, the first configuration information M1 with write-in data can be sent to HSSI High-Speed Serial Interface device 200 through the above way.At a high speedAfter serial interface device 200 receives and restores the first configuration information M1, the program for executing write-in can be corresponded to.
By taking HSSI High-Speed Serial Interface agreement is JESD204b agreement as an example, high-speed serial interface circuit 140,240 includesTransport layer (transport layer) circuit, physical layer (Physical layer) circuit and the link of JESD204b agreementCircuit needed for layer (Link layer) circuit etc. can specifically execute JESD204b agreement.
First coding configuration order is embedded in the example among first frame/second frame by following further clarification.With high speedSerial interface protocol is for JESD204b agreement, mapped data to be sent is corresponding to multiple the 8 of a transmission channelBit byte (octets), and multiple octets form frame (a first frame F1_1~F1_N and the second frame F2_ i.e. shown in FIG. 11~F2_N).In addition, a frame may include an at least data sample (i.e. composition first frame F1_1~F1_N and the second frame F2_1~The first data sample and the second data sample of F2_N), and each data sample can carry 1 to 3 control bit.It should be notedIt is the quantity of the total bit of single data sample, control bit in single data sample, the number with the data sample in single frameAmount can be adjusted according to actual demand, and the present invention is not intended to limit this.
Fig. 2 is the schematic diagram of a frame depicted in an embodiment according to the present invention.Example referring to figure 2., frame F1It can be made of 13 octets.In addition, frame F1 may include multiple data sample S1~S8, and each data sample S1~S8 canCarry 1 control bit and 12 sample bits.That is, the total bit of each data sample S1~S8 is 13, and frame F1 canWith 8 control bit CS.This 8 control bit CS can be used to transmit coding configuration order of the invention and (encode first with confidenceThe the first coding configuration order X1 and the second coding configuration order X2 for ceasing M1 and the second configuration information M2 and generating).It is known that, in the example of Fig. 2, when the digit for encoding configuration order is greater than 8, coding configuration order needs to pass by multiple framesIt is defeated.
In the example of Fig. 2, the control bit CS centralized configuration of data sample S1~S8 is in the ending of frame F1, but the present invention is simultaneouslyIt is not limited to this.In other embodiments, the control bit of data sample S1~S8 can centralized configuration in the beginning of frame F1, or beatDissipate the tail end for being configured at each data sample S1~S8.However, the transport layer standard of JESD204B agreement gives very flexiblyFrame format, Fig. 2 is only exemplary illustrated is not intended to limit the invention.
The example further explained below for encoding the first configuration information and generating the first configuration-direct.Fig. 3 is according to this hairThe schematic diagram of first coding configuration order depicted in a bright embodiment.Referring to figure 3., the first coding configuration order cmd1 isA kind of example of first coding configuration order X1 shown in FIG. 1, the first coding configuration order cmd1 includes leading character 31, start bit32, operational order 33, destination address 34 and specific data 35.In an embodiment, when operational order 33 is reading orderWhen, the specific data 35 of the first coding configuration order cmd1 is to read serial number.When operational order 33 is write back data order, theThe specific data 35 of one coding configuration order cmd1 is to write back read data.When operational order 33 is writing commands, the first codingThe specific data 35 of configuration order cmd1 is write-in data.
In the example of Fig. 3, leading character 31 includes 28 leading character positions, and leading character position is all the first place value ' 1 '.StartingPosition is the second place value ' 0 ' for being different from the first place value ' 1 '.Operational order 33 includes 2 command bits, and destination address 34 includes8 address bits.Specific data 35 includes 16 specific data positions.Based on above-mentioned configuration, when HSSI High-Speed Serial Interface device 100 transmitsMultiple first frame F1_1~F1_N with the first coding configuration order cmd1 are to HSSI High-Speed Serial Interface device 200, the first codingLeading character 31, start bit 32, operational order 33, destination address 34 and specific data 35 in configuration order cmd1 can be according toSequence is received by HSSI High-Speed Serial Interface device 200.
Specifically, in an embodiment, in order to allow the receiving end for receiving the first coding configuration order cmd1 canIdentify the beginning of the first coding configuration order cmd1 and correct decoding, leading character 31 can by all first place values it is multiple beforeLead symbol byte at, start bit 32 can by all second place values an at least start byte at.Also, the quantity of leading character position willGreater than the summation of the quantity of start bit, the quantity of operative position, the quantity of address bit and the quantity of specific data position.Such as Fig. 3Shown in example, quantity, the quantity of operative position, the quantity of address bit and summation of quantity of specific data position of start bit etc.In 27 positions (1+2+8+16=27), therefore the quantity of leading character position is configured and at least equal to 28 positions.However, Fig. 3 is onlyExemplary illustrated to be not intended to limit the invention, the present invention can not limit the number of leading character position and start bit.LifeEnabling the number of position, mesh address bit and specific data position can also be actual demand and configures.
It is further to note that the coding with operational order, destination address and specific data is matched in an embodimentSetting order can transmit using N number of frame as the period.Using the first coding configuration order of the frame format of Fig. 2 and Fig. 3 as example, due to theThe data volume of one coding configuration order cmd1 is 55, and each frame is only capable of the data volume of transmission 8, therefore the first coding is matchedOrder cmd1 needs are set to transmit by least seven frame as shown in Figure 2.
Fig. 4 A is the schematic diagram of the transmission of data depicted in an embodiment according to the present invention.A referring to figure 4., if high speedThe data transfer task that serial interface device 100 is initiated is when reading data from another HSSI High-Speed Serial Interface device 200, and first compilesThe operational order of code configuration order X1 is reading order.First is matched after first coding of the decoding of decoding circuit 230 configuration order X1Confidence breath M1 is exported to information-processing circuit 210, wherein the first configuration information M1 includes reading order 41 and destination address‘A'42.Therefore, information processing electricity 210 can obtain in storage element 220 according to reading order 41 and destination address ' A ' 42Positioned at the data ' A ' of destination address ' A '.Later, it includes write back data order 43, destination address that information processing electricity 210 is exportable' A ' 44, and write the second configuration information M2 of back read data ' A ' 45.Coding circuit 250 encodes the second configuration information M2 and generatesSecond coding configuration order X2, and the second coding configuration order X2 is embedded in the control bit in multiple second frames, cause theTwo coding configuration order X2 can return to HSSI High-Speed Serial Interface device 100 by multiple second frames.In this way, high speed serializationThe information-processing circuit 120 of interface arrangement 100 can be obtained by receiving the second coding configuration order X2 from the second configuration information M2It takes and writes back read data ' A ' 45.
Fig. 4 B is the schematic diagram of the transmission of data depicted in an embodiment according to the present invention.B referring to figure 4., if high speedThe data transfer task that serial interface device 100 is initiated is that data will be written to be transmitted to another HSSI High-Speed Serial Interface device 200, theThe operational order of one coding configuration order X1 is writing commands.Furthermore, first coding of the decoding of decoding circuit 230 configuration lifeThe first configuration information M1 is exported to information-processing circuit 210 after enabling X1, wherein the first configuration information M1 include writing commands 47,Destination address ' B ' 48 and write-in data ' B ' 49.Therefore, information processing electricity 210 can be according to writing commands 47 and destination address' B ' 48 and the storage space for destination address ' B ' of the write-in of data ' B ' 49 into storage element 220 will be written pointing out.
Based on above-mentioned, in response in different types of data transfer task, information-processing circuit 210 may be in response to receiveOne configuration information M1 and the operation executed include: to write back read data from the first configuration information M1 acquisition, by the first configuration information M1In write-in data storage to the storage element 220 of high speed serial interface device 200 among, or according to the first configuration information M1In destination address from the storage element 220 of oneself acquisition write back read data.Based on identical principle, information-processing circuit 110The operation that may be in response to receive the second configuration information M2 and execute includes: to write back read data from the second configuration information M2 acquisition,Among the storage element 120 of the write-in data storage in the second configuration information M2 to high speed serial interface device 100, Huo ZheyiBack read data is write from the storage element 120 of oneself acquisition according to the destination address in the second configuration information M2.
It is noted that task is written in the reading data task of either Fig. 4 A or the data of Fig. 4 B, data existTransmission process is by the way of one-way transmission, without using (Handshake) program of shaking hands for needing to return response.It borrowsThe bandwidth availability ratio between two HSSI High-Speed Serial Interface devices 100,200 can be improved in this.
Fig. 5 A and Fig. 5 B is the flow chart of data transmission method depicted in an embodiment according to the present invention.The present embodimentData transmission method related implementation detail and relevant apparatus feature can be by above-mentioned each embodiment about Fig. 1 to Fig. 4 BIn narration, enough teachings, suggestion and embodiment are obtained, is not repeated here herein.
A referring to figure 5. generates the first configuration information in response to initiating data transfer task in step S501.In stepS502 carries out coded treatment to the first configuration information and generates the first coding configuration order.In step S503, it is based on high speed serializationFirst coding configuration order is embedded among the control bit of multiple first data samples by interface protocol.In step S504, foundationHSSI High-Speed Serial Interface agreement transmits multiple first frames composed by the first data sample to another HSSI High-Speed Serial Interface device, with logicalIt crosses transmission the first coding configuration order and carries out data transmission task to another HSSI High-Speed Serial Interface device.
B referring to figure 5. is received from another HSSI High-Speed Serial Interface device in step S505 and is formed the multiple of multiple second framesSecond data sample.In step S506, obtained by the control bit that high-speed serial interface circuit obtains each second data sampleSecond coding configuration order.In step S507, decoding processing is carried out to the second coding configuration order and extracts the second configuration information.In step S508, operation is executed into data transfer task or to carry out another HSSI High-Speed Serial Interface device according to the second configuration informationAnother data transfer task initiated.
In conclusion in an embodiment of the present invention, only being connect originally to carry out the high speed serialization of high speed data transfersMouth also can be used to execute the data transfer task being responsible for originally by another coffret, and the configuration of another coffret then can evidenceTo omit.By omit configuration coffret to chip in, the pin number of chip can be reduced, and therefore reduce manufacturing cost withChip area.In addition to this, the number by the control bit of flexible configuration and position, the present invention can be adjusted accordingly on to carry outThe transmission rate of data transfer task is stated, the mass data that high-speed can be more carried out simultaneously by the data sample in frame is transmitted,From the efficiency for improving interface transmission.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical fieldMiddle tool usually intellectual, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, thus it is of the inventionProtection scope should be defined by the scope of the appended claims.