CN109192740B - Array substrate and preparation method thereof - Google Patents
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- CN109192740B CN109192740BCN201811108511.XACN201811108511ACN109192740BCN 109192740 BCN109192740 BCN 109192740BCN 201811108511 ACN201811108511 ACN 201811108511ACN 109192740 BCN109192740 BCN 109192740B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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Abstract
Translated fromChinese
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
Organic electroluminescent Display panels (OLEDs) gradually become the mainstream of the Display field by virtue of their excellent properties such as low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility, and can be widely applied to terminal products such as smart phones, tablet computers, televisions, and the like. The flexible OLED panel is gradually becoming the mainstream of the OLED panel due to its high flexibility and being capable of satisfying various special structures.
The conventional flexible OLED panel usually comprises a plurality of organic film layers with high flexibility and a plurality of inorganic film layers, and the inorganic film layers are usually very dense, so that the film layer stress in the flexible OLED panel is increased, the flexibility of the flexible OLED panel is poor, the film layers are easy to crack and peel when the flexible OLED panel is bent, and the flexibility requirement of the OLED panel is difficult to meet.
Disclosure of Invention
The invention provides an array substrate, a preparation method thereof and a display panel, and aims to solve the problem that the inorganic film layer in the existing flexible OLED panel increases the film layer stress, so that the flexibility requirement of the OLED panel is difficult to meet.
In order to solve the above problems, the present invention discloses an array substrate, including:
a substrate;
electronic devices formed on the substrate and a first composite layer located between adjacent electronic devices;
wherein the first composite layer includes at least an organic planarization layer.
Optionally, the electronic device comprises a thin film transistor comprising:
an inorganic isolation buffer layer formed on the substrate;
an active layer formed on the inorganic isolation buffer layer;
a first inorganic gate insulating layer formed on the active layer;
a gate electrode formed on the first inorganic gate insulating layer;
a composite inorganic film layer formed on the gate electrode;
a source electrode and a drain electrode formed on the composite inorganic film layer in the same layer;
the composite inorganic film layer is provided with a gap between the source electrode and the drain electrode, and the organic flat layer is filled in the gap.
Optionally, the depth of the gap is less than or equal to the thickness of the composite inorganic film layer.
Optionally, the composite inorganic film layer includes a second inorganic gate insulating layer and an interlayer inorganic insulating layer, and the second inorganic gate insulating layer is disposed near the gate electrode.
Optionally, the first composite layer further includes the inorganic isolation buffer layer, the first inorganic gate insulating layer, and the second inorganic gate insulating layer, which are stacked, where the inorganic isolation buffer layer is disposed near the substrate, and the organic planarization layer is disposed near the second inorganic gate insulating layer.
Optionally, the organic planarization layer has a thickness greater than or equal to 0.5 micrometers and less than or equal to 4 micrometers.
Optionally, additional traces are further formed on the organic planarization layer.
In order to solve the above problems, the present invention also discloses a method for manufacturing an array substrate, comprising:
providing a substrate;
forming an electronic device and an inorganic composite layer between the electronic devices on the substrate;
removing at least part of the inorganic composite layer to form a first composite layer;
forming an organic planarization layer covering the electronic device and the first composite layer.
Optionally, the electronic device includes a thin film transistor, and the forming of the electronic device and the inorganic composite layer between the electronic devices on the substrate includes:
forming an inorganic isolation buffer layer on the substrate;
forming an active layer on the inorganic isolation buffer layer;
forming a first inorganic gate insulating layer;
forming a gate electrode on the first inorganic gate insulating layer;
forming a composite inorganic film layer;
forming a source electrode and a drain electrode on the same layer on the composite inorganic film layer;
etching the composite inorganic film layer between the source electrode and the drain electrode by taking the source and drain electrode pattern as a mask pattern to form a gap;
the forming of the organic planarization layer includes:
and filling the gap to form an organic flat layer.
Optionally, after the forming the organic planarization layer, the method further includes:
and forming additional routing lines on the organic flat layer.
Compared with the prior art, the invention has the following advantages:
in an embodiment of the present invention, an array substrate may include a substrate, electronic devices formed on the substrate, and a first composite layer between adjacent electronic devices, wherein the first composite layer includes at least an organic planarization layer. In the embodiment of the invention, the organic flat layer with higher flexibility can replace part or all of the originally formed inorganic film layers between the adjacent electronic devices, so that part of stress of the array substrate can be released, the electronic devices are prevented from being damaged due to bending, and the flexibility of the whole display panel is improved.
Drawings
Fig. 1 is a cross-sectional view of an array substrate according to a first embodiment of the present invention;
fig. 2 is a cross-sectional view of another array substrate according to a first embodiment of the present invention;
fig. 3 is a flowchart illustrating a method for manufacturing an array substrate according to a second embodiment of the present invention;
fig. 4 is a cross-sectional view illustrating an array substrate after an interlayer inorganic insulating layer is formed according to a second embodiment of the present invention;
fig. 5 is a cross-sectional view illustrating an array substrate after at least a portion of an inorganic composite layer is removed according to a second embodiment of the present invention.
Description of reference numerals:
10-substrate, 20-first composite layer, 30-organic flat layer, 01-inorganic isolation buffer layer, 02-active layer, 03-first inorganic gate insulating layer, 04-grid electrode, 05-first polar plate, 06-composite inorganic film layer, 061-second inorganic gate insulating layer, 062-interlayer inorganic insulating layer, 07-source electrode, 08-drain electrode, 09-second polar plate, 010-additional wiring.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example one
Fig. 1 is a schematic cross-sectional view illustrating an array substrate according to a first embodiment of the present invention. Referring to fig. 1, the array substrate includes asubstrate 10, electronic devices formed on thesubstrate 10, and a firstcomposite layer 20 located between adjacent electronic devices, where the firstcomposite layer 20 at least includes anorganic planarization layer 30, that is, a portion or all of an inorganic film layer originally formed between adjacent electronic devices may be replaced by theorganic planarization layer 30 having high flexibility, so that a portion of stress of the array substrate may be released, and thus, flexibility of the entire display panel may be improved, and damage of the electronic devices due to bending may be avoided. In an actual manufacturing process of the array substrate, after the inorganic film layer between adjacent electronic devices is formed, a portion or all of the inorganic film layer may be removed to form a film layer gap, and then the film layer gap may be filled with theorganic planarization layer 30 to form the firstcomposite layer 20.
Referring to fig. 1, an electronic device may include a thin film transistor, wherein the thin film transistor may include an inorganicisolation buffer layer 01 formed on asubstrate 10, anactive layer 02 formed on the inorganicisolation buffer layer 01, a first inorganicgate insulating layer 03 formed on theactive layer 02, agate electrode 04 formed on the first inorganicgate insulating layer 03, a compositeinorganic film layer 06 formed on thegate electrode 04, and asource electrode 07 and adrain electrode 08 formed on the compositeinorganic film layer 06 in the same layer.
The inorganicisolation buffer layer 01 may include a single layer or multiple layers having an isolation buffer function, which is not particularly limited in this embodiment of the present invention. In addition, the compositeinorganic film layer 06 has a gap between thesource electrode 07 and thedrain electrode 08, and the gap is filled with theorganic planarization layer 30, wherein the depth of the gap may be less than or equal to the thickness of the compositeinorganic film layer 06, that is, a part or all of the inorganic film layer originally formed between thesource electrode 07 and thedrain electrode 08 may be replaced by theorganic planarization layer 30 with high flexibility, so that a part of the stress of the array substrate may be released, and the flexibility of the entire display panel may be improved.
In practical applications, the compositeinorganic film 06 may specifically include a second inorganic gate insulating layer 061 and an interlayer inorganicinsulating layer 062, where the second inorganic gate insulating layer 061 is disposed close to thegate 04, that is, only the inorganicisolation buffer layer 01, the first inorganicgate insulating layer 03, and the second inorganic gate insulating layer 061 are remained except for theactive layer 02 and thegate 04 in the film below the source-drain 08 gap. In the actual preparation process of the array substrate, the film layer gap formed after removing part or all of the inorganic film layer between the adjacent electronic devices can be formed simultaneously with the gap on the compositeinorganic film layer 06 through the etching process, so that the etching times can be reduced, and the preparation efficiency of the array substrate can be improved. Therefore, the inorganic film layer remaining below the film layer gap is the same as the inorganic film layer remaining below the source-drain 08 gap, corresponding to the preparation method of simultaneously forming the film layer gap between adjacent electronic devices and the gap between the source-drain 08. I.e., the firstcomposite layer 20 between adjacent electronic devices, may further include an inorganicisolation buffer layer 01, a first inorganicgate insulating layer 03, and a second inorganic gate insulating layer 061, which are stacked, wherein the inorganicisolation buffer layer 01 is disposed adjacent to thesubstrate 10, and theorganic planarization layer 30 is disposed adjacent to the second inorganic gate insulating layer 061.
Further, the electronic device can further comprise a storage capacitor, the storage capacitor and the thin film transistor are located in different areas of the array substrate, and the storage capacitor and the thin film transistor can be used for keeping the display state of the pixel. The storage capacitor may specifically include afirst plate 05 formed on the first inorganicgate insulating layer 03, a second inorganic insulating layer formed on thefirst plate 05, and asecond plate 09 formed on the second inorganic insulating layer and opposite to thefirst plate 05, wherein thefirst plate 05 may be formed in the same layer as thegate 04 of the thin film transistor, and the interlayer inorganic insulatinglayer 062 covers thesecond plate 09. Anorganic planarization layer 30 having high flexibility is formed in the gap between the inorganic film layer and the storage capacitor.
In addition, the electronic device may further include traces, such as gate lines, data lines, plate traces of storage capacitors, and the like, which is not particularly limited in this embodiment of the present invention. The grid line and thegrid 04 of the thin film transistor can be formed on the same layer and connected with thegrid 04; the data line may be formed in the same layer as the source/drain 08 of the thin film transistor and connected to thesource electrode 07; the routing of thefirst plate 05 of the storage capacitor can be formed on the same layer as thefirst plate 05 and connected with thefirst plate 05; the storage capacitorsecond plate 09 may be formed in the same layer as thesecond plate 09, and connected to thesecond plate 09. In the embodiment of the invention, the organic film layer with low compactness and good flexibility can replace part or all of the inorganic film layers originally formed between the thin film transistor and the storage capacitor and between the routing wires, so that the flexibility of the whole display panel is improved, and the requirement of the array substrate on the dielectric property can be met by filling the organic film layer.
In practical applications, the thickness of the etched inorganic film layer may be greater than or equal to 0.01 micrometers and less than or equal to 1 micrometer, that is, the thickness of theorganic planarization layer 30 filled between the gaps of the inorganic film layer may be greater than or equal to 0.01 micrometers and less than or equal to 1 micrometer.
In addition, in practical applications, in order to ensure the thickness uniformity of the array substrate, theorganic planarization layer 30 includes not only the portion filled in the gap of the inorganic film layer, but also the portion covering all other structures of the array substrate, and thus, the thickness of theorganic planarization layer 30 at each region is different, wherein the thickness of the thickest position of theorganic planarization layer 30 may be greater than or equal to 0.5 micrometers and less than or equal to 4 micrometers, and in a preferred implementation, the thickness of the thickest position of theorganic planarization layer 30 may be greater than or equal to 0.8 micrometers and less than or equal to 1.6 micrometers.
Further, referring to fig. 2, anadditional trace 010 may be further formed on theorganic planarization layer 30, that is, the array substrate improved in the embodiment of the present invention may be an array substrate in a single-layer trace layout manner, or an array substrate in a multi-layer trace layout manner. Theadditional routing 010 specifically includes anadditional routing 010 of a thin film transistor and anadditional routing 010 of a storage capacitor, the two layers of routing of the thin film transistor can be connected through a via hole at a corresponding position on the organicflat layer 30, and the two layers of routing of the storage capacitor can also be connected through a via hole at a corresponding position on the organicflat layer 30.
Further, in order to ensure the thickness uniformity of the array substrate, after theadditional trace 010 of the thin film transistor is formed, a planarization layer covering theadditional trace 010 may be formed again. In addition, after the planarization layer covering theadditional trace 010 is formed, a film layer such as a water-oxygen isolation layer and a package layer may be formed.
In an embodiment of the present invention, an array substrate may include a substrate, electronic devices formed on the substrate, and a first composite layer between adjacent electronic devices, wherein the first composite layer includes at least an organic planarization layer. In the embodiment of the invention, the organic flat layer with higher flexibility can replace part or all of the originally formed inorganic film layers between the adjacent electronic devices, so that part of stress of the array substrate can be released, the electronic devices are prevented from being damaged due to bending, and the flexibility of the whole display panel is improved.
Example two
Referring to fig. 3, a flowchart illustrating steps of a method for manufacturing an array substrate according to a second embodiment of the present invention is shown, where the method may include the following steps:
step 301: a substrate is provided.
In embodiments of the invention, the substrate may be a flexible substrate, or a rigid substrate with relatively little flexibility.
Step 302: an electronic device and an inorganic composite layer between the electronic devices are formed on a substrate.
In an embodiment of the present invention, the electronic device may include a thin film transistor, a storage capacitor, and a trace. Specifically, referring to fig. 4, an inorganic isolation buffer layer may be first formed on a substrate, an active layer may then be formed on the inorganic isolation buffer layer through a patterning process, a first inorganic gate insulating layer may then be formed, wherein the first inorganic gate insulating layer covers the active layer, a gate line connected to the gate electrode, a first plate of a storage capacitor, and a first plate wire may then be formed on the first inorganic gate insulating layer through the patterning process, and a composite inorganic film layer may then be formed, wherein the composite inorganic film layer covers the gate electrode and the first plate, and a source electrode and a drain electrode, and a data line connected to the source electrode may then be formed on the composite inorganic film layer in the same layer through the patterning process, wherein both the source electrode and the drain electrode may be connected to the active layer through via holes on the composite inorganic film layer and the first inorganic insulating layer.
The composite inorganic film layer in the thin film transistor may include a second inorganic gate insulating layer and an interlayer inorganic insulating layer, wherein the second inorganic gate insulating layer is disposed near the gate electrode. In an actual manufacturing process, after the gate electrode, the gate line, the first electrode plate and the first electrode plate wiring are formed on the first inorganic gate insulating layer, the second inorganic gate insulating layer may be formed first, and then the second electrode plate and the second electrode plate wiring of the storage capacitor may be formed on the same layer, so that the interlayer inorganic insulating layer may be formed.
Referring to fig. 4, the inorganic composite layer between the electronic devices includes an inorganic isolation buffer layer, a first inorganic gate insulating layer, a second inorganic gate insulating layer, and an interlayer inorganic insulating layer.
Step 303: and removing at least part of the inorganic composite layer.
In an embodiment of the present invention, after forming the source and drain electrodes of the thin film transistor, at least a portion of the inorganic composite layer may be removed by an etching process, thereby obtaining an array substrate with at least a portion of the inorganic composite layer removed, as shown in fig. 5. In practical applications, the inorganic composite film with a certain thickness may be removed according to actual flexibility requirements, or even all of the inorganic composite films may be removed, which is not specifically limited in the embodiment of the present invention.
In the thin film transistor, after the source electrode and the drain electrode are formed, the composite inorganic film layer between the source electrode and the drain electrode can be etched by using the source/drain electrode pattern as a mask pattern, so that a gap is formed. In practical application, the gaps inside the thin film transistors and the film layer gaps between adjacent electronic devices can be formed through a one-time etching process, so that for the whole array substrate, after the source electrodes and the drain electrodes of the thin film transistors are formed, the composite inorganic film layers between the adjacent electronic devices and the composite inorganic film layers inside each electronic device can be etched by taking the electronic device patterns as mask patterns, and thus the film layer gaps between the adjacent electronic devices and the gaps inside each electronic device are formed. Of course, in practical applications, the gap inside the thin film transistor and the film layer gap between adjacent electronic devices may also be formed by two etching processes, which is not specifically limited in the embodiment of the present invention.
In addition, for the preparation method of simultaneously forming the gap inside the thin film transistor and the film layer gap between adjacent electronic devices by one-time etching process, in order to avoid the damage of the gate electrode of the thin film transistor due to etching, in practical application, only the interlayer inorganic insulating layer and a part of the second inorganic gate insulating layer in the inorganic composite layer can be removed, that is, a part of the second inorganic gate insulating layer can be remained on the gate electrode, so that the gate electrode of the thin film transistor can be prevented from being etched.
Specifically, the etching process may include a dry etching process or a wet etching process, wherein an etching gas of the dry etching process may include tetrafluoromethane or trifluoromethane, and an etching liquid of the wet etching process may include hydrofluoric acid, which is not particularly limited in this embodiment of the present invention.
Step 304: and forming an organic flat layer, wherein the organic flat layer covers the electronic device and the first composite layer.
In the embodiment of the invention, in consideration of the absence of the inorganic film layer between the electronic devices and the requirement of the array substrate for the dielectric property, after removing at least part of the inorganic composite layer, an organic planarization layer covering the electronic devices and the first composite layer can be formed, see fig. 1, so that the organic planarization layer can fill the gap of the absent inorganic film layer, thereby ensuring the thickness uniformity of the array substrate and the requirement of the dielectric property. Therefore, the array substrate with the single-layer routing layout mode can be obtained.
Further, in practical applications, an array substrate with a multilayer routing layout may be prepared, and accordingly, additional routing lines may be formed on the organic planarization layer, as shown in fig. 2. Further, in order to ensure the thickness uniformity of the array substrate, after the additional trace of the thin film transistor is formed, a planarization layer covering the additional trace may be formed again. In addition, after the planar layer covering the additional trace is formed, film layers such as a water-oxygen isolation layer and a packaging layer may also be formed, which is not specifically limited in the embodiment of the present invention.
In the embodiment of the invention, the electronic device and the inorganic composite layer between the electronic devices can be formed on the substrate, then at least part of the inorganic composite layer can be removed through an etching process to form the first composite layer, and further an organic flat layer covering the electronic devices and the first composite layer can be formed. In the embodiment of the invention, at least part of the inorganic composite layer between the electronic devices can be removed, and the gap formed after the inorganic composite layer is removed is filled and removed by the organic flat layer, so that the organic flat layer with higher flexibility can replace part or all of the originally formed inorganic film layers between the adjacent electronic devices, thereby releasing part of stress of the array substrate, avoiding the electronic devices from being damaged due to bending, and improving the flexibility of the whole display panel.
EXAMPLE III
The embodiment of the invention also discloses a display panel which comprises the display substrate.
In an embodiment of the present invention, an array substrate of a display panel may include a substrate, electronic devices formed on the substrate, and a first composite layer between adjacent electronic devices, wherein the first composite layer includes at least an organic planarization layer. In the embodiment of the invention, the organic flat layer with higher flexibility can replace part or all of the originally formed inorganic film layers between the adjacent electronic devices, so that part of stress of the array substrate can be released, the electronic devices are prevented from being damaged due to bending, and the flexibility of the whole display panel is improved.
While, for purposes of simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present invention is not limited by the illustrated ordering of acts, as some steps may occur in other orders or concurrently with other steps in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The array substrate and the method for manufacturing the same provided by the invention are described in detail above, and the principle and the embodiment of the invention are explained in the present document by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. An array substrate, comprising:
a substrate;
electronic devices formed on the substrate, and a first composite layer between adjacent electronic devices; the adjacent electronic devices are arranged along a direction parallel to the substrate;
wherein the first composite layer comprises at least an organic planarization layer;
the electronic device includes a thin film transistor including:
an inorganic isolation buffer layer formed on the substrate;
an active layer formed on the inorganic isolation buffer layer;
a first inorganic gate insulating layer formed on the active layer;
a gate electrode formed on the first inorganic gate insulating layer;
a composite inorganic film layer formed on the gate electrode;
a source electrode and a drain electrode formed on the composite inorganic film layer, wherein the source electrode and the drain electrode are arranged on the same layer;
the composite inorganic film layer is provided with a gap between the source electrode and the drain electrode, and the organic flat layer is filled in the gap; the organic planarization layer also covers the source electrode and the drain electrode.
2. The array substrate of claim 1, wherein the depth of the gap is less than or equal to the thickness of the composite inorganic film layer.
3. The array substrate of claim 1, wherein the composite inorganic film layer comprises a second inorganic gate insulating layer and an interlayer inorganic insulating layer, the second inorganic gate insulating layer being disposed adjacent to the gate electrode.
4. The array substrate of claim 3, wherein the first composite layer further comprises the inorganic isolation buffer layer, the first inorganic gate insulating layer and the second inorganic gate insulating layer in a stacked arrangement, the inorganic isolation buffer layer is disposed adjacent to the substrate, and the organic planarization layer is disposed adjacent to the second inorganic gate insulating layer.
5. The array substrate of claim 1, wherein the organic planarization layer has a thickness greater than or equal to 0.5 micrometers and less than or equal to 4 micrometers.
6. The array substrate of any one of claims 1 to 5, wherein additional traces are further formed on the organic planarization layer.
7. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming electronic devices and an inorganic composite layer between adjacent electronic devices on the substrate; the adjacent electronic devices are arranged along a direction parallel to the substrate;
removing at least part of the inorganic composite layer;
forming an organic flat layer covering the electronic device and the rest of the inorganic composite layer;
wherein the electronic device comprises a thin film transistor, and the forming of the electronic device and the inorganic composite layer between the electronic devices on the substrate comprises:
forming an inorganic isolation buffer layer on the substrate;
forming an active layer on the inorganic isolation buffer layer;
forming a first inorganic gate insulating layer;
forming a gate electrode on the first inorganic gate insulating layer;
forming a composite inorganic film layer;
forming a source electrode and a drain electrode on the composite inorganic film layer, wherein the source electrode and the drain electrode are arranged on the same layer;
etching the composite inorganic film layer between the source electrode and the drain electrode by taking the source and drain electrode pattern as a mask pattern to form a gap;
the forming of the organic planarization layer includes:
filling the gap to form an organic flat layer;
wherein the organic planarization layer also covers the source electrode and the drain electrode.
8. The method of claim 7, further comprising, after the forming the organic planarization layer:
and forming additional routing lines on the organic flat layer.
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| CN108550612A (en)* | 2018-05-29 | 2018-09-18 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
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