技术领域technical field
本发明涉及显示技术领域，尤其涉及一种像素单元、驱动方法、像素模组及其驱动方法和显示装置。The present invention relates to the field of display technology, in particular to a pixel unit, a driving method, a pixel module, a driving method thereof, and a display device.
背景技术Background technique
OLED(有机发光二极管)具有主动发光，无视角问题，重量轻，厚度小，高亮度，高发光效率，响应速度快，动态画面质量高，使用温度范围广，可实现柔性显示，工艺简单，成本低，抗震能力强都一系列优点。然而由于OLED显示需要复杂的像素补偿电路，制约了OLED显示屏的PPI(Pixels Per Inch，每英寸所拥有的像素数目)的提高。OLED (Organic Light Emitting Diode) has active light emission, no viewing angle problem, light weight, small thickness, high brightness, high luminous efficiency, fast response speed, high dynamic picture quality, wide temperature range, flexible display, simple process and low cost Low, strong earthquake resistance are a series of advantages. However, since the OLED display requires a complex pixel compensation circuit, the improvement of the PPI (Pixels Per Inch, the number of pixels per inch) of the OLED display is restricted.
发明内容Contents of the invention
本发明的主要目的在于提供一种像素单元、驱动方法、像素模组及其驱动方法和显示装置，解决现有技术中无法实现高PPI(Pixels Per Inch，每英寸所拥有的像素数目)的问题。The main purpose of the present invention is to provide a pixel unit, a driving method, a pixel module and its driving method, and a display device, so as to solve the problem that high PPI (Pixels Per Inch, the number of pixels per inch) cannot be achieved in the prior art .
为了达到上述目的，本发明提供了一种像素单元，包括第一发光元件和第二发光元件，所述像素单元还包括：In order to achieve the above object, the present invention provides a pixel unit, including a first light-emitting element and a second light-emitting element, and the pixel unit further includes:
驱动电路，控制端与驱动节点连接，第一端与第一电压端连接，用于在所述驱动节点的控制下，导通或断开所述第一电压端与所述驱动电路的第二端之间的连接；A driving circuit, the control terminal is connected to the driving node, the first terminal is connected to the first voltage terminal, and is used to turn on or off the first voltage terminal and the second voltage terminal of the driving circuit under the control of the driving node. connection between terminals;
初始电路，分别与初始控制线、所述驱动节点和初始电压端连接，用于在所述初始控制线的控制下，控制将所述初始电压端上的初始电压写入所述驱动节点；an initial circuit, respectively connected to the initial control line, the driving node, and the initial voltage terminal, for controlling writing of the initial voltage on the initial voltage terminal into the driving node under the control of the initial control line;
储能电路，第一端与所述驱动节点连接，第二端与数据写入节点连接；An energy storage circuit, the first end of which is connected to the driving node, and the second end is connected to the data writing node;
补偿控制电路，分别与第n行栅线、数据线、所述数据写入节点、所述驱动节点和所述驱动电路的第二端连接，用于在所述第n行栅线的控制下，控制将所述数据线上的数据电压写入所述数据写入节点，并控制所述驱动节点和所述驱动电路的第二端之间连通；n为正整数；The compensation control circuit is connected to the gate line of the nth row, the data line, the data writing node, the driving node, and the second end of the driving circuit respectively, for controlling the gate line of the nth row , controlling to write the data voltage on the data line into the data writing node, and controlling the communication between the driving node and the second end of the driving circuit; n is a positive integer;
数据写入电路，分别与写入控制线、第二电压端和所述数据写入节点连接，用于在所述写入控制线的控制下，控制将第二电压端输出的第二电压写入所述数据写入节点，以相应改变所述驱动节点的电位；a data writing circuit, connected to the writing control line, the second voltage terminal and the data writing node respectively, and used to control the writing of the second voltage output by the second voltage terminal under the control of the writing control line; into the data writing node to change the potential of the driving node accordingly;
第一发光控制电路，分别与所述驱动电路的第二端、第一发光控制线和第一发光元件连接，用于在所述第一发光控制线的控制下，控制导通或断开所述驱动电路的第二端与所述第一发光元件之间的连接；以及，The first light emission control circuit is respectively connected to the second end of the driving circuit, the first light emission control line and the first light emitting element, and is used to control the turn on or off of the light emission control line under the control of the first light emission control line. a connection between the second end of the driving circuit and the first light emitting element; and,
第二发光控制电路，分别与所述驱动电路的第二端、第二发光控制线和第二发光元件连接，用于在所述第二发光控制线的控制下，控制导通或断开所述驱动电路的第二端与所述第二发光元件之间的连接。The second light-emitting control circuit is respectively connected to the second end of the drive circuit, the second light-emitting control line and the second light-emitting element, and is used to control the turning on or off of the second light-emitting control line under the control of the second light-emitting control line. connection between the second end of the drive circuit and the second light emitting element.
实施时，所述写入控制线为第n+1行栅线；During implementation, the write control line is the n+1th row of gate lines;
n大于1，所述初始控制线为第n-1行栅线；或者，n等于1，所述初始控制线为起始信号线。If n is greater than 1, the initial control line is the n-1th row of gate lines; or, n is equal to 1, the initial control line is the initial signal line.
实施时，所述第一发光元件为第一有机发光二极管，所述第二发光元件为第二有机发光二极管；During implementation, the first light-emitting element is a first organic light-emitting diode, and the second light-emitting element is a second organic light-emitting diode;
所述驱动电路包括驱动晶体管，所述驱动晶体管的栅极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端；The drive circuit includes a drive transistor, the gate of the drive transistor is the control terminal of the drive circuit, the first terminal of the drive transistor is the first terminal of the drive circuit, and the second terminal of the drive transistor is the control terminal of the drive circuit. the second end of the drive circuit;
所述初始电路包括初始晶体管，所述初始晶体管的栅极与所述初始控制线连接，所述初始晶体管的第一极与所述驱动节点连接，所述初始晶体管的第二极与所述初始电压端连接；The initial circuit includes an initial transistor, the gate of the initial transistor is connected to the initial control line, the first pole of the initial transistor is connected to the driving node, and the second pole of the initial transistor is connected to the initial voltage terminal connection;
所述储能电路包括存储电容，所述存储电容的第一端与所述驱动节点连接，所述存储电容的第二端与所述数据写入节点连接。The energy storage circuit includes a storage capacitor, a first end of the storage capacitor is connected to the driving node, and a second end of the storage capacitor is connected to the data writing node.
实施时，所述补偿控制电路包括第一补偿控制晶体管和第二补偿控制晶体管，其中，During implementation, the compensation control circuit includes a first compensation control transistor and a second compensation control transistor, wherein,
所述第一补偿控制晶体管的栅极与所述第n行栅线连接，所述第一补偿控制晶体管的第一极与所述驱动节点连接，所述第一补偿控制晶体管的第二极与驱动电路的第二端连接；The gate of the first compensation control transistor is connected to the gate line of the nth row, the first pole of the first compensation control transistor is connected to the driving node, and the second pole of the first compensation control transistor is connected to The second end of the driving circuit is connected;
所述第二补偿控制晶体管的栅极与所述第n行栅线连接，所述第二补偿控制晶体管的第一极与所述数据写入节点连接，所述第二补偿控制晶体管的第二极与所述数据线连接；The gate of the second compensation control transistor is connected to the gate line of the nth row, the first pole of the second compensation control transistor is connected to the data writing node, and the second electrode of the second compensation control transistor The pole is connected with the data line;
所述数据写入电路包括数据写入晶体管，所述数据写入晶体管的栅极与所述写入控制线连接，所述数据写入晶体管的第一极与所述第二电压端连接，所述数据写入晶体管的第二极与所述数据写入节点连接。The data writing circuit includes a data writing transistor, the gate of the data writing transistor is connected to the writing control line, and the first pole of the data writing transistor is connected to the second voltage terminal, so The second pole of the data writing transistor is connected to the data writing node.
实施时，所述第一发光控制电路包括第一发光控制晶体管，所述第一发光控制晶体管的栅极与所述第一发光控制线连接，所述第一发光控制晶体管的第一极与所述驱动电路的第二端连接，所述第一发光控制晶体管的第二极与所述第一发光元件连接；During implementation, the first light emission control circuit includes a first light emission control transistor, the gate of the first light emission control transistor is connected to the first light emission control line, and the first electrode of the first light emission control transistor is connected to the first light emission control line. The second end of the driving circuit is connected, and the second pole of the first light-emitting control transistor is connected to the first light-emitting element;
所述第二发光控制电路包括第二发光控制晶体管，所述第二发光控制晶体管的栅极与所述第二发光控制线连接，所述第二发光控制晶体管的第一极与所述驱动电路的第二端连接，所述第二发光控制晶体管的第二极与所述第二发光元件连接。The second light emission control circuit includes a second light emission control transistor, the gate of the second light emission control transistor is connected to the second light emission control line, and the first electrode of the second light emission control transistor is connected to the drive circuit The second end of the second light emission control transistor is connected to the second light emitting element.
本发明还提供了一种像素驱动方法，应用于上述的像素单元，一显示周期包括依次设置的第一显示子周期和第二显示子周期，所述第一显示子周期包括依次设置的第一初始阶段、第一补偿阶段、第一数据写入阶段和第一发光阶段，所述第二显示子周期包括依次设置的第二初始阶段、第二补偿阶段、第二数据写入阶段和第二发光阶段，所述像素驱动方法包括：The present invention also provides a pixel driving method, which is applied to the above-mentioned pixel unit. A display period includes a first display sub-period and a second display sub-period arranged sequentially, and the first display sub-period includes a first display sub-period arranged sequentially. an initial stage, a first compensation stage, a first data writing stage, and a first light-emitting stage, and the second display sub-cycle includes a second initial stage, a second compensation stage, a second data writing stage, and a second In the light emitting stage, the pixel driving method includes:
在所述第一初始阶段和所述第二初始阶段，初始电压端输出初始电压，初始电路在初始控制线的控制下，控制将所述初始电压写入驱动节点；In the first initial stage and the second initial stage, the initial voltage terminal outputs an initial voltage, and the initial circuit controls writing the initial voltage into the driving node under the control of an initial control line;
在所述第一补偿阶段和所述第二补偿阶段，数据线输出数据电压，补偿控制电路在第n行栅线的控制下，控制将所述数据电压写入所述数据写入节点，并控制所述驱动节点和驱动电路的第二端之间连通；n为正整数；In the first compensation stage and the second compensation stage, the data line outputs a data voltage, and the compensation control circuit controls the writing of the data voltage into the data writing node under the control of the gate line in the nth row, and Controlling the communication between the driving node and the second end of the driving circuit; n is a positive integer;
在所述第一数据写入阶段和所述第二数据写入阶段，在写入控制线的控制下，数据写入电路将第二电压端输出的第二电压V2写入数据写入节点，以将所述数据电压写入所述驱动节点；In the first data writing phase and the second data writing phase, under the control of the writing control line, the data writing circuit writes the second voltage V2 output from the second voltage terminal into the data writing node, to write the data voltage into the driving node;
在所述第一发光阶段，驱动电路在所述驱动节点的控制下，导通所述第一电压端与所述驱动电路的第二端之间的连接，第一发光控制电路在第一发光控制线的控制下，控制导通所述驱动电路的第二端与所述第一发光元件之间的连接，所述驱动电路驱动第一发光元件发光；In the first light-emitting stage, the driving circuit conducts the connection between the first voltage terminal and the second terminal of the driving circuit under the control of the driving node, and the first light-emitting control circuit Under the control of the control line, the connection between the second end of the driving circuit and the first light-emitting element is controlled and turned on, and the driving circuit drives the first light-emitting element to emit light;
在所述第二发光阶段，驱动电路在所述驱动节点的控制下，导通所述第一电压端与所述驱动电路的第二端之间的连接，第二发光控制电路在第二发光控制线的控制下，控制导通所述驱动电路的第二端与所述第二发光元件之间的连接，所述驱动电路驱动第二发光元件发光。In the second light-emitting stage, the driving circuit conducts the connection between the first voltage terminal and the second terminal of the driving circuit under the control of the driving node, and the second light-emitting control circuit Under the control of the control line, the connection between the second end of the driving circuit and the second light emitting element is controlled to be turned on, and the driving circuit drives the second light emitting element to emit light.
实施时，本发明所述的像素驱动方法还包括：During implementation, the pixel driving method described in the present invention also includes:
在所述第一补偿阶段和所述第二补偿阶段，所述驱动电路导通其第一端和所述第二端之间的连接，直至所述驱动节点的电位变为V1+Vth，V1为第一电压端输出的第一电压，Vth为所述驱动电路包括的驱动晶体管的阈值电压；In the first compensation phase and the second compensation phase, the driving circuit conducts the connection between its first terminal and the second terminal until the potential of the driving node becomes V1+Vth, V1 is the first voltage output by the first voltage terminal, and Vth is the threshold voltage of the driving transistor included in the driving circuit;
在所述第一数据写入阶段和所述第二数据写入阶段，控制驱动节点的电位变为V1+V2-Vdata+Vth。In the first data writing phase and the second data writing phase, the potential of the control driving node becomes V1+V2−Vdata+Vth.
本发明还提供了一种像素模组，包括两个上述的像素单元；The present invention also provides a pixel module, including two above-mentioned pixel units;
第一像素单元包括第2n-1行第m列发光元件和第2n行第m列发光元件，第二像素单元包括第2n+1行第m列发光元件和第2n+2行第m列发光元件；The first pixel unit includes light-emitting elements in row 2n-1, column m, and row 2n, column m, and the second pixel unit includes light-emitting elements in row 2n+1, column m, and row 2n+2, column m. element;
所述第一像素单元包括的第一初始电路与第n初始控制线连接，所述第二像素单元包括的第二初始电路与第n+1初始控制线连接；The first initial circuit included in the first pixel unit is connected to the nth initial control line, and the second initial circuit included in the second pixel unit is connected to the n+1th initial control line;
所述第一像素单元包括的第一补偿控制电路与第n行栅线连接，所述第二像素单元包括的第二补偿控制电路与第n+1行栅线连接；The first compensation control circuit included in the first pixel unit is connected to the nth row of gate lines, and the second compensation control circuit included in the second pixel unit is connected to the n+1th row of gate lines;
所述第一像素单元包括的第一数据写入电路与第n写入控制线连接，所述第二像素单元包括的第二数据写入电路与第n+1写入控制线连接；The first data writing circuit included in the first pixel unit is connected to the nth writing control line, and the second data writing circuit included in the second pixel unit is connected to the n+1th writing control line;
所述第一像素单元包括的第一发光控制电路与第2n-1行发光控制线连接，所述第一像素单元包括的第二发光控制电路与第2n行发光控制线连接，所述第二像素单元包括的第三发光控制电路与第2n-1行发光控制线连接，所述第二像素单元包括的第四发光控制电路与第2n行发光控制线连接；The first light emission control circuit included in the first pixel unit is connected to the light emission control line of the 2n-1th row, the second light emission control circuit included in the first pixel unit is connected to the light emission control line of the 2nth row, and the second The third light emission control circuit included in the pixel unit is connected to the light emission control line in the 2n-1th row, and the fourth light emission control circuit included in the second pixel unit is connected to the light emission control line in the 2nth row;
n和m都为正整数。Both n and m are positive integers.
实施时，所述第n写入控制线为第n+1行栅线，所述第n+1行写入控制线为第n+2行栅线；During implementation, the nth write control line is the n+1th row of gate lines, and the n+1th row of write control lines is the n+2th row of gate lines;
n等于1，第n初始控制线为起始信号线，第n+1初始控制线为第n行栅线；或者，n大于1，第n初始控制线为第n-1行栅线，第n+1初始控制线为第n行栅线。n is equal to 1, the nth initial control line is the initial signal line, the n+1th initial control line is the nth row of gate lines; or, n is greater than 1, the nth initial control line is the n-1th row of gate lines, The n+1 initial control line is the nth row of gate lines.
本发明还提供了一种像素驱动方法，应用于上述的像素模组，一显示周期包括依次设置的第一显示子周期和第二显示子周期，所述第一显示子周期包括依次设置的第一初始阶段、第一补偿阶段、第一数据写入阶段、第二数据写入阶段和第一发光阶段，所述第二显示子周期包括依次设置的第二初始阶段、第二补偿阶段、第三数据写入阶段、第四数据写入阶段和第二发光阶段，所述像素驱动方法包括：The present invention also provides a pixel driving method, which is applied to the above-mentioned pixel module. A display cycle includes a first display sub-cycle and a second display sub-cycle arranged in sequence, and the first display sub-cycle includes a second display sub-cycle arranged in sequence. An initial phase, a first compensation phase, a first data writing phase, a second data writing phase and a first light emitting phase, the second display sub-cycle includes the second initial phase, the second compensation phase, the second Three data writing phases, a fourth data writing phase and a second light emitting phase, the pixel driving method includes:
在第一初始阶段和第二初始阶段，初始电压端输出初始电压，第一初始电路在第n初始控制线的控制下，控制将所述初始电压写入第一驱动节点；n为正整数；所述第一驱动节点为第一像素单元中的驱动节点；In the first initial stage and the second initial stage, the initial voltage terminal outputs an initial voltage, and the first initial circuit controls writing the initial voltage into the first driving node under the control of the nth initial control line; n is a positive integer; The first driving node is a driving node in the first pixel unit;
在第一补偿阶段，数据线输出第一数据电压，第一补偿控制电路在第n行栅线的控制下，控制将所述第一数据电压写入第一数据写入节点，并控制所述第一驱动节点和所述第一驱动电路的第二端之间连通；初始电压端输出初始电压，第二初始电路在第n+1初始控制线的控制下，控制将所述初始电压写入第二驱动节点；第一数据写入节点为第一像素单元中的数据写入节点，第二驱动节点为第二像素单元中的驱动节点；In the first compensation stage, the data line outputs the first data voltage, and the first compensation control circuit controls the writing of the first data voltage into the first data writing node under the control of the gate line in the nth row, and controls the The first drive node is connected to the second terminal of the first drive circuit; the initial voltage terminal outputs an initial voltage, and the second initial circuit controls writing the initial voltage into The second driving node; the first data writing node is a data writing node in the first pixel unit, and the second driving node is a driving node in the second pixel unit;
在所述第一数据写入阶段，在第n写入控制线的控制下，第一数据写入电路将第二电压端输出的第二电压V2写入第一数据写入节点；数据线输出第二数据电压，第二补偿控制电路在第n+1行栅线的控制下，控制将第二数据电压写入所述第二数据写入节点，并控制第二驱动节点和第二驱动电路的第二端之间连通；第二数据写入节点为第二像素单元中的数据写入节点；In the first data writing phase, under the control of the nth writing control line, the first data writing circuit writes the second voltage V2 output from the second voltage terminal into the first data writing node; the data line output For the second data voltage, the second compensation control circuit controls the writing of the second data voltage into the second data writing node under the control of the n+1th gate line, and controls the second driving node and the second driving circuit connected between the second ends; the second data writing node is the data writing node in the second pixel unit;
在第二数据写入阶段，在第n+1写入控制线的控制下，第二数据写入电路将第二电压V2写入第二数据写入节点；In the second data writing phase, under the control of the n+1th writing control line, the second data writing circuit writes the second voltage V2 into the second data writing node;
在所述第一发光阶段，第一驱动电路在第一驱动节点的控制下，导通第一电压端与所述第一驱动电路的第二端之间的连接，第一发光控制电路在第2n-1行发光控制线的控制下，控制导通所述第一驱动电路的第二端与第2n-1行第m列发光元件之间的连接，所述第一驱动电路驱动第2n-1行第m列发光元件发光；第二驱动电路在第二驱动节点的控制下，导通第一电压端与第二驱动电路的第二端之间的连接，第三发光控制电路在第2n-1行发光控制线的控制下，控制导通第二驱动电路的第二端与第2n+1行第m列发光元件之间的连接，所述第二驱动电路驱动第2n+1行第m列发光元件发光；In the first light-emitting stage, the first driving circuit conducts the connection between the first voltage terminal and the second terminal of the first driving circuit under the control of the first driving node, and the first light-emitting control circuit Under the control of the 2n-1 row light emitting control line, the connection between the second terminal of the first driving circuit and the light-emitting element in the mth column of the 2n-1th row is controlled, and the first driving circuit drives the 2n-th row. The light-emitting element in the mth column of the first row emits light; the second driving circuit conducts the connection between the first voltage terminal and the second terminal of the second driving circuit under the control of the second driving node, and the third light-emitting control circuit -Under the control of row 1 light emitting control line, the connection between the second terminal of the second driving circuit and the light emitting element in row 2n+1th column m is controlled and turned on, and the second driving circuit drives row 2n+1th row m columns of light-emitting elements emit light;
在所述第二补偿阶段，数据线输出第三数据电压，第一补偿控制电路在第n行栅线的控制下，控制将第三数据电压写入第一数据写入节点，并控制第一驱动节点和所述第一驱动电路的第二端之间连通；初始电压端输出初始电压，第二初始电路在第n+1初始控制线的控制下，控制将初始电压写入第二驱动节点；In the second compensation stage, the data line outputs the third data voltage, and the first compensation control circuit controls the writing of the third data voltage into the first data writing node under the control of the gate line in the nth row, and controls the first The driving node is connected to the second terminal of the first driving circuit; the initial voltage terminal outputs an initial voltage, and the second initial circuit controls writing the initial voltage into the second driving node under the control of the n+1th initial control line ;
在所述第三数据写入阶段，在第n写入控制线的控制下，第二数据写入电路将第二电压V2写入第二数据写入节点，以将第三数据电压写入第一驱动节点；数据线输出第四数据电压，第二补偿控制电路在第n+1行栅线的控制下，控制将第四数据电压写入第二数据写入节点，并控制第二驱动节点和第二驱动电路的第二端之间连通；In the third data writing phase, under the control of the nth writing control line, the second data writing circuit writes the second voltage V2 into the second data writing node, so as to write the third data voltage into the nth a driving node; the data line outputs the fourth data voltage, and the second compensation control circuit controls the writing of the fourth data voltage into the second data writing node under the control of the n+1th gate line, and controls the second driving node communicated with the second end of the second drive circuit;
在第四数据写入阶段，在第n+1写入控制线的控制下，第二数据写入电路将第二电压V2写入第二数据写入节点，以将第四数据电压写入第二驱动节点；In the fourth data writing phase, under the control of the n+1th writing control line, the second data writing circuit writes the second voltage V2 into the second data writing node, so as to write the fourth data voltage into the Two drive nodes;
在所述第二发光阶段，第一驱动电路在第一驱动节点的控制下，导通第一电压端与第一驱动电路的第二端之间的连接，第四发光控制电路在第2n行发光控制线的控制下，控制导通第一驱动电路的第二端与第2n行第m列发光元件之间的连接，第一驱动电路驱动第2n行第m列发光元件发光；第二驱动电路在第二驱动节点的控制下，导通第一电压端与第二驱动电路的第二端之间的连接，第四发光控制电路在第2n行发光控制线的控制下，控制导通第二驱动电路的第二端与第2n+2行第m列发光元件之间的连接，第二驱动电路驱动第2n+2行第m列发光元件发光；In the second light-emitting stage, the first drive circuit conducts the connection between the first voltage terminal and the second terminal of the first drive circuit under the control of the first drive node, and the fourth light-emitting control circuit is in row 2n Under the control of the light emission control line, the connection between the second terminal of the first drive circuit and the light-emitting element in the mth column of the 2nth row is controlled and turned on, and the first drive circuit drives the light-emitting element in the mth column of the 2nth row to emit light; the second drive Under the control of the second drive node, the circuit conducts the connection between the first voltage terminal and the second terminal of the second drive circuit, and the fourth light emission control circuit controls the conduction of the second The connection between the second end of the second driving circuit and the light-emitting element in the mth column of the 2n+2th row, the second driving circuit drives the light-emitting element in the mth column of the 2n+2th row to emit light;
m为正整数。m is a positive integer.
本发明还提供给了一种显示装置，包括N级M列上述的像素模组，N和M都为正整数。The present invention also provides a display device, comprising the above-mentioned pixel modules in N stages and M columns, where N and M are both positive integers.
实施时，第n级第m列像素模组包括的第一像素单元包括第2n-1行第m列发光元件和第2n行第m列发光元件；n和m都为正整数；During implementation, the first pixel unit included in the nth level mth column pixel module includes the 2n-1th row mth column light emitting element and the 2nth row mth column light emitting element; both n and m are positive integers;
第n级第m列像素模组包括的第一像素单元分别与第n初始控制线、第n行栅线、第n写入控制线、第2n-1行发光控制线和第2n行发光控制线连接；The first pixel unit included in the nth level mth column pixel module is respectively connected with the nth initial control line, the nth row gate line, the nth write control line, the 2n-1th row light emission control line and the 2nth row light emission control line line connection;
第n级第m列像素模组包括的第二像素单元包括第2n+1行第m列发光元件和第2n+2行第m列发光元件；The second pixel unit included in the nth level mth column pixel module includes the 2n+1th row mth column light emitting element and the 2n+2th row mth column light emitting element;
第n级第m列像素模组包括的第二像素单元分别与第n+1初始控制线、第n+1行栅线、第n+1写入控制线、所述第2n-1行发光控制线和所述第2n行发光控制线连接。The second pixel unit included in the nth-level and mth-column pixel module is respectively connected to the n+1th initial control line, the n+1th row gate line, the n+1th writing control line, and the 2n-1th row to emit light. The control line is connected to the light emitting control line of the 2nth row.
实施时，所述第n写入控制线为第n+1行栅线，所述第n+1写入控制线为第n+2行栅线；During implementation, the nth writing control line is the n+1th row of gate lines, and the n+1th writing control line is the n+2th row of gate lines;
n等于1，第n初始控制线为起始信号线，第n+1初始控制线为第n行栅线；或者，n大于1，第n初始控制线为第n-1行栅线，第n+1初始控制线为第n行栅线。n is equal to 1, the nth initial control line is the initial signal line, the n+1th initial control line is the nth row of gate lines; or, n is greater than 1, the nth initial control line is the n-1th row of gate lines, The n+1 initial control line is the nth row of gate lines.
与现有技术相比，本发明所述的像素单元、驱动方法、像素模组及其驱动方法和显示装置通过一个像素补偿电路驱动两个发光元件发光，实现像素补偿电路复用，利于实现高PPI。Compared with the prior art, the pixel unit, driving method, pixel module and its driving method, and display device described in the present invention drive two light-emitting elements to emit light through a pixel compensation circuit, realizing multiplexing of pixel compensation circuits, which is beneficial to realize high PPI.
附图说明Description of drawings
图1是本发明实施例所述的像素单元的结构图；FIG. 1 is a structural diagram of a pixel unit according to an embodiment of the present invention;
图2是本发明实施例所述的像素单元的工作时序图；Fig. 2 is a working sequence diagram of the pixel unit described in the embodiment of the present invention;
图3是本发明所述的像素单元的第一具体实施例的电路图；Fig. 3 is a circuit diagram of the first specific embodiment of the pixel unit according to the present invention;
图4是本发明所述的像素单元的第二具体实施例的电路图；Fig. 4 is a circuit diagram of a second specific embodiment of the pixel unit according to the present invention;
图5是本发明所述的像素单元的第二具体实施例的工作时序图；Fig. 5 is a working sequence diagram of the second specific embodiment of the pixel unit according to the present invention;
图6是本发明实施例所述的像素模组的结构框图；6 is a structural block diagram of a pixel module according to an embodiment of the present invention;
图7是本发明所述的像素模组的一具体实施例的电路图；Fig. 7 is a circuit diagram of a specific embodiment of the pixel module according to the present invention;
图8是本发明所述的像素模组的该具体实施例的工作时序图。FIG. 8 is a working sequence diagram of the specific embodiment of the pixel module of the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。The transistors used in all the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, one pole is called the first pole, and the other pole is called the second pole. In actual operation, the first electrode may be a drain, and the second electrode may be a source; or, the first electrode may be a source, and the second electrode may be a drain.
如图1所示，本发明实施例所述的像素单元包括第一发光元件EL1和第二发光元件EL2，所述像素单元还包括：As shown in FIG. 1, the pixel unit according to the embodiment of the present invention includes a first light emitting element EL1 and a second light emitting element EL2, and the pixel unit further includes:
驱动电路11，控制端与驱动节点a连接，第一端与第一电压端VT1连接，用于在所述驱动节点a的控制下，导通或断开所述第一电压端VT1与所述驱动电路11的第二端之间的连接；The driving circuit 11, the control terminal is connected to the driving node a, the first terminal is connected to the first voltage terminal VT1, and is used to turn on or off the first voltage terminal VT1 and the first voltage terminal VT1 under the control of the driving node a. a connection between the second ends of the drive circuit 11;
初始电路12，分别与初始控制线Gate(n-1)、所述驱动节点a和用于输入初始电压Vinit的初始电压端连接，用于在初始控制线Gate(n-1)的控制下，控制将所述初始电压端上的初始电压Vinit写入所述驱动节点；The initial circuit 12 is respectively connected to the initial control line Gate (n-1), the driving node a, and the initial voltage terminal for inputting the initial voltage Vinit, for controlling the initial control line Gate (n-1), controlling to write the initial voltage Vinit on the initial voltage terminal into the driving node;
储能电路13，第一端与所述驱动节点a连接，第二端与数据写入节点b连接；An energy storage circuit 13, the first end of which is connected to the driving node a, and the second end is connected to the data writing node b;
补偿控制电路14，分别与第n行栅线Gate(n)、数据线Data、所述数据写入节点b、所述驱动节点a和所述驱动电路11的第二端连接，用于在所述第n行栅线Gate(n)的控制下，控制将所述数据线Data上的数据电压写入所述数据写入节点b，并控制所述驱动节点a和所述驱动电路11的第二端之间连通；n为正整数；The compensation control circuit 14 is respectively connected to the gate line Gate(n) of the nth row, the data line Data, the data writing node b, the driving node a, and the second end of the driving circuit 11, for Under the control of the gate line Gate(n) of the nth row, the data voltage on the data line Data is controlled to be written into the data writing node b, and the drive node a and the first gate of the drive circuit 11 are controlled. The two ends are connected; n is a positive integer;
数据写入电路15，分别与写入控制线EMn、第二电压端VT2和所述数据写入节点b连接，用于在所述写入控制线EMn的控制下，控制将第二电压端VT2输出的第二电压写入所述数据写入节点b，以相应改变所述驱动节点a的电位；The data writing circuit 15 is respectively connected to the writing control line EMn, the second voltage terminal VT2 and the data writing node b, and is used to control the second voltage terminal VT2 under the control of the writing control line EMn. The output second voltage is written into the data writing node b, so as to change the potential of the driving node a correspondingly;
第一发光控制电路16，分别与所述驱动电路11的第二端、第一发光控制线EM(n_1)和第一发光元件EL1连接，用于在所述第一发光控制线EM(n_1)的控制下，控制导通或断开所述驱动电路11的第二端与所述第一发光元件EL1之间的连接；以及，The first light emission control circuit 16 is respectively connected to the second end of the driving circuit 11, the first light emission control line EM(n_1) and the first light emission element EL1, and is used to control the light emission on the first light emission control line EM(n_1) Under the control of , control the connection between the second end of the driving circuit 11 and the first light emitting element EL1 to be turned on or off; and,
第二发光控制电路17，分别与所述驱动电路11的第二端、第二发光控制线EM(n_2)和第二发光元件EL2连接，用于在所述第二发光控制线EM(n_2)的控制下，控制导通或断开所述驱动电路11的第二端与所述第二发光元件EL2之间的连接。The second light emission control circuit 17 is respectively connected to the second end of the driving circuit 11, the second light emission control line EM(n_2) and the second light emission element EL2, and is used to control the light emission on the second light emission control line EM(n_2) Under the control of , the connection between the second end of the driving circuit 11 and the second light emitting element EL2 is controlled to be turned on or off.
本发明实施例所述的像素单元，通过一个像素补偿电路驱动两个发光元件发光，实现像素补偿电路复用，每两个亚像素的驱动电路由12T2C(12T2C指的是采用12个晶体管和2个电容)减少为7T1C(7T1C指的是采用7个晶体管和1个电容)，实现高PPI AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极管)显示器件。In the pixel unit described in the embodiment of the present invention, one pixel compensation circuit drives two light-emitting elements to emit light to realize the multiplexing of the pixel compensation circuit. capacitor) is reduced to 7T1C (7T1C refers to the use of 7 transistors and 1 capacitor), to achieve a high PPI AMOLED (Active-matrix organic light emitting diode, active matrix organic light emitting diode) display device.
如图2所示，本发明如图1所示的像素单元的实施例在工作时，一显示周期包括依次设置的第一显示子周期Subframe1和第二显示子周期Subframe2，所述第一显示子周期Subframe1包括依次设置的第一初始阶段t1、第一补偿阶段t2、第一数据写入阶段t3和第一发光阶段t4，所述第二显示子周期Subframe2包括依次设置的第二初始阶段t5、第二补偿阶段t6、第二数据写入阶段t7和第二发光阶段t8，As shown in Figure 2, when the embodiment of the pixel unit shown in Figure 1 of the present invention is in operation, a display cycle includes a first display sub-period Subframe1 and a second display sub-period Subframe2 arranged in sequence, the first display sub-period The period Subframe1 includes the first initial stage t1, the first compensation stage t2, the first data writing stage t3 and the first light emitting stage t4 arranged in sequence, and the second display subframe Subframe2 includes the second initial stage t5, The second compensation period t6, the second data writing period t7 and the second light emitting period t8,
在所述第一初始阶段t1和所述第二初始阶段t5，初始电压端输出初始电压Vinit，初始电路12在初始控制线Gate(n-1)的控制下，控制将所述初始电压Vinit写入驱动节点a；In the first initial stage t1 and the second initial stage t5, the initial voltage terminal outputs the initial voltage Vinit, and the initial circuit 12 controls the writing of the initial voltage Vinit under the control of the initial control line Gate(n-1). Enter drive node a;
在所述第一补偿阶段t2和所述第二补偿阶段t6，数据线Data输出数据电压Vdata，补偿控制电路14在第n行栅线Gate(n)的控制下，控制将所述数据电压Vdata写入所述数据写入节点b，并控制所述驱动节点a和驱动电路11的第二端之间连通；n为正整数；In the first compensation phase t2 and the second compensation phase t6, the data line Data outputs the data voltage Vdata, and the compensation control circuit 14 controls the data voltage Vdata under the control of the gate line Gate(n) in the nth row. Writing the data into node b, and controlling the communication between the driving node a and the second end of the driving circuit 11; n is a positive integer;
在所述第一数据写入阶段t3和所述第二数据写入阶段t7，在写入控制线EMn的控制下，数据写入电路15将第二电压端VT2输出的第二电压V2写入数据写入节点b，以将所述数据电压Vdata写入所述驱动节点a；In the first data writing phase t3 and the second data writing phase t7, under the control of the writing control line EMn, the data writing circuit 15 writes the second voltage V2 output from the second voltage terminal VT2 into writing data into node b, so as to write the data voltage Vdata into the driving node a;
在所述第一发光阶段t4，驱动电路11在所述驱动节点a的控制下，导通所述第一电压端VT1与所述驱动电路11的第二端之间的连接，第一发光控制电路16在第一发光控制线EM(n_1)的控制下，控制导通所述驱动电路11的第二端与所述第一发光元件EL1之间的连接，所述驱动电路11驱动第一发光元件EL1发光；In the first light-emitting period t4, the driving circuit 11 conducts the connection between the first voltage terminal VT1 and the second terminal of the driving circuit 11 under the control of the driving node a, and the first light-emitting control Under the control of the first light emission control line EM(n_1), the circuit 16 controls and conducts the connection between the second end of the driving circuit 11 and the first light emitting element EL1, and the driving circuit 11 drives the first light emitting element Element EL1 emits light;
在所述第二发光阶段t8，驱动电路11在所述驱动节点a的控制下，导通所述第一电压端VT1与所述驱动电路11的第二端之间的连接，第二发光控制电路17在第二发光控制线EM(n_2)的控制下，控制导通所述驱动电路11的第二端与所述第二发光元件EL2之间的连接，所述驱动电路11驱动第二发光元件EL2发光。In the second light emitting stage t8, under the control of the driving node a, the driving circuit 11 conducts the connection between the first voltage terminal VT1 and the second terminal of the driving circuit 11, and the second light emitting control Under the control of the second light emission control line EM(n_2), the circuit 17 controls and conducts the connection between the second end of the driving circuit 11 and the second light emitting element EL2, and the driving circuit 11 drives the second light emitting element EL2. Element EL2 emits light.
在优选情况下，所述写入控制线可以为第n+1行栅线，这样可利用现有的栅线进行写入控制，减少控制线数量，从而不需设置用于为写入控制线提供写入控制信号的写入控制电路，利于实现高PPI(Pixels Per Inch，每英寸所拥有的像素数目)。In a preferred case, the writing control line can be the gate line of the n+1th row, so that the existing gate line can be used for writing control, reducing the number of control lines, so that there is no need to set the gate line for writing The writing control circuit that provides the writing control signal is beneficial to realize high PPI (Pixels Per Inch, the number of pixels per inch).
并且，当n大于1时，所述初始控制线为第n-1行栅线；或者，当n等于1时，所述初始控制线为起始信号线。Moreover, when n is greater than 1, the initial control line is the n-1th row of gate lines; or, when n is equal to 1, the initial control line is the initial signal line.
具体的，所述第一发光元件可以为第一有机发光二极管，所述第二发光元件可以为第二有机发光二极管；Specifically, the first light emitting element may be a first organic light emitting diode, and the second light emitting element may be a second organic light emitting diode;
所述驱动电路可以包括驱动晶体管，所述驱动晶体管的栅极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端；The drive circuit may include a drive transistor, the gate of the drive transistor is the control terminal of the drive circuit, the first terminal of the drive transistor is the first terminal of the drive circuit, and the second terminal of the drive transistor is the control terminal of the drive circuit. the second end of the drive circuit;
所述初始电路可以包括初始晶体管，所述初始晶体管的栅极与所述初始控制线连接，所述初始晶体管的第一极与所述驱动节点连接，所述初始晶体管的第二极与所述初始电压端连接；The initial circuit may include an initial transistor, the gate of the initial transistor is connected to the initial control line, the first pole of the initial transistor is connected to the driving node, and the second pole of the initial transistor is connected to the Initial voltage terminal connection;
所述储能电路可以包括存储电容，所述存储电容的第一端与所述驱动节点连接，所述存储电容的第二端与所述数据写入节点连接。The energy storage circuit may include a storage capacitor, a first end of the storage capacitor is connected to the driving node, and a second end of the storage capacitor is connected to the data writing node.
在具体实施时，所述补偿控制电路可以包括第一补偿控制晶体管和第二补偿控制晶体管，其中，In specific implementation, the compensation control circuit may include a first compensation control transistor and a second compensation control transistor, wherein,
所述第一补偿控制晶体管的栅极与所述第n行栅线连接，所述第一补偿控制晶体管的第一极与所述驱动节点连接，所述第一补偿控制晶体管的第二极与驱动电路的第二端连接；The gate of the first compensation control transistor is connected to the gate line of the nth row, the first pole of the first compensation control transistor is connected to the driving node, and the second pole of the first compensation control transistor is connected to The second end of the driving circuit is connected;
所述第二补偿控制晶体管的栅极与所述第n行栅线连接，所述第二补偿控制晶体管的第一极与所述数据写入节点连接，所述第二补偿控制晶体管的第二极与所述数据线连接；The gate of the second compensation control transistor is connected to the gate line of the nth row, the first pole of the second compensation control transistor is connected to the data writing node, and the second electrode of the second compensation control transistor The pole is connected with the data line;
所述数据写入电路包括数据写入晶体管，所述数据写入晶体管的栅极与所述写入控制线连接，所述数据写入晶体管的第一极与所述第二电压端连接，所述数据写入晶体管的第二极与所述数据写入节点连接。The data writing circuit includes a data writing transistor, the gate of the data writing transistor is connected to the writing control line, and the first pole of the data writing transistor is connected to the second voltage terminal, so The second pole of the data writing transistor is connected to the data writing node.
具体的，所述第一发光控制电路可以包括第一发光控制晶体管，所述第一发光控制晶体管的栅极与所述第一发光控制线连接，所述第一发光控制晶体管的第一极与所述驱动电路的第二端连接，所述第一发光控制晶体管的第二极与所述第一发光元件连接；Specifically, the first light emission control circuit may include a first light emission control transistor, the gate of the first light emission control transistor is connected to the first light emission control line, the first electrode of the first light emission control transistor is connected to the The second end of the driving circuit is connected, and the second pole of the first light-emitting control transistor is connected to the first light-emitting element;
所述第二发光控制电路包括第二发光控制晶体管，所述第二发光控制晶体管的栅极与所述第二发光控制线连接，所述第二发光控制晶体管的第一极与所述驱动电路的第二端连接，所述第二发光控制晶体管的第二极与所述第二发光元件连接。The second light emission control circuit includes a second light emission control transistor, the gate of the second light emission control transistor is connected to the second light emission control line, and the first electrode of the second light emission control transistor is connected to the drive circuit The second end of the second light emission control transistor is connected to the second light emitting element.
下面通过一具体实施例来说明本发明所述的像素单元。The pixel unit of the present invention is described below through a specific embodiment.
如图3所示，本发明所述的像素单元的第一具体实施例包括第一有机发光二极管OLED1、第二有机发光二极管OLED2、驱动电路、初始电路、储能电路、补偿控制电路、数据写入电路、第一发光控制电路和第二发光控制电路，其中，As shown in Figure 3, the first specific embodiment of the pixel unit of the present invention includes a first organic light emitting diode OLED1, a second organic light emitting diode OLED2, a driving circuit, an initial circuit, an energy storage circuit, a compensation control circuit, a data write input circuit, the first lighting control circuit and the second lighting control circuit, wherein,
所述驱动电路包括驱动晶体管T3，所述初始电路包括初始晶体管T1，所述储能电路包括存储电容Cst，所述补偿控制电路包括第一补偿控制晶体管T2和第二补偿控制晶体管T4，所述数据写入电路包括数据写入晶体管T5，所述第一发光控制电路包括第一发光控制晶体管T6，所述第二发光控制电路包括第二发光控制晶体管T7；The drive circuit includes a drive transistor T3, the initial circuit includes an initial transistor T1, the energy storage circuit includes a storage capacitor Cst, the compensation control circuit includes a first compensation control transistor T2 and a second compensation control transistor T4, the The data writing circuit includes a data writing transistor T5, the first light emitting control circuit includes a first light emitting control transistor T6, and the second light emitting control circuit includes a second light emitting control transistor T7;
T3的栅极与驱动节点a连接，T3的源极与用于输入高电压Vdd的高电压输入端ELVDD连接；The gate of T3 is connected to the driving node a, and the source of T3 is connected to the high voltage input terminal ELVDD for inputting the high voltage Vdd;
T2的栅极与第n行栅线Gate(n)连接，T2的源极与所述驱动节点a连接，T2的漏极与T3的漏极连接；The gate of T2 is connected to the gate line Gate(n) of the nth row, the source of T2 is connected to the driving node a, and the drain of T2 is connected to the drain of T3;
T4的栅极与Gate(n)连接，T4的源极与所述数据写入节点b连接，T4的漏极与数据线Data连接；The gate of T4 is connected to Gate(n), the source of T4 is connected to the data writing node b, and the drain of T4 is connected to the data line Data;
Cst的第一端与所述驱动节点a连接，Cst的第二端与数据写入节点b连接；The first end of Cst is connected to the driving node a, and the second end of Cst is connected to the data writing node b;
T1的栅极与初始控制线Gate(n-1)连接，T1的源极与所述驱动节点a连接，T1的漏极接入初始电压Vinit；The gate of T1 is connected to the initial control line Gate(n-1), the source of T1 is connected to the driving node a, and the drain of T1 is connected to the initial voltage Vinit;
T5的栅极与写入控制线EMn连接，T5的源极与高电压输入端ELVDD连接，T5的漏极与所述数据写入节点b连接；The gate of T5 is connected to the writing control line EMn, the source of T5 is connected to the high voltage input terminal ELVDD, and the drain of T5 is connected to the data writing node b;
T6的栅极与第一发光控制线EM(n_1)连接，T6的源极与T3的源极连接，T6的漏极与OLED1的阳极连接；OLED1的阴极与用于输入低电压Vss的低电压输入端ELVSS连接；The gate of T6 is connected to the first light emission control line EM (n_1), the source of T6 is connected to the source of T3, the drain of T6 is connected to the anode of OLED1; the cathode of OLED1 is connected to the low voltage for inputting the low voltage Vss input ELVSS connection;
T7的栅极与第二发光控制线EM(n_2)连接，T7的源极与T3的源极连接，T7的漏极与OLED2的阳极连接；OLED2的阴极与用于输入低电压Vss的低电压输入端ELVSS连接；The gate of T7 is connected to the second light emission control line EM (n_2), the source of T7 is connected to the source of T3, the drain of T7 is connected to the anode of OLED2; the cathode of OLED2 is connected to the low voltage for inputting the low voltage Vss input ELVSS connection;
n为正整数。n is a positive integer.
在图3所示的像素单元的第一具体实施例中，所有的晶体管都为p型晶体管，但不以此为限；在实际操作时，如上晶体管也可以被替换为n型晶体管。In the first specific embodiment of the pixel unit shown in FIG. 3 , all transistors are p-type transistors, but not limited thereto; in actual operation, the above transistors can also be replaced by n-type transistors.
如图2所示，本发明如图3所示的像素单元的第一具体实施例在工作时，一显示周期包括依次设置的第一显示子周期Subframe1和第二显示子周期Subframe2，所述第一显示子周期Subframe1包括依次设置的第一初始阶段t1、第一补偿阶段t2、第一数据写入阶段t3和第一发光阶段t4，所述第二显示子周期Subframe2包括依次设置的第二初始阶段t5、第二补偿阶段t6、第二数据写入阶段t7和第二发光阶段t8，As shown in Figure 2, when the first specific embodiment of the pixel unit shown in Figure 3 of the present invention is in operation, a display cycle includes a first display sub-period Subframe1 and a second display sub-period Subframe2 arranged in sequence, the first display sub-period Subframe2 A display sub-period Subframe1 includes the first initial stage t1, the first compensation stage t2, the first data writing stage t3 and the first light-emitting stage t4 arranged in sequence, and the second display sub-cycle Subframe2 includes the second initial stage t4 arranged in sequence. stage t5, second compensation stage t6, second data writing stage t7 and second light emitting stage t8,
在第一初始阶段t1，Gate(n)、EMn、EM(n_1)和EM(n_2)都输出高电平，Gate(n-1)输出低电平，T1打开，将所述驱动节点a的电位复位为Vinit；In the first initial stage t1, Gate(n), EMn, EM(n_1) and EM(n_2) all output high level, Gate(n-1) outputs low level, T1 is turned on, and the Potential reset to Vinit;
在第一补偿阶段t2，Data输出数据电压Vdata，Gate(n-1)、EMn、EM(n_1)和EM(n_2)输出高电平，Gate(n)输出低电平，T2和T4都打开，以将Vdata写入数据写入节点b，并使得T3的栅极与T3的漏极连接，T3打开，此时所述驱动节点a的电位为Vdd+Vth；Vth为T3的阈值电压；In the first compensation stage t2, Data outputs data voltage Vdata, Gate(n-1), EMn, EM(n_1) and EM(n_2) output high level, Gate(n) outputs low level, T2 and T4 are both open , so as to write Vdata into data into node b, and connect the gate of T3 to the drain of T3, and T3 is turned on. At this time, the potential of the driving node a is Vdd+Vth; Vth is the threshold voltage of T3;
在第一数据写入阶段t3，EMn输出低电平，Gate(n-1)、Gate(n)、EM(n_1)和EM(n_2)输出高电平，T5打开，以将Vdd写入所述数据写入节点b，从而使得所述驱动节点a的电位变为2Vdd+Vth-Vdata；In the first data writing phase t3, EMn outputs a low level, Gate(n-1), Gate(n), EM(n_1) and EM(n_2) output a high level, and T5 is turned on to write Vdd into all Writing the data into node b, so that the potential of the driving node a becomes 2Vdd+Vth-Vdata;
在第一发光阶段t4，EM(n_1)和EMn输出低电平，Gate(n-1)、Gate(n)和EM(n_2)都输出高电平，T5打开，T3和T6打开，以驱动OLED1发光，OLED2不发光；In the first light-emitting phase t4, EM(n_1) and EMn output low level, Gate(n-1), Gate(n) and EM(n_2) all output high level, T5 is turned on, T3 and T6 are turned on to drive OLED1 emits light, OLED2 does not emit light;
在第二初始阶段t5，Gate(n)、EMn、EM(n_1)和EM(n_2)都输出高电平，Gate(n-1)输出低电平，T1打开，将所述驱动节点a的电位复位为Vinit；In the second initial stage t5, Gate(n), EMn, EM(n_1) and EM(n_2) all output a high level, Gate(n-1) outputs a low level, T1 is turned on, and the drive node a Potential reset to Vinit;
在第二补偿阶段t6，Data输出数据电压Vdata，Gate(n-1)、EMn、EM(n_1)和EM(n_2)输出高电平，Gate(n)输出低电平，T2和T4都打开，以将Vdata写入数据写入节点b，并使得T3的栅极与T3的漏极连接，T3打开，此时所述驱动节点a的电位为Vdd+Vth；Vth为T3的阈值电压；In the second compensation stage t6, Data outputs data voltage Vdata, Gate(n-1), EMn, EM(n_1) and EM(n_2) output high level, Gate(n) outputs low level, T2 and T4 are both open , so as to write Vdata into data into node b, and connect the gate of T3 to the drain of T3, and T3 is turned on. At this time, the potential of the driving node a is Vdd+Vth; Vth is the threshold voltage of T3;
在第二数据写入阶段t7，EMn输出低电平，Gate(n-1)、Gate(n)、EM(n_1)和EM(n_2)输出高电平，T5打开，以将Vdd写入所述数据写入节点b，从而使得所述驱动节点a的电位变为2Vdd+Vth-Vdata；In the second data writing phase t7, EMn outputs a low level, Gate(n-1), Gate(n), EM(n_1) and EM(n_2) output a high level, and T5 is turned on to write Vdd into all Writing the data into node b, so that the potential of the driving node a becomes 2Vdd+Vth-Vdata;
在第二发光阶段t8，EM(n_2)和EMn输出低电平，Gate(n-1)、Gate(n)和EM(n_1)都输出高电平，T5打开，T3和T7打开，以驱动OLED2发光，OLED1不发光。In the second light-emitting phase t8, EM(n_2) and EMn output low level, Gate(n-1), Gate(n) and EM(n_1) all output high level, T5 is turned on, T3 and T7 are turned on to drive OLED2 emits light, OLED1 does not emit light.
如图4所示，本发明所述的像素单元的第二具体实施例包括第一有机发光二极管OLED1、第二有机发光二极管OLED2、驱动电路、初始电路、储能电路、补偿控制电路、数据写入电路、第一发光控制电路和第二发光控制电路，其中，As shown in Figure 4, the second specific embodiment of the pixel unit of the present invention includes a first organic light emitting diode OLED1, a second organic light emitting diode OLED2, a driving circuit, an initial circuit, an energy storage circuit, a compensation control circuit, a data write input circuit, the first lighting control circuit and the second lighting control circuit, wherein,
所述驱动电路包括驱动晶体管T3，所述初始电路包括初始晶体管T1，所述储能电路包括存储电容Cst，所述补偿控制电路包括第一补偿控制晶体管T2和第二补偿控制晶体管T4，所述数据写入电路包括数据写入晶体管T5，所述第一发光控制电路包括第一发光控制晶体管T6，所述第二发光控制电路包括第二发光控制晶体管T7；The drive circuit includes a drive transistor T3, the initial circuit includes an initial transistor T1, the energy storage circuit includes a storage capacitor Cst, the compensation control circuit includes a first compensation control transistor T2 and a second compensation control transistor T4, the The data writing circuit includes a data writing transistor T5, the first light emitting control circuit includes a first light emitting control transistor T6, and the second light emitting control circuit includes a second light emitting control transistor T7;
T3的栅极与驱动节点a连接，T3的源极与用于输入高电压Vdd的高电压输入端ELVDD连接；The gate of T3 is connected to the driving node a, and the source of T3 is connected to the high voltage input terminal ELVDD for inputting the high voltage Vdd;
T2的栅极与第n行栅线Gate(n)连接，T2的源极与所述驱动节点a连接，T2的漏极与T3的漏极连接；The gate of T2 is connected to the gate line Gate(n) of the nth row, the source of T2 is connected to the driving node a, and the drain of T2 is connected to the drain of T3;
T4的栅极与Gate(n)连接，T4的源极与所述数据写入节点b连接，T4的漏极与数据线Data连接；The gate of T4 is connected to Gate(n), the source of T4 is connected to the data writing node b, and the drain of T4 is connected to the data line Data;
Cst的第一端与所述驱动节点a连接，Cst的第二端与数据写入节点b连接；The first end of Cst is connected to the driving node a, and the second end of Cst is connected to the data writing node b;
T1的栅极与初始控制线Gate(n-1)连接，T1的源极与所述驱动节点a连接，T1的漏极接入初始电压Vinit；The gate of T1 is connected to the initial control line Gate(n-1), the source of T1 is connected to the driving node a, and the drain of T1 is connected to the initial voltage Vinit;
T5的栅极与第n+1行栅线Gate(n+1)连接，T5的源极与高电压输入端ELVDD连接，T5的漏极与所述数据写入节点b连接；The gate of T5 is connected to the n+1th gate line Gate(n+1), the source of T5 is connected to the high voltage input terminal ELVDD, and the drain of T5 is connected to the data writing node b;
T6的栅极与第一发光控制线EM(n_1)连接，T6的源极与T3的源极连接，T6的漏极与OLED1的阳极连接；OLED1的阴极与用于输入低电压Vss的低电压输入端ELVSS连接；The gate of T6 is connected to the first light emission control line EM (n_1), the source of T6 is connected to the source of T3, the drain of T6 is connected to the anode of OLED1; the cathode of OLED1 is connected to the low voltage for inputting the low voltage Vss input ELVSS connection;
T7的栅极与第二发光控制线EM(n_2)连接，T7的源极与T3的源极连接，T7的漏极与OLED2的阳极连接；OLED2的阴极与用于输入低电压Vss的低电压输入端ELVSS连接；The gate of T7 is connected to the second light emission control line EM (n_2), the source of T7 is connected to the source of T3, the drain of T7 is connected to the anode of OLED2; the cathode of OLED2 is connected to the low voltage for inputting the low voltage Vss input ELVSS connection;
n为正整数。n is a positive integer.
在图4所示的像素单元的第二具体实施例中，所有的晶体管都为p型晶体管，但不以此为限；在实际操作时，如上晶体管也可以被替换为n型晶体管。In the second specific embodiment of the pixel unit shown in FIG. 4 , all transistors are p-type transistors, but not limited thereto; in actual operation, the above transistors can also be replaced by n-type transistors.
本发明如图4所示的像素单元的第二具体实施例与本发明如图3所示的像素单元的第一具体实施例的差别仅在于：T5的栅极与Gate(n+1)连接，从而不需设置EMn，并不需设置用于为写入控制线提供写入控制信号的写入控制电路，利于实现高PPI(Pixels PerInch，每英寸所拥有的像素数目)。The difference between the second specific embodiment of the pixel unit shown in Figure 4 of the present invention and the first specific embodiment of the pixel unit shown in Figure 3 of the present invention is only that the gate of T5 is connected to Gate (n+1) , so that there is no need to set EMn, and there is no need to set a write control circuit for providing a write control signal for the write control line, which is beneficial to realize high PPI (Pixels PerInch, the number of pixels per inch).
如图5所示，本发明如图4所示的像素单元的第二具体实施例在工作时，一显示周期包括依次设置的第一显示子周期Subframe1和第二显示子周期Subframe2，所述第一显示子周期Subframe1包括依次设置的第一初始阶段t1、第一补偿阶段t2、第一数据写入阶段t3和第一发光阶段t4，所述第二显示子周期Subframe2包括依次设置的第二初始阶段t5、第二补偿阶段t6、第二数据写入阶段t7和第二发光阶段t8，As shown in Figure 5, when the second specific embodiment of the pixel unit shown in Figure 4 of the present invention is in operation, a display cycle includes a first display sub-period Subframe1 and a second display sub-period Subframe2 arranged in sequence, the first display sub-period Subframe2 A display sub-period Subframe1 includes the first initial stage t1, the first compensation stage t2, the first data writing stage t3 and the first light-emitting stage t4 arranged in sequence, and the second display sub-cycle Subframe2 includes the second initial stage t4 arranged in sequence. stage t5, second compensation stage t6, second data writing stage t7 and second light emitting stage t8,
在第一初始阶段t1，Gate(n)、Gate(n+1)、EM(n_1)和EM(n_2)都输出高电平，Gate(n-1)输出低电平，T1打开，将所述驱动节点a的电位复位为Vinit；In the first initial stage t1, Gate(n), Gate(n+1), EM(n_1) and EM(n_2) all output high level, Gate(n-1) outputs low level, T1 is turned on, and all The potential of the driving node a is reset to Vinit;
在第一补偿阶段t2，Data输出数据电压Vdata，Gate(n-1)、Gate(n+1)、EM(n_1)和EM(n_2)输出高电平，Gate(n)输出低电平，T2和T4都打开，以将Vdata写入数据写入节点b，并使得T3的栅极与T3的漏极连接，T3打开，此时所述驱动节点a的电位为Vdd+Vth；Vth为T3的阈值电压；In the first compensation stage t2, Data outputs data voltage Vdata, Gate(n-1), Gate(n+1), EM(n_1) and EM(n_2) output high level, and Gate(n) outputs low level, Both T2 and T4 are turned on to write Vdata into node b, and connect the gate of T3 to the drain of T3, and T3 is turned on. At this time, the potential of the driving node a is Vdd+Vth; Vth is T3 threshold voltage;
在第一数据写入阶段t3，Gate(n+1)输出低电平，Gate(n-1)、Gate(n)、EM(n_1)和EM(n_2)输出高电平，T5打开，以将Vdd写入所述数据写入节点b，从而使得所述驱动节点a的电位变为2Vdd+Vth-Vdata；In the first data writing stage t3, Gate(n+1) outputs low level, Gate(n-1), Gate(n), EM(n_1) and EM(n_2) output high level, and T5 is turned on to writing Vdd into the data writing node b, so that the potential of the driving node a becomes 2Vdd+Vth-Vdata;
在第一发光阶段t4，EM(n_1)输出低电平，Gate(n-1)、Gate(n)、Gate(n+1)和EM(n_2)都输出高电平，T5打开，T3和T6打开，以驱动OLED1发光，OLED2不发光；In the first light-emitting phase t4, EM(n_1) outputs low level, Gate(n-1), Gate(n), Gate(n+1) and EM(n_2) all output high level, T5 is turned on, T3 and T6 is turned on to drive OLED1 to emit light, while OLED2 does not emit light;
在第二初始阶段t5，Gate(n)、Gate(n+1)、EM(n_1)和EM(n_2)都输出高电平，Gate(n-1)输出低电平，T1打开，将所述驱动节点a的电位复位为Vinit；In the second initial stage t5, Gate(n), Gate(n+1), EM(n_1) and EM(n_2) all output high level, Gate(n-1) outputs low level, T1 is turned on, and all The potential of the driving node a is reset to Vinit;
在第二补偿阶段t6，Data输出数据电压Vdata，Gate(n-1)、Gate(n+1)、EM(n_1)和EM(n_2)输出高电平，Gate(n)输出低电平，T2和T4都打开，以将Vdata写入数据写入节点b，并使得T3的栅极与T3的漏极连接，T3打开，此时所述驱动节点a的电位为Vdd+Vth；Vth为T3的阈值电压；In the second compensation stage t6, Data outputs data voltage Vdata, Gate(n-1), Gate(n+1), EM(n_1) and EM(n_2) output high level, and Gate(n) outputs low level, Both T2 and T4 are turned on to write Vdata into node b, and connect the gate of T3 to the drain of T3, and T3 is turned on. At this time, the potential of the driving node a is Vdd+Vth; Vth is T3 threshold voltage;
在第二数据写入阶段t7，Gate(n+1)输出低电平，Gate(n-1)、Gate(n)、EM(n_1)和EM(n_2)输出高电平，T5打开，以将Vdd写入所述数据写入节点b，从而使得所述驱动节点a的电位变为2Vdd+Vth-Vdata；In the second data writing phase t7, Gate(n+1) outputs low level, Gate(n-1), Gate(n), EM(n_1) and EM(n_2) output high level, and T5 is turned on to writing Vdd into the data writing node b, so that the potential of the driving node a becomes 2Vdd+Vth-Vdata;
在第二发光阶段t8，EM(n_2)输出低电平，Gate(n-1)、Gate(n)、Gate(n+1)和EM(n_1)都输出高电平，T5打开，T3和T7打开，以驱动OLED2发光，OLED1不发光。In the second lighting stage t8, EM(n_2) outputs low level, Gate(n-1), Gate(n), Gate(n+1) and EM(n_1) all output high level, T5 is turned on, T3 and T7 is turned on to drive OLED2 to emit light, while OLED1 does not emit light.
本发明实施例所述的像素驱动方法，应用于上述的像素单元，一显示周期包括依次设置的第一显示子周期和第二显示子周期，所述第一显示子周期包括依次设置的第一初始阶段、第一补偿阶段、第一数据写入阶段和第一发光阶段，所述第二显示子周期包括依次设置的第二初始阶段、第二补偿阶段、第二数据写入阶段和第二发光阶段，所述像素驱动方法包括：The pixel driving method described in the embodiment of the present invention is applied to the above-mentioned pixel unit. A display period includes a first display sub-period and a second display sub-period arranged in sequence, and the first display sub-period includes a first display sub-period arranged in sequence. an initial stage, a first compensation stage, a first data writing stage, and a first light-emitting stage, and the second display sub-cycle includes a second initial stage, a second compensation stage, a second data writing stage, and a second In the light emitting stage, the pixel driving method includes:
在所述第一初始阶段和所述第二初始阶段，初始电压端输出初始电压，初始电路在初始控制线的控制下，控制将所述初始电压写入驱动节点；In the first initial stage and the second initial stage, the initial voltage terminal outputs an initial voltage, and the initial circuit controls writing the initial voltage into the driving node under the control of an initial control line;
在所述第一补偿阶段和所述第二补偿阶段，数据线输出数据电压，补偿控制电路在第n行栅线的控制下，控制将所述数据电压写入所述数据写入节点，并控制所述驱动节点和驱动电路的第二端之间连通；n为正整数；In the first compensation stage and the second compensation stage, the data line outputs a data voltage, and the compensation control circuit controls the writing of the data voltage into the data writing node under the control of the gate line in the nth row, and Controlling the communication between the driving node and the second end of the driving circuit; n is a positive integer;
在所述第一数据写入阶段和所述第二数据写入阶段，在写入控制线的控制下，数据写入电路将第二电压端输出的第二电压V2写入数据写入节点，以将所述数据电压写入所述驱动节点；In the first data writing phase and the second data writing phase, under the control of the writing control line, the data writing circuit writes the second voltage V2 output from the second voltage terminal into the data writing node, to write the data voltage into the driving node;
在所述第一发光阶段，驱动电路在所述驱动节点的控制下，导通所述第一电压端与所述驱动电路的第二端之间的连接，第一发光控制电路在第一发光控制线的控制下，控制导通所述驱动电路的第二端与所述第一发光元件之间的连接，所述驱动电路驱动第一发光元件发光；In the first light-emitting stage, the driving circuit conducts the connection between the first voltage terminal and the second terminal of the driving circuit under the control of the driving node, and the first light-emitting control circuit Under the control of the control line, the connection between the second end of the driving circuit and the first light-emitting element is controlled and turned on, and the driving circuit drives the first light-emitting element to emit light;
在所述第二发光阶段，驱动电路在所述驱动节点的控制下，导通所述第一电压端与所述驱动电路的第二端之间的连接，第二发光控制电路在第二发光控制线的控制下，控制导通所述驱动电路的第二端与所述第二发光元件之间的连接，所述驱动电路驱动第二发光元件发光。In the second light-emitting stage, the driving circuit conducts the connection between the first voltage terminal and the second terminal of the driving circuit under the control of the driving node, and the second light-emitting control circuit Under the control of the control line, the connection between the second end of the driving circuit and the second light emitting element is controlled to be turned on, and the driving circuit drives the second light emitting element to emit light.
本发明实施例所述的像素驱动方法应用于的像素单元包括两个发光元件，本发明实施例所述的像素驱动方法分时驱动所述两个发光元件发光，从而使得像素单元可以由12T2C结构简化为7T1C结构，实现高PPI。The pixel unit to which the pixel driving method described in the embodiment of the present invention is applied includes two light-emitting elements, and the pixel driving method described in the embodiment of the present invention drives the two light-emitting elements to emit light in time, so that the pixel unit can be composed of a 12T2C structure Simplified to 7T1C structure to achieve high PPI.
具体的，本发明所述的像素驱动方法还包括：Specifically, the pixel driving method described in the present invention also includes:
在所述第一补偿阶段和所述第二补偿阶段，所述驱动电路导通其第一端和所述第二端之间的连接，直至所述驱动节点的电位变为V1+Vth，V1为第一电压端输出的第一电压，Vth为所述驱动电路包括的驱动晶体管的阈值电压；In the first compensation phase and the second compensation phase, the driving circuit conducts the connection between its first terminal and the second terminal until the potential of the driving node becomes V1+Vth, V1 is the first voltage output by the first voltage terminal, and Vth is the threshold voltage of the driving transistor included in the driving circuit;
在所述第一数据写入阶段和所述第二数据写入阶段，控制驱动节点的电位变为V1+V2-Vdata+Vth，从而使得在发光阶段驱动晶体管的栅源电压可以补偿所述驱动晶体管的阈值电压。In the first data writing phase and the second data writing phase, the potential of the control driving node becomes V1+V2-Vdata+Vth, so that the gate-source voltage of the driving transistor in the light-emitting phase can compensate the driving threshold voltage of the transistor.
本发明实施例所述的像素模组，包括两个上述的像素单元；The pixel module described in the embodiment of the present invention includes two above-mentioned pixel units;
第一像素单元包括第2n-1行第m列发光元件和第2n行第m列发光元件，第二像素单元包括第2n+1行第m列发光元件和第2n+2行第m列发光元件；The first pixel unit includes light-emitting elements in row 2n-1, column m, and row 2n, column m, and the second pixel unit includes light-emitting elements in row 2n+1, column m, and row 2n+2, column m. element;
所述第一像素单元包括的第一初始电路与第n初始控制线连接，所述第二像素单元包括的第二初始电路与第n+1初始控制线连接；The first initial circuit included in the first pixel unit is connected to the nth initial control line, and the second initial circuit included in the second pixel unit is connected to the n+1th initial control line;
所述第一像素单元包括的第一补偿控制电路与第n行栅线连接，所述第二像素单元包括的第二补偿控制电路与第n+1行栅线连接；The first compensation control circuit included in the first pixel unit is connected to the nth row of gate lines, and the second compensation control circuit included in the second pixel unit is connected to the n+1th row of gate lines;
所述第一像素单元包括的第一数据写入电路与第n写入控制线连接，所述第二像素单元包括的第二数据写入电路与第n+1写入控制线连接；The first data writing circuit included in the first pixel unit is connected to the nth writing control line, and the second data writing circuit included in the second pixel unit is connected to the n+1th writing control line;
所述第一像素单元包括的第一发光控制电路与第2n-1行发光控制线连接，所述第一像素单元包括的第二发光控制电路与第2n行发光控制线连接，所述第二像素单元包括的第三发光控制电路与第2n-1行发光控制线连接，所述第二像素单元包括的第四发光控制电路与第2n行发光控制线连接；The first light emission control circuit included in the first pixel unit is connected to the light emission control line of the 2n-1th row, the second light emission control circuit included in the first pixel unit is connected to the light emission control line of the 2nth row, and the second The third light emission control circuit included in the pixel unit is connected to the light emission control line in the 2n-1th row, and the fourth light emission control circuit included in the second pixel unit is connected to the light emission control line in the 2nth row;
n和m都为正整数。Both n and m are positive integers.
在具体实施时，本发明实施例所述的像素模组包括两个本发明实施例所述的像素单元，第一像素单元包括第2n-1行第m列发光元件和第2n行第m列发光元件，第二像素单元包括第2n+1行第m列发光元件和第2n+2行第m列发光元件，第一像素单元分别与第2n-1行发光控制线EM(2n-1)和第2n行发光控制线EM(2n)连接，第二像素单元也分别与第2n-1行发光控制线EM(2n-1)和第2n行发光控制线EM(2n)连接，也即，In specific implementation, the pixel module described in the embodiment of the present invention includes two pixel units described in the embodiment of the present invention, and the first pixel unit includes light-emitting elements in the mth column of the 2n-1th row and the mth column of the 2nth row The light-emitting element, the second pixel unit includes a light-emitting element in the mth column of the 2n+1 row and the m-th column light-emitting element in the 2n+2th row, and the first pixel unit is connected to the light emitting control line EM(2n-1) in the 2n-1 row respectively. It is connected to the light emission control line EM(2n) in the 2nth row, and the second pixel unit is also connected to the light emission control line EM(2n-1) in the 2n-1th row and the light emission control line EM(2n) in the 2nth row, that is,
第2n-1行第m列发光元件和第2n行第m列发光元件共用第一像素单元包括的第一像素驱动单元，第2n+1行第m列发光元件和第2n+2行第m列发光元件共用第二像素的单元包括的第二像素驱动单元，并位于相邻行同一列的两像素单元共用两条发光控制线：第2n-1行发光控制线和第2n行发光控制线。The m-th column light-emitting element in the 2n-1 row and the m-th column light-emitting element in the 2n-th row share the first pixel driving unit included in the first pixel unit, and the m-th column light-emitting element in the 2n+1 row and the m-th row in the 2n+2 row The column light-emitting elements share the second pixel driving unit included in the unit of the second pixel, and two pixel units located in the same column in adjacent rows share two light-emitting control lines: the light-emitting control line of the 2n-1th row and the light-emitting control line of the 2nth row .
在具体实施时，所述第一像素单元可以为第n级第m列像素单元，所述第二像素单元可以为第n+1级第m列像素单元。In a specific implementation, the first pixel unit may be a pixel unit in the mth column of the nth level, and the second pixel unit may be a pixel unit in the mth column of the n+1th level.
在优选情况下，所述第n写入控制线为第n+1行栅线，所述第n+1行写入控制线为第n+2行栅线。In a preferred situation, the nth writing control line is the gate line of the n+1th row, and the writing control line of the n+1th row is the gate line of the n+2th row.
具体的，n等于1，第n初始控制线为起始信号线，第n+1初始控制线为第n行栅线；或者，n大于1，第n初始控制线为第n-1行栅线，第n+1初始控制线为第n行栅线。Specifically, n is equal to 1, the nth initial control line is the initial signal line, and the n+1th initial control line is the nth row of gate lines; or, n is greater than 1, the nth initial control line is the n-1th row of gate lines line, the n+1th initial control line is the nth row of gate lines.
如图6所示，第一像素单元Pixeln，m分别与第2n-1行发光控制线EM(2n-1)和第2n行发光控制线EM(2n)连接，第二像素单元Pixeln+1,m分别与第2n-1行发光控制线EM(2n-1)和第2n行发光控制线EM(2n)连接；As shown in FIG. 6, the first pixel unit Pixeln, m is respectively connected to the 2n-th row of light emission control line EM (2n-1) and the 2nth row of light emission control line EM (2n), and the second pixel unit Pixeln+1, m is respectively connected to the light emission control line EM(2n-1) of row 2n-1 and the light emission control line EM(2n) of row 2n;
第一像素单元Pixeln,m与第n行栅线Gate(n)连接；The first pixel unit Pixeln,m is connected to the gate line Gate(n) of the nth row;
第二像素单元Pixeln+1,m与第n+1行栅线Gate(n+1)连接；The second pixel unit Pixeln+1,m is connected to the gate line Gate(n+1) of the n+1th row;
所述第一像素单元Pixeln,m与第n写入控制线EMn连接，所述第二像素单元Pixel1,m与第n+1写入控制线EMn+1连接。The first pixel unit Pixeln,m is connected to the nth writing control line EMn, and the second pixel unit Pixel1,m is connected to the n+1th writing control line EMn+1.
本发明实施例所述的像素模组在工作时，一显示周期包括依次设置的第一显示子周期和第二显示子周期，所述第一显示子周期包括依次设置的第一初始阶段、第一补偿阶段、第一数据写入阶段、第二数据写入阶段和第一发光阶段，所述第二显示子周期包括依次设置的第二初始阶段、第二补偿阶段、第三数据写入阶段、第四数据写入阶段和第二发光阶段，When the pixel module described in the embodiment of the present invention is working, a display cycle includes a first display sub-cycle and a second display sub-cycle arranged in sequence, and the first display sub-cycle includes a first initial stage, a second display sub-cycle arranged in sequence A compensation phase, a first data writing phase, a second data writing phase, and a first light-emitting phase, the second display sub-cycle includes a second initial phase, a second compensation phase, and a third data writing phase arranged in sequence , the fourth data writing phase and the second light emitting phase,
在第一初始阶段和第二初始阶段，初始电压端输出初始电压，第一初始电路在第n初始控制线的控制下，控制将所述初始电压写入第一驱动节点；n为正整数；所述第一驱动节点为第一像素单元中的驱动节点；In the first initial stage and the second initial stage, the initial voltage terminal outputs an initial voltage, and the first initial circuit controls writing the initial voltage into the first driving node under the control of the nth initial control line; n is a positive integer; The first driving node is a driving node in the first pixel unit;
在第一补偿阶段，数据线输出第一数据电压，第一补偿控制电路在第n行栅线的控制下，控制将所述第一数据电压写入第一数据写入节点，并控制所述第一驱动节点和所述第一驱动电路的第二端之间连通；初始电压端输出初始电压，第二初始电路在第n+1初始控制线的控制下，控制将所述初始电压写入第二驱动节点；第一数据写入节点为第一像素单元中的数据写入节点，第二驱动节点为第二像素单元中的驱动节点；In the first compensation stage, the data line outputs the first data voltage, and the first compensation control circuit controls the writing of the first data voltage into the first data writing node under the control of the gate line in the nth row, and controls the The first drive node is connected to the second terminal of the first drive circuit; the initial voltage terminal outputs an initial voltage, and the second initial circuit controls writing the initial voltage into The second driving node; the first data writing node is a data writing node in the first pixel unit, and the second driving node is a driving node in the second pixel unit;
在所述第一数据写入阶段，在第n写入控制线的控制下，第一数据写入电路将第二电压端输出的第二电压V2写入第一数据写入节点；数据线输出第二数据电压，第二补偿控制电路在第n+1行栅线的控制下，控制将第二数据电压写入所述第二数据写入节点，并控制第二驱动节点和第二驱动电路的第二端之间连通；第二数据写入节点为第二像素单元中的数据写入节点；In the first data writing phase, under the control of the nth writing control line, the first data writing circuit writes the second voltage V2 output from the second voltage terminal into the first data writing node; the data line output For the second data voltage, the second compensation control circuit controls the writing of the second data voltage into the second data writing node under the control of the n+1th gate line, and controls the second driving node and the second driving circuit connected between the second ends; the second data writing node is the data writing node in the second pixel unit;
在第二数据写入阶段，在第n+1写入控制线的控制下，第二数据写入电路将第二电压V2写入第二数据写入节点；In the second data writing phase, under the control of the n+1th writing control line, the second data writing circuit writes the second voltage V2 into the second data writing node;
在所述第一发光阶段，第一驱动电路在第一驱动节点的控制下，导通第一电压端与所述第一驱动电路的第二端之间的连接，第一发光控制电路在第2n-1行发光控制线的控制下，控制导通所述第一驱动电路的第二端与第2n-1行第m列发光元件之间的连接，所述第一驱动电路驱动第2n-1行第m列发光元件发光；第二驱动电路在第二驱动节点的控制下，导通第一电压端与第二驱动电路的第二端之间的连接，第三发光控制电路在第2n-1行发光控制线的控制下，控制导通第二驱动电路的第二端与第2n+1行第m列发光元件之间的连接，所述第二驱动电路驱动第2n+1行第m列发光元件发光；In the first light-emitting stage, the first driving circuit conducts the connection between the first voltage terminal and the second terminal of the first driving circuit under the control of the first driving node, and the first light-emitting control circuit Under the control of the 2n-1 row light emitting control line, the connection between the second terminal of the first driving circuit and the light-emitting element in the mth column of the 2n-1th row is controlled, and the first driving circuit drives the 2n-th row. The light-emitting element in the mth column of the first row emits light; the second driving circuit conducts the connection between the first voltage terminal and the second terminal of the second driving circuit under the control of the second driving node, and the third light-emitting control circuit -Under the control of row 1 light emitting control line, the connection between the second terminal of the second driving circuit and the light emitting element in row 2n+1th column m is controlled and turned on, and the second driving circuit drives row 2n+1th row m columns of light-emitting elements emit light;
在所述第二补偿阶段，数据线输出第三数据电压，第一补偿控制电路在第n行栅线的控制下，控制将第三数据电压写入第一数据写入节点，并控制第一驱动节点和所述第一驱动电路的第二端之间连通；初始电压端输出初始电压，第二初始电路在第n+1初始控制线的控制下，控制将初始电压写入第二驱动节点；In the second compensation stage, the data line outputs the third data voltage, and the first compensation control circuit controls the writing of the third data voltage into the first data writing node under the control of the gate line in the nth row, and controls the first The driving node is connected to the second terminal of the first driving circuit; the initial voltage terminal outputs an initial voltage, and the second initial circuit controls writing the initial voltage into the second driving node under the control of the n+1th initial control line ;
在所述第三数据写入阶段，在第n写入控制线的控制下，第二数据写入电路将第二电压V2写入第二数据写入节点，以将第三数据电压写入第一驱动节点；数据线输出第四数据电压，第二补偿控制电路在第n+1行栅线的控制下，控制将第四数据电压写入第二数据写入节点，并控制第二驱动节点和第二驱动电路的第二端之间连通；In the third data writing phase, under the control of the nth writing control line, the second data writing circuit writes the second voltage V2 into the second data writing node, so as to write the third data voltage into the nth a driving node; the data line outputs the fourth data voltage, and the second compensation control circuit controls the writing of the fourth data voltage into the second data writing node under the control of the n+1th gate line, and controls the second driving node communicated with the second end of the second drive circuit;
在第四数据写入阶段，在第n+1写入控制线的控制下，第二数据写入电路将第二电压V2写入第二数据写入节点，以将第四数据电压写入第二驱动节点；In the fourth data writing phase, under the control of the n+1th writing control line, the second data writing circuit writes the second voltage V2 into the second data writing node, so as to write the fourth data voltage into the Two drive nodes;
在所述第二发光阶段，第一驱动电路在第一驱动节点的控制下，导通第一电压端与第一驱动电路的第二端之间的连接，第四发光控制电路在第2n行发光控制线的控制下，控制导通第一驱动电路的第二端与第2n行第m列发光元件之间的连接，第一驱动电路驱动第2n行第m列发光元件发光；第二驱动电路在第二驱动节点的控制下，导通第一电压端与第二驱动电路的第二端之间的连接，第四发光控制电路在第2n行发光控制线的控制下，控制导通第二驱动电路的第二端与第2n+2行第m列发光元件之间的连接，第二驱动电路驱动第2n+2行第m列发光元件发光。In the second light-emitting stage, the first drive circuit conducts the connection between the first voltage terminal and the second terminal of the first drive circuit under the control of the first drive node, and the fourth light-emitting control circuit is in row 2n Under the control of the light emission control line, the connection between the second terminal of the first drive circuit and the light-emitting element in the mth column of the 2nth row is controlled and turned on, and the first drive circuit drives the light-emitting element in the mth column of the 2nth row to emit light; the second drive Under the control of the second drive node, the circuit conducts the connection between the first voltage terminal and the second terminal of the second drive circuit, and the fourth light emission control circuit controls the conduction of the second The second terminal of the second drive circuit is connected to the light-emitting element in the mth column of the 2n+2th row, and the second drive circuit drives the light-emitting element in the mth column of the 2n+2th row to emit light.
下面通过一具体实施例来说明本发明所述的像素模组。The pixel module described in the present invention will be described below through a specific embodiment.
本发明所述的像素模组的一具体实施例包括第一像素单元和第二像素单元；A specific embodiment of the pixel module described in the present invention includes a first pixel unit and a second pixel unit;
如图7所示，第一像素单元包括第2n-1行第m列有机发光二极管OLED2n-1,m、第2n行第m列有机发光二极管OLED2n,m、第一驱动电路、第一初始电路、第一储能电路、第一补偿控制电路、第一数据写入电路、第一发光控制电路和第二发光控制电路，其中，As shown in FIG. 7 , the first pixel unit includes an organic light emitting diode OLED2n-1, m in row 2n-1, column m, organic light emitting diode OLED2n, m in row 2n, m, a first driving circuit, and a first initial circuit. , a first energy storage circuit, a first compensation control circuit, a first data writing circuit, a first light emission control circuit and a second light emission control circuit, wherein,
所述第一驱动电路包括第一驱动晶体管T3，所述第一初始电路包括第一初始晶体管T1，所述第一储能电路包括第一存储电容Cst1，所述第一补偿控制电路包括第一补偿控制晶体管T2和第二补偿控制晶体管T4，所述第一数据写入电路包括第一数据写入晶体管T5，所述第一发光控制电路包括第一发光控制晶体管T6，所述第二发光控制电路包括第二发光控制晶体管T7；The first drive circuit includes a first drive transistor T3, the first initial circuit includes a first initial transistor T1, the first energy storage circuit includes a first storage capacitor Cst1, and the first compensation control circuit includes a first Compensation control transistor T2 and a second compensation control transistor T4, the first data writing circuit includes a first data writing transistor T5, the first light emission control circuit includes a first light emission control transistor T6, and the second light emission control The circuit includes a second light emitting control transistor T7;
T3的栅极与第一驱动节点a1连接，T3的源极与用于输入高电压Vdd的高电压输入端ELVDD连接；The gate of T3 is connected to the first driving node a1, and the source of T3 is connected to the high voltage input terminal ELVDD for inputting the high voltage Vdd;
T2的栅极与第n行栅线Gate(n)连接，T2的源极与所述第一驱动节点a1连接，T2的漏极与T3的漏极连接；The gate of T2 is connected to the gate line Gate(n) of the nth row, the source of T2 is connected to the first driving node a1, and the drain of T2 is connected to the drain of T3;
T4的栅极与Gate(n)连接，T4的源极与第一数据写入节点b1连接，T4的漏极与第n数据线Data(n)连接；The gate of T4 is connected to Gate(n), the source of T4 is connected to the first data writing node b1, and the drain of T4 is connected to the nth data line Data(n);
Cst1的第一端与所述第一驱动节点a1连接，Cst1的第二端与所述第一数据写入节点b1连接；The first end of Cst1 is connected to the first driving node a1, and the second end of Cst1 is connected to the first data writing node b1;
T1的栅极与第n初始控制线Gate(n-1)连接，T1的源极与所述第一驱动节点a1连接，T1的漏极接入初始电压Vinit；The gate of T1 is connected to the nth initial control line Gate(n-1), the source of T1 is connected to the first driving node a1, and the drain of T1 is connected to the initial voltage Vinit;
T5的栅极与第n+1行栅线Gate(n+1)连接，T5的源极与高电压输入端ELVDD连接，T5的漏极与所述第一数据写入节点b1连接；The gate of T5 is connected to the n+1th gate line Gate(n+1), the source of T5 is connected to the high voltage input terminal ELVDD, and the drain of T5 is connected to the first data writing node b1;
T6的栅极与第2n-1行发光控制线EM(2n-1)连接，T6的源极与T3的源极连接，T6的漏极与OLED2n-1,m的阳极连接；OLED2n-1,m的阴极与用于输入低电压Vss的低电压输入端ELVSS连接；The gate of T6 is connected to the light emitting control line EM(2n-1) of row 2n-1, the source of T6 is connected to the source of T3, the drain of T6 is connected to the anode of OLED2n-1,m; OLED2n-1, The cathode of m is connected to the low voltage input terminal ELVSS for inputting the low voltage Vss;
T7的栅极与第2n行发光控制线EM(2n)连接，T7的源极与T3的源极连接，T7的漏极与OLED2n,m的阳极连接；OLED2n,m的阴极与用于输入低电压Vss的低电压输入端ELVSS连接；The gate of T7 is connected to the light emission control line EM(2n) of row 2n, the source of T7 is connected to the source of T3, the drain of T7 is connected to the anode of OLED2n, m; the cathode of OLED2n, m is connected to the input low The low voltage input ELVSS of the voltage Vss is connected;
第二像素单元包括第2n+1行第m列有机发光二极管OLED2n+1,m、第2n+2行第m列有机发光二极管OLED2n+2,m、第二驱动电路、第二初始电路、第二储能电路、第二补偿控制电路、第二数据写入电路、第三发光控制电路和第四发光控制电路，其中，The second pixel unit includes an organic light emitting diode OLED2n+1,m in row 2n+1 and column m in row 2n+1, an organic light emitting diode OLED2n+2,m in row 2n+2 and column m, a second driving circuit, a second initial circuit, and a second driving circuit. Two energy storage circuits, a second compensation control circuit, a second data writing circuit, a third light emission control circuit and a fourth light emission control circuit, wherein,
所述第二驱动电路包括第二驱动晶体管T2-3，所述第二初始电路包括第二初始晶体管T2-1，所述第二储能电路包括第二存储电容Cst2，所述第二补偿控制电路包括第三补偿控制晶体管T2-2和第四补偿控制晶体管T2-4，所述第二数据写入电路包括第二数据写入晶体管T2-5，所述第三发光控制电路包括第三发光控制晶体管T2-6，所述第四发光控制电路包括第四发光控制晶体管T2-7；The second drive circuit includes a second drive transistor T2-3, the second initial circuit includes a second initial transistor T2-1, the second energy storage circuit includes a second storage capacitor Cst2, and the second compensation control The circuit includes a third compensation control transistor T2-2 and a fourth compensation control transistor T2-4, the second data writing circuit includes a second data writing transistor T2-5, and the third lighting control circuit includes a third lighting Control transistor T2-6, the fourth light emission control circuit includes a fourth light emission control transistor T2-7;
T2-3的栅极与第二驱动节点a2连接，T2-3的源极与用于输入高电压Vdd的高电压输入端ELVDD连接；The gate of T2-3 is connected to the second driving node a2, and the source of T2-3 is connected to the high voltage input terminal ELVDD for inputting the high voltage Vdd;
T2-2的栅极与第n+1行栅线Gate(n+1)连接，T2-2的源极与所述第二驱动节点a2连接，T2-2的漏极与T2-3的漏极连接；The gate of T2-2 is connected to the gate line Gate(n+1) of row n+1, the source of T2-2 is connected to the second driving node a2, and the drain of T2-2 is connected to the drain of T2-3 pole connection;
T2-4的栅极与Gate(n+1)连接，T2-4的源极与第二数据写入节点b2连接，T2-4的漏极与第n+1数据线Data(n+1)连接；The gate of T2-4 is connected to Gate(n+1), the source of T2-4 is connected to the second data writing node b2, and the drain of T2-4 is connected to the n+1th data line Data(n+1) connect;
Cst2的第一端与所述第二驱动节点a2连接，Cst2的第二端与所述第二数据写入节点b2连接；The first end of Cst2 is connected to the second driving node a2, and the second end of Cst2 is connected to the second data writing node b2;
T2-1的栅极与第n行栅线Gate(n)连接，T2-1的源极与所述第二驱动节点a2连接，T2-1的漏极接入初始电压Vinit；The gate of T2-1 is connected to the gate line Gate(n) of the nth row, the source of T2-1 is connected to the second driving node a2, and the drain of T2-1 is connected to the initial voltage Vinit;
所述第n行栅线Gate(n)即为第n+1初始控制线；The gate line Gate(n) in the nth row is the n+1th initial control line;
T2-5的栅极与第n+2行栅线Gate(n+2)连接，T2-5的源极与高电压输入端ELVDD连接，T2-5的漏极与所述第二数据写入节点b2连接；The gate of T2-5 is connected to the n+2th gate line Gate (n+2), the source of T2-5 is connected to the high voltage input terminal ELVDD, and the drain of T2-5 is connected to the second data writing Node b2 connects;
T2-6的栅极与第2n-1行发光控制线EM(2n-1)连接，T2-6的源极与T2-3的源极连接，T2-6的漏极与OLED2n+1,m的阳极连接；OLED2n+1,m的阴极与用于输入低电压Vss的低电压输入端ELVSS连接；The gate of T2-6 is connected to the light emitting control line EM(2n-1) of row 2n-1, the source of T2-6 is connected to the source of T2-3, and the drain of T2-6 is connected to OLED2n+1,m The anode of OLED2n+1, m is connected to the low voltage input terminal ELVSS for inputting the low voltage Vss;
T2-7的栅极与第2n行发光控制线EM(2n)连接，T2-7的源极与T2-3的源极连接，T2-7的漏极与OLED2n+2,m的阳极连接；OLED2n+2,m的阴极与用于输入低电压Vss的低电压输入端ELVSS连接。The gate of T2-7 is connected to the light emitting control line EM(2n) of row 2n, the source of T2-7 is connected to the source of T2-3, and the drain of T2-7 is connected to the anode of OLED2n+2,m; The cathodes of OLED2n+2,m are connected to the low voltage input terminal ELVSS for inputting the low voltage Vss.
在图7所示的像素模组的具体实施例中，所有的晶体管都为p型晶体管，但不以此为限。In the specific embodiment of the pixel module shown in FIG. 7 , all transistors are p-type transistors, but not limited thereto.
如图8所示，本发明如图7所示的像素模组的具体实施例在工作时，一显示周期Subframe包括依次设置的第一显示子周期Subframe1和第二显示子周期Subframe2，所述第一显示子周期Subframe1包括依次设置的第一初始阶段t11、第一补偿阶段t12、第一数据写入阶段t13、第二数据写入阶段t14和第一发光阶段t15，所述第二显示子周期包括依次设置的第二初始阶段t21、第二补偿阶段t22、第三数据写入阶段t23、第四数据写入阶段t24和第二发光阶段t25；As shown in Figure 8, when the specific embodiment of the pixel module shown in Figure 7 of the present invention is working, a display period Subframe includes a first display subframe Subframe1 and a second display subframe Subframe2 arranged in sequence, the first display period Subframe A display sub-period Subframe1 includes the first initial phase t11, the first compensation phase t12, the first data writing phase t13, the second data writing phase t14 and the first light-emitting phase t15 which are arranged in sequence. The second display sub-cycle Including the second initial stage t21, the second compensation stage t22, the third data writing stage t23, the fourth data writing stage t24 and the second light emitting stage t25 arranged in sequence;
在第一初始阶段t11，初始电压端输出初始电压Vinit，Gate(n-1)输出低电平，T1打开，以将Vinit写入第一驱动节点a1；In the first initial stage t11, the initial voltage terminal outputs an initial voltage Vinit, Gate(n-1) outputs a low level, and T1 is turned on, so as to write Vinit into the first driving node a1;
在第一补偿阶段t12，Data(n)输出第一数据电压Vdata1，Gate(n)输出低电平，T2和T4都打开，以将Vdata1写入第一数据写入节点b1，第一驱动节点a1与T3的漏极连接，T3打开，此时a1的电位为Vdd+Vth，Vth为T3的阈值电压；初始电压端输出初始电压Vinit，T2-1打开，以将Vinit写入第二驱动节点a2；In the first compensation stage t12, Data(n) outputs the first data voltage Vdata1, Gate(n) outputs a low level, T2 and T4 are both turned on, so as to write Vdata1 into the first data writing node b1, and the first driving node a1 is connected to the drain of T3, and T3 is turned on. At this time, the potential of a1 is Vdd+Vth, and Vth is the threshold voltage of T3; the initial voltage terminal outputs the initial voltage Vinit, and T2-1 is turned on to write Vinit into the second drive node a2;
在所述第一数据写入阶段t13，Gate(n+1)输出低电平，T5打开，以将Vdd写入所述第一数据写入节点b1，从而使得所述第一驱动节点a1的电位变为2Vdd+Vth-Vdata1；Data(n+1)输出第二数据电压Vdata2，T2-2和T2-4都打开，以将Vdata2写入第二数据写入节点b2，第二驱动节点a2与T2-3的漏极连接，T2-3打开，此时a2的电位为Vdd+Vth2，Vth2为T2-3的阈值电压；In the first data writing phase t13, Gate (n+1) outputs a low level, and T5 is turned on to write Vdd into the first data writing node b1, so that the first driving node a1 The potential becomes 2Vdd+Vth-Vdata1; Data(n+1) outputs the second data voltage Vdata2, T2-2 and T2-4 are both turned on, so as to write Vdata2 into the second data write node b2, and the second drive node a2 Connect to the drain of T2-3, T2-3 is turned on, at this time the potential of a2 is Vdd+Vth2, and Vth2 is the threshold voltage of T2-3;
在第二数据写入阶段t14，Gate(n+2)输出低电平，T2-5打开，以将Vdd写入第二数据写入节点b2，从而使得所述第二驱动节点a2的电位变为2Vdd+Vth2-Vdata2；In the second data writing phase t14, Gate (n+2) outputs a low level, and T2-5 is turned on to write Vdd into the second data writing node b2, so that the potential of the second driving node a2 becomes It is 2Vdd+Vth2-Vdata2;
在第一发光阶段t15，EM(2n-1)输出低电平，EM(2n)输出高电平，T3和T6都打开，以驱动OLED2n-1,m发光，T2-3和T2-6也都打开，以驱动OLED2n+1,m发光；In the first light-emitting stage t15, EM (2n-1) outputs low level, EM (2n) outputs high level, T3 and T6 are both turned on to drive OLED2n-1, m to emit light, T2-3 and T2-6 also Both are turned on to drive OLED2n+1,m to emit light;
在第二初始阶段t21，初始电压端输出初始电压Vinit，Gate(n-1)输出低电平，T1打开，以将Vinit写入第一驱动节点a1；In the second initial stage t21, the initial voltage terminal outputs the initial voltage Vinit, the Gate(n-1) outputs a low level, and T1 is turned on, so as to write Vinit into the first driving node a1;
在第二补偿阶段t22，Data(n)输出第三数据电压Vdata3，Gate(n)输出低电平，T2和T4打开，以将Vdata3写入第一数据写入节点b1，第一驱动节点a1与T3的漏极连接，T3打开，此时a1的电位为Vdd+Vth，Vth为T3的阈值电压；初始电压端输出初始电压Vinit，T2-1打开，以将Vinit写入第二驱动节点a2；In the second compensation stage t22, Data(n) outputs the third data voltage Vdata3, Gate(n) outputs a low level, T2 and T4 are turned on, so as to write Vdata3 into the first data writing node b1, and the first driving node a1 Connect to the drain of T3, T3 is turned on, at this time the potential of a1 is Vdd+Vth, and Vth is the threshold voltage of T3; the initial voltage terminal outputs the initial voltage Vinit, and T2-1 is turned on to write Vinit into the second drive node a2 ;
在第三数据写入阶段t23，Gate(n+1)输出低电平，T5打开，以将Vdd写入所述第一数据写入节点b1，从而使得所述第一驱动节点a1的电位变为2Vdd+Vth-Vdata3；Data(n+1)输出第四数据电压Vdata4，T2-2和T2-4都打开，以将Vdata4写入第二数据写入节点b2，第二驱动节点a2与T2-3的漏极连接，T2-3打开，此时a2的电位为Vdd+Vth2，Vth2为T2-3的阈值电压；In the third data writing phase t23, Gate (n+1) outputs a low level, and T5 is turned on to write Vdd into the first data writing node b1, so that the potential of the first driving node a1 becomes 2Vdd+Vth-Vdata3; Data(n+1) outputs the fourth data voltage Vdata4, both T2-2 and T2-4 are turned on, so as to write Vdata4 into the second data writing node b2, and the second driving node a2 and T2 The drain of -3 is connected, and T2-3 is turned on. At this time, the potential of a2 is Vdd+Vth2, and Vth2 is the threshold voltage of T2-3;
在第四数据写入阶段t24，Gate(n+2)输出低电平，T2-5打开，以将Vdd写入第二数据写入节点b2，从而使得所述第二驱动节点a2的电位变为2Vdd+Vth2-Vdata4；In the fourth data writing phase t24, Gate (n+2) outputs a low level, and T2-5 is turned on to write Vdd into the second data writing node b2, so that the potential of the second driving node a2 becomes It is 2Vdd+Vth2-Vdata4;
在第二发光阶段t12，EM(2n)输出低电平，EM(2n-1)输出高电平，T3和T7都打开，以驱动OLED2n,m发光，T2-3和T2-7也都打开，以驱动OLED2n+2,m发光。In the second light-emitting stage t12, EM (2n) outputs low level, EM (2n-1) outputs high level, T3 and T7 are both turned on to drive OLED2n, m to emit light, T2-3 and T2-7 are also turned on , to drive OLED2n+2,m to emit light.
本发明实施例所述的像素驱动方法，应用于上述的像素模组，一显示周期包括依次设置的第一显示子周期和第二显示子周期，所述第一显示子周期包括依次设置的第一初始阶段、第一补偿阶段、第一数据写入阶段、第二数据写入阶段和第一发光阶段，所述第二显示子周期包括依次设置的第二初始阶段、第二补偿阶段、第三数据写入阶段、第四数据写入阶段和第二发光阶段，所述像素驱动方法包括：The pixel driving method described in the embodiment of the present invention is applied to the above-mentioned pixel module. A display cycle includes a first display sub-cycle and a second display sub-cycle arranged in sequence, and the first display sub-cycle includes a second display sub-cycle arranged in sequence. An initial phase, a first compensation phase, a first data writing phase, a second data writing phase and a first light emitting phase, the second display sub-cycle includes the second initial phase, the second compensation phase, the second Three data writing phases, a fourth data writing phase and a second light emitting phase, the pixel driving method includes:
在第一初始阶段和第二初始阶段，初始电压端输出初始电压，第一初始电路在第n初始控制线的控制下，控制将所述初始电压写入第一驱动节点；n为正整数；所述第一驱动节点为第一像素单元中的驱动节点；In the first initial stage and the second initial stage, the initial voltage terminal outputs an initial voltage, and the first initial circuit controls writing the initial voltage into the first driving node under the control of the nth initial control line; n is a positive integer; The first driving node is a driving node in the first pixel unit;
在第一补偿阶段，数据线输出第一数据电压，第一补偿控制电路在第n行栅线的控制下，控制将所述第一数据电压写入第一数据写入节点，并控制所述第一驱动节点和所述第一驱动电路的第二端之间连通；初始电压端输出初始电压，第二初始电路在第n+1初始控制线的控制下，控制将所述初始电压写入第二驱动节点；第一数据写入节点为第一像素单元中的数据写入节点，第二驱动节点为第二像素单元中的驱动节点；In the first compensation stage, the data line outputs the first data voltage, and the first compensation control circuit controls the writing of the first data voltage into the first data writing node under the control of the gate line in the nth row, and controls the The first drive node is connected to the second terminal of the first drive circuit; the initial voltage terminal outputs an initial voltage, and the second initial circuit controls writing the initial voltage into The second driving node; the first data writing node is a data writing node in the first pixel unit, and the second driving node is a driving node in the second pixel unit;
在所述第一数据写入阶段，在第n写入控制线的控制下，第一数据写入电路将第二电压端输出的第二电压V2写入第一数据写入节点；数据线输出第二数据电压，第二补偿控制电路在第n+1行栅线的控制下，控制将第二数据电压写入所述第二数据写入节点，并控制第二驱动节点和第二驱动电路的第二端之间连通；第二数据写入节点为第二像素单元中的数据写入节点；In the first data writing phase, under the control of the nth writing control line, the first data writing circuit writes the second voltage V2 output from the second voltage terminal into the first data writing node; the data line output For the second data voltage, the second compensation control circuit controls the writing of the second data voltage into the second data writing node under the control of the n+1th gate line, and controls the second driving node and the second driving circuit connected between the second ends; the second data writing node is the data writing node in the second pixel unit;
在第二数据写入阶段，在第n+1写入控制线的控制下，第二数据写入电路将第二电压V2写入第二数据写入节点；In the second data writing phase, under the control of the n+1th writing control line, the second data writing circuit writes the second voltage V2 into the second data writing node;
在所述第一发光阶段，第一驱动电路在第一驱动节点的控制下，导通第一电压端与所述第一驱动电路的第二端之间的连接，第一发光控制电路在第2n-1行发光控制线的控制下，控制导通所述第一驱动电路的第二端与第2n-1行第m列发光元件之间的连接，所述第一驱动电路驱动第2n-1行第m列发光元件发光；第二驱动电路在第二驱动节点的控制下，导通第一电压端与第二驱动电路的第二端之间的连接，第三发光控制电路在第2n-1行发光控制线的控制下，控制导通第二驱动电路的第二端与第2n+1行第m列发光元件之间的连接，所述第二驱动电路驱动第2n+1行第m列发光元件发光；In the first light-emitting stage, the first driving circuit conducts the connection between the first voltage terminal and the second terminal of the first driving circuit under the control of the first driving node, and the first light-emitting control circuit Under the control of the 2n-1 row light emitting control line, the connection between the second terminal of the first driving circuit and the light-emitting element in the mth column of the 2n-1th row is controlled, and the first driving circuit drives the 2n-th row. The light-emitting element in the mth column of the first row emits light; the second driving circuit conducts the connection between the first voltage terminal and the second terminal of the second driving circuit under the control of the second driving node, and the third light-emitting control circuit -Under the control of row 1 light emitting control line, the connection between the second terminal of the second driving circuit and the light emitting element in row 2n+1th column m is controlled and turned on, and the second driving circuit drives row 2n+1th row m columns of light-emitting elements emit light;
在所述第二补偿阶段，数据线输出第三数据电压，第一补偿控制电路在第n行栅线的控制下，控制将第三数据电压写入第一数据写入节点，并控制第一驱动节点和所述第一驱动电路的第二端之间连通；初始电压端输出初始电压，第二初始电路在第n+1初始控制线的控制下，控制将初始电压写入第二驱动节点；In the second compensation stage, the data line outputs the third data voltage, and the first compensation control circuit controls the writing of the third data voltage into the first data writing node under the control of the gate line in the nth row, and controls the first The driving node is connected to the second terminal of the first driving circuit; the initial voltage terminal outputs an initial voltage, and the second initial circuit controls writing the initial voltage into the second driving node under the control of the n+1th initial control line ;
在所述第三数据写入阶段，在第n写入控制线的控制下，第二数据写入电路将第二电压V2写入第二数据写入节点，以将第三数据电压写入第一驱动节点；数据线输出第四数据电压，第二补偿控制电路在第n+1行栅线的控制下，控制将第四数据电压写入第二数据写入节点，并控制第二驱动节点和第二驱动电路的第二端之间连通；In the third data writing phase, under the control of the nth writing control line, the second data writing circuit writes the second voltage V2 into the second data writing node, so as to write the third data voltage into the nth a driving node; the data line outputs the fourth data voltage, and the second compensation control circuit controls the writing of the fourth data voltage into the second data writing node under the control of the n+1th gate line, and controls the second driving node communicated with the second end of the second drive circuit;
在第四数据写入阶段，在第n+1写入控制线的控制下，第二数据写入电路将第二电压V2写入第二数据写入节点，以将第四数据电压写入第二驱动节点；In the fourth data writing phase, under the control of the n+1th writing control line, the second data writing circuit writes the second voltage V2 into the second data writing node, so as to write the fourth data voltage into the Two drive nodes;
在所述第二发光阶段，第一驱动电路在第一驱动节点的控制下，导通第一电压端与第一驱动电路的第二端之间的连接，第四发光控制电路在第2n行发光控制线的控制下，控制导通第一驱动电路的第二端与第2n行第m列发光元件之间的连接，第一驱动电路驱动第2n行第m列发光元件发光；第二驱动电路在第二驱动节点的控制下，导通第一电压端与第二驱动电路的第二端之间的连接，第四发光控制电路在第2n行发光控制线的控制下，控制导通第二驱动电路的第二端与第2n+2行第m列发光元件之间的连接，第二驱动电路驱动第2n+2行第m列发光元件发光；In the second light-emitting stage, the first drive circuit conducts the connection between the first voltage terminal and the second terminal of the first drive circuit under the control of the first drive node, and the fourth light-emitting control circuit is in row 2n Under the control of the light emission control line, the connection between the second terminal of the first drive circuit and the light-emitting element in the mth column of the 2nth row is controlled and turned on, and the first drive circuit drives the light-emitting element in the mth column of the 2nth row to emit light; the second drive Under the control of the second drive node, the circuit conducts the connection between the first voltage terminal and the second terminal of the second drive circuit, and the fourth light emission control circuit controls the conduction of the second The connection between the second end of the second driving circuit and the light-emitting element in the mth column of the 2n+2th row, the second driving circuit drives the light-emitting element in the mth column of the 2n+2th row to emit light;
m为正整数。m is a positive integer.
本发明实施例所述的显示装置，包括N级M列上述的像素模组，N和M都为正整数。The display device described in the embodiment of the present invention includes N stages and M columns of the above-mentioned pixel modules, where N and M are both positive integers.
具体的，第n级第m列像素模组包括的第一像素单元包括第2n-1行第m列发光元件和第2n行第m列发光元件；n和m都为正整数；Specifically, the first pixel unit included in the nth level mth column pixel module includes the 2n-1th row mth column light-emitting element and the 2nth row mth column light-emitting element; both n and m are positive integers;
第n级第m列像素模组包括的第一像素单元分别与第n初始控制线、第n行栅线、第n写入控制线、第2n-1行发光控制线和第2n行发光控制线连接；The first pixel unit included in the nth level mth column pixel module is respectively connected with the nth initial control line, the nth row gate line, the nth write control line, the 2n-1th row light emission control line and the 2nth row light emission control line line connection;
第n级第m列像素模组包括的第二像素单元包括第2n+1行第m列发光元件和第2n+2行第m列发光元件；The second pixel unit included in the nth level mth column pixel module includes the 2n+1th row mth column light emitting element and the 2n+2th row mth column light emitting element;
第n级第m列像素模组包括的第二像素单元分别与第n+1初始控制线、第n+1行栅线、第n+1写入控制线、所述第2n-1行发光控制线和所述第2n行发光控制线连接。The second pixel unit included in the nth-level and mth-column pixel module is respectively connected to the n+1th initial control line, the n+1th row gate line, the n+1th writing control line, and the 2n-1th row to emit light. The control line is connected to the light emitting control line of the 2nth row.
本发明实施例所述的显示装置在工作时，在一帧显示时间的前半部分，位于奇数行的发光元件发光，在一帧显示时间的后半部分，位于偶数行的发光元件发光。When the display device described in the embodiment of the present invention is working, the light-emitting elements located in odd rows emit light in the first half of a frame display time, and the light-emitting elements located in even rows emit light in the second half of a frame display time.
在优选情况下，所述第n写入控制线为第n+1行栅线，所述第n+1写入控制线为第n+2行栅线，这样可利用现有的栅线进行写入控制，减少控制线数量，从而不需设置用于为写入控制线提供写入控制信号的写入控制电路，利于实现高PPI(Pixels Per Inch，每英寸所拥有的像素数目)。In a preferred situation, the nth writing control line is the n+1th row of gate lines, and the n+1th writing control line is the n+2th row of gate lines, so that the existing gate lines can be used to perform Write control, reducing the number of control lines, so that there is no need to set a write control circuit for providing write control signals for the write control lines, which is conducive to achieving high PPI (Pixels Per Inch, the number of pixels per inch).
具体的，n等于1，第n初始控制线为起始信号线，第n+1初始控制线为第n行栅线；或者，n大于1，第n初始控制线为第n-1行栅线，第n+1初始控制线为第n行栅线。Specifically, n is equal to 1, the nth initial control line is the initial signal line, and the n+1th initial control line is the nth row of gate lines; or, n is greater than 1, the nth initial control line is the n-1th row of gate lines line, the n+1th initial control line is the nth row of gate lines.
本发明实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。The display device provided by the embodiments of the present invention may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810928371.4ACN109003574B (en) | 2018-08-15 | 2018-08-15 | Pixel unit, driving method, pixel module and driving method thereof, and display device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810928371.4ACN109003574B (en) | 2018-08-15 | 2018-08-15 | Pixel unit, driving method, pixel module and driving method thereof, and display device |
| Publication Number | Publication Date |
|---|---|
| CN109003574Atrue CN109003574A (en) | 2018-12-14 |
| CN109003574B CN109003574B (en) | 2021-01-22 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810928371.4AActiveCN109003574B (en) | 2018-08-15 | 2018-08-15 | Pixel unit, driving method, pixel module and driving method thereof, and display device |
| Country | Link |
|---|---|
| CN (1) | CN109003574B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109493794A (en)* | 2019-01-24 | 2019-03-19 | 鄂尔多斯市源盛光电有限责任公司 | Pixel circuit, image element driving method and display device |
| CN109671397A (en)* | 2019-02-15 | 2019-04-23 | 京东方科技集团股份有限公司 | Glow current control circuit, pixel circuit, display device and display driving method |
| CN110197638A (en)* | 2019-06-28 | 2019-09-03 | 上海天马有机发光显示技术有限公司 | A kind of driving method of display panel, display device and display panel |
| CN111063306A (en)* | 2019-12-16 | 2020-04-24 | 深圳市华星光电半导体显示技术有限公司 | Pixel circuit, driving method thereof and display panel |
| CN111833822A (en)* | 2020-04-17 | 2020-10-27 | 北京奕斯伟计算技术有限公司 | Backlight source, backlight module, backlight driving method and display device |
| CN112435629A (en)* | 2020-11-24 | 2021-03-02 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN113327555A (en)* | 2021-06-25 | 2021-08-31 | 合肥京东方卓印科技有限公司 | Pixel circuit, display panel and control method |
| WO2021185328A1 (en)* | 2020-03-19 | 2021-09-23 | 京东方科技集团股份有限公司 | Shift register and drive method, and display device |
| WO2021238897A1 (en)* | 2020-05-25 | 2021-12-02 | 京东方科技集团股份有限公司 | Pixel circuit, pixel driving method, and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1801298A (en)* | 2005-01-05 | 2006-07-12 | 三星Sdi株式会社 | Display device and driving method thereof |
| CN103456267A (en)* | 2013-08-26 | 2013-12-18 | 北京京东方光电科技有限公司 | Touch display drive circuit and drive method and display device thereof |
| CN104021757A (en)* | 2014-05-30 | 2014-09-03 | 京东方科技集团股份有限公司 | Pixel circuit and driving method thereof, and display apparatus |
| CN104157240A (en)* | 2014-07-22 | 2014-11-19 | 京东方科技集团股份有限公司 | Pixel drive circuit, driving method, array substrate and display device |
| US9215777B2 (en)* | 2012-12-13 | 2015-12-15 | Samsung Display Co., Ltd. | Pixel and organic light emitting display device using the same |
| CN106448566A (en)* | 2016-10-28 | 2017-02-22 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving method and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1801298A (en)* | 2005-01-05 | 2006-07-12 | 三星Sdi株式会社 | Display device and driving method thereof |
| US9215777B2 (en)* | 2012-12-13 | 2015-12-15 | Samsung Display Co., Ltd. | Pixel and organic light emitting display device using the same |
| CN103456267A (en)* | 2013-08-26 | 2013-12-18 | 北京京东方光电科技有限公司 | Touch display drive circuit and drive method and display device thereof |
| CN104021757A (en)* | 2014-05-30 | 2014-09-03 | 京东方科技集团股份有限公司 | Pixel circuit and driving method thereof, and display apparatus |
| CN104157240A (en)* | 2014-07-22 | 2014-11-19 | 京东方科技集团股份有限公司 | Pixel drive circuit, driving method, array substrate and display device |
| CN106448566A (en)* | 2016-10-28 | 2017-02-22 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving method and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109493794A (en)* | 2019-01-24 | 2019-03-19 | 鄂尔多斯市源盛光电有限责任公司 | Pixel circuit, image element driving method and display device |
| US11380261B2 (en) | 2019-01-24 | 2022-07-05 | Ordos Yuansheng Optoelectronics Co., Ltd. | Pixel circuit, pixel driving method and display device |
| CN109671397A (en)* | 2019-02-15 | 2019-04-23 | 京东方科技集团股份有限公司 | Glow current control circuit, pixel circuit, display device and display driving method |
| CN109671397B (en)* | 2019-02-15 | 2020-08-14 | 京东方科技集团股份有限公司 | Light emission current control circuit, pixel circuit, display device, and display driving method |
| CN110197638A (en)* | 2019-06-28 | 2019-09-03 | 上海天马有机发光显示技术有限公司 | A kind of driving method of display panel, display device and display panel |
| CN111063306A (en)* | 2019-12-16 | 2020-04-24 | 深圳市华星光电半导体显示技术有限公司 | Pixel circuit, driving method thereof and display panel |
| US11289017B2 (en) | 2019-12-16 | 2022-03-29 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Pixel circuit and related driving method, and display panel |
| WO2021185328A1 (en)* | 2020-03-19 | 2021-09-23 | 京东方科技集团股份有限公司 | Shift register and drive method, and display device |
| US11847966B2 (en) | 2020-03-19 | 2023-12-19 | Boe Technology Group Co., Ltd. | Shift register and driving method therefor, and display apparatus |
| CN111833822B (en)* | 2020-04-17 | 2021-10-22 | 北京奕斯伟计算技术有限公司 | Backlight source, backlight module, backlight driving method and display device |
| CN111833822A (en)* | 2020-04-17 | 2020-10-27 | 北京奕斯伟计算技术有限公司 | Backlight source, backlight module, backlight driving method and display device |
| WO2021238897A1 (en)* | 2020-05-25 | 2021-12-02 | 京东方科技集团股份有限公司 | Pixel circuit, pixel driving method, and display device |
| US11663961B2 (en) | 2020-05-25 | 2023-05-30 | Boe Technology Group Co., Ltd. | Pixel circuit, pixel driving method and display device |
| CN112435629A (en)* | 2020-11-24 | 2021-03-02 | 京东方科技集团股份有限公司 | Display substrate and display device |
| WO2022110650A1 (en)* | 2020-11-24 | 2022-06-02 | 京东方科技集团股份有限公司 | Display substrate and display device |
| US12033573B2 (en) | 2020-11-24 | 2024-07-09 | Boe Technology Group Co., Ltd. | Display substrate and display device |
| CN113327555A (en)* | 2021-06-25 | 2021-08-31 | 合肥京东方卓印科技有限公司 | Pixel circuit, display panel and control method |
| Publication number | Publication date |
|---|---|
| CN109003574B (en) | 2021-01-22 |
| Publication | Publication Date | Title |
|---|---|---|
| CN109003574A (en) | Pixel unit, driving method, pixel mould group and its driving method and display device | |
| CN115691425B (en) | Pixel circuit and driving method thereof, and display panel | |
| CN110268465B (en) | Pixel circuit, display panel and driving method of pixel circuit | |
| US11335241B2 (en) | Sub pixel circuit, pixel circuit, driving method thereof, display module and display device | |
| CN207217082U (en) | Pixel circuit and display device | |
| CN109523956B (en) | Pixel circuit, driving method thereof and display device | |
| CN109979394B (en) | Pixel circuit and driving method thereof, array substrate and display device | |
| CN105895028B (en) | A kind of pixel circuit and driving method and display equipment | |
| CN109754757B (en) | Pixel driving circuit, display device and pixel driving method | |
| US12027114B2 (en) | Pixel driving circuit, method for driving the same and display device | |
| WO2019062579A1 (en) | Pixel circuit and driving method thereof, and display device | |
| US20200211464A1 (en) | Pixel circuit and driving method thereof, and display panel | |
| WO2022110940A1 (en) | Pixel circuit and driving method thereof, and display panel | |
| WO2023016138A1 (en) | Pixel driving circuit and display panel | |
| CN111445858A (en) | Pixel circuit, driving method thereof and display device | |
| CN108597450A (en) | Pixel circuit and its driving method, display panel | |
| WO2015032141A1 (en) | Pixel circuit and display | |
| CN109509433A (en) | Pixel circuit, display device and image element driving method | |
| WO2020151657A1 (en) | Pixel circuit, pixel drive method, and display apparatus | |
| CN106205490A (en) | organic light emitting display | |
| WO2021208729A1 (en) | Display driving module, display driving method, and display device | |
| WO2016146053A1 (en) | Display device, and pixel circuit and driving method thereof | |
| KR102404766B1 (en) | Scan driver and display apparatus having the same | |
| CN109256094A (en) | Pixel circuit, pixel driving method, and display device | |
| CN104157239A (en) | Pixel circuit, driving method of pixel circuit, and display device adopting pixel circuit |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |