Detailed Description
There are various types of isolated power converters, such as forward converters, flyback converters, and push-pull converters, and the problems of the prior art will be described below by taking flyback converters as an example.
Referring to fig. 1, fig. 1 shows a prior art power converter control circuit. The transformer X1 electrically isolates the input end from the output end, the secondary side feedback transmitting circuit obtains the output voltage for accurately controlling the output voltage, and the information of the output voltage is transmitted back to the primary side feedback receiving circuit by using an optocoupler, a transformer, an isolation capacitor and other elements, the primary side feedback receiving circuit is connected with the primary side controller, and the primary side controller realizes the purpose of adjusting the output voltage by controlling the first switching tube Q1. However, such control methods add additional components, such as optocouplers, transformers, isolation capacitors, etc., which are typically bulky and expensive, adding to the bulk and cost of the power converter.
Fig. 2 shows another prior art power converter control circuit. In the prior art, a primary voltage converter is added at an output end to realize accurate control of output voltage. The voltage converter may be a linear regulator LR1, and its operating principle is that the amplifier AMP1 controls the gate of Qs1 according to the difference between the sampled output voltage VO2S and the first reference voltage VREF1, thereby controlling the on-resistance of the power transistor Qs 1. When VO2 is higher than a preset voltage, the on-resistance of Qs1 is adjusted to be high, and when VO2 is lower than the preset voltage, the on-resistance of Qs1 is adjusted to be low, so that accurate control of output voltage is realized. The efficiency of the whole power converter is the product of the original flyback converter efficiency and the linear regulator LR1, whereas the theoretical efficiency of LR1 is not higher than VO2/VO1 (VO 2 is less than VO 1), thus resulting in a reduced efficiency of the power converter.
In order to solve the above technical problems, the embodiments of the present application provide a power converter control circuit, and the power converter control circuit in the embodiments of the present application will be described in detail with reference to the accompanying drawings.
Examples
Referring specifically to fig. 3, fig. 3 shows a power converter control circuit provided in an embodiment of the present application, where the power converter control circuit includes: transformer X1, transformer driver 210, secondary side controller 110, secondary side diode Ds1, output capacitance Co, and load.
In a specific implementation manner of the power converter and the control circuit thereof provided by the embodiment of the application, the homonymous end of the main side coil L11 of the transformer is connected with the power supply voltage, the heteronymous end of the L11 is connected with one end of the transformer driver 210, and the other end of the transformer driver 210 is connected with the ground potential GND1 of the main side; the opposite-name end of the secondary side coil L22 of the transformer is connected with the positive electrode of the secondary side diode Ds1, the same-name end of the secondary side coil L22 is connected with the secondary side ground potential GND2, the negative electrode of the secondary side coil Ds1 is connected with the output voltage VO1, and the output capacitor Co and the load are connected between the VO1 and the GND2 in parallel.
The secondary side controller 110 includes a secondary side signal detection circuit 111 and an energy storage capacitor group 112, an input end of the secondary side signal detection circuit 111 is connected with any position of the secondary side circuit, an output end of the secondary side signal detection circuit 111 is connected with a control end of the energy storage capacitor group 112, the energy storage capacitor group has three energy storage ends, a first energy storage end is connected to a connection point between Ds1 and L22, a second energy storage end is connected with VO1, a third energy storage end is connected with GND2, and the secondary side circuit is a circuit communicated with L22.
The storage capacitor bank 112 includes integrated Metal-Insulator-Metal (MIM) capacitors and Metal-Oxide-Metal (MOM) capacitors.
The embodiment of the application provides a secondary side signal detection circuit to obtain an electrical signal of a secondary side circuit, so as to judge the working state of a power converter, and correspondingly adjust the capacitance value of the energy storage capacitor group according to the working state of the power converter, thereby controlling the energy transmitted to an output end.
Referring to fig. 4, the secondary side signal detection circuit 111 includes a first sampling resistor Rs1, a second sampling resistor Rs2, a comparator COMP1, and a digital controller 1121; rs1 and Rs2 are connected in series, and Rs1 and Rs2 connected in series are connected with a load in parallel; the positive input terminal of COMP1 is connected between Rs1 and Rs2, the negative input terminal of COMP1 is connected to the first reference voltage VREF1, and the output terminal VCCTRL of the comparator is connected to the input terminal of the digital controller 1121.
The storage capacitor group includes a first capacitor element Cs1, one end of Cs1 is connected to a connection point of Ds1 and L22, the other end of Cs1 is connected to GND2, and an output end of 1121 is connected to a control end of Cs 1. Cs1 may include a plurality of capacitors and a plurality of control terminals, and 1121 may include a plurality of output terminals.
Referring to fig. 5, the first capacitance element Cs1 includes a plurality of first capacitors Cs1k (k=1, 2 … N) and a plurality of first switches S1k (k=1, 2 … N), and the number of the first capacitors Cs1k is the same as the number of the first switches S1 k; each of the plurality of first capacitors Cs1k is connected in series with a corresponding first switch S1k, the plurality of first capacitors Cs1k and the corresponding first switches S1k connected in series are connected in parallel between the anode of the secondary diode Ds1 and the ground, and the control end of each of the plurality of first switches S1k is connected with the output end of the digital controller 1121.
Referring to fig. 6, the storage capacitor group includes a second capacitor Cs2, one end of Cs2 is connected to the connection point between Ds1 and L22, the other end of Cs2 is connected to VO1, and the output end of 1121 is connected to the control end of Cs 1. Cs2 may include a plurality of capacitors and a plurality of control terminals, and 1121 may include a plurality of output terminals.
Referring to fig. 7, the second capacitive element includes a plurality of second capacitors Cs2k (k=1, 2 … N) and a plurality of second switches S2k (k=1, 2 … N), and the number of the second capacitors Cs2k is the same as the number of the second switches S2 k; each of the plurality of second capacitors Cs2k is connected in series with a corresponding second switch S2k, the plurality of second capacitors Cs2k and the second switch S2k connected in series are connected in parallel between the connection point of Ds1 and L22 and VO1, and a control end of each of the plurality of second switches S2k is connected to an output end of the digital controller 1121.
The transformer driver 210 includes a main side switching transistor Q1, a main side capacitor C1, and a main side controller 2101. One end of Q1 is connected with an L11 synonym end, the other end of Q1 is connected with the ground potential of a main edge, and Q1 can be NMOS; c1 is connected in parallel with Q1, C1 comprises at least the parasitic capacitor of Q1, C1 can comprise the parasitic capacitor of Q1 and an auxiliary capacitor, and the parasitic capacitor is connected in parallel with the auxiliary capacitor; the input end of the main side controller 2101 is connected with the L11 synonym end, and the output end of the main side controller 2101 is connected with the Q1 control end.
The working principle of the power converter control circuit provided by the embodiment of the application is as follows:
the main side switching transistor Q1 is turned on and off alternately, and when Q1 is turned on, the current of the main side coil L11 rises, and energy is stored in L11. At this time, the secondary diode Ds1 is turned off, and no energy is transmitted to the output terminal.
When Q1 is off, the energy stored in L11 is transferred to the secondary side. The energy in the leakage inductance of X1 is not transmitted to the secondary side, and in order to prevent the energy in the leakage inductance from being dissipated, the leakage inductance of X1 resonates with the primary side capacitor C1. The energy transferred to the secondary side is split into two parts, one part is trapped and stored by the storage capacitor bank 112 and the other part is transferred to the output terminal through Ds 1. Secondary side signal detection circuit 111 adjusts the energy trapped by storage capacitor bank 112 based on the secondary side electrical signal it detects. When the detected secondary side electrical signal is lower than the preset voltage, the energy storage capacitor bank 112 intercepts less energy, and more energy is transmitted to the output end; when the detected secondary side electrical signal is higher than the preset voltage, the energy storage capacitor intercepts more energy, less energy can be transmitted to the output end, and the output voltage can be adjusted by controlling the energy transmitted to the output end.
Referring to fig. 5, a first sampling resistor Rs1 and a second sampling resistor Rs2 form a sampling circuit for an output voltage, and the output voltage VO1 is sampled to obtain VO1S. VO1S is compared with the first reference voltage VREF1 through a comparator COMP 1. COMP1 outputs a regulated voltage VCCTRL and controls the digital controller 1121, the digital controller 1121 being coupled to the first capacitive element Cs1 and controlling the size of Cs 1.
When the first capacitance element Cs1 is small, the operation waveform is as shown in fig. 8 (a). One duty cycle of the power converter is divided into 3 phases. t1 to t2 are the first phases in which the gate voltage VG1 of the first switch Q1 is high and Q1 is turned on. The Q1 gate voltage VD1 is 0, the positive electrode voltage VS1 of the secondary diode Ds1 is clamped at a negative voltage, ds1 is turned off, and no current flows through Ds 1. t2 to t3 are the second phase, the switch-off is performed at the time point Q1 at t2, the VD1 voltage rises, and energy is transferred from the primary side to the secondary side, and because Cs1 is smaller, VS1 rises rapidly until Ds1 positive voltage VS1 reaches the sum of the output voltage and the diode turn-on voltage. T3 to T are the third phases in which energy is transferred to the output via Ds 1. The leakage inductance of the secondary coil L22 resonates with Cs1 after the Ds1 current drops to 0. And the switch is turned back on at the time point Q1. When the first storage capacitor Cs1 is large, the operation waveform is as shown in fig. 8 (b). In the second phase, Q1 is turned off, VD1 voltage is raised, energy is transferred from the primary side to the secondary side, and because Cs1 is larger, a longer time is required to raise VS1 to the sum of the output voltage and the Ds1 on voltage. In this process more energy that would have been transferred to the output through Ds1 is trapped by Cs1 and therefore less energy is transferred to the output than if Cs1 were smaller, the output voltage is lower.
When the output voltage is higher than the preset voltage, i.e., VO1S is higher than VREF1, the regulated voltage VCCTRL output by the comparator COMP1 is high, resulting in an increase in Cs 1. Cs1 traps more energy transferred to the output, resulting in a drop in output voltage. Similarly, when the output voltage is lower than the preset voltage, i.e., VO1S is lower than VREF1, the regulated voltage VCCTRL output by the comparator COMP1 is low, resulting in a decrease in Cs 1. Cs1 traps less energy transferred to the output, resulting in an increase in output voltage. Therefore, the output voltage fluctuates around the preset voltage, and the ripple wave of the output voltage can be reduced by utilizing the filtering function of the output capacitor Co, so that the accurate and stable output voltage is obtained.
Referring to fig. 5, the first capacitance element Cs1 includes a plurality of first capacitors Cs1k (k=1, 2 … N) having one end connected to the Ds1 positive electrode and the other end connected to one end of the first switch S1k (k=1, 2, … N), and the other end of S1k (k=1, 2, … N) connected to GND 2. Specifically, S1k (k=1, 2, … N) may be MOS, and S1k (k=1, 2, … N) may be NMOS. The digital controller 1121 controls on or off of S1k (k=1, 2, … N) according to the comparison result of the comparator COMP1, so that the magnitude of the energy storage capacitance value actually connected to the circuit can be adjusted. When the output voltage is higher than the preset voltage, i.e., VO1S is higher than VREF1, VCCTRL controls digital controller 1121 to turn on more switches, increase the value of the storage capacitor, and trap more energy to reduce the output voltage. When the output voltage is lower than the preset voltage, i.e., VO1S is lower than VREF1, VCCTRL controls digital controller 1121 to turn off more switches, reduce the value of the storage capacitor, and trap less energy to increase the output voltage.
Referring to fig. 6, the second capacitor Cs2 has one end connected to the positive electrode Ds1 and the other end connected to the negative electrode Ds 1. The comparator COMP1 compares the magnitudes of VO1S and VREF1 and outputs a regulated voltage VCCTRL to control the digital controller 1121, the digital controller 1121 being coupled to Cs2 and controlling the magnitude of Cs 2. The principle of the embodiment shown in fig. 6 is similar to that of the embodiment shown in fig. 4, in that immediately after Q1, the voltage across Cs2 is negative, so that in order to turn on Ds1, cs2 needs to be charged to the turn-on voltage of Ds1 first, and therefore, a part of the energy transmitted to the output terminal is trapped by Cs 2. The energy trapped by Cs2 can be regulated by regulating the size of Cs2, cs2 is increased when the output voltage is higher than the preset voltage, cs2 is reduced when the output voltage is lower than the preset voltage, and thus the size of the output voltage can be controlled.
Referring to fig. 7, the second capacitive element includes a plurality of second capacitors Cs2k (k=1, 2 … N), one end of the second capacitor Cs2k (k=1, 2 … N) is connected to the Ds1 positive electrode, the other end is connected to one end of the second switch S2k (k=1, 2, … N), and the other end of the second switch S2k (k=1, 2, … N) is connected to the Ds1 negative electrode. Specifically, S2k (k=1, 2, … N) may be MOS, and S2k (k=1, 2, … N) may be PMOS. The digital controller 1121 controls on or off of S2k (k=1, 2, … N) according to the comparison result of the comparator COMP1, so that the magnitude of the energy storage capacitance value actually connected to the circuit can be adjusted. When the output voltage is higher than the preset voltage, i.e., VO1S is higher than VREF1, VCCTRL controls digital controller 1121 to turn on more switches, increase the value of the storage capacitor, and trap more energy to reduce the output voltage. When the output voltage is lower than the preset voltage, i.e., VO1S is lower than VREF1, VCCTRL controls digital controller 1121 to turn off more switches, reduce the value of the storage capacitor, and trap less energy to increase the output voltage.
Referring to fig. 9, fig. 9 is another circuit diagram of a power converter and a control circuit thereof according to an embodiment of the application, where the power converter and the control circuit thereof include: transformer X1, transformer driver 210, secondary side controller 110, secondary side diode Ds1, output capacitance Co, and load. The same-name end of a main side coil L11 of the transformer is connected with a power supply voltage, the different-name end of the L11 is connected with one end of a transformer driver 210, and the other end of the transformer driver 210 is connected with a main side ground potential GND 1; the same-name end of a secondary coil L22 of the transformer is connected with the negative electrode of the secondary diode Ds1, the different-name end of the secondary coil L22 is connected with the output voltage VO1, the positive electrode of the secondary diode Ds1 is connected with the secondary ground potential GND2, and the output capacitor Co and the load are connected between the output voltages VO1 and GND2 in parallel.
The secondary side controller 110 includes a secondary side signal detection circuit 111 and an energy storage capacitor group 112, an input end of the secondary side signal detection circuit 111 is connected with any position of the secondary side circuit, an output end of the secondary side signal detection circuit 111 is connected with a control end of the energy storage capacitor 112, the energy storage capacitor group has three energy storage ends, a first energy storage end is connected to a connection point between Ds1 and L22, a second energy storage end is connected with VO1, a third energy storage end is connected with GND2, and the secondary side circuit is a circuit communicated with a secondary side coil L22 of the transformer X1.
An embodiment of the present application provides a power converter control circuit including: the transformer, the transformer driver, the secondary side controller, the secondary side diode, the output capacitor and the load; the secondary diode and the load are sequentially connected in series between two ends of a secondary coil of the transformer, and the output capacitor is connected with the load in parallel; the secondary side controller comprises a secondary side signal detection circuit and an energy storage capacitor group, wherein the input end of the secondary side signal detection circuit is connected with any position of the secondary side circuit, the output end of the secondary side signal detection circuit is connected with the control end of the energy storage capacitor, the energy storage capacitor group is provided with three energy storage ends, the first energy storage end is connected to a connection point of the secondary side diode and a secondary side coil of the transformer, the second energy storage end is connected with the output voltage, and the third energy storage end is connected with the secondary side ground potential. The secondary side circuit is a circuit communicated with a secondary side coil of the transformer. The embodiment of the application provides a secondary side signal detection circuit to obtain an electrical signal of the secondary side circuit, so that the working state of the power converter is judged, and the capacitance value of the energy storage capacitor is correspondingly adjusted according to the working state of the power converter, so that the energy transmitted to the output end is controlled.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the apparatus class embodiments, the description is relatively simple as it is substantially similar to the method embodiments, and reference is made to the description of the method embodiments for relevant points.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes. It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.