技术领域technical field
本发明涉及一种高压金属氧化物半导体晶体管(Metal-Oxide-SemiconductorField Effect Transistor，MOSFET)，尤指一种整合有电流检测元件的高压MOSFET。The invention relates to a high-voltage metal-oxide-semiconductor transistor (Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET), especially a high-voltage MOSFET integrated with a current detection element.
背景技术Background technique
高压MOSFET是一种半导体元件，一般是指可以耐受超过5V以上的漏源极跨压(drain-to-source voltage)的MOSFET。应用上，可以用来切换负载，或是用于电源管理上在不同电压电位间的转换，或是做为高功率放大器中的功率元件。A high-voltage MOSFET is a semiconductor element, and generally refers to a MOSFET that can withstand a drain-to-source voltage of more than 5V. In application, it can be used to switch loads, or to switch between different voltage potentials in power management, or as a power element in a high-power amplifier.
高压MOSFET往往需要操作于高电流。图1A显示现有的一种电流检测架构。高压MOSFET 10的源端S直接连接到一个检测电阻RCS1，其跨压VCS可以忠实的反映流通电流ID，提供给其他电路作相对应的控制。但是，这样的检测架构下，流通电流ID全部都必须流经检测电阻RCS1。对于相当大的流通电流ID而言，检测电阻RCS1会产生相当可观的能量损耗。High voltage MOSFETs are often required to operate at high currents. Figure 1A shows an existing current sensing architecture. The source terminal S of the high-voltage MOSFET 10 is directly connected to a detection resistor RCS1, and its cross-voltage VCS can faithfully reflect the current ID , which can be provided to other circuits for corresponding control. However, under such a detection architecture, all the current ID must flow through the detection resistorRCS1 . For a relatively large flow current ID, the sense resistorRCS1 will cause a considerable energy loss.
图1B显示现有的另一种电流检测架构。高压MOSFET 12整合有一电流检测高压MOSFET NCS以及主要高压MOSFET NM。电流检测高压MOSFET NCS的检测端CS与检测电阻RCS2串接，而主要高压MOSFET NM的源端S直接接地。利用电流映射(current mirror)的原理，使流经电流检测高压MOSFET NCS的电流大约与主要高压MOSFET NM的电流成比例。如此，检测电阻RCS2的跨压VCS大致反映流通电流ID，且大多数的流通电流ID并没有流过检测电阻RCS2，检测电阻RCS2不会消耗太多能量。Figure 1B shows another existing current sensing architecture. The high voltage MOSFET 12 integrates a current sensing high voltage MOSFET NCS and main high voltage MOSFET NM. The detection terminal CS of the current detection high-voltage MOSFET NCS is connected in series with the detection resistor RCS2, and the source terminal S of the main high-voltage MOSFET NM is directly grounded. Using the principle of current mirror, the current flowing through the current sensing high-voltage MOSFET NCS is approximately proportional to the current of the main high-voltage MOSFET NM. In this way, the cross-voltage VCS of the detection resistorRCS2 roughly reflects the current ID, and most of the current ID does not flow through the detection resistorRCS2 , so the detection resistor RCS2 does not consume too much energy.
图1A与图1B也同时隐含了一件事，正常操作时，高压MOSFET 10与12都可能不得不击穿而释放能量。以高压MOSFET 12为例，在当高压MOSFET 12从导通状态(开启)，刚刚切换到不导通状态(关闭)时，电感LP的电流将对高压MOSFET 12的漏端D充电而可能产生超过高压MOSFET12的击穿电压的高压。功率元件有一个规格，称为单脉冲雪崩能量(Energyduring avalanche for single pulse，EAS)，其指的是功率元件在一单脉冲雪崩操作下，可以释放的最大能量。EAS越大，通常意味着功率元件比较强壮，对于能量释放的比较均匀。FIG. 1A and FIG. 1B also imply one thing, during normal operation, both high voltage MOSFETs 10 and 12 may have to break down and release energy. Taking the high-voltage MOSFET 12 as an example, when the high-voltage MOSFET 12 has just switched from the conduction state (on) to the non-conduction state (off), the current of the inductor LP will charge the drain terminal D of the high-voltage MOSFET 12, which may generate more than The breakdown voltage of the high voltage MOSFET 12 is high. The power element has a specification called Energyduring avalanche for single pulse (EAS), which refers to the maximum energy that the power element can release under a single pulse avalanche operation. The larger the EAS, usually means that the power element is stronger and the energy release is more uniform.
发明内容Contents of the invention
本发明实施例公开一种高压半导体元件，具有良好的单脉冲雪崩能量。该高压半导体元件包含有一主要高压开关元件以及一电流检测元件。该主要高压开关元件包含有数个开关单元，排列为一第一矩阵。每个开关单元具有一开关单元宽度。该电流检测元件包含有数个检测单元，排列为一第二矩阵。每个检测单元具有一检测单元宽度，大于该主要单元宽度。The embodiment of the invention discloses a high-voltage semiconductor element, which has good single-pulse avalanche energy. The high voltage semiconductor element includes a main high voltage switch element and a current detection element. The main high-voltage switch element includes several switch units arranged in a first matrix. Each switch unit has a switch unit width. The current detection element includes several detection units arranged in a second matrix. Each detection unit has a detection unit width greater than the main unit width.
本发明实施例公开一种高压半导体元件，具有良好的单脉冲雪崩能量。该高压半导体元件包含有一主要高压开关元件以及一电流检测元件。该主要高压开关元件包含有数个开关单元，排列为一第一矩阵。每个开关单元具有一第一接触洞比例。该电流检测元件包含有数个检测单元，排列为一第二矩阵。每个检测单元具有一第二接触洞比例，大于该第一接触洞比例。The embodiment of the invention discloses a high-voltage semiconductor element, which has good single-pulse avalanche energy. The high voltage semiconductor element includes a main high voltage switch element and a current detection element. The main high-voltage switch element includes several switch units arranged in a first matrix. Each switch unit has a first contact hole ratio. The current detection element includes several detection units arranged in a second matrix. Each detection unit has a second contact hole ratio which is greater than the first contact hole ratio.
本发明实施例公开一种制作方法，适用于制造一高压半导体元件于一半导体基底上。该制造方法包含有：在该半导体基底上形成图案化的一栅导电层；对该半导体基底进行掺杂制作工艺，以于该半导体基底上形成一体区以及一源区，其中，该体区与该源区由同一掩模(mask)所定义，且该掩模包含有该栅导电层；形成一多晶硅间介电层于该栅导电层上；去除部分的该多晶硅间介电层，以形成一接触洞；以及，在该接触洞内形成一金属层；其中，去除部分的该多晶硅间介电层的该步骤也去除了部分的该源区，因此，该金属层可同时接触该体区与该源区。The embodiment of the invention discloses a manufacturing method, which is suitable for manufacturing a high-voltage semiconductor element on a semiconductor substrate. The manufacturing method includes: forming a patterned gate conductive layer on the semiconductor substrate; performing a doping process on the semiconductor substrate to form an integral region and a source region on the semiconductor substrate, wherein the body region and a source region are formed on the semiconductor substrate. The source region is defined by the same mask (mask), and the mask includes the gate conductive layer; forming an interpolysilicon dielectric layer on the gate conductive layer; removing part of the interpolysilicon dielectric layer to form a contact hole; and, forming a metal layer in the contact hole; wherein, the step of removing part of the interpolysilicon dielectric layer also removes part of the source region, so that the metal layer can simultaneously contact the body region with the source area.
本发明实施例公开一种高压半导体元件，形成于一半导体基底上，包含有一栅导电层、一体区以及一源区。该栅导电层作为该高压半导体元件的一栅极。该体区以及该源区，分别做为该高压半导体元件的一体极以及一源极。该半导体基底作为该高压半导体元件的一漏极，且该体区以及该源区由同一掩模所定义，通过掺杂制作工艺而形成。The embodiment of the present invention discloses a high-voltage semiconductor element, which is formed on a semiconductor substrate and includes a gate conductive layer, an integral region and a source region. The gate conductive layer is used as a gate of the high voltage semiconductor element. The body region and the source region are respectively used as a body electrode and a source electrode of the high-voltage semiconductor device. The semiconductor base is used as a drain of the high-voltage semiconductor element, and the body region and the source region are defined by the same mask and formed through a doping process.
附图说明Description of drawings
图1A与图1B显示现有的两种电流检测架构的示意图；FIG. 1A and FIG. 1B show schematic diagrams of two existing current detection architectures;
图2显示图1B中的高压MOSFET 12的上视图；FIG. 2 shows a top view of the high voltage MOSFET 12 in FIG. 1B;
图3举例显示图2中区域20的一上视图；Figure 3 shows an example of a top view of area 20 in Figure 2;
图4为沿着图2中的IV-IV线的一剖视图；Fig. 4 is a sectional view along line IV-IV in Fig. 2;
图5举例显示图2中区域20的另一可能的上视图；Fig. 5 shows another possible top view of area 20 in Fig. 2 by way of example;
图6为图5中沿着VI-VI线的一剖视图；Fig. 6 is a sectional view along line VI-VI in Fig. 5;
图7显示图6中的寄生元件，经历EAS测试时的等效电路图；Fig. 7 shows the parasitic element in Fig. 6, the equivalent circuit diagram when undergoing EAS test;
图8举例显示图2中区域20的另一可能的上视图；Fig. 8 shows another possible top view of area 20 in Fig. 2 by way of example;
图9举例显示图2中区域20的另一可能的上视图；Fig. 9 shows another possible top view of area 20 in Fig. 2 by way of example;
图10举例显示图2中区域20的另一可能的上视图；Fig. 10 shows another possible top view of area 20 in Fig. 2 by way of example;
图11举例显示图2中区域20的另一可能的上视图；Fig. 11 shows another possible top view of area 20 in Fig. 2 by way of example;
图12举例显示图2中区域20的另一可能的上视图；Fig. 12 shows another possible top view of area 20 in Fig. 2 by way of example;
图13显示了一种制作方法60的示意图，适用于制造图1B中的高压MOSFET 12；FIG. 13 shows a schematic diagram of a manufacturing method 60, which is suitable for manufacturing the high-voltage MOSFET 12 in FIG. 1B;
图14-1～图14-6为高压MOSFET 12的示意图，在制造方法60的不同阶段的剖视图；14-1 to 14-6 are schematic diagrams of the high-voltage MOSFET 12, cross-sectional views at different stages of the manufacturing method 60;
图15显示本发明所实施的一种制作方法90的示意图，适用于制造图1B中的高压MOSFET 12；FIG. 15 shows a schematic diagram of a manufacturing method 90 implemented by the present invention, which is suitable for manufacturing the high-voltage MOSFET 12 in FIG. 1B;
图16-1～图16-4为高压MOSFET 12，在制造方法90的不同阶段的剖视图。16-1 to 16-4 are cross-sectional views of high voltage MOSFET 12 at different stages of manufacturing method 90 .
符号说明Symbol Description
10 高压MOSFET10 High Voltage MOSFETs
12 高压MOSFET12 High voltage MOSFETs
14 源极14 source
16 检测极16 detection poles
18 栅极18 grid
20 区域20 areas
22 场氧化层22 field oxide
24 电流检测元件区24 Current detection element area
26 高压开关元件区26 High voltage switching element area
32 背面金属层32 back metal layer
34 N型基底34 N-type base
36 N型外延层36 N-type epitaxial layer
38 P型体区38 P-type body region
40、40’ N+源区40, 40' N+ source region
42 栅氧化层42 Gate Oxide
44 栅导电层44 Gate conductive layer
45 多晶硅间介电层45 Interpoly Dielectric Layer
46 金属层46 metal layer
48、481、48’ 接触洞48, 481, 48’ contact holes
50 垂直方向栅线50 vertical grid lines
52 水平方向栅线52 horizontal grid lines
60、90 制作方法60, 90 production method
62、64、66、68、70、72、74、76、78、80、92、94步骤62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 92, 94 steps
BJCS、BJMAIN 双极性接面晶体管BJCS , BJMAIN Bipolar Junction Transistor
CCS1、CCS2、CCS11、CCS12、CCS21、CCS22、CCS31、CCS32检测单元CCS1 , CCS2 , CCS11 , CCS12 , CCS21 , CCS22 , CCS31 , CCS32 detection units
CM1、CM2、CM11、CM12、CM21、CM22、CM31、CM32开关单元CM1 , CM2 , CM11 , CM12 , CM21 , CM22 , CM31 , CM32 switch units
CONWD-CS1、CONWD-MAIN 接触洞宽度CONWD-CS1 , CONWD-MAIN contact hole width
CS 检测端CS detection terminal
D 漏端D drain
G 栅端G grid terminal
GWTHMAIN、GWTHCS 栅线宽度GWTHMAIN , GWTHCS gate line width
ID 流通电流ID flow current
LP 电感LP inductance
NCS 电流检测高压MOSFETNCS Current Sense High Voltage MOSFETs
NM 主要高压MOSFETNM main high voltage MOSFET
PTCHCS、PTCHCS1、PTCHCS2、PTCHCS3 检测单元宽度PTCHCS , PTCHCS1 , PTCHCS2 , PTCHCS3 detection unit width
PTCHMAIN 开关单元宽度PTCHMAIN switch unit width
RCS1 检测电阻RCS1 sense resistor
RCS2 检测电阻RCS2 sense resistor
RCS、RMAIN 寄生电阻RCS , RMAIN parasitic resistance
S 源端S source
VCS 跨压VCS voltage across
IV-IV、VI-VI 线IV-IV, VI-VI line
具体实施方式Detailed ways
在本说明书中，有一些相同的符号，其表示具有相同或是类似的结构、功能、原理的元件，且为业界具有一般知识能力者可以依据本说明书的教导而推知。为说明书的简洁度考虑，相同的符号的元件将不再重述。In this specification, there are some same symbols, which represent elements with the same or similar structure, function, and principle, and those with general knowledge in the industry can infer based on the teaching of this specification. For the sake of brevity in the description, elements with the same symbols will not be repeated.
图2显示图1B中的高压MOSFET 12的上视图，其形成于一半导体芯片上。半导体芯片的一正面上有栅极18、源极14以及检测极16，可以分别做为高压MOSFET 12的栅端G、源端S、以及检测端CS。半导体芯片的一背面(未显示)则有一漏极，可以作为高压MOSFET 12的漏端D。FIG. 2 shows a top view of the high voltage MOSFET 12 of FIG. 1B, which is formed on a semiconductor chip. A front side of the semiconductor chip has a gate 18 , a source 14 and a detection terminal 16 , which can be used as the gate terminal G, the source terminal S and the detection terminal CS of the high voltage MOSFET 12 respectively. A backside (not shown) of the semiconductor chip has a drain, which can be used as the drain terminal D of the high voltage MOSFET 12 .
图3举例显示图2中区域20的一上视图。图4为沿着图2中的IV-IV线的一剖视图。FIG. 3 shows an example of a top view of the area 20 in FIG. 2 . FIG. 4 is a cross-sectional view along line IV-IV in FIG. 2 .
图3主要显示了栅导电层44以及场氧化层22的图案。在图3中，场氧化层22所围成的是一电流检测元件区24，用来形成电流检测高压MOSFET NCS；电流检测元件区24与场氧化层22之外的是一高压开关元件区26，用来形成主要高压MOSFET NM。电流检测高压MOSFETNCS可以视为由数个完全相同的检测单元排成一个矩阵所构成，如同检测单元CCS1与CCS2所举例的。类似的，主要高压MOSFET NM可以视为由数个完全相同的开关单元排列为另一矩阵所构成，如同开关单元CM1与CM2所举例的。每个检测单元有一开关单元宽度PTCHMAIN，每个检测单元有一检测单元宽度PTCHCS。在图3中，每个检测单元与每个开关单元都一样，所以开关单元宽度PTCHMAIN等于检测单元宽度PTCHCS。在高压开关元件区26内或是电流检测元件区24内，栅导电层44的栅宽度(gate width)都一样。简单的说，高压开关元件区26与电流检测元件区24共用同一个单元。FIG. 3 mainly shows the patterns of the gate conductive layer 44 and the field oxide layer 22 . In FIG. 3 , the field oxide layer 22 surrounds a current detection element area 24 for forming a current detection high-voltage MOSFET NCS; the area outside the current detection element area 24 and the field oxide layer 22 is a high-voltage switching element area 26 , used to form the main high-voltage MOSFET NM. The current detection high-voltage MOSFET NCS can be regarded as composed of several identical detection units arranged in a matrix, as the detection units CCS1 and CCS2 are exemplified. Similarly, the main high-voltage MOSFET NM can be regarded as composed of several identical switch units arranged in another matrix, as exemplified by the switch units CM1 and CM2 . Each detection unit has a switching unit width PTCHMAIN , and each detection unit has a detection unit width PTCHCS . In FIG. 3 , each detection unit is the same as each switch unit, so the switch unit width PTCHMAIN is equal to the detection unit width PTCHCS . In the high voltage switch element region 26 or in the current detection element region 24, the gate width of the gate conductive layer 44 is the same. In short, the high-voltage switch element area 26 and the current detection element area 24 share the same unit.
图4中显示有背面金属层32、N型基底34、N型外延层36、P型体区38、N+源区40、栅氧化层42、栅导电层44、多晶硅间介电层45、金属层46、场氧化层22。堆叠的一栅氧化层42与一栅导电层44构成一栅结构。图4中同时显示有数个接触洞48，由去除部分的多晶硅间介电层45所构成。在高压开关元件区26中，金属层46通过接触洞48接触N+源区40与P型体区38，作为高压MOSFET 12的源端S。在电流检测元件区24中，金属层46通过接触洞48接触N+源区40与P型体区38，作为高压MOSFET 12的检测端CS。背面金属层32可以作为高压MOSFET 12的漏端D。所有的栅导电层44都短路在一起，可以作为高压MOSFET 12的栅端G。4 shows a back metal layer 32, an N-type substrate 34, an N-type epitaxial layer 36, a P-type body region 38, an N+ source region 40, a gate oxide layer 42, a gate conductive layer 44, an interpolysilicon dielectric layer 45, a metal layer 46, field oxide layer 22. A gate oxide layer 42 and a gate conductive layer 44 are stacked to form a gate structure. Also shown in FIG. 4 are several contact holes 48 formed by removing part of the inter-polysilicon dielectric layer 45 . In the high-voltage switch element region 26 , the metal layer 46 contacts the N+ source region 40 and the P-type body region 38 through the contact hole 48 , serving as the source terminal S of the high-voltage MOSFET 12 . In the current detection element region 24 , the metal layer 46 contacts the N+ source region 40 and the P-type body region 38 through the contact hole 48 , serving as the detection terminal CS of the high voltage MOSFET 12 . The back metal layer 32 can serve as the drain terminal D of the high voltage MOSFET 12 . All the gate conductive layers 44 are short-circuited together and can be used as the gate terminal G of the high voltage MOSFET 12 .
从实验上得知，当高压MOSFET 12以图3与图4所显示的结构实施时，且电流检测元件区24中的面积以及元件架构都不变时，高压MOSFET 12的EAS，不会随着电流检测元件区24的面积增加而增加。可以猜测得知，电流检测元件区24应该是相对的脆弱，导致大部分的EAS流经电流检测元件区24，而将其烧毁，所以高压MOSFET 12的EAS无法从电流检测元件区24的面积增加变强壮而得利。It is known from experiments that when the high voltage MOSFET 12 is implemented with the structures shown in FIGS. The area of the current detection element region 24 increases to increase. It can be guessed that the current detection element area 24 should be relatively fragile, causing most of the EAS to flow through the current detection element area 24 and burn it, so the EAS of the high voltage MOSFET 12 cannot be increased from the area of the current detection element area 24 Be strong and profit.
在本发明的一实施例中，每个开关单元的开关单元宽度小于每个检测单元的检测单元宽度。每个开关单元具有一第一接触洞比例，其为单一开关单元的接触洞面积对单一开关单元面积的比例。每个检测单元具有一第二接触洞比例，其为单一检测单元的接触洞面积对单一检测单元面积的比例。在另一实施例中，该第二接触洞比例大于该第一接触洞比例。In an embodiment of the present invention, the switch unit width of each switch unit is smaller than the detection unit width of each detection unit. Each switch unit has a first contact hole ratio, which is the ratio of the contact hole area of a single switch unit to the area of a single switch unit. Each detection unit has a second contact hole ratio, which is the ratio of the contact hole area of a single detection unit to the area of a single detection unit. In another embodiment, the second contact hole ratio is greater than the first contact hole ratio.
在本发明的实施例中，因为单元宽度的差异或是接触洞比例的差异，可以使得检测单元变得比较不容易击穿。因此，EAS可能可以通过开关单元而释放。当开关单元的数量增多时，因为能量可以通过较大面积释放，所以EAS就可以相对应的增加。换言之，本发明的实施例可以具有良好的EAS。In the embodiment of the present invention, because of the difference in the cell width or the difference in the proportion of the contact hole, the detection cell becomes less prone to breakdown. Therefore, EAS may be released by switching the unit. When the number of switch units increases, because energy can be released through a larger area, the EAS can increase accordingly. In other words, embodiments of the present invention may have good EAS.
根据本发明的实施例，图5举例显示图2中区域20的另一可能的上视图。图6为图5中沿着VI-VI线的一剖视图。According to an embodiment of the present invention, FIG. 5 exemplarily shows another possible top view of the area 20 in FIG. 2 . FIG. 6 is a cross-sectional view along line VI-VI in FIG. 5 .
图5主要显示了栅导电层44以及场氧化层22的图案。在图5中，电流检测元件区24用来形成图1B中的电流检测高压MOSFET NCS；高压开关元件区26用来形成图1B中的主要高压MOSFET NM。电流检测高压MOSFET NCS可以视为由数个完全相同的检测单元排成一个矩阵所构成，如同检测单元CCS11与CCS12所举例的。类似的，主要高压MOSFET NM可以视为由数个完全相同的开关单元排列为另一矩阵所构成，如同开关单元CM11与CM12所举例的。每个检测单元有一开关单元宽度PTCHMAIN，每个检测单元有一检测单元宽度PTCHCS1。在图5中，单一检测单元与单一开关单元并不相同。与图3相较之下，图5中的电流检测元件区24跟图3中的电流检测元件区24大致相同，但是每两条栅线去除掉一条。因此，如同图5所示，检测单元宽度PTCHCS1大约是开关单元宽度PTCHMAIN的两倍。在本发明的其他实施例中，检测单元宽度大于开关单元宽度，其可能是整数倍或是非整数倍。FIG. 5 mainly shows the patterns of the gate conductive layer 44 and the field oxide layer 22 . In FIG. 5, the current sensing element area 24 is used to form the current sensing high voltage MOSFET NCS in FIG. 1B; the high voltage switching element area 26 is used to form the main high voltage MOSFET NM in FIG. 1B. The current detection high-voltage MOSFET NCS can be regarded as composed of several identical detection units arranged in a matrix, as the detection units CCS11 and CCS12 are exemplified. Similarly, the main high-voltage MOSFET NM can be regarded as composed of several identical switching units arranged in another matrix, as the switching unitsCM11 andCM12 are exemplified. Each detection unit has a switching unit width PTCHMAIN , and each detection unit has a detection unit width PTCHCS1 . In FIG. 5 , the single detection unit is not the same as the single switch unit. Compared with FIG. 3 , the current detection element region 24 in FIG. 5 is substantially the same as the current detection element region 24 in FIG. 3 , but one of every two gate lines is removed. Therefore, as shown in FIG. 5, the detection cell width PTCHCS1 is approximately twice the switching cell width PTCHMAIN . In other embodiments of the present invention, the detection unit width is greater than the switch unit width, which may be an integer multiple or a non-integer multiple.
图6中同时显示有数个接触洞48与481，由去除部分的多晶硅间介电层45所构成。在高压开关元件区26中，金属层46通过接触洞48接触N+源区40与P型体区38，作为高压MOSFET 12的源端S。在电流检测元件区24中，金属层46通过接触洞481接触N+源区40与P型体区38，作为高压MOSFET 12的检测端CS。接触洞481的接触洞宽度CONWD-CS1大于接触洞48的接触洞宽度CONWD-MAIN。背面金属层32可以作为高压MOSFET 12的漏端D。在图6中，检测单元宽度PTCHCS1是开关单元宽度PTCHMAIN的两倍。在高压开关元件区26内或是电流检测元件区24内，栅导电层44的栅宽度(gate width)都一样。多晶硅间介电层45在栅导电层44的侧壁留下来的厚度也差不多都一样。高压开关元件区26的接触洞比例，定义为单一开关单元的接触洞面积对单一开关单元面积的比例，大约等于接触洞宽度CONWD-MAIN除以开关单元宽度PTCHMAIN。电流检测元件区24的接触洞比例，其为单一检测单元的接触洞面积对单一检测单元面积的比例，大约等于接触洞宽度CONWD-CS1除以检测单元宽度PTCHCS1。因此，在图6中，高压开关元件区26的接触洞比例小于电流检测元件区24的接触洞比例。FIG. 6 also shows several contact holes 48 and 481 formed by removing part of the interpoly dielectric layer 45 . In the high-voltage switch element region 26 , the metal layer 46 contacts the N+ source region 40 and the P-type body region 38 through the contact hole 48 , serving as the source terminal S of the high-voltage MOSFET 12 . In the current detection element region 24 , the metal layer 46 contacts the N+ source region 40 and the P-type body region 38 through the contact hole 481 , serving as the detection terminal CS of the high voltage MOSFET 12 . The contact hole width CONWD-CS1 of the contact hole 481 is greater than the contact hole width CONWD-MAIN of the contact hole 48 . The back metal layer 32 can serve as the drain terminal D of the high voltage MOSFET 12 . In FIG. 6, the detection cell width PTCHCS1 is twice the switching cell width PTCHMAIN . In the high voltage switch element region 26 or in the current detection element region 24, the gate width of the gate conductive layer 44 is the same. The thickness of the inter-polysilicon dielectric layer 45 left on the sidewall of the gate conductive layer 44 is almost the same. The contact hole ratio of the high-voltage switching element area 26 is defined as the ratio of the contact hole area of a single switch unit to the area of a single switch unit, which is approximately equal to the contact hole width CONWD-MAIN divided by the switch unit width PTCHMAIN . The contact hole ratio of the current detection element area 24 is the ratio of the contact hole area of a single detection unit to the area of a single detection unit, approximately equal to the contact hole width CONWD-CS1 divided by the detection unit width PTCHCS1 . Therefore, in FIG. 6 , the proportion of contact holes in the high voltage switching element region 26 is smaller than that in the current detecting element region 24 .
图6中也显示了一些寄生元件。NPN双极性接面晶体管(Bipolar JunctionTransistor，BJT)BJMAIN，在高压开关元件区26中，由N+源区40、P型体区38以及N型外延层36所构成。类似的，NPN BJT BJCS是由电流检测元件区24中的N+源区40、P型体区38以及N型外延层36所构成。寄生电阻RMAIN以及RCS分别代表BJT BJMAIN与BJCS的基极(base electrode)到金属层46之间的电阻。Some parasitic elements are also shown in Figure 6. The NPN bipolar junction transistor (Bipolar Junction Transistor, BJT) BJMAIN is composed of an N+ source region 40 , a P-type body region 38 and an N-type epitaxial layer 36 in the high-voltage switch element region 26 . Similarly, the NPN BJT BJCS is composed of the N+ source region 40 , the P-type body region 38 and the N-type epitaxial layer 36 in the current detection element region 24 . The parasitic resistances RMAIN and RCS respectively represent the resistances between the base electrodes of the BJT BJMAIN and BJCS to the metal layer 46 .
图7显示图6中的寄生元件，经历EAS测试时的等效电路图。EAS的电流IEAS从漏端D或是背面金属层32进入。然后流过BJT BJMAIN与BJCS其中导通的一个，而释放到接地线。寄生电阻RMAIN以及RCS越大，越容易造成BJT BJMAIN与BJCS的基极电压升高而导通。Figure 7 shows the equivalent circuit diagram of the parasitic elements in Figure 6 when subjected to EAS testing. The current IEAS of EAS enters from the drain terminal D or the back metal layer 32 . Then it flows through one of BJT BJMAIN and BJCS , which is turned on, and is released to the ground wire. The larger the parasitic resistances RMAIN and RCS are, the easier it is to cause the base voltage of BJT BJMAIN and BJCS to rise and turn on.
图6与图4的高压开关元件区26有相同的接触洞宽度CONWD-MAIN。但相较之下，图6的电流检测元件区24的接触洞宽度CONWD-CS1大于图4的电流检测元件区24的接触洞宽度(未标示)。因此，可以得知图6中的寄生电阻RCS将会小于图4中相对应的寄生电阻。换言之，相较之下，图6的电流检测元件区24在EAS测试之下将比较不会导通，电流IEAS比较可能可以通过大面积的高压开关元件区26的BJTBJMAIN释放。The high voltage switching element region 26 in FIG. 6 has the same contact hole width CONWD-MAIN as that in FIG. 4 . But in comparison, the contact hole width CONWD-CS1 of the current detection element region 24 in FIG. 6 is larger than the contact hole width (not shown) in the current detection element region 24 of FIG. 4 . Therefore, it can be known that the parasitic resistance RCS in FIG. 6 will be smaller than the corresponding parasitic resistance in FIG. 4 . In other words, in comparison, the current detection element region 24 in FIG. 6 will not conduct under the EAS test, and the current IEAS is more likely to be released through the BJTBJMAIN of the large-area high-voltage switching element region 26 .
实验上也证明了，将高压MOSFET 12的上视图，从图3改变为图5，可以确实地增加高压MOSFET 12的EAS。Experiments have also proved that changing the top view of the high voltage MOSFET 12 from FIG. 3 to FIG. 5 can indeed increase the EAS of the high voltage MOSFET 12 .
根据本发明的实施例，图8举例显示图2中区域20的另一可能的上视图。图8类似图5与图3，主要显示了栅导电层44以及场氧化层22的图案。在图8中，电流检测元件区24具有数个完全相同的检测单元，排成一个矩阵，如同检测单元CCS21与CCS22所举例的。类似的，高压开关元件区26具有数个完全相同的开关单元，排列为另一矩阵，如同开关单元CM21与CM22所举例的。每个检测单元有一开关单元宽度PTCHMAIN，每个检测单元有一检测单元宽度PTCHCS2。与图3相较之下，图8中的电流检测元件区24与图3中的电流检测元件区24相同，但是每三条栅线只保留一条，而删除了其他两条。因此，如同图8所示，检测单元宽度PTCHCS2大约是开关单元宽度PTCHMAIN的三倍。According to an embodiment of the present invention, FIG. 8 exemplarily shows another possible top view of the area 20 in FIG. 2 . FIG. 8 is similar to FIG. 5 and FIG. 3 , mainly showing the patterns of the gate conductive layer 44 and the field oxide layer 22 . In FIG. 8 , the current detection element area 24 has several identical detection units arranged in a matrix, as the detection units CCS21 and CCS22 are exemplified. Similarly, the high-voltage switching element area 26 has several identical switching units arranged in another matrix, as the switching units CM21 and CM22 are exemplified. Each detection unit has a switching unit width PTCHMAIN , and each detection unit has a detection unit width PTCHCS2 . Compared with FIG. 3 , the current detection element area 24 in FIG. 8 is the same as the current detection element area 24 in FIG. 3 , but only one of every three gate lines is reserved, and the other two are deleted. Therefore, as shown in FIG. 8, the detection cell width PTCHCS2 is approximately three times the switching cell width PTCHMAIN .
图8中，在高压开关元件区26内或是电流检测元件区24内，栅导电层44的栅宽度都一样。高压开关元件区26的接触洞比例大约等于开关单元的栅间隙(两条栅线间的距离)对开关单元宽度PTCHMAIN的比例。类似的，电流检测元件区24的接触洞比例大约等于检测单元的栅间隙对检测单元宽度PTCHCS2的比例。明显的，图8中的高压开关元件区26的接触洞比例，小于电流检测元件区24的接触洞比例。In FIG. 8 , the gate width of the gate conductive layer 44 is the same in both the high voltage switch element region 26 and the current detection element region 24 . The ratio of the contact hole in the high voltage switch element region 26 is approximately equal to the ratio of the gate gap (distance between two gate lines) of the switch unit to the width PTCHMAIN of the switch unit. Similarly, the ratio of the contact holes in the current detection element region 24 is approximately equal to the ratio of the gate gap of the detection unit to the width PTCHCS2 of the detection unit. Obviously, the proportion of contact holes in the high voltage switch element region 26 in FIG. 8 is smaller than the proportion of contact holes in the current detection element region 24 .
在图5与图8中，高压开关元件区26中的开关单元，大致跟电流检测元件区24中的检测单元，有类似或是一样的单元结构。举例来说，图5与图8中开关单元与检测单元在外型上都是长方形，且开关单元与检测单元中的栅导电层44所构成的栅线都只有沿着上下延伸。但本发明并不限于此，在其他实施例中，开关单元与检测单元并不需要有一样或是类似的单元结构。In FIG. 5 and FIG. 8 , the switching units in the high-voltage switching element area 26 generally have a similar or the same unit structure as the detecting units in the current detecting element area 24 . For example, the switch unit and the detection unit in FIG. 5 and FIG. 8 are both rectangular in shape, and the gate lines formed by the gate conductive layer 44 in the switch unit and the detection unit only extend up and down. But the present invention is not limited thereto. In other embodiments, the switch unit and the detection unit do not need to have the same or similar unit structure.
根据本发明的实施例，图9举例显示图2中区域20的另一可能的上视图。在图9中，电流检测元件区24具有数个完全相同的检测单元，排成一个矩阵，如同检测单元CCS31与CCS32所举例的。类似的，高压开关元件区26具有数个完全相同的开关单元，排列为另一矩阵，如同开关单元CM31与CM32所举例的。检测单元宽度PTCHCS3大约是开关单元宽度PTCHMAIN的两倍。图9中，开关单元的接触洞比例大约等于单一开关单元中，栅导电层44之外的区域占整个单一开关单元的面积比例；检测单元的接触洞比例大约等于单一检测单元中，栅导电层44之外的区域占整个单一检测单元的面积比例。从图9可以得知，开关单元的接触洞比例小于检测单元的接触洞比例。According to an embodiment of the present invention, FIG. 9 exemplarily shows another possible top view of the area 20 in FIG. 2 . In FIG. 9 , the current detection element area 24 has several identical detection units arranged in a matrix, as the detection units CCS31 and CCS32 are exemplified. Similarly, the high voltage switching element area 26 has several identical switching units arranged in another matrix, as the switching unitsCM31 andCM32 are exemplified. The detection cell width PTCHCS3 is approximately twice the switching cell width PTCHMAIN . In Fig. 9, the ratio of the contact hole of the switch unit is approximately equal to the area ratio of the area outside the gate conductive layer 44 in the single switch unit; the ratio of the contact hole of the detection unit is approximately equal to that of the gate conductive layer in the single detection unit Areas other than 44% account for the area ratio of the entire single detection unit. It can be seen from FIG. 9 that the ratio of the contact hole of the switch unit is smaller than that of the detection unit.
在图9中，开关单元与检测单元在外型上都是长方形。开关单元的栅线只有沿着上下延伸，但是检测单元的栅线不只是上下延伸，也有左右延伸。图9中，高压开关元件区26(作为主要高压MOSFET NM)的栅图案(由栅导电层44所构成)，明显的跟电流检测元件区24(作为电流检测高压MOSFET NCS)的栅图案不同。而且，图9中，电流检测元件区24的栅图案不只是通过上下垂直方向栅线50，也通过左右水平方向栅线52，来跟高压开关元件区26的栅图案相电连接。电流检测元件区24的栅图案通过两个方向跟压开关元件区26的栅图案相连接，一个是水平方向，另一个是垂直方向。In FIG. 9 , the switch unit and the detection unit are both rectangular in shape. The gate lines of the switch unit only extend up and down, but the gate lines of the detection unit not only extend up and down, but also extend left and right. In FIG. 9, the gate pattern (consisting of the gate conductive layer 44) of the high-voltage switch element region 26 (as the main high-voltage MOSFET NM) is obviously different from the gate pattern of the current detection element region 24 (as the current-detection high-voltage MOSFET NCS). Moreover, in FIG. 9 , the gate pattern of the current detection element region 24 is electrically connected to the gate pattern of the high voltage switching element region 26 not only through the vertical gate lines 50 but also through the left and right horizontal gate lines 52 . The gate pattern of the current detection element region 24 is connected to the gate pattern of the pressure switch element region 26 through two directions, one is horizontal direction and the other is vertical direction.
根据本发明的实施例，图10举例显示图2中区域20的另一可能的上视图。图10与图9的差异，在于电流检测元件区24中的检测单元的数目与排列成的矩阵。图9中，6个检测单元排列成2x3的矩阵。图10中，5个检测单元排列成H型的矩阵。According to an embodiment of the present invention, FIG. 10 exemplarily shows another possible top view of the area 20 in FIG. 2 . The difference between FIG. 10 and FIG. 9 lies in the number and matrix arrangement of the detection units in the current detection element area 24 . In Figure 9, six detection units are arranged in a 2x3 matrix. In Fig. 10, five detection units are arranged in an H-shaped matrix.
根据本发明的实施例，图11举例显示图2中区域20的另一可能的上视图。在图11中，高压开关元件区26内的开关单元在外型上是长方形，而电流检测元件区24内的检测单元在外型上是正六角形(Hexagon)。图11中，开关单元的接触洞比例小于检测单元的接触洞比例。According to an embodiment of the present invention, FIG. 11 exemplarily shows another possible top view of the area 20 in FIG. 2 . In FIG. 11 , the switch units in the high-voltage switching element area 26 are rectangular in shape, while the detection units in the current detection element area 24 are in a regular hexagonal shape. In FIG. 11 , the ratio of the contact hole of the switch unit is smaller than the ratio of the contact hole of the detection unit.
根据本发明的实施例，图12举例显示图2中区域20的另一可能的上视图。在图12中，高压开关元件区26内的开关单元，以及电流检测元件区24内的检测单元，在外型上都是正六角形。图12中的开关单元与检测单元具有一样的栅线宽，但开关单元具有较小的边长。因此，图12中，开关单元的接触洞比例小于检测单元的接触洞比例。According to an embodiment of the present invention, FIG. 12 illustrates another possible top view of the area 20 in FIG. 2 . In FIG. 12 , the switch units in the high-voltage switch element area 26 and the detection units in the current detection element area 24 are regular hexagonal in shape. The switch unit in FIG. 12 has the same gate line width as the detection unit, but the switch unit has a smaller side length. Therefore, in FIG. 12 , the ratio of the contact hole of the switch unit is smaller than the ratio of the contact hole of the detection unit.
图13显示了一种制作方法60，适用于制造图1B中的高压MOSFET 12于一半导体基底上，而产生图4或是图6的剖视图。图14-1～图14-6为高压MOSFET 12，在制造方法60的不同阶段的剖视图。FIG. 13 shows a fabrication method 60 suitable for fabricating the high voltage MOSFET 12 shown in FIG. 1B on a semiconductor substrate to produce the cross-sectional view of FIG. 4 or FIG. 6 . 14-1 to 14-6 are cross-sectional views of high voltage MOSFET 12 at different stages of manufacturing method 60 .
制作方法60从步骤62开始，提供N型基底34。Fabrication method 60 begins at step 62 , providing an N-type substrate 34 .
步骤64接续步骤62，在N型基底34上，用外延的方式，形成N型外延层36，如同图14-1所示。Step 64 is continued with step 62, and an N-type epitaxial layer 36 is formed on the N-type substrate 34 by means of epitaxy, as shown in FIG. 14-1 .
步骤66在N型外延层36形成图案化的场氧化层22，如同第14-2图所示。步骤66利用一黄光制作工艺，以一光掩模(在说明书中称为FOX光掩模)定义场氧化层22所在的隔绝区以及主动区，而主动区是用来稍后形成晶体管等主动元件的区域。因为场氧化层22的形成，步骤66也大致定义了高压开关元件区26以及电流检测元件区24。Step 66 forms a patterned field oxide layer 22 on the N-type epitaxial layer 36, as shown in FIG. 14-2. Step 66 uses a yellow light manufacturing process to define the isolation region where the field oxide layer 22 is located and the active region with a photomask (referred to as a FOX photomask in the specification), and the active region is used to form transistors and other active regions later. The area of the element. Step 66 also roughly defines the high voltage switching element region 26 and the current sensing element region 24 due to the formation of the field oxide layer 22 .
步骤68依序的形成栅氧化层42与栅导电层44，堆叠在N型外延层36与场氧化层22上。栅导电层44可以包含有一多晶硅层。Step 68 sequentially forms the gate oxide layer 42 and the gate conductive layer 44 to be stacked on the N-type epitaxial layer 36 and the field oxide layer 22 . The gate conductive layer 44 may include a polysilicon layer.
步骤70图案化栅氧化层42与栅导电层44，如同图14-3所示。步骤70利用一黄光制作工艺，以一光掩模(在说明书中称为GATE光掩模)定义栅导电层44要保留的区域，并用一蚀刻制作工艺去除掉不保留的区域中的栅导电层44与栅氧化层42。剩下来的栅导电层44可以做为栅极或是栅线。在一实施例中，高压开关元件区26以及电流检测元件区24中的栅线宽度GWTHMAIN与GWTHCS一样。Step 70 is to pattern the gate oxide layer 42 and the gate conductive layer 44 , as shown in FIG. 14-3 . Step 70 utilizes a yellow light manufacturing process to define the area where the grid conductive layer 44 will remain with a photomask (referred to as a GATE photomask in the specification), and removes the grid conductive layer in the non-retained area with an etching manufacturing process. layer 44 and gate oxide layer 42 . The remaining gate conductive layer 44 can be used as a gate or a gate line. In one embodiment, the gate line width GWTHMAIN in the high voltage switch element region 26 and the current detection element region 24 is the same as GWTHCS .
步骤72以栅导电层44以及场氧化层22作为一掩模，进行一掺杂制作工艺，在N型外延层36中形成P型体区38。步骤72并没有使用光掩模。举例来说，可以先进行离子注入制作工艺，然后进行扩散制作工艺，让P型体区38扩散到部分导电层44的下方。Step 72 uses the gate conductive layer 44 and the field oxide layer 22 as a mask to perform a doping process to form the P-type body region 38 in the N-type epitaxial layer 36 . Step 72 does not use a photomask. For example, the ion implantation process can be performed first, and then the diffusion process can be performed to allow the P-type body region 38 to diffuse under the part of the conductive layer 44 .
接续步骤72，步骤74采用一光掩模(在说明书中称为N+光掩模)，通过黄光跟掺杂制作工艺，在N型外延层36上形成N+源区40，如同图14-4所示。通过离子注入制作工艺，N+源区40大致形成于导电层44两侧的N型外延层36上。在图14-4中，两两栅导电层44之间有两个N+源区40，彼此的距离由GATE光掩模所定义，两个N+源区40中间曝露出部分的P型体区38。Following step 72, step 74 uses a photomask (referred to as an N+ photomask in the specification) to form an N+ source region 40 on the N-type epitaxial layer 36 through a yellow light and doping process, as shown in FIG. 14-4 shown. Through the ion implantation process, the N+ source region 40 is roughly formed on the N-type epitaxial layer 36 on both sides of the conductive layer 44 . In FIG. 14-4, there are two N+ source regions 40 between two gate conductive layers 44, and the distance between them is defined by the GATE photomask, and a part of the P-type body region 38 is exposed in the middle of the two N+ source regions 40. .
步骤76以沉积制作工艺(deposition process)，在栅导电层44与N型外延层36上形成多晶硅间介电层45，其材质可以是二氧化硅。In step 76 , a deposition process is used to form an interpolysilicon dielectric layer 45 on the gate conductive layer 44 and the N-type epitaxial layer 36 , and its material may be silicon dioxide.
步骤78采用一光掩模(在说明书中称为CON光掩模)，通过黄光跟蚀刻制作工艺，去除掉部分的多晶硅间介电层45，形成接触洞48，如图14-5所示。接触洞48的底部由N+源区40与P型体区38所构成，接触洞48的侧壁由多晶硅间介电层45所构成。Step 78 uses a photomask (referred to as a CON photomask in the specification) to remove part of the inter-polysilicon dielectric layer 45 through the yellow light and etching process to form a contact hole 48, as shown in FIG. 14-5 . The bottom of the contact hole 48 is formed by the N+ source region 40 and the P-type body region 38 , and the sidewall of the contact hole 48 is formed by the interpolysilicon dielectric layer 45 .
步骤80以沉积制作工艺(deposition process)，在多晶硅间介电层45与接触洞48内，形成金属层46。金属层46跟N+源区40与P型体区38形成欧姆接触。In step 80 , a metal layer 46 is formed in the inter-polysilicon dielectric layer 45 and the contact hole 48 by a deposition process. The metal layer 46 forms an ohmic contact with the N+ source region 40 and the P-type body region 38 .
步骤82采用一光掩模(在说明书中称为MTL光掩模)，通过黄光跟蚀刻制作工艺，去除掉部分的金属层46，如图14-6所示。Step 82 uses a photomask (referred to as an MTL photomask in the specification) to remove part of the metal layer 46 through photolithography and etching, as shown in FIG. 14-6 .
接续步骤82，背面金属层32可以形成在N型基底34的背面，而得到图4或是图6的剖视图。Following step 82 , the backside metal layer 32 may be formed on the backside of the N-type substrate 34 to obtain the cross-sectional view of FIG. 4 or FIG. 6 .
在图13中的制作方法60，至少需要有5道光掩模，包含有FOX光掩模、GATE光掩模、N+光掩模、CON光掩模以及MTL光掩模。In the manufacturing method 60 in FIG. 13 , at least five photomasks are required, including a FOX photomask, a GATE photomask, an N+ photomask, a CON photomask and an MTL photomask.
图15显示依据本发明所实施的一种制作方法90，适用于制造图1B中的高压MOSFET12于一半导体基底上，而产生图16-4的剖视图。图16-1～图16-3为高压MOSFET 12，在制造方法90的不同阶段的剖视图。相较于图13中的制作方法60，图15的制作方法90需要的光掩模数量比较少。FIG. 15 shows a manufacturing method 90 implemented according to the present invention, suitable for manufacturing the high voltage MOSFET 12 in FIG. 1B on a semiconductor substrate, resulting in the cross-sectional view of FIG. 16-4 . 16-1 to 16-3 are cross-sectional views of high voltage MOSFET 12 at different stages of manufacturing method 90 . Compared with the manufacturing method 60 in FIG. 13 , the manufacturing method 90 in FIG. 15 requires fewer photomasks.
图15的步骤62、64、66、68、70、72可以参考图13与其相关说明而得知，不再累述。Steps 62 , 64 , 66 , 68 , 70 , and 72 in FIG. 15 can be known by referring to FIG. 13 and related descriptions thereof, and will not be repeated here.
在图15中，接续步骤72，步骤92以栅导电层44以及场氧化层22作为一掩模，进行一掺杂制作工艺，在N型外延层36中形成N+源区40’，如同图16-1所示。步骤92并没有使用光掩模，使用的掩模跟步骤72的一样。因此，N+源区40’的位置，大致跟P型体区38的位置差不多。在一扩散制作工艺中，P型体区38扩散的比N+源区40’远，所以P型体区38大约完整的包围了N+源区40’的下方与侧面，如同图16-1所示。且在图16-1中，两两栅导电层44之间只有一个N+源区40’。In FIG. 15, following step 72, step 92 uses the gate conductive layer 44 and the field oxide layer 22 as a mask to perform a doping process to form an N+ source region 40' in the N-type epitaxial layer 36, as shown in FIG. 16 -1 shown. Step 92 does not use a photomask, the same mask used in step 72 is used. Therefore, the position of the N+ source region 40' is roughly the same as that of the P-type body region 38. In a diffusion manufacturing process, the P-type body region 38 diffuses farther than the N+ source region 40', so the P-type body region 38 completely surrounds the bottom and sides of the N+ source region 40', as shown in FIG. 16-1 . And in Fig. 16-1, there is only one N+ source region 40' between two gate conductive layers 44.
图15中，步骤76接续步骤92。步骤76可以参照图13与相关说明而得知，不再累述。In FIG. 15, step 76 continues step 92. Step 76 can be known with reference to FIG. 13 and related descriptions, and will not be repeated here.
步骤94接续步骤76，其采用CON光掩模，通过黄光跟蚀刻制作工艺，去除掉部分的多晶硅间介电层45以及N+源区40’，形成接触洞48’，如图16-2所示。接触洞48’的底部仅仅由P型体区38所构成，而接触洞48’的侧壁由N+源区40’与多晶硅间介电层45所构成。Step 94 is continued with step 76, which uses a CON photomask to remove part of the interpolysilicon dielectric layer 45 and the N+ source region 40' through the yellow light and etching process to form a contact hole 48', as shown in Figure 16-2 Show. The bottom of the contact hole 48' is only formed by the P-type body region 38, and the sidewall of the contact hole 48' is formed by the N+ source region 40' and the interpolysilicon dielectric layer 45.
步骤80以沉积制作工艺，在多晶硅间介电层45与接触洞48’内，形成金属层46。金属层46跟N+源区40’与P型体区38形成欧姆接触。In step 80, a metal layer 46 is formed in the inter-polysilicon dielectric layer 45 and the contact hole 48' by a deposition process. The metal layer 46 forms an ohmic contact with the N+ source region 40' and the P-type body region 38.
步骤82采用一MTL光掩模，通过黄光跟蚀刻制作工艺，去除掉部分的金属层46，如图16-3所示。Step 82 uses an MTL photomask to remove a part of the metal layer 46 through photolithography and etching, as shown in FIG. 16-3 .
接续步骤82，背面金属层32可以形成在N型基底34的背面，而得到图16-4的剖视图。Following step 82, the back metal layer 32 may be formed on the back of the N-type substrate 34 to obtain the cross-sectional view of FIG. 16-4.
在图15中的制作方法90，至少需要有4道光掩模，包含有FOX光掩模、GATE光掩模、CON光掩模以及MTL光掩模，但不需要图13的制作方法90的步骤74所使用的N+光掩模。相较之下，图15的制作方法90需要比较少的光掩模，因此，制作工艺费用可能比较低廉。In the manufacturing method 90 in FIG. 15 , at least 4 photomasks are required, including the FOX photomask, the GATE photomask, the CON photomask and the MTL photomask, but the steps of the manufacturing method 90 in FIG. 13 are not required. 74 N+ photomasks used. In comparison, the manufacturing method 90 of FIG. 15 requires fewer photomasks, and therefore, the manufacturing process cost may be lower.
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710339696.4ACN108878420B (en) | 2017-05-15 | 2017-05-15 | High-voltage semiconductor device with single-pulse avalanche energy and method of making the same |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710339696.4ACN108878420B (en) | 2017-05-15 | 2017-05-15 | High-voltage semiconductor device with single-pulse avalanche energy and method of making the same |
| Publication Number | Publication Date |
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| CN108878420Atrue CN108878420A (en) | 2018-11-23 |
| CN108878420B CN108878420B (en) | 2020-08-14 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201710339696.4AActiveCN108878420B (en) | 2017-05-15 | 2017-05-15 | High-voltage semiconductor device with single-pulse avalanche energy and method of making the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4974059A (en)* | 1982-12-21 | 1990-11-27 | International Rectifier Corporation | Semiconductor high-power mosfet device |
| US5753529A (en)* | 1994-05-05 | 1998-05-19 | Siliconix Incorporated | Surface mount and flip chip technology for total integrated circuit isolation |
| CN1366332A (en)* | 2001-01-17 | 2002-08-28 | 世界先进积体电路股份有限公司 | Method for manufacturing double-layer gate of metal oxide semiconductor device |
| US6870201B1 (en)* | 1997-11-03 | 2005-03-22 | Infineon Technologies Ag | High voltage resistant edge structure for semiconductor components |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4974059A (en)* | 1982-12-21 | 1990-11-27 | International Rectifier Corporation | Semiconductor high-power mosfet device |
| US5753529A (en)* | 1994-05-05 | 1998-05-19 | Siliconix Incorporated | Surface mount and flip chip technology for total integrated circuit isolation |
| US6870201B1 (en)* | 1997-11-03 | 2005-03-22 | Infineon Technologies Ag | High voltage resistant edge structure for semiconductor components |
| CN1366332A (en)* | 2001-01-17 | 2002-08-28 | 世界先进积体电路股份有限公司 | Method for manufacturing double-layer gate of metal oxide semiconductor device |
| Publication number | Publication date |
|---|---|
| CN108878420B (en) | 2020-08-14 |
| Publication | Publication Date | Title |
|---|---|---|
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