CN108807377B

Movatterモバイル変換

Info

Publication number: CN108807377B
Application number: CN201710304556.3A
Authority: CN
Inventors: 周飞
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-05-03
Filing date: 2017-05-03
Publication date: 2020-07-10
Anticipated expiration: 2037-05-03
Also published as: CN108807377A

Abstract

Translated fromChinese

本发明提供一种半导体器件及其形成方法，其中形成方法包括：提供衬底，所述衬底具有第一开口和第二开口，以第一图形化层为掩膜，去除所述第二开口内的第二保护层和第一保护层，暴露出所述第二开口底部的第一栅氧层；去除所述第二开口底部的第一栅氧层和所述第一开口内的第二保护层暴露出所述第一开口底部的第一保护层；在所述第二开口底部形成第二栅氧层。所述形成方法能够避免出现光刻胶残留，同时也防止刻蚀工艺对于核心区的膜层损伤，从而提高半导体器件的沟道区质量，减少漏电流，提高半导体器件的性能和可靠性。

The present invention provides a semiconductor device and a method for forming the same, wherein the forming method includes: providing a substrate, the substrate has a first opening and a second opening, and using the first patterned layer as a mask, removing the second opening The second protective layer and the first protective layer inside the second opening expose the first gate oxide layer at the bottom of the second opening; remove the first gate oxide layer at the bottom of the second opening and the second gate oxide layer in the first opening The protective layer exposes the first protective layer at the bottom of the first opening; and a second gate oxide layer is formed on the bottom of the second opening. The formation method can avoid photoresist residues, and also prevent the etching process from damaging the film layer in the core region, thereby improving the quality of the channel region of the semiconductor device, reducing leakage current, and improving the performance and reliability of the semiconductor device.

Description

Translated fromChinese

半导体器件及其形成方法Semiconductor device and method of forming the same

技术领域technical field

本发明涉及半导体制造技术领域，尤其涉及一种半导体器件及其形成方法。The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor device and a method for forming the same.

背景技术Background technique

晶体管作为最基本的半导体器件，目前正被广泛应用。随着半导体器件的元件密度和集成度的提高，栅极尺寸也越来越短，传统的晶体管对沟道电流的控制能力变弱，产生短沟道效应，最终影响半导体器件的电学性能。As the most basic semiconductor device, transistors are being widely used. With the improvement of the component density and integration of semiconductor devices, the gate size is also getting shorter and shorter, and the traditional transistor's ability to control the channel current becomes weaker, resulting in a short channel effect, which ultimately affects the electrical performance of the semiconductor device.

为了进一步缩小器件尺寸、提高器件密度，在半导体器件的基础上，引入了高K金属栅晶体管，即以高K介质材料作为栅介质层，以金属材料作为栅极；而且，为了改善高K介质材料的栅介质层与鳍部之间的结合状态，在所述高K介质材料的栅介质层与鳍部之间还需要形成栅氧层进行粘合。所述高K金属栅晶体管采用后栅(gate last)工艺形成，其中一种后栅工艺是在去除多晶硅的伪栅极层并形成栅极沟槽之后，再于栅极沟槽的内壁表面形成高K介质材料的栅介质层。In order to further reduce device size and improve device density, high-K metal gate transistors are introduced on the basis of semiconductor devices, that is, high-K dielectric materials are used as gate dielectric layers and metal materials are used as gate electrodes; and, in order to improve high-K dielectric materials For the bonding state between the gate dielectric layer of the material and the fins, a gate oxide layer needs to be formed between the gate dielectric layer of the high-K dielectric material and the fins for bonding. The high-K metal gate transistor is formed by a gate last process, one of which is to form a gate last process on the inner wall surface of the gate trench after removing the dummy gate layer of polysilicon and forming the gate trench. Gate dielectric layer of high-K dielectric material.

然而，随着半导体器件的密度提高，尺寸缩小，半导体器件的制造工艺难度提高，而所形成的半导体器件的性能变差，可靠性下降。However, as the density of the semiconductor device increases and the size decreases, the manufacturing process of the semiconductor device becomes more difficult, and the performance of the formed semiconductor device deteriorates and the reliability decreases.

发明内容SUMMARY OF THE INVENTION

本发明解决的问题是提供一种半导体器件及其形成方法，所形成的半导体器件的漏电流得到控制，驱动电流提高，功耗减小，稳定性改善。The problem solved by the present invention is to provide a semiconductor device and a method for forming the same, the leakage current of the formed semiconductor device is controlled, the driving current is increased, the power consumption is reduced, and the stability is improved.

为解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供衬底，所述衬底包括核心区和外围区，所述衬底上具有介质结构，所述介质结构内具有第一开口和第二开口，所述第一开口位于外围区，所述第二开口位于核心区，所述第一开口和第二开口底部的衬底上分别具有第一栅氧层，所述第一栅氧层表面具有第一保护层；在所述核心区和所述外围区的介质结构上、第一开口的侧壁和底部、以及第二开口的侧壁和底部形成第二保护层；在所述第二保护层上形成第一图形化层，所述第一图形化层暴露出所述第二开口内的第二保护层；以第一图形化层为掩膜，去除所述第二开口内的第二保护层和第一保护层，暴露出所述第二开口底部的第一栅氧层；在去除所述第二开口内的第二保护层和第一保护层之后，去除所述第一图形化层；在去除所述第一图形化层之后，去除所述第二开口底部的第一栅氧层和所述第一开口内的第二保护层，暴露出所述第一开口底部的第一保护层；在去除所述第二开口底部的第一栅氧层和所述第一开口内的第二保护层之后，在所述第二开口底部形成第二栅氧层。In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, the substrate includes a core region and a peripheral region, the substrate has a dielectric structure, and the dielectric structure has a first an opening and a second opening, the first opening is located in the peripheral region, the second opening is located in the core region, the substrate at the bottom of the first opening and the second opening respectively has a first gate oxide layer, the first opening A first protective layer is formed on the surface of the gate oxide layer; a second protective layer is formed on the dielectric structures of the core region and the peripheral region, the sidewalls and bottoms of the first openings, and the sidewalls and bottoms of the second openings; A first patterned layer is formed on the second protective layer, and the first patterned layer exposes the second protective layer in the second opening; the first patterned layer is used as a mask to remove the second protective layer The second protective layer and the first protective layer in the opening expose the first gate oxide layer at the bottom of the second opening; after removing the second protective layer and the first protective layer in the second opening, remove all the the first patterned layer; after removing the first patterned layer, the first gate oxide layer at the bottom of the second opening and the second protective layer in the first opening are removed to expose the first a first protection layer at the bottom of the opening; after removing the first gate oxide layer at the bottom of the second opening and the second protection layer in the first opening, a second gate oxide layer is formed at the bottom of the second opening.

可选的，所述衬底包括：基底以及位于基底上的隔离层。所述基底上具有鳍部；所述隔离层覆盖所述鳍部的部分侧壁，且所述隔离层的顶部低于所述鳍部的顶部。Optionally, the substrate includes: a base and an isolation layer on the base. The substrate has fins; the isolation layer covers part of the sidewalls of the fins, and the top of the isolation layer is lower than the top of the fins.

可选的，所述隔离层的材料为氧化硅。Optionally, the material of the isolation layer is silicon oxide.

可选的，所述第一栅氧层和第一保护层的形成步骤包括：在形成介质结构、第一开口和第二开口之前，在所述衬底表面形成第一栅氧层；对所述第一栅氧层进行表面处理，在所述第一栅氧层表面形成第一保护层。Optionally, the step of forming the first gate oxide layer and the first protective layer includes: before forming the dielectric structure, the first opening and the second opening, forming a first gate oxide layer on the surface of the substrate; Surface treatment is performed on the first gate oxide layer, and a first protective layer is formed on the surface of the first gate oxide layer.

可选的，所述第一栅氧层材料为氧化硅。Optionally, the material of the first gate oxide layer is silicon oxide.

可选的，所述第一栅氧层的形成工艺为原位蒸汽生成工艺。Optionally, the formation process of the first gate oxide layer is an in-situ steam generation process.

可选的，所述表面处理的步骤包括：对所述第一栅氧层表面进行解耦等离子体氮化工艺，在第一栅氧层表面形成初始保护层；对所述初始保护层进行退火工艺，形成第一保护层。Optionally, the surface treatment step includes: performing a decoupling plasma nitridation process on the surface of the first gate oxide layer to form an initial protective layer on the surface of the first gate oxide layer; annealing the initial protective layer process to form a first protective layer.

可选的，所述介质结构内的所述第一开口和所述第二开口的形成步骤包括：分别在所述核心区和外围区的衬底上形成伪栅极结构，所述伪栅极结构包括伪栅层，所述伪栅层位于第一保护层上；形成源区和漏区，所述源区和漏区分别位于所述伪栅极结构两侧的衬底中；在所述衬底上形成介质结构，所述介质结构覆盖所述伪栅极结构的侧壁，且所述介质结构暴露出所述伪栅层顶部；去除所述伪栅层并暴露出所述第一保护层，在所述外围区的介质结构内形成第一开口，在所述核心区的介质结构内形成第二开口。Optionally, the step of forming the first opening and the second opening in the dielectric structure includes: forming a dummy gate structure on the substrate of the core region and the peripheral region, respectively, the dummy gate The structure includes a dummy gate layer, the dummy gate layer is located on the first protective layer; a source region and a drain region are formed, and the source region and the drain region are respectively located in the substrate on both sides of the dummy gate structure; A dielectric structure is formed on the substrate, the dielectric structure covers the sidewalls of the dummy gate structure, and the dielectric structure exposes the top of the dummy gate layer; the dummy gate layer is removed and the first protection is exposed layer, a first opening is formed in the dielectric structure of the peripheral region, and a second opening is formed in the dielectric structure of the core region.

可选的，所述伪栅极结构还包括：位于所述伪栅层侧壁的侧墙。Optionally, the dummy gate structure further includes: spacers located on the sidewalls of the dummy gate layer.

可选的，第一介质层以及位于第一介质层上的第二介质层。Optionally, the first dielectric layer and the second dielectric layer located on the first dielectric layer.

可选的，所述第二介质层的硬度高于所述第一介质层的硬度。Optionally, the hardness of the second dielectric layer is higher than the hardness of the first dielectric layer.

可选的，去除伪栅层的工艺为湿法刻蚀工艺和干法刻蚀工艺中的一种或两种组合。Optionally, the process of removing the dummy gate layer is one or a combination of a wet etching process and a dry etching process.

可选的，所述以第一图形化层为掩膜，去除所述第二开口内的第二保护层和第一保护层的步骤包括：所述第一图形化层填充满所述第一开口，且所述第一图形化层还位于所述外围区的介质结构之上；以第一图形化层为掩膜，去除所述核心区的的第二保护层，直至暴露出所述第二开口的所述第一保护层为止；在去除所述核心区的第二保护层之后，去除所述第二开口内的所述第一保护层，直至暴露出所述第二开口的所述衬底上的所述第一栅氧层为止；在去除第二开口内的第一保护层之后，去除第一图形化层。Optionally, the step of removing the second protective layer and the first protective layer in the second opening by using the first patterned layer as a mask includes: the first patterned layer is filled with the first opening, and the first patterned layer is also located on the dielectric structure in the peripheral area; using the first patterned layer as a mask, remove the second protective layer in the core area until the first patterned layer is exposed. until the first protective layer of the two openings; after removing the second protective layer of the core region, remove the first protective layer in the second opening until the second protective layer of the second opening is exposed until the first gate oxide layer on the substrate; after removing the first protective layer in the second opening, the first patterning layer is removed.

可选的，所述第一保护层材质为氮氧化硅。Optionally, the material of the first protective layer is silicon oxynitride.

可选的，所述第二保护层的材料为氧化硅。Optionally, the material of the second protective layer is silicon oxide.

可选的，所述第二保护层的形成工艺为原子层沉积工艺。Optionally, the formation process of the second protective layer is an atomic layer deposition process.

可选的，去除所述第二保护层的工艺为湿法刻蚀工艺，所述湿法刻蚀工艺的工艺参数包括：氢氟酸与水的质量百分比为1:500～1:2000，刻蚀时间5秒～1000秒，过刻量50％～300％。Optionally, the process of removing the second protective layer is a wet etching process, and the process parameters of the wet etching process include: the mass percentage of hydrofluoric acid and water is 1:500-1:2000, and the The etching time is 5 seconds to 1000 seconds, and the overetching amount is 50% to 300%.

可选的，去除所述第一保护层的工艺为干法刻蚀工艺，所述干法刻蚀工艺的工艺参数包括：He的气体流量为600sccm～2000sccm，NH₃的气体流量为200sccm～500sccm，NF₃的气体流量为20sccm～200sccm；压强为2torr～10torr，刻蚀时间5秒～100秒，过刻量50％～100％。Optionally, the process of removing the first protective layer is a dry etching process, and the process parameters of the dry etching process include: the gas flow rate of He is 600sccm～2000sccm, and the gas flow rate of NH₃ is 200sccm～500sccm , the gas flow of NF₃ is 20sccm-200sccm; the pressure is 2torr-10torr, the etching time is 5-100 seconds, and the overetching amount is 50%-100%.

可选的，在所述外围区的第一保护层表面形成填充所述第一开口的第一栅极结构；在所述核心区的第二栅氧层表面形成填充所述第二开口的第二栅极结构。Optionally, a first gate structure filling the first opening is formed on the surface of the first protective layer in the peripheral region; a first gate structure filling the second opening is formed on the surface of the second gate oxide layer in the core region. Two gate structure.

本发明还提供一种采用上述任意一项方法形成的半导体器件。The present invention also provides a semiconductor device formed by any one of the above methods.

与现有技术相比，本发明的技术方案具有以下优点：Compared with the prior art, the technical solution of the present invention has the following advantages:

本发明技术方案提供的形成方法中，在去除所述核心区的第二保护层和第一保护层之后，此时衬底表面暴露出核心区的第一栅氧层和所述外围区的第二保护层，由于所述第一栅氧层和第二保护层的材料均为氧化硅，因此在去除外围区的第二保护层的同时，可将所述核心区的第一栅氧层去除，降低了核心区鳍部暴露在刻蚀环境中的风险，从而提高半导体器件的沟道区质量，减少漏电流，提高半导体器件的性能和可靠性。In the formation method provided by the technical solution of the present invention, after the second protective layer and the first protective layer in the core region are removed, the surface of the substrate exposes the first gate oxide layer in the core region and the first gate oxide layer in the peripheral region. Two protective layers, since the first gate oxide layer and the second protective layer are made of silicon oxide, the first gate oxide layer in the core region can be removed while removing the second protective layer in the peripheral region , reducing the risk of exposure of the core region fin to the etching environment, thereby improving the quality of the channel region of the semiconductor device, reducing leakage current, and improving the performance and reliability of the semiconductor device.

进一步，所述核心区的第一保护层和第二保护层分两步进行去除。先通过湿法刻蚀工艺，去除材质为氧化硅的所述第二保护层；再通过干法刻蚀工艺去除材质为氮氧化硅的所述第一保护层。由于干法刻蚀为各向异性的等离子刻蚀工艺，对于不同材料间的刻蚀选择比较高，因此，在刻蚀材质为氮氧化硅的所述第一保护层时，对于材质为氧化硅的所述第一栅氧层不会产生影响，确保在后续对核心区的所述第一栅氧层进行去除时，不会有过刻蚀的风险，提高半导体器件的电学可靠性。Further, the first protective layer and the second protective layer of the core region are removed in two steps. First, a wet etching process is used to remove the second protective layer made of silicon oxide; then, a dry etching process is used to remove the first protective layer made of silicon oxynitride. Since dry etching is an anisotropic plasma etching process, the etching selection between different materials is relatively high. Therefore, when etching the first protective layer made of silicon oxynitride, the material is silicon oxide when etching the first protective layer. The first gate oxide layer will not be affected, which ensures that there is no risk of over-etching when the first gate oxide layer in the core region is subsequently removed, and the electrical reliability of the semiconductor device is improved.

附图说明Description of drawings

图1至图4是一种半导体器件的形成过程的剖面结构示意图；1 to 4 are schematic cross-sectional structural diagrams of a process of forming a semiconductor device;

图5至图17是本发明实施例的半导体器件的形成过程的剖面结构示意图。5 to 17 are schematic cross-sectional structural diagrams of a process of forming a semiconductor device according to an embodiment of the present invention.

具体实施方式Detailed ways

如背景技术所述，随着半导体器件的密度提高，尺寸缩小，所形成的半导体器件的性能变差，可靠性下降。As described in the background art, as the density and size of semiconductor devices increase, the performance and reliability of the formed semiconductor devices deteriorate.

对于外围的半导体器件来说，由于栅氧层在形成伪栅极层之前形成，则去除所述伪栅极层的工艺会损伤所述栅氧层。随着半导体器件的尺寸愈小，所述栅氧层的损伤对器件性能的影响更明显。以下将结合附图进行说明。For the peripheral semiconductor device, since the gate oxide layer is formed before the dummy gate layer is formed, the process of removing the dummy gate layer will damage the gate oxide layer. As the size of the semiconductor device becomes smaller, the damage of the gate oxide layer has a more obvious influence on the device performance. The following description will be made with reference to the accompanying drawings.

图1至图4是一种半导体器件的形成过程的剖面结构示意图。FIG. 1 to FIG. 4 are schematic cross-sectional structural diagrams of a process of forming a semiconductor device.

请参考图1，提供衬底100，所述衬底100包括外围区110和核心区120，所述外围区110和核心区120的衬底100表面分别具有鳍部101；在所述衬底100表面形成隔离层102；在所述隔离层102和鳍部101上形成介质层103，所述外围区110的介质层内具有第一开口111，所述核心区120的介质层内具有第二开口121，所述第一开口111和第二开口121底部的衬底上分别具有伪栅介质层104。Referring to FIG. 1 , a substrate 100 is provided, the substrate 100 includes aperipheral region 110 and acore region 120 , and the surfaces of the substrate 100 of theperipheral region 110 and thecore region 120 respectively havefins 101 ; Anisolation layer 102 is formed on the surface; adielectric layer 103 is formed on theisolation layer 102 and thefins 101 , theperipheral region 110 has afirst opening 111 in the dielectric layer, and thecore region 120 has a second opening in thedielectric layer 121, a dummy gatedielectric layer 104 is respectively provided on the substrate at the bottom of thefirst opening 111 and thesecond opening 121.

请参考图2，在所述外围区110和所述核心区120的介质层103上、第一开口111的侧壁和底部、以及第二开口121的侧壁和底部形成第二保护层106；在所述第二保护层106上形成第一图形化层131，所述第一图形化层131暴露出所述第二开口121内的第二保护层106。Referring to FIG. 2 , a secondprotective layer 106 is formed on thedielectric layer 103 of theperipheral region 110 and thecore region 120 , the sidewalls and bottoms of thefirst openings 111 , and the sidewalls and bottoms of thesecond openings 121 ; A first patternedlayer 131 is formed on the secondprotective layer 106 , and the first patternedlayer 131 exposes the secondprotective layer 106 in thesecond opening 121 .

请参考图3，以第一图形化层131为掩膜，去除核心区120的介质层103上和所述第二开口121内的第二保护层106、以及第二开口121底部的伪栅介质层104。Referring to FIG. 3 , using the first patternedlayer 131 as a mask, remove the secondprotective layer 106 on thedielectric layer 103 of thecore region 120 and in thesecond opening 121 , and the dummy gate dielectric at the bottom of the second opening 121layer 104 .

请参考图4，在去除核心区120的介质层103上和所述第二开口121内的第二保护层106、以及第二开口121底部的伪栅介质层104之后，去除所述第一图形化层131(如图3所示)；在去除图形化层131之后，去除所述外围区110的介质层103上和所述第一开口111内第二保护层106(如图3所示)。Referring to FIG. 4 , after removing the secondprotective layer 106 on thedielectric layer 103 of thecore region 120 and in thesecond opening 121 , and the dummy gatedielectric layer 104 at the bottom of thesecond opening 121 , the first pattern is removed. After removing thepatterned layer 131, remove the secondprotective layer 106 on thedielectric layer 103 in theperipheral region 110 and in the first opening 111 (as shown in FIG. 3) .

所述第一开口111和第二开口121在去除伪栅介质层上的伪栅层之后形成，由于所述伪栅介质层104在去除伪栅层的工艺中受到损伤，因此，所述核心区的伪栅介质层104并不适用于用作核心区器件的栅极氧化层，而外围区对于栅氧层的密度以及内部缺陷数量要求较低，因此能够保留外围区的所述伪栅介质层104。Thefirst opening 111 and thesecond opening 121 are formed after the dummy gate layer on the dummy gate dielectric layer is removed. Since the dummy gatedielectric layer 104 is damaged in the process of removing the dummy gate layer, the core region is The dummy gatedielectric layer 104 is not suitable for use as the gate oxide layer of the device in the core region, and the peripheral region has lower requirements on the density of the gate oxide layer and the number of internal defects, so the dummy gate dielectric layer in the peripheral region can be retained 104.

为了去除核心区120的伪栅介质层，保留外围区的伪栅介质层，需要在外围区形成第一图形化层131作为掩膜。而在形成第一图形化层131之前，所形成的第二保护层106能阻止所述核心区120和所述外围区110的伪栅介质层104发生反应，避免出现光刻胶残留以及膜层结构损伤。然而，由于在去除所述第一开口111内第二保护层106之前，已经暴露出核心区120鳍部101的部分侧壁和顶部表面，因此在刻蚀第二保护层106的过程中，对核心区120的鳍部101造成损伤。所述受损的鳍部101不仅容易引起经时击穿(Time DependentDielectric Breakdown，简称TDDB)，导致短沟道效应，减少驱动电流，提高功耗，还容易引起偏压温度不稳定效应(Bias Temperature Instability，简称BTI)，所形成的半导体结构性能变差。In order to remove the dummy gate dielectric layer in thecore region 120 and retain the dummy gate dielectric layer in the peripheral region, a first patternedlayer 131 needs to be formed in the peripheral region as a mask. Before forming the first patternedlayer 131, the formed secondprotective layer 106 can prevent the dummy gatedielectric layer 104 in thecore region 120 and theperipheral region 110 from reacting, so as to avoid photoresist residues and film layers. Structural damage. However, before the secondprotective layer 106 in thefirst opening 111 is removed, part of the sidewalls and the top surface of thefins 101 of thecore region 120 have been exposed. Therefore, in the process of etching the secondprotective layer 106, the Thefins 101 of thecore region 120 cause damage. The damagedfins 101 not only easily cause Time Dependent Dielectric Breakdown (TDDB), cause short channel effect, reduce driving current and increase power consumption, but also easily cause bias temperature instability effect (Bias Temperature). Instability, referred to as BTI), the performance of the formed semiconductor structure deteriorates.

为了解决上述技术问题，本发明提供了一种半导体器件的形成方法，通过将核心区的第一保护层和第二保护层去除之后，然后在去除外围区的第二保护层的同时，将所述核心区的第一栅氧层去除，能够防止刻蚀工艺对于核心区的损伤，从而提高半导体器件的沟道区质量，减少漏电流，提高半导体器件的性能和可靠性。In order to solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor device. The removal of the first gate oxide layer in the core region can prevent damage to the core region caused by the etching process, thereby improving the quality of the channel region of the semiconductor device, reducing leakage current, and improving the performance and reliability of the semiconductor device.

为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

提供衬底，所述衬底包括核心区和外围区，所述衬底上具有介质结构，所述介质结构内具有第一开口和第二开口，所述第一开口位于外围区，所述第二开口位于核心区，所述第一开口和第二开口底部的衬底上分别具有第一栅氧层，所述第一栅氧层表面具有第一保护层。以下结合图5至图10对介质结构、第一开口、第二开口、第一栅氧层和第一保护层的形成过程进行说明。A substrate is provided, the substrate includes a core region and a peripheral region, the substrate has a dielectric structure, the dielectric structure has a first opening and a second opening, the first opening is located in the peripheral region, and the first opening is located in the peripheral region. Two openings are located in the core region, a first gate oxide layer is respectively formed on the substrate at the bottom of the first opening and the second opening, and a first protective layer is formed on the surface of the first gate oxide layer. The formation process of the dielectric structure, the first opening, the second opening, the first gate oxide layer and the first protective layer will be described below with reference to FIGS. 5 to 10 .

请参考图5，提供衬底，所述衬底包括核心区220和外围区210。Referring to FIG. 5 , a substrate is provided, and the substrate includes acore region 220 and aperipheral region 210 .

在本实施例中，所述衬底包括：基底200以及位于基底上的隔离层202。所述基底上具有鳍部201；所述隔离层覆盖所述鳍部的部分侧壁，且所述隔离层的顶部低于所述鳍部的顶部。In this embodiment, the substrate includes: abase 200 and anisolation layer 202 on the base. The substrate hasfins 201; the isolation layer covers part of the sidewalls of the fins, and the top of the isolation layer is lower than the top of the fins.

在其它实施例中，所述衬底为平面基底。In other embodiments, the substrate is a planar substrate.

所述核心区220用于形成核心器件，所述外围区210用于形成外围器件。所述核心区220的核心器件密度大于外围区210的外围器件密度，且所述核心器件的特征尺寸(Critical Dimension，简称CD)小于所述外围区器件的特征尺寸。所述核心器件的工作电流或工作电压小于所述外围器件的工作电流或工作电压。Thecore region 220 is used to form core devices, and theperipheral region 210 is used to form peripheral devices. The core device density of thecore region 220 is greater than the peripheral device density of theperipheral region 210 , and the critical dimension (Critical Dimension, CD for short) of the core device is smaller than that of the peripheral region device. The working current or working voltage of the core device is smaller than the working current or working voltage of the peripheral device.

在本实施例中，所述基底200和鳍部201的形成步骤包括：提供半导体基底；在所述半导体基底的部分表面形成初始图形化层，所述初始图形化层需要覆盖形成鳍部201的对应位置和形状；以所述初始图形化层为掩膜，刻蚀所述半导体基底，形成所述基底200和所述鳍部201。In this embodiment, the steps of forming thesubstrate 200 and thefins 201 include: providing a semiconductor substrate; forming an initial patterning layer on a part of the surface of the semiconductor substrate, and the initial patterning layer needs to cover the surface where thefins 201 are formed. Corresponding positions and shapes; using the initial patterning layer as a mask, etching the semiconductor substrate to form thesubstrate 200 and thefins 201 .

所述半导体基底的材料可以是单晶硅、多晶硅或者非晶硅；半导体基底的材料也可以是硅、锗、锗化硅、砷化镓等半导体材料；所述半导体基底还可以是绝缘体上的硅、锗、锗化硅、砷化镓等半导体材料。在本实施例中，所述半导体基底为单晶硅衬底，即所述鳍部201和基底200的材料为单晶硅。The material of the semiconductor substrate can be single crystal silicon, polycrystalline silicon or amorphous silicon; the material of the semiconductor substrate can also be semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc.; the semiconductor substrate can also be on an insulator Semiconductor materials such as silicon, germanium, silicon germanium, and gallium arsenide. In this embodiment, the semiconductor substrate is a single crystal silicon substrate, that is, the materials of thefins 201 and thesubstrate 200 are single crystal silicon.

在本实施例中，所述初始图形化层为光刻胶层，采用涂布工艺和光刻工艺形成。在另一实施例中，为了缩小所述鳍部201的特征尺寸，以及相邻鳍部201之间的距离，所述光刻胶层采用多重图形化掩膜工艺形成。In this embodiment, the initial patterning layer is a photoresist layer, which is formed by a coating process and a photolithography process. In another embodiment, in order to reduce the feature size of thefins 201 and the distance betweenadjacent fins 201 , the photoresist layer is formed by a multiple patterning mask process.

刻蚀所述半导体基底的工艺为各向异性的干法刻蚀工艺。所述鳍部201的侧壁相对于基底200的表面垂直或倾斜，且当所述鳍部201的侧壁相对于基底200表面倾斜时，所述鳍部201的底部尺寸大于顶部尺寸。在本实施例中，所述鳍部201的侧壁相对于基底200表面垂直。The process of etching the semiconductor substrate is an anisotropic dry etching process. The sidewalls of thefins 201 are perpendicular or inclined with respect to the surface of thebase 200 , and when the sidewalls of thefins 201 are inclined with respect to the surface of thebase 200 , the bottom size of thefins 201 is larger than the top size. In this embodiment, the sidewalls of thefins 201 are perpendicular to the surface of thesubstrate 200 .

在另一实施例中，所述鳍部通过刻蚀形成于基底表面的半导体层上；所述半导体层采用选择性外延沉积工艺形成于所述基底表面。所述基底为硅、锗、锗化硅等基底，也可以为绝缘体上硅、锗、锗化硅等基底；所述基底还可以为玻璃基底或者III-V族化合物基底。所述半导体层的材料为硅、锗、碳化硅或硅锗。In another embodiment, the fins are formed on the semiconductor layer on the surface of the substrate by etching; the semiconductor layer is formed on the surface of the substrate by a selective epitaxial deposition process. The substrate may be a substrate such as silicon, germanium, silicon germanium, or the like, and may also be a substrate such as silicon-on-insulator, germanium, or silicon germanium; the substrate may also be a glass substrate or a III-V group compound substrate. The material of the semiconductor layer is silicon, germanium, silicon carbide or silicon germanium.

所述隔离层202的形成步骤包括：在所述基底200和鳍部201的表面形成隔离膜；平坦化所述隔离膜；在平坦或所述隔离膜之后，回刻蚀所述隔离膜直至暴露出部分鳍部201侧壁为止。The steps of forming theisolation layer 202 include: forming an isolation film on the surfaces of thesubstrate 200 and thefins 201 ; planarizing the isolation film; after flattening or the isolation film, etching back the isolation film until exposed until part of the side wall of thefins 201 is exposed.

在本实施例中，所述隔离层202的材料为氧化硅；所述隔离层202的厚度是所述鳍部201高度的1/4～1/2。所述隔离膜的形成工艺为流体化学气相沉积工艺(FlowableChemical Vapor Deposition，简称FCVD)。In this embodiment, the material of theisolation layer 202 is silicon oxide; the thickness of theisolation layer 202 is 1/4˜1/2 of the height of thefin portion 201 . The formation process of the isolation film is a fluid chemical vapor deposition process (Flowable Chemical Vapor Deposition, FCVD for short).

在其他实施例中，所述隔离膜还能够采用其他化学气相沉积工艺或物理气相沉积工艺形成；所述其他化学气相沉积工艺包括等离子体增强化学气相沉积工艺(PECVD)或者高深宽比化学气相沉积工艺(HARP)。In other embodiments, the isolation film can also be formed by other chemical vapor deposition processes or physical vapor deposition processes; the other chemical vapor deposition processes include plasma enhanced chemical vapor deposition (PECVD) or high aspect ratio chemical vapor deposition Process (HARP).

所述平坦化工艺为化学机械抛光工艺(CMP)。在本实施例中，所述化学机械抛光工艺以直至暴露出所述鳍部201的顶部表面为止。回刻蚀所述隔离膜的工艺为湿法刻蚀工艺或干法刻蚀工艺中的一种或两种组合。The planarization process is a chemical mechanical polishing process (CMP). In this embodiment, the chemical mechanical polishing process is performed until the top surface of thefins 201 is exposed. The process of etching back the isolation film is one or a combination of a wet etching process or a dry etching process.

请参考图6，在所述衬底的表面形成初始第一栅氧层213。Referring to FIG. 6, an initial firstgate oxide layer 213 is formed on the surface of the substrate.

所述初始第一栅氧层213作为伪栅介质层，用于在后续去除伪栅层时保护所述衬底的表面。The initial firstgate oxide layer 213 serves as a dummy gate dielectric layer for protecting the surface of the substrate when the dummy gate layer is subsequently removed.

在本实施例中，所述初始第一栅氧层213用于形成后续外围区210的第一栅氧层，用于增强外围区210的鳍部201与后续形成的第一栅介质层之间的结合强度。In this embodiment, the initial firstgate oxide layer 213 is used to form the first gate oxide layer of the subsequentperipheral region 210 to strengthen the gap between thefins 201 of theperipheral region 210 and the subsequently formed first gate dielectric layer binding strength.

在本实施例中，所述初始第一栅氧层213形成于所述基底200和所述鳍部201之上，并覆盖所述鳍部201的侧壁和顶部表面。In this embodiment, the initial firstgate oxide layer 213 is formed on thesubstrate 200 and thefins 201 and covers the sidewalls and top surfaces of thefins 201 .

在本实施例中，所述初始第一栅氧化层213的材料为氧化硅，所述第一栅氧化层213的形成工艺为原位蒸汽生成工艺(In-Situ Steam Generation，简称ISSG)；所述初始第一栅氧层213的厚度为20埃～60埃。所述原位蒸汽生成工艺的参数包括：温度为700℃～1200℃，气体包括氢气和氧气，氧气流量为1slm～50slm，氢气流量为1slm～10slm，时间为10秒～5分钟。所述原位蒸汽生成工艺形成的初始第一栅氧层具有良好的阶梯覆盖能力，能够使所形成的初始第一栅氧层紧密地覆盖于所述鳍部201的侧壁表面，且所形成的所述初始第一栅氧层的厚度均匀。In this embodiment, the material of the initial firstgate oxide layer 213 is silicon oxide, and the formation process of the firstgate oxide layer 213 is an in-situ steam generation process (In-Situ Steam Generation, ISSG for short); The initial thickness of the firstgate oxide layer 213 is 20 angstroms˜60 angstroms. The parameters of the in-situ steam generation process include: the temperature is 700°C to 1200°C, the gas includes hydrogen and oxygen, the oxygen flow is 1 slm to 50 slm, the hydrogen flow is 1 slm to 10 slm, and the time is 10 seconds to 5 minutes. The initial first gate oxide layer formed by the in-situ steam generation process has a good step coverage capability, so that the formed initial first gate oxide layer can tightly cover the sidewall surface of thefin portion 201, and the formed initial first gate oxide layer can be formed. The thickness of the initial first gate oxide layer is uniform.

在另一实施例中，所述初始第一栅氧层213的形成工艺为化学氧化工艺；所述化学氧化工艺的步骤包括：采用通入臭氧的水溶液对所述鳍部201暴露出的侧壁和顶部表面进行氧化，在所述鳍部201的侧壁和表面形成第一氧化层。其中，在所述通入臭氧的水溶液中，臭氧在水中的浓度为1％～15％。In another embodiment, the formation process of the initial firstgate oxide layer 213 is a chemical oxidation process; the chemical oxidation process includes: using an aqueous solution into which ozone is passed to the exposed sidewalls of thefins 201 and the top surface are oxidized, and a first oxide layer is formed on the sidewalls and surfaces of thefins 201 . Wherein, in the ozone-infused aqueous solution, the concentration of ozone in the water is 1% to 15%.

请参考图7，对所述初始第一栅氧层213(如图6所示)进行表面处理，形成第一栅氧层203以及位于第一栅氧层203表面的第一保护层204。Referring to FIG. 7 , the initial first gate oxide layer 213 (as shown in FIG. 6 ) is subjected to surface treatment to form a firstgate oxide layer 203 and a firstprotective layer 204 on the surface of the firstgate oxide layer 203 .

所述表面处理的步骤包括：采用解耦等离子体氮化工艺对初始第一栅氧层表面进行处理，在所述第一栅氧层203表面形成初始保护层；对所述初始保护层进行退火工艺，形成第一保护层204。从所述第一保护层204的膜层外表面至所述第一保护层内表面的方向，氮的含量呈现逐步递减的趋势。The surface treatment step includes: using a decoupling plasma nitridation process to treat the surface of the initial first gate oxide layer, forming an initial protective layer on the surface of the firstgate oxide layer 203; and annealing the initial protective layer process to form the firstprotective layer 204 . From the outer surface of the film layer of the firstprotective layer 204 to the inner surface of the first protective layer, the nitrogen content has a gradually decreasing trend.

所述第一栅氧层203并不适用于用作所述核心区220的器件的栅极氧化层，而所述外围区210对于栅氧层的密度以及内部缺陷数量要求较低，因此，能够保留所述外围区210的所述第一栅氧层203。The firstgate oxide layer 203 is not suitable for being used as the gate oxide layer of the device in thecore region 220, and theperipheral region 210 has lower requirements on the density of the gate oxide layer and the number of internal defects, so it can The firstgate oxide layer 203 of theperipheral region 210 remains.

所述第一保护层204则能够在后续去除伪栅层的刻蚀工艺中，减少所述第一栅氧层203受到损伤。当后续去除伪栅层的刻蚀工艺包括等离子体干法刻蚀工艺时，所述等离子体刻蚀工艺容易对鳍部201的内部造成损伤，而所述第一保护层204的密度和硬度较高，从而能够用于阻挡等离子，避免鳍部201受到损伤，由此能够减少外围区210形成的半导体器件的漏电流，改善电学性能。The firstprotective layer 204 can reduce damage to the firstgate oxide layer 203 in the subsequent etching process of removing the dummy gate layer. When the subsequent etching process for removing the dummy gate layer includes a plasma dry etching process, the plasma etching process is likely to cause damage to the interior of thefins 201 , and the density and hardness of the firstprotective layer 204 are relatively high. It can be used to block plasma and prevent thefins 201 from being damaged, thereby reducing the leakage current of the semiconductor device formed by theperipheral region 210 and improving the electrical performance.

在本实施例中，所述第一栅氧层203的材料为氧化硅，所述第一保护层204的材料为氮氧化硅。In this embodiment, the material of the firstgate oxide layer 203 is silicon oxide, and the material of the firstprotective layer 204 is silicon oxynitride.

在本实施例中，所述第一保护层204覆盖暴露于所述隔离层202之上的所述鳍部201的侧壁和顶部表面。在后续去除伪栅层时，所述第一保护层204的密度和硬度有利于保护所述第一栅氧层203和鳍部201；而且，由于所述第一保护层204的介电系数较高，有利于抑制鳍部201与后续形成的第一栅介质层之间的载流子隧穿现象，减少漏电流。In this embodiment, the firstprotective layer 204 covers the sidewalls and top surfaces of thefins 201 exposed on theisolation layer 202 . When the dummy gate layer is subsequently removed, the density and hardness of the firstprotective layer 204 are beneficial to protect the firstgate oxide layer 203 and thefins 201; moreover, since the dielectric coefficient of the firstprotective layer 204 is relatively high High, which is beneficial to suppress the carrier tunneling phenomenon between thefin portion 201 and the subsequently formed first gate dielectric layer and reduce leakage current.

所述第一栅氧层203的厚度为10埃～50埃，所述第一保护层204的厚度为10埃～25埃。出于后续同时去除所述第一栅氧层和后续形成的第二保护层的目的，所述第一栅氧层203的厚度与后续第二保护层的厚度呈现对应关系。The thickness of the firstgate oxide layer 203 is 10 angstroms to 50 angstroms, and the thickness of the firstprotective layer 204 is 10 angstroms to 25 angstroms. For the purpose of removing the first gate oxide layer and the subsequently formed second protective layer at the same time, the thickness of the firstgate oxide layer 203 has a corresponding relationship with the thickness of the subsequent second protective layer.

后续形成介质结构、第一开口和第二开口。以下结合图8至图10对所述介质结构、以及介质结构内的第一开口和第二开口的形成步骤进行说明。The dielectric structure, the first opening and the second opening are subsequently formed. The following describes the dielectric structure and the steps of forming the first opening and the second opening in the dielectric structure with reference to FIGS. 8 to 10 .

请参考图8，分别在所述核心区220和外围区210的衬底上形成伪栅极结构，所述伪栅极结构包括伪栅层205，所述伪栅层205位于第一保护层204之上。Referring to FIG. 8 , a dummy gate structure is formed on the substrates of thecore region 220 and theperipheral region 210 respectively. The dummy gate structure includes adummy gate layer 205 , and thedummy gate layer 205 is located on the firstprotective layer 204 . above.

所述伪栅层205的材料为多晶硅。所述伪栅层205的形成步骤包括：在所述第一保护层表面形成伪栅极膜；对所述伪栅极膜进行平坦化；在所述平坦化工艺之后，在所述伪栅极膜表面形成第二图形化层，所述第二图形化层覆盖需要形成伪栅层205的位置和形状；以所述第二图形化层为掩膜，刻蚀所述伪栅极膜，直至暴露出所述衬底的表面为止，形成伪栅层。The material of thedummy gate layer 205 is polysilicon. The steps of forming thedummy gate layer 205 include: forming a dummy gate film on the surface of the first protective layer; planarizing the dummy gate film; A second patterned layer is formed on the surface of the film, and the second patterned layer covers the position and shape where thedummy gate layer 205 needs to be formed; using the second patterned layer as a mask, the dummy gate film is etched until A dummy gate layer is formed until the surface of the substrate is exposed.

在本实施例中，还包括：在所述伪栅层205的侧壁表面形成侧墙215；在所述伪栅层205和侧墙两侧的鳍部201内形成源区和漏区。In this embodiment, the method further includes: formingspacers 215 on the sidewall surfaces of thedummy gate layer 205 ; forming source regions and drain regions in thefins 201 on both sides of thedummy gate layer 205 and the spacers.

所述侧墙215的材料包括氧化硅、氮化硅和氮氧化硅中的一种或多种组合。所述侧墙215的形成步骤包括：采用沉积工艺在所述伪栅层205表面形成侧墙膜；回刻蚀所述侧墙膜直至暴露出所述伪栅层205的顶部表面，形成侧墙215。The material of thespacer 215 includes one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. The steps of forming thespacer 215 include: forming a spacer film on the surface of thedummy gate layer 205 by a deposition process; etching back the spacer film until the top surface of thedummy gate layer 205 is exposed to form aspacer 215.

所述源区和漏区的形成工艺为离子注入工艺和原位掺杂工艺中的一种或两种组合。在一实施例中，所述源区和漏区以离子注入工艺形成。在另一实施例中，所述源区和漏区的形成步骤还包括：在所述伪栅层205和侧墙215两侧的鳍部201内形成凹槽；采用选择性外延沉积工艺在所述凹槽内形成应力层；在所述应力层内掺杂离子，形成源区和漏区。当所形成的半导体器件为PMOS晶体管时，所述应力层的材料为硅锗，所述应力层内掺杂的离子为P型离子，且所述应力层为∑型应力层。当所形成的半导体器件为NMOS晶体管时，所述应力层的材料为碳化硅，所述应力层内掺杂的离子为N型离子。The formation process of the source region and the drain region is one or a combination of an ion implantation process and an in-situ doping process. In one embodiment, the source and drain regions are formed by an ion implantation process. In another embodiment, the forming step of the source region and the drain region further includes: forming grooves in thefins 201 on both sides of thedummy gate layer 205 and thesidewall spacers 215; A stress layer is formed in the groove; ions are doped in the stress layer to form a source region and a drain region. When the formed semiconductor device is a PMOS transistor, the material of the stressor layer is silicon germanium, the ions doped in the stressor layer are P-type ions, and the stressor layer is a sigma-type stressor layer. When the formed semiconductor device is an NMOS transistor, the material of the stressor layer is silicon carbide, and the ions doped in the stressor layer are N-type ions.

请参考图9，在所述衬底上形成介质结构230，所述介质结构230覆盖所述伪栅极结构的侧壁，且所述介质结构230暴露出所述伪栅层205的顶部。Referring to FIG. 9 , adielectric structure 230 is formed on the substrate, thedielectric structure 230 covers the sidewalls of the dummy gate structure, and thedielectric structure 230 exposes the top of thedummy gate layer 205 .

所述介质结构230包括第一介质层231以及位于第一介质层231上的第二介质层232，且所述第二介质层232的硬度高于所述第一介质层231的硬度。所述第二介质层232由于硬度较高，用于在后续在进行研磨时作为第一介质层的保护层。其中所述第一介质层231的厚度为250埃～500埃，所述第二介质层232的厚度为300埃～1000埃。Thedielectric structure 230 includes a firstdielectric layer 231 and asecond dielectric layer 232 located on thefirst dielectric layer 231 , and the hardness of thesecond dielectric layer 232 is higher than that of thefirst dielectric layer 231 . Thesecond dielectric layer 232 is used as a protective layer of the first dielectric layer during subsequent grinding due to its high hardness. The thickness of thefirst dielectric layer 231 is 250 angstroms to 500 angstroms, and the thickness of thesecond dielectric layer 232 is 300 angstroms to 1000 angstroms.

所述介质结构230的形成步骤包括：在所述隔离层202和所述伪栅层205的表面形成第一介质膜和第二介质膜；平坦化所述第一介质膜和第二介质膜直至暴露出所述伪栅层205的顶部表面为止，形成所述介质结构230。The steps of forming thedielectric structure 230 include: forming a first dielectric film and a second dielectric film on the surfaces of theisolation layer 202 and thedummy gate layer 205; planarizing the first dielectric film and the second dielectric film until Thedielectric structure 230 is formed until the top surface of thedummy gate layer 205 is exposed.

所述第一介质膜和所述第二介质膜的形成工艺为化学气相沉积工艺、物理气相沉积工艺和原子层沉积工艺的一种或多种组合。所述介质结构230的材料为氧化硅、氮化硅、氧氮化硅、低k介质材料(介电系数为大于或等于2.5，小于3.9，例如多孔氧化硅、或多孔氮化硅)或超低k介质材料(介电系数小于2.5，例如多孔SiCOH)中的一种或多种组合。The formation process of the first dielectric film and the second dielectric film is one or more combinations of chemical vapor deposition, physical vapor deposition and atomic layer deposition. The material of thedielectric structure 230 is silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material (dielectric coefficient is greater than or equal to 2.5, less than 3.9, such as porous silicon oxide or porous silicon nitride) or super One or more combinations of low-k dielectric materials (dielectric coefficient less than 2.5, such as porous SiCOH).

在本实施例中，所述第一介质层231和第二介质层232的材料为氧化硅。In this embodiment, the materials of thefirst dielectric layer 231 and thesecond dielectric layer 232 are silicon oxide.

请参考图10，去除所述伪栅层205(如图9所示)并暴露出所述第一保护层204，在所述外围区210的介质结构230内形成第一开口211，在所述核心区220的介质结构230内形成第二开口221。Referring to FIG. 10 , the dummy gate layer 205 (as shown in FIG. 9 ) is removed to expose the firstprotective layer 204 , and afirst opening 211 is formed in thedielectric structure 230 of theperipheral region 210 . Asecond opening 221 is formed in thedielectric structure 230 of thecore region 220 .

去除所述伪栅层205的工艺为干法刻蚀工艺、湿法刻蚀工艺中的一种或两种组合；其中，所述干法刻蚀工艺为各向异性的干法刻蚀工艺。The process of removing thedummy gate layer 205 is one or a combination of a dry etching process and a wet etching process; wherein, the dry etching process is an anisotropic dry etching process.

在本实施例中，所述伪栅层205的材料为多晶硅，去除所述伪栅层205的工艺为等离子干法刻蚀工艺。所述等离子体干法刻蚀工艺的参数包括：气体包括碳氟气体、HBr和Cl₂中的一种或两种、以及载气，所述碳氟气体包括CF₄、CHF₃、CH₂F₂、CH₃F；所述载气为惰性气体，例如He的气体流量为50sccm～400sccm，压强为3mtorr～8mtorr。In this embodiment, the material of thedummy gate layer 205 is polysilicon, and the process of removing thedummy gate layer 205 is a plasma dry etching process. The parameters of the plasma dry etching process include: the gas includes fluorocarbon gas, one or both of HBr and Cl₂ , and a carrier gas, and the fluorocarbon gas includes CF₄ , CHF₃ , CH₂ F_2. CH₃ F; the carrier gas is an inert gas, for example, the gas flow rate of He is 50 sccm-400 sccm, and the pressure is 3 mtorr-8 mtorr.

在所述等离子体干法刻蚀工艺中，具有能量的等离子体容易对所述鳍部201内部造成损伤，而所述第一保护层204的密度和硬度较高，从而能够在扩散所述伪栅层205的过程中，阻挡所述等离子体的轰击，从而避免鳍部201内受到等离子体损伤。In the plasma dry etching process, the plasma with energy is likely to cause damage to the interior of thefins 201, and the density and hardness of the firstprotective layer 204 are high, so that the dummy can be diffused During the process of thegate layer 205 , the bombardment of the plasma is blocked, so as to prevent thefins 201 from being damaged by the plasma.

在另一实施例中，去除所述伪栅极层205的工艺为湿法刻蚀工艺，所述湿法刻蚀工艺的刻蚀液为氢氟酸溶液。In another embodiment, the process of removing thedummy gate layer 205 is a wet etching process, and the etching solution of the wet etching process is a hydrofluoric acid solution.

请参考图11，在所述核心区220和所述外围区210的介质结构230上、第一开口211的侧壁和底部、以及第二开口221的侧壁和底部形成第二保护层206。Referring to FIG. 11 , a secondprotective layer 206 is formed on thedielectric structures 230 of thecore region 220 and theperipheral region 210 , the sidewalls and bottoms of thefirst openings 211 , and the sidewalls and bottoms of thesecond openings 221 .

在所述核心区220和所述外围区210表面形成所述第二保护层206，所述第二保护层206完全覆盖所述核心区220和所述外围区210的表面；当后续去除第一图形化层时，所述第二保护层206能阻止材质为氮氧化硅的所述第一保护层204发生反应，避免出现光刻胶残留以及膜层结构损伤。The secondprotective layer 206 is formed on the surfaces of thecore region 220 and theperipheral region 210, and the secondprotective layer 206 completely covers the surfaces of thecore region 220 and theperipheral region 210; When the layer is patterned, the secondprotective layer 206 can prevent the firstprotective layer 204 made of silicon oxynitride from reacting, so as to avoid photoresist residue and damage to the film structure.

所述第二保护层206的形成工艺为化学气相沉积工艺、物理气相沉积工艺和原子层沉积工艺中的一种或多种组合。所述第二保护层206在光刻工艺中能避免与光阻以及显影和剥离药液发生反应，因此，所述第二保护层206的材料为氧化硅或与之类似的具有相同特性的材料。The formation process of the secondprotective layer 206 is one or more combinations of chemical vapor deposition, physical vapor deposition and atomic layer deposition. The secondprotective layer 206 can avoid reacting with photoresist and developing and stripping chemicals during the photolithography process. Therefore, the material of the secondprotective layer 206 is silicon oxide or similar materials with the same characteristics. .

在本实施例中，所述第二保护层206的材质为氧化硅，厚度为10埃～60埃。在后续工艺中，同时去除所述核心区220的所述第一栅氧层203和所述外围区210的所述的第二保护层206，所述第一栅氧层203的厚度与所述第二保护层206的厚度呈现对应关系。In this embodiment, the material of the secondprotective layer 206 is silicon oxide, and the thickness is 10 angstroms to 60 angstroms. In a subsequent process, the firstgate oxide layer 203 of thecore region 220 and the secondprotective layer 206 of theperipheral region 210 are simultaneously removed, and the thickness of the firstgate oxide layer 203 is the same as the thickness of the The thickness of the secondprotective layer 206 presents a corresponding relationship.

请参考图12，在所述第二保护层206上形成第一图形化层240，所述第一图形化层240暴露出所述第二开口221内的第二保护层206。Referring to FIG. 12 , a firstpatterned layer 240 is formed on the secondprotective layer 206 , and the first patternedlayer 240 exposes the secondprotective layer 206 in thesecond opening 221 .

所述第一图形化层240为图形化的光刻胶层，所述第一图形化层240填充满所述第一开口211。在本实施例中，所述第一图形化层240还覆盖于介质结构230的表面。The firstpatterned layer 240 is a patterned photoresist layer, and the first patternedlayer 240 fills thefirst opening 211 . In this embodiment, the first patternedlayer 240 also covers the surface of thedielectric structure 230 .

所述第一图形化层240的形成步骤包括：在所述第二保护层206上形成光刻胶层，所述光刻胶层填充满所述第一开口211和所述第二开口221；采用掩膜光刻工艺对光刻胶层形成初始图形化层；在形成初始图形化层之后，对光刻胶进行图形化，形成第一图形化层240。The step of forming the first patternedlayer 240 includes: forming a photoresist layer on the secondprotective layer 206, the photoresist layer filling thefirst opening 211 and thesecond opening 221; A mask photolithography process is used to form an initial patterned layer on the photoresist layer; after the initial patterned layer is formed, the photoresist is patterned to form a firstpatterned layer 240 .

请参考图13，以第一图形化层240为掩膜，去除所述第二开口221内的第二保护层206(如图12所示)和第一保护层204(如图12所示)，暴露出所述第二开口221底部的第一栅氧层203。Referring to FIG. 13 , using the first patternedlayer 240 as a mask, remove the second protective layer 206 (shown in FIG. 12 ) and the first protective layer 204 (shown in FIG. 12 ) in thesecond opening 221 , the firstgate oxide layer 203 at the bottom of thesecond opening 221 is exposed.

去除所述第二开口221内的第二保护层206和第一保护层204的步骤包括：以第一图形化层240为掩膜，去除所述第二开口221内的第二保护层206；以第一图形化层240为掩膜，去除所述第二开口221内的第一保护层204，暴露出所述第二开口221底部的第一栅氧层203。The step of removing the secondprotective layer 206 and the firstprotective layer 204 in thesecond opening 221 includes: using the first patternedlayer 240 as a mask, removing the secondprotective layer 206 in thesecond opening 221; Using the first patternedlayer 240 as a mask, the firstprotective layer 204 in thesecond opening 221 is removed to expose the firstgate oxide layer 203 at the bottom of thesecond opening 221 .

所述外围区210对于栅氧层的密度以及内部缺陷数量要求较低，因此，能够保留所述外围区210的所述第一栅氧层203。Theperipheral region 210 has lower requirements on the density of the gate oxide layer and the number of internal defects, so the firstgate oxide layer 203 in theperipheral region 210 can be retained.

去除所述第二开口221内的第二保护层206和第一保护层204的工艺为湿法刻蚀工艺和干法刻蚀工艺中的一种或两种组合。The process of removing the secondprotective layer 206 and the firstprotective layer 204 in thesecond opening 221 is one or a combination of a wet etching process and a dry etching process.

在本实施例中，所述第二保护层206的材料为氧化硅，去除所述第二保护层206的工艺为湿法刻蚀工艺；所述第一保护层204的材料为氧化硅，去除所述第一保护层204的工艺为干法刻蚀工艺，所述干法刻蚀工艺为各向异性的干法刻蚀工艺。In this embodiment, the material of the secondprotective layer 206 is silicon oxide, and the process of removing the secondprotective layer 206 is a wet etching process; the material of the firstprotective layer 204 is silicon oxide, and the process of removing the secondprotective layer 206 is a wet etching process. The process of the firstprotective layer 204 is a dry etching process, and the dry etching process is an anisotropic dry etching process.

去除所述第二保护层206的工艺为湿法刻蚀工艺。所述湿法刻蚀工艺的参数包括：氢氟酸与水的质量百分比为1:500～1:2000，刻蚀时间5秒～1000秒，过刻量50％～300％。The process of removing the secondprotective layer 206 is a wet etching process. The parameters of the wet etching process include: the mass percentage of hydrofluoric acid and water is 1:500-1:2000, the etching time is 5-1000 seconds, and the overetching amount is 50%-300%.

所述湿法刻蚀工艺采用氢氟酸去除氧化硅，由于氢氟酸的刻蚀选择性，不会对位于所述第二保护层206下方的材料为氮氧化硅的所述第一保护层204产生刻蚀。由于氢原子与氟原子间结合的能力相对较强，使得氢氟酸在水中不能完全被电离，理论上低浓度的所述氢氟酸是一种弱酸。但当浓度较低时，所述湿法刻蚀速率过慢，不利用高效生产；而当浓度过高时，氢氟酸在与所述材料为氧化硅的第二保护层206反应时，生成物可以继续和过量的氢氟酸反应，生成强酸性的氟硅酸而导致产生副反应，因此，所述湿法刻蚀工艺中对于氢氟酸与水的质量百分比需进行控制。The wet etching process uses hydrofluoric acid to remove silicon oxide. Due to the etching selectivity of hydrofluoric acid, the first protective layer under the secondprotective layer 206 is not treated with silicon oxynitride. 204 Etching occurs. Due to the relatively strong ability of bonding between hydrogen atoms and fluorine atoms, hydrofluoric acid cannot be completely ionized in water. In theory, the low concentration of hydrofluoric acid is a weak acid. However, when the concentration is low, the wet etching rate is too slow to utilize efficient production; and when the concentration is too high, the hydrofluoric acid reacts with the secondprotective layer 206 made of silicon oxide to generate The compound can continue to react with excess hydrofluoric acid to generate strongly acidic fluorosilicic acid, resulting in side reactions. Therefore, the mass percentage of hydrofluoric acid and water needs to be controlled in the wet etching process.

在本实施例中，去除所述第一保护层204的工艺为干法刻蚀工艺能够为干法刻蚀工艺，所述干法刻蚀工艺为各向同性的SICONI干法刻蚀工艺。所述SICONI干法刻蚀工艺在各个不同方向上的刻蚀速率均匀，能够均匀地去除位于鳍部201侧壁和顶部表面的第一保护层204。In this embodiment, the process for removing the firstprotective layer 204 is a dry etching process, which can be a dry etching process, and the dry etching process is an isotropic SICONI dry etching process. The SICONI dry etching process has uniform etching rates in different directions, and can uniformly remove the firstprotective layer 204 located on the sidewalls and the top surface of thefins 201 .

所述SICONI干法刻蚀工艺的参数包括：He的气体流量为600sccm～2000sccm，NH₃的气体流量为200sccm～500sccm，NF₃的气体流量为20sccm～200sccm；压强为2torr～10torr，刻蚀时间5秒～100秒，过刻量50％～100％。The parameters of the SICONI dry etching process include: the gas flow rate of He is 600sccm-2000sccm, the gas flow rate of NH₃ is 200sccm-500sccm, the gas flow rate of NF₃ is 20sccm-200sccm; the pressure is 2torr-10torr, and the etching time is 5 seconds to 100 seconds, over-scale 50% to 100%.

请参考图14，在去除所述第二开口221内的第二保护层206(如图12所示)和第一保护层204(如图12所示)之后，去除所述第一图形化层240(如图13所示)。Referring to FIG. 14 , after removing the second protective layer 206 (shown in FIG. 12 ) and the first protective layer 204 (shown in FIG. 12 ) in thesecond opening 221 , the first patterned layer is removed 240 (as shown in Figure 13).

在本实施例中，去除所述第一图形化层240的过程中，所述第二保护层206用于保护第一保护层204，避免材质为氮氧化硅的第一保护层204发生反应而出现损伤。去除所述第一图形化层240的工艺为灰化工艺和湿法工艺中的一种或两种组合。In this embodiment, during the process of removing the first patternedlayer 240 , the secondprotective layer 206 is used to protect the firstprotective layer 204 to avoid the reaction of the firstprotective layer 204 made of silicon oxynitride. Damage occurs. The process of removing the first patternedlayer 240 is one or a combination of an ashing process and a wet process.

在本实施列中，去除所述第一图形化层240的工艺为灰化工艺和湿法工艺的组合工艺。其中，所述灰化工艺的参数包括：压强为50mtorr～900mtorr，功率1000w～2700w，N₂的气体流量为500sccm～4000sccm，H₂的气体流量为50sccm～1000sccm，温度为80℃～250℃。其中，所述湿法工艺的参数包括：H₂SO₄和水的体积百分比为3:1～6:1，温度100℃～130℃。In this embodiment, the process of removing the first patternedlayer 240 is a combined process of an ashing process and a wet process. The parameters of the ashing process include: the pressure is 50mtorr-900mtorr, the power is 1000w-2700w, the gas flow rate of N₂ is 500sccm-4000sccm, the gas flow rate of H₂ is 50sccm-1000sccm, and the temperature is 80-250°C. Wherein, the parameters of the wet process include: the volume percentage of H₂ SO₄ and water is 3:1-6:1, and the temperature is 100°C-130°C.

所述灰化工艺为等离子体灰化工艺，在灰化去除材料为光刻胶的所述第一图形化层240之后，等离子体处理会在衬底的表面残留大量有机物，这要求必须通过强的氧化溶剂进行清除。所述湿法工艺中通过含有H₂SO₄的水溶液来清除等离子导致的有机物或聚合物残留，确保衬底表面的洁净度，避免产生工艺缺陷。The ashing process is a plasma ashing process. After the first patternedlayer 240 whose material is photoresist is removed by ashing, a large amount of organic substances will remain on the surface of the substrate after the plasma treatment, which requires strong oxidizing solvent for removal. In the wet process, an aqueous solution containing H₂ SO₄ is used to remove the residual organic matter or polymer caused by the plasma, so as to ensure the cleanliness of the substrate surface and avoid process defects.

请参考图15，在去除所述第一图形化层240(如图13所示)之后，去除所述第二开口221底部的第一栅氧层203(如图14所示)和所述第一开口211内的第二保护层206(如图14所示)，暴露出所述第一开口211底部的第一保护层204。Referring to FIG. 15 , after removing the first patterned layer 240 (as shown in FIG. 13 ), remove the first gate oxide layer 203 (as shown in FIG. 14 ) and the first gate oxide layer 203 (as shown in FIG. 14 ) at the bottom of thesecond opening 221 The secondprotective layer 206 in an opening 211 (as shown in FIG. 14 ) exposes the firstprotective layer 204 at the bottom of thefirst opening 211 .

去除所述第二开口221底部的第一栅氧层203和所述第一开口211内的第二保护层206的工艺为湿法刻蚀工艺或各向同性的干法刻工艺中的一种或两种组合。The process of removing the firstgate oxide layer 203 at the bottom of thesecond opening 221 and the secondprotective layer 206 in thefirst opening 211 is one of a wet etching process or an isotropic dry etching process or a combination of both.

所述第一栅氧层203和所述第二保护层206的材料均为氧化硅，且位于所述第一栅氧层203之下为核心区220鳍部201，位于所述第二保护层206之下为外围区210的所述第一保护层204。干法刻蚀工艺中的等离子体的轰击，很容易对所述第一栅氧层203之下的核心区220鳍部201造成损伤，因此，优选用湿法刻蚀工艺用于去除第一栅氧层203和所述第二保护层206。The materials of the firstgate oxide layer 203 and the secondprotective layer 206 are both silicon oxide, and under the firstgate oxide layer 203 are thecore regions 220fins 201 located in the second protective layer Below 206 is the firstprotective layer 204 of theperipheral region 210 . The plasma bombardment in the dry etching process can easily damage thefins 201 of thecore region 220 under the firstgate oxide layer 203. Therefore, a wet etching process is preferably used to remove the firstgate Oxygen layer 203 and the secondprotective layer 206 .

在本实施例中，去除第一栅氧层203和所述第二保护层206的工艺为湿法刻蚀工艺，参数包括：氢氟酸与水的质量百分比为1:500～1:2000，刻蚀时间5秒～1000秒，过刻量50％～300％。In this embodiment, the process of removing the firstgate oxide layer 203 and the secondprotective layer 206 is a wet etching process, and the parameters include: the mass percentage of hydrofluoric acid and water is 1:500-1:2000, The etching time is 5 seconds to 1000 seconds, and the overetching amount is 50% to 300%.

请参考图16，在去除所述第二开口221底部的第一栅氧层203(如图14所示)和所述第一开口211内的第二保护层206(如图14所示)之后，在所述第二开口221底部形成第二栅氧层207。Referring to FIG. 16 , after removing the firstgate oxide layer 203 at the bottom of the second opening 221 (as shown in FIG. 14 ) and the secondprotective layer 206 in the first opening 211 (as shown in FIG. 14 ) , a secondgate oxide layer 207 is formed at the bottom of thesecond opening 221 .

所述第二栅氧层207用作核心区220形成的半导体器件的栅氧层。所述第二栅氧层207的材料为氧化硅；所述第二栅氧层207的形成工艺为热氧化工艺或湿法氧化工艺。The secondgate oxide layer 207 is used as a gate oxide layer of the semiconductor device formed by thecore region 220 . The material of the secondgate oxide layer 207 is silicon oxide; the formation process of the secondgate oxide layer 207 is a thermal oxidation process or a wet oxidation process.

所述第二栅氧层207的厚度为8埃～15埃。在本实施例中，所述第二栅氧层207的形成工艺为热氧化工艺。所述热氧化工艺的参数包括：时间100秒～1000秒，压强为50mtorr～～300torr，氧气与氮气的气体流量比为1/20～1/5。The thickness of the secondgate oxide layer 207 is 8 angstroms˜15 angstroms. In this embodiment, the formation process of the secondgate oxide layer 207 is a thermal oxidation process. The parameters of the thermal oxidation process include: time from 100 seconds to 1000 seconds, pressure from 50 mtorr to 300 torr, and gas flow ratio of oxygen to nitrogen from 1/20 to 1/5.

请参考图17，在所述外围区210的第一保护层204表面形成填充所述第一开口211的第一栅极结构；在所述核心区220的第二栅氧层207表面形成填充所述第二开口221的第二栅极结构。Referring to FIG. 17 , a first gate structure filling thefirst opening 211 is formed on the surface of the firstprotective layer 204 of theperipheral region 210 ; a filling gate structure is formed on the surface of the secondgate oxide layer 207 of thecore region 220 The second gate structure of thesecond opening 221 is described.

所述第一栅极结构包括位于所述第一保护层204上的第一栅介质层212，所述第一栅介质层212覆盖所述外围区210的介质结构230的顶部表面和所述第一开口211的侧壁和底部表面；所述第二栅极结构包括位于所述第二栅氧层207上的第二栅介质层222，所述第二栅介质层222覆盖所述核心区220的介质结构230的顶部表面和所述第二开口221的侧壁和底部表面。The first gate structure includes a first gate dielectric layer 212 on the firstprotective layer 204 , and the first gate dielectric layer 212 covers the top surface of thedielectric structure 230 of theperipheral region 210 and the first gate dielectric layer 212 . The sidewall and bottom surface of anopening 211 ; the second gate structure includes a secondgate dielectric layer 222 on the secondgate oxide layer 207 , and the secondgate dielectric layer 222 covers thecore region 220 the top surface of thedielectric structure 230 and the sidewall and bottom surfaces of thesecond opening 221 .

所述第一栅介质层212和所述第二栅介质层222的材料为高k介质材料(介电系数大于3.9)；所述高k介质材料包括氧化铪、氧化锆、氧化铪硅、氧化镧、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛或氧化铝。The materials of the first gate dielectric layer 212 and the secondgate dielectric layer 222 are high-k dielectric materials (dielectric coefficient is greater than 3.9); the high-k dielectric materials include hafnium oxide, zirconium oxide, hafnium silicon oxide, oxide Lanthanum, zirconia silicon, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

所述第一栅介质层212和所述第二栅介质层222的形成步骤为化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺的一种或多种组合。The first gate dielectric layer 212 and the secondgate dielectric layer 222 are formed by one or more combinations of chemical vapor deposition, physical vapor deposition or atomic layer deposition.

在一实施例中，第一栅极结构还包括位于第一栅介质层212表面的第一功函数层，第二栅极结构还包括位于第二栅介质层222表面的第二功函数层。具体的，在形成所述第一栅介质层212和所述第二栅介质层222之后，在所述第一栅介质层212表面形成第一功函数层，在所述第二栅介质层222表面形成第二功函数层。形成所述第一功函数层和第二功函数层的工艺步骤包括：在所述第一栅介质层212和所述第二栅介质层222的表面形成功函数膜，且所述功函数膜覆盖所述介质结构230的顶部表面；平坦化所述功函数膜，直至暴露出所述介质结构230的表面为止，形成第一功函数层和第二功函数层。在第一功函数层的材料和第二功函数层的材料能够相同或不同。In one embodiment, the first gate structure further includes a first work function layer on the surface of the first gate dielectric layer 212 , and the second gate structure further includes a second work function layer on the surface of the secondgate dielectric layer 222 . Specifically, after the first gate dielectric layer 212 and the secondgate dielectric layer 222 are formed, a first work function layer is formed on the surface of the first gate dielectric layer 212 , and a first work function layer is formed on the second gate dielectric layer 222 A second work function layer is formed on the surface. The process steps of forming the first work function layer and the second work function layer include: forming a work function film on the surface of the first gate dielectric layer 212 and the secondgate dielectric layer 222, and the work function film Covering the top surface of thedielectric structure 230; planarizing the work function film until the surface of thedielectric structure 230 is exposed, forming a first work function layer and a second work function layer. The material in the first work function layer and the material in the second work function layer can be the same or different.

综上，本实施例中，在去除所述核心区的第二保护层和第一保护层之后，此时衬底表面暴露出核心区的第一栅氧层和所述外围区的第二保护层，由于所述第一栅氧层和第二保护层的材料均为氧化硅，因此在去除外围区的第二保护层的同时，可将所述核心区的第一栅氧层去除，降低了核心区鳍部暴露在刻蚀环境中的风险，从而高半导体器件的沟道区质量，减少漏电流，提高半导体器件的性能和可靠性。To sum up, in this embodiment, after the second protective layer and the first protective layer in the core region are removed, the surface of the substrate exposes the first gate oxide layer in the core region and the second protective layer in the peripheral region. Since the materials of the first gate oxide layer and the second protective layer are both silicon oxide, while removing the second protective layer in the peripheral region, the first gate oxide layer in the core region can be removed, reducing the The risk of exposure of the fins in the core region to the etching environment is avoided, so that the quality of the channel region of the semiconductor device is improved, the leakage current is reduced, and the performance and reliability of the semiconductor device are improved.

虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.