技术领域technical field
本发明涉及半导体制造领域，特别是涉及一种T型栅制备方法。The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a T-shaped gate.
背景技术Background technique
以砷化镓(GaAs)、氮化镓(GaN)为代表的化合物半导体材料具有许多优良的特性，如高临界击穿电场、高电子迁移率、高二维电子气浓度和良好的高温工作能力等。基于化合物半导体的高电子迁移率晶体管(HEMT)、异质结构场效应晶体管(HFET)等器件已经得到了广泛应用，尤其在射频、微波等需要大功率和高频率的领域具有明显优势。Compound semiconductor materials represented by gallium arsenide (GaAs) and gallium nitride (GaN) have many excellent characteristics, such as high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration and good high temperature working ability Wait. Devices such as high electron mobility transistors (HEMTs) and heterostructure field effect transistors (HFETs) based on compound semiconductors have been widely used, especially in fields requiring high power and high frequency such as radio frequency and microwave.
在化合物半导体射频功率器件的制作工艺中，栅电极的制作是关键的制作工艺，T型栅的加工工艺更是难点中的难点；目前，在深亚微米化合物半导体器件制作中，一般采用电子束光刻和多层胶的方法制作T型栅。T型栅是指截面形状呈现蘑菇型的T状栅电极，这样其下部接触半导体表面的栅根很窄，从而可以提高器件的截至频率，而上部的栅帽很宽，可以降低栅极的电阻。在实际工艺制作中，采用I线紫外曝光的光刻工艺可以将栅极的线宽最低做到0.35微米左右，采用电子束光刻可以将线宽做到0.1微米以下。但是，由于受到设备的限制，电子束光刻制作T型栅只能进行逐点扫描，因此其加工效率极低，而采用I线紫外光刻制作的T型栅线宽又不能满足器件对线宽要求。In the manufacturing process of compound semiconductor RF power devices, the production of gate electrodes is the key process, and the processing technology of T-shaped gates is even more difficult. At present, in the production of deep submicron compound semiconductor devices, electron beams are generally used. The method of photolithography and multi-layer glue is used to make the T-shaped grid. T-shaped gate refers to a T-shaped gate electrode with a mushroom-shaped cross-sectional shape, so that the gate root of the lower part contacting the semiconductor surface is very narrow, which can increase the cut-off frequency of the device, while the upper gate cap is very wide, which can reduce the resistance of the gate. . In the actual manufacturing process, the photolithography process of I-line ultraviolet exposure can reduce the line width of the gate to a minimum of about 0.35 microns, and the electron beam lithography can achieve a line width of less than 0.1 microns. However, due to the limitation of the equipment, the T-grid made by electron beam lithography can only be scanned point by point, so its processing efficiency is extremely low, and the line width of the T-shaped grid made by I-line ultraviolet lithography cannot meet the requirements of device alignment. wide requirements.
发明内容Contents of the invention
基于此，有必要针对电子束制作T型栅的加工效率极低的问题，提供一种新的T型栅制备方法。Based on this, it is necessary to provide a new T-shaped grid preparation method for the problem of extremely low processing efficiency of the T-shaped grid fabricated by electron beams.
本发明提供一种T型栅制备方法，包括：The invention provides a method for preparing a T-shaped grid, comprising:
形成势垒层；form a barrier layer;
在所述势垒层上形成第一光刻胶层,并在所述第一光刻胶层形成栅根凹槽，其中，所述第一光刻胶层为深紫外光刻胶层；Forming a first photoresist layer on the barrier layer, and forming a root groove on the first photoresist layer, wherein the first photoresist layer is a deep ultraviolet photoresist layer;
在所述栅根凹槽内和所述深紫外光刻胶层上形成金属层；forming a metal layer in the root groove and on the deep ultraviolet photoresist layer;
在所述金属层上形成第二光刻胶层，并在所述第二光刻胶层形成栅帽图形；forming a second photoresist layer on the metal layer, and forming a gate cap pattern on the second photoresist layer;
刻蚀未被所述栅帽图形覆盖部分的金属层；etching the metal layer not covered by the gate cap pattern;
去除所述深紫外光刻胶层和栅帽图形。removing the deep ultraviolet photoresist layer and gate cap pattern.
可选的，所述在所述势垒层上形成深紫外光刻胶层的步骤包括：Optionally, the step of forming a deep ultraviolet photoresist layer on the barrier layer includes:
在所述势垒层上涂覆一层用于193纳米-248纳米波长光刻的深紫外光刻胶，在大于90摄氏度的温度下，烘烤60秒以上的时间。Coating a layer of deep ultraviolet photoresist for 193nm-248nm wavelength photolithography on the barrier layer, and baking at a temperature greater than 90 degrees Celsius for more than 60 seconds.
可选的，所述在所述光刻胶层形成栅根凹槽的步骤包括：对所述深紫外光刻胶进行曝光和烘烤以产生化学放大式光反应，然后在显影溶液中显影，使深紫外光刻胶产生栅根凹槽。Optionally, the step of forming grid root grooves in the photoresist layer includes: exposing and baking the deep ultraviolet photoresist to generate a chemically amplified photoreaction, and then developing in a developing solution, The deep UV photoresist is made to create the root grooves.
可选的，所述金属层包括多层金属薄膜。Optionally, the metal layer includes a multi-layer metal film.
可选的，所述深紫外光刻胶的厚度为0.5微米以上。Optionally, the thickness of the deep ultraviolet photoresist is more than 0.5 micron.
可选的，所述去除所述深紫外光刻胶层和栅帽图形的步骤包括：将所述深紫外光刻胶层和栅帽图形溶解在溶剂中。Optionally, the step of removing the deep ultraviolet photoresist layer and the gate cap pattern includes: dissolving the deep ultraviolet photoresist layer and the gate cap pattern in a solvent.
可选的，所述势垒层为AlGaAs、AlGaN、InGaP、ScAlN和InAlN中任意一种或多种材料的叠加。Optionally, the barrier layer is a superposition of any one or more materials among AlGaAs, AlGaN, InGaP, ScAlN and InAlN.
可选的，所述第二光刻胶层为i-line光刻胶或者g-line光刻胶或者深紫外光刻胶。Optionally, the second photoresist layer is i-line photoresist or g-line photoresist or deep ultraviolet photoresist.
上述T型栅制备方法，可以使T型栅的接触线宽小于200纳米同时又提高了的T型栅的制备效率。并且由于栅帽与势垒层之间不存在介质，具有较小的栅极电容，提高了半导体器件的性能。The above method for preparing the T-shaped grid can make the contact line width of the T-shaped grid less than 200 nanometers and at the same time improve the preparation efficiency of the T-shaped grid. And because there is no medium between the gate cap and the potential barrier layer, the gate capacitance is small, and the performance of the semiconductor device is improved.
附图说明Description of drawings
图1为等待制作栅极的半导体器件的示意图；1 is a schematic diagram of a semiconductor device waiting to make a gate;
图2-图8是表示制备根据本发明的一些实施例的T型栅的示意图。2-8 are schematic diagrams showing the preparation of T-shaped grids according to some embodiments of the present invention.
图中标号：Labels in the figure:
1-衬底；2-缓冲层；3-势垒层；4-源极；5-漏极；6-深紫外光刻胶层；7-栅根凹槽；8-金属层；9-光刻胶层；10-T型栅。1-substrate; 2-buffer layer; 3-barrier layer; 4-source; 5-drain; 6-deep ultraviolet photoresist layer; 7-gate groove; 8-metal layer; 9-light Resist layer; 10-T gate.
具体实施方式Detailed ways
以下结合附图和具体实施例对本发明提出的T型栅制备方法作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。The preparation method of the T-shaped grid proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.
在图1示意性的示出了一种化合物半导体结构。包括：衬底1，所述衬底材料包括但不限于蓝宝石、碳化硅、硅、金刚石、砷化镓、氮化镓和氮化铝等材料。所述衬底1的厚度为50到1000微米。所述衬底1上可以形成缓冲层2，用于提供电流流动的路径。所述缓冲层2可以为GaAs，GaN、InP、InN、AlN、InGaAs或者InGaN等一种或多种材料组合。所述缓冲层2的厚度为50到10000纳米。所述缓冲层2上可以形成势垒层3，所述势垒层3可以是AlGaAs、AlGaN、InGaP、ScAlN、InAlN等合金材料一种或多种的叠加。所述势垒层3的厚度为3到100纳米。A compound semiconductor structure is schematically shown in FIG. 1 . Including: a substrate 1, the substrate material includes but not limited to sapphire, silicon carbide, silicon, diamond, gallium arsenide, gallium nitride, aluminum nitride and other materials. The thickness of the substrate 1 is 50 to 1000 microns. A buffer layer 2 may be formed on the substrate 1 for providing a path for current flow. The buffer layer 2 may be GaAs, GaN, InP, InN, AlN, InGaAs or InGaN or a combination of one or more materials. The buffer layer 2 has a thickness of 50 to 10000 nanometers. A barrier layer 3 may be formed on the buffer layer 2, and the barrier layer 3 may be a superposition of one or more alloy materials such as AlGaAs, AlGaN, InGaP, ScAlN, and InAlN. The barrier layer 3 has a thickness of 3 to 100 nanometers.
在上述材料生长完之后，通常先形成欧姆接触电极，即源极4和漏极5。所述源极4和漏极5分别位于所述势垒层3两侧的所述缓冲层2上。所述源极4和漏极5之间的区域可以称为沟道，在源极4和漏极5被施加电压后，载流子从源极4移动到漏极5。所述源极4和漏极5可以为钛、铝、镍、金、铂等金属中任意多种组成的合金。在所述源极4和漏极5形成之后，下一步，则需要在所述势垒层3上形成栅极以控制载流子的流动。而一方面，为了提高半导体器件的工作频率，所述栅极的接触线宽需要尽可能的小；另一方面，栅极的电阻和栅极-源极电容必须更可能的低。因此对栅极形成工艺提出了很高的要求。After the above materials are grown, the ohmic contact electrodes, namely the source 4 and the drain 5 are usually formed first. The source 4 and the drain 5 are respectively located on the buffer layer 2 on both sides of the barrier layer 3 . The region between the source 4 and the drain 5 may be called a channel, and after the source 4 and the drain 5 are applied with a voltage, carriers move from the source 4 to the drain 5 . The source electrode 4 and the drain electrode 5 may be alloys composed of any metals such as titanium, aluminum, nickel, gold, and platinum. After the source 4 and the drain 5 are formed, the next step is to form a gate on the barrier layer 3 to control the flow of carriers. On the one hand, in order to increase the operating frequency of the semiconductor device, the contact line width of the gate needs to be as small as possible; on the other hand, the resistance and gate-source capacitance of the gate must be as low as possible. Therefore, high requirements are imposed on the gate formation process.
以下将结合图2-图7具体描述本发明所提供的T型栅制备方法。The preparation method of the T-shaped gate provided by the present invention will be described in detail below with reference to FIGS. 2-7 .
请参考图2，在形成如图1所示的结构后，在所述势垒层3上形成深紫外光刻胶层6，所述深紫外光刻胶层6需要一定的厚度来达到保护沟道的作用，通常其厚度大于0.5微米。。所述深紫外光刻胶层6覆盖所述势垒层3，同时也可以覆盖所述源极4和漏极5。具体的，可以在所述势垒层3上涂覆一层用于193纳米-248纳米波长光刻的深紫外光刻胶，在大于90摄氏度的温度下，烘烤超过60秒的时间。在所述势垒层3表面光滑的情况下，可以在所述深紫外光刻胶层的上表面或者下表面涂上抗反射层，抑制紫外光的反射。Please refer to FIG. 2, after forming the structure shown in FIG. 1, a deep ultraviolet photoresist layer 6 is formed on the barrier layer 3, and the deep ultraviolet photoresist layer 6 needs a certain thickness to reach the protection groove The role of the channel, usually its thickness is greater than 0.5 microns. . The deep ultraviolet photoresist layer 6 covers the barrier layer 3 , and may also cover the source electrode 4 and the drain electrode 5 . Specifically, a layer of deep ultraviolet photoresist for 193nm-248nm wavelength photolithography can be coated on the barrier layer 3, and baked at a temperature greater than 90 degrees Celsius for more than 60 seconds. When the surface of the barrier layer 3 is smooth, an anti-reflection layer can be coated on the upper or lower surface of the deep ultraviolet photoresist layer to suppress the reflection of ultraviolet light.
请参考图3，对所述旋涂深紫外光刻胶4的晶圆采用深紫外步进式光刻机进行曝光和烘烤以产生化学放大式光反应，然后在显影溶液中显影，使深紫外光刻胶4产生栅根凹槽7。采用合适的光刻工艺条件，本发明形成的所述栅根凹槽7的宽度能够小于200纳米，从而能够使后续形成的栅根的线宽小于200纳米。所述显影溶液可以是四甲基氢氧化氨。Please refer to FIG. 3, the wafer of the spin-coated deep ultraviolet photoresist 4 is exposed and baked by a deep ultraviolet stepper to produce a chemically amplified photoreaction, and then developed in a developing solution to make the deep The UV photoresist 4 creates the root groove 7 . Using suitable photolithography process conditions, the width of the gate root groove 7 formed in the present invention can be less than 200 nanometers, so that the line width of the subsequently formed gate root can be less than 200 nanometers. The developing solution may be tetramethylammonium hydroxide.
请参考图4，在所述栅根凹槽7内和所述深紫外光刻胶层6上形成金属层8。所述金属层8由多层金属薄膜组成，所述金属薄膜可以为NiAu、NiAl、PtAu等等。所述金属层8可以采用物理气相沉积工艺形成。首选沉积的是较薄的金属薄膜，厚度约为10-100纳米，且可以与势垒层3形成良好的肖特基接触。然后沉积较厚的金属薄膜，以提高栅极的导电率。所述栅根凹槽7内填充的金属，形成T型栅的栅根。所述栅根的与势垒层层的接触线宽能够小于200纳米。Referring to FIG. 4 , a metal layer 8 is formed in the grid root groove 7 and on the deep ultraviolet photoresist layer 6 . The metal layer 8 is composed of multi-layer metal films, and the metal films can be NiAu, NiAl, PtAu and so on. The metal layer 8 can be formed by a physical vapor deposition process. The preferred deposition is a relatively thin metal film with a thickness of about 10-100 nanometers, which can form a good Schottky contact with the barrier layer 3 . A thicker metal film is then deposited to increase the conductivity of the gate. The metal filled in the root groove 7 forms the root of the T-shaped grid. The contact line width of the gate root and the barrier layer can be less than 200 nanometers.
请参考图5，在所述金属层8上方旋涂形成第二光刻胶层9，所述第二光刻胶层9覆盖所述金属层8。所述第二光刻胶层9可以为深紫外、i-line或者g-line型光刻胶。Referring to FIG. 5 , a second photoresist layer 9 is formed on the metal layer 8 by spin coating, and the second photoresist layer 9 covers the metal layer 8 . The second photoresist layer 9 can be deep ultraviolet, i-line or g-line photoresist.
请参考图6，对所述第二光刻胶层9进行光刻工艺，在所述第二光刻胶9上形成栅帽图形，即保留栅根凹槽7对应上方的部分光刻胶层，所述栅帽图形与所述栅根凹槽在竖直方向上相重叠。Please refer to FIG. 6 , perform a photolithography process on the second photoresist layer 9, and form a grid cap pattern on the second photoresist layer 9, that is, retain a portion of the photoresist layer corresponding to the grid root groove 7 , the grid cap pattern overlaps the grid root groove in the vertical direction.
请参考图7，对未被第二光刻胶层9覆盖的金属层8进行刻蚀，去除未被第二光刻胶层9覆盖的金属层8，以形成栅帽。所述栅帽和栅根构成T型栅10。所述刻蚀可以为等离子体干法刻蚀，所述等离子干法刻蚀的工艺条件取决于所述金属层的材料种类，可以从纯物理溅射刻蚀变化为反应性化学刻蚀，在某些情况下还需要进行湿法腐蚀来去除特定的金属薄层。Referring to FIG. 7 , the metal layer 8 not covered by the second photoresist layer 9 is etched to remove the metal layer 8 not covered by the second photoresist layer 9 to form a gate cap. The grid cap and grid root form a T-shaped grid 10 . The etching can be plasma dry etching, and the process conditions of the plasma dry etching depend on the material type of the metal layer, and can be changed from pure physical sputter etching to reactive chemical etching. In some cases wet etching is also required to remove specific thin metal layers.
请参考图8，去除剩余的深紫外光刻胶层6和第二光刻胶层9。可以将剩余的光刻胶在高温情况下采用溶剂溶解去除，最终在所述势垒层3上只保留T型栅10。Referring to FIG. 8 , the remaining deep ultraviolet photoresist layer 6 and the second photoresist layer 9 are removed. The remaining photoresist can be dissolved and removed with a solvent at high temperature, and finally only the T-shaped gate 10 remains on the barrier layer 3 .
上述实施例以在图1所示半导体器件上形成T型栅为例，可以理解的是，本领域技术人员在其他半导体器件上，采用本发明所提供的方法形成T型栅也在本申请的保护范围之内。本发明提供的方法适用于任何砷化镓，氮化镓，磷化铟以及对应的三元或者四元化合物半导体材料系统。The foregoing embodiment takes the formation of a T-shaped gate on the semiconductor device shown in FIG. 1 as an example. It can be understood that those skilled in the art can use the method provided by the present invention to form a T-shaped gate on other semiconductor devices. within the scope of protection. The method provided by the invention is applicable to any gallium arsenide, gallium nitride, indium phosphide and corresponding ternary or quaternary compound semiconductor material systems.
采用本方法制备T型栅的效率可以到达每小时100片晶圆(一片晶圆上具有多个含有T型栅结构的晶片)，而传统的电子束光刻工艺制备一个同样结构的晶圆需要将近一天的时间。因此，本发明所提供制备方法在可以使T型栅的接触线宽小于200纳米同时又提高了的T型栅的制备效率。并且由于栅帽与势垒层之间不存在介质，具有较小的栅极电容，提高了半导体器件的性能。Adopting this method to prepare the efficiency of T-shaped grid can reach 100 wafers per hour (one wafer has a plurality of wafers containing T-shaped grid structure), while the traditional electron beam lithography process needs to prepare a wafer with the same structure. nearly a day. Therefore, the preparation method provided by the present invention can make the contact line width of the T-shaped grid less than 200 nanometers and at the same time improve the preparation efficiency of the T-shaped grid. And because there is no medium between the gate cap and the potential barrier layer, the gate capacitance is small, and the performance of the semiconductor device is improved.
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810519181.7ACN108807162A (en) | 2018-05-28 | 2018-05-28 | T-type grid preparation method |
| Application Number | Priority Date | Filing Date | Title |
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| CN201810519181.7ACN108807162A (en) | 2018-05-28 | 2018-05-28 | T-type grid preparation method |
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| CN108807162Atrue CN108807162A (en) | 2018-11-13 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201810519181.7APendingCN108807162A (en) | 2018-05-28 | 2018-05-28 | T-type grid preparation method |
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| WD01 | Invention patent application deemed withdrawn after publication | Application publication date:20181113 |