A kind of boostrap circuitTechnical field
The present invention relates to technical field of integrated circuits, and in particular to a kind of boostrap circuit of integrated circuit high-side switch, it is specialIt is not to be related to a kind of boostrap circuit with under-voltage protection.
Background technology
With the development of integrated circuit and the raising of integrated level, more and more products use the high side of integrated MOS deviceSwitch, such as the driving of the supply convertor of switching mode, audio frequency power amplifier, motor etc..Because NMOS device is in identical area itemUnder part, there is the driving capability of bigger and smaller conducting resistance than PMOS, so more and more high-side switch use NMOSDevice is integrated, especially in high-tension circuit.The NMOS used as high-side switch tube connects power supply because of one end,A driving voltage more higher than supply voltage is needed to go driving grid that NMOS tube could be allowed to be operated in linear zone or deep linear zone,Play its conducting advantage.So needing a boostrap circuit to generate a driving voltage more higher than supply voltage.
Traditional boostrap circuit and its typical case such as Fig. 1.Wherein MNHS be high-side switch tube, specifically by NMOS tube LaiIntegration realization.Because the drain electrode of MNHS connects input voltage VIN, and the output of its grid circuit driven controls, so wantingIt is a voltage more higher than input voltage VIN to seek the power supply of driving circuit, which is referred to as bootstrap voltage mode BS.Driving circuitGeneral circuit all controlled by logic is controlled by level shifting circuit, and the wherein input of logic control circuit is the logic of systemControl signal, and the function of level shifting circuit is the power domain of the output signal of logic control circuit by general internal electricitySource and be converted into bootstrap voltage mode BS and MNHS source output voltage SW.
Traditional boostrap circuit is made of linear voltage regulator, diode D1 and the bootstrap capacitor C1 in Fig. 1.When SW is low electricityUsually, the out-put supply of linear voltage regulator charges to bootstrap capacitor C1, when SW is high level, will pass through bootstrap capacitor C1 institutesThe charge of storage raises bootstrap voltage mode BS, obtains voltage BS more higher than supply voltage, the power supply as driving circuit.This circuitThe acting as of middle diode D1 prevents current flowing backwards.
In the circuit structure of Fig. 1, its shortcoming is that：BS is set to have sufficiently high voltage, it is necessary to assure linear voltage regulatorThere is time enough to charging bootstrap capacitor.Diversified and control model the complication that can be applied with IC products,It is low level voltage not ensure that output SW to have enough time, that is, cannot be guaranteed the time of charging, such as open in DC-DCIn the certain applications for closing buck converter.At this moment, bootstrap capacitor stored charge will slow consumption, cause bootstrap voltage mode to dropIt is low, the conduction property of high-side switch is directly affected, the power-efficient of product is reduced or even capability error occurs.
Invention content
Have in view of that, the technical problem to be solved in the present invention is to provide a kind of boostrap circuits, in linear voltage regulator without footIn the case that the enough time is to charging bootstrap capacitor, it still can guarantee sufficiently high bootstrap voltage mode, ensured the good of high-side switchThe power-efficient of conduction property and entire product.
A kind of boostrap circuit provided by the invention is applied to the driving of NMOS tube MNHS, the driving circuit of NMOS tube MNHSSupply voltage is BS, and the source output voltage of NMOS tube MNHS is SW, and boostrap circuit includes：Linear voltage regulator, diode D1 andThe input terminal of bootstrap capacitor C1, linear voltage regulator connect diode for inputting supply voltage VIN, the output end of linear voltage regulatorThe anode of D1, the cathode of diode D1 are used to provide supply voltage BS, the moon of diode D1 for the driving circuit of NMOS tube MNHSPole is also connected with one end of capacitance C1, and the other end of capacitance C1 is used to connect the source electrode of NMOS tube, it is characterised in that：It also adds deficientVoltage protection circuit and pull-down circuit；
Under-voltage protecting circuit detects the voltage difference between voltage BS and voltage SW, when the voltage difference is less than setting value, owesVoltage protection circuit exports high level to pull-down circuit；
Pull-down circuit is allowed to persistently become by the rising edge triggering meeting actuation voltage SW of under-voltage protecting circuit input high levelOne section of set time of low level, and linear voltage regulator will give bootstrap capacitor C1 chargings within this time.
As a kind of specific embodiment of under-voltage protecting circuit, including：V/I conversions, comparator and resistance R1, V/ITwo input terminals of conversion are respectively used to input voltage BS and the output end of voltage SW, V/I conversion connects the one of resistance R1 simultaneouslyThe reverse input end at end and comparator, the other end ground connection of resistance R1, the noninverting input of comparator are used to input setting value, thanOutput end compared with device is the output end of under-voltage protecting circuit.
As the improvement of above-mentioned under-voltage protecting circuit specific implementation mode, further include：Resistance R2 and switching tube MN2, resistanceThe one end R2 connects the other end of resistance R1, the other end ground connection of resistance R2, and the drain electrode of switching tube MN2 connects one end of resistance R2,The other end of the source electrode connection resistance R2 of switching tube MN2, the output end of the grid connection comparator of switching tube MN2.
As a kind of specific embodiment of V/I conversions, including：PMOS tube MP1, PMOS tube MP2, high pressure NMOS pipeMN1, resistance R3 and capacitance C2, the source electrode of PMOS tube MP1 are the first input end of V/I conversions, the drain electrode connection electricity of PMOS tube MP1Hinder one end of R3, the other end of resistance R3 is the second input terminal of V/I conversions, the source electrode of PMOS tube MP2 simultaneously with PMOS tube MP1Source electrode connected with one end of capacitance, the grid of PMOS tube MP2 simultaneously with the grid of PMOS tube MP1, the other end of capacitance andThe drain electrode of PMOS tube MP1 connects, the drain electrode of the drain electrode connection high pressure NMOS pipe MN1 of PMOS tube MP2, high pressure NMOS pipe MN1'sGrid connects the other end of resistance R3, and the source electrode of high pressure NMOS pipe MN1 is the output end of V/I conversions.
One of improvement as under-voltage protecting circuit specific implementation mode, the setting value of the noninverting input input of comparatorIt is generated by zero-temperature coefficient electric current and resistance R4, the output end of zero-temperature coefficient electric current connects the noninverting input and resistance R4 of comparator simultaneouslyOne end, resistance R4 the other end ground connection.
Two of improvement as under-voltage protecting circuit specific implementation mode, further include resistance R5 and capacitance C3, and resistance R5 connectsIt being connected between the output end and the reverse input end of comparator of V/I conversions, one end of capacitance C3 connects the reverse input end compared with device,The other end of capacitance C3 is grounded.
As a kind of specific embodiment of pull-down circuit, including：Constant time lag circuit, NMOS tube MNPD and current limliting electricityHinder RPD；The output end of the input terminal connection under-voltage protecting circuit of constant time lag circuit, the grid of NMOS tube MNPD, which is connected and fixed, to be prolongedWhen circuit output end, the source electrode ground connection of NMOS tube MNPD, the drain electrode of NMOS tube MNPD is connected with one end of resistance RPD, resistanceThe other end of RPD is used to connect the source electrode of NMOS tube MNHS；Constant time lag circuit is used for under-voltage protecting circuit input high levelRising edge be converted to the high impulse of set time, which controls NMOS tube MNPD conductings, is low electricity by voltage SW drop-downsIt is flat.
It should be noted that：Describe that " constant time lag circuit is for will be under-voltage in above-mentioned pull-down circuit specific implementation modeThe rising edge of protection circuit input high level is converted to the high impulse of set time ", " the high electricity of under-voltage protecting circuit input thereinIt is flat " with " the under-voltage protecting circuit output high level " of invention content third section not contradiction.Invention content third section is directed to" under-voltage protecting circuit " is the generation main body of " high level ", therefore with " output "；Herein for be " constant time lag circuit ",It is the reception object of " high level ", therefore with " input ".Other similar descriptions no longer illustrate in present specification.
Improvement as above-mentioned boostrap circuit technical solution, it is characterised in that：Further include that under-voltage protection is enabled, under-voltage protectionThe enable signal of enabled output under-voltage protecting circuit, when only under-voltage protecting circuit output signal is high level, under-voltage protection electricityRoad could work normally.
Another improvement as above-mentioned boostrap circuit technical solution, it is characterised in that：Further include duty ratio detection, lightCarry detection and nor gate X1；
Duty ratio detection exports high for the switching signal duty ratio of detection switch power supply when duty ratio is greater than the set valueLevel；Underloading detection exports high level for the load of detection switch power supply when load is less than setting value；
The output signal of duty ratio detection and the output signal of underloading detection obtain under-voltage protection by nor gate X1 operationsThe enable signal of circuit.
As a kind of specific embodiment of duty ratio detection, including：Level shifting circuit single-ended turns both-end, levelDetection and comparator；The input of duty detection circuit is voltage SW, and voltage SW turns its power domain through level shifting circuitIt is changed to internal electric source and ground, the transformed signal of level shifting circuit is converted to the clock letter of difference by Single-to-differenticonversion conversion circuitNumber, the clock signal of this difference detects its high level and low duration by level sensitive circuit, and generation represents heightThis is sent into comparator to voltage analog signal and is compared by the voltage analog signal of level and low level effective time, you canGenerate the duty ratio detection output signal for representing the whether big Mr. Yu's setting value of duty ratio.
As a kind of specific embodiment of underloading detection, including：Voltage sample pipe MNS, current sample pipe MPS1 withMPS2, current mirror MP4 and MP5, bias current MN1 and MN2, and the sample circuit of feedback pipe MP3 composition and resistance R6 withThe underloading comparison circuit of R4, positive temperature coefficient electric current Iptat and comparator composition；The drain electrode of voltage sample pipe MNS is for connectingThe source electrode of NMOS tube MNHS, the grid of voltage sample pipe MNS are used to connect the grid of NMOS tube MNHS, voltage sample pipe MNSSource electrode, the drain electrode of current sample pipe MPS1, the source electrode of current mirror MP4, current mirror MP4 of the source electrode successively through current sample pipe MPS1Drain electrode, the drain electrode of bias current MN1, be grounded after the source electrode of bias current MN1, the source electrode of current sample pipe MPS2 is for connectingThe drain electrode of NMOS tube MNHS, the drain electrode for the source electrode, current mirror MP5 of current sample pipe MPS2 to drain successively through current mirror MP5,It is grounded after the drain electrode of bias current MN2, the source electrode of bias current MN2, the grid connection of current sample pipe MPS1 and MPS2 are followed byGround, the drain electrode of connection current mirror MP5 after the grid connection of current mirror MP4 and MP5, after the grid connection of bias current MN1 and MN2For connecting voltage bias input signal, the source electrode of the source electrode connection current mirror MP5 of feedback pipe MP3, the grid of feedback pipe MP3 connectsThe drain electrode of current mirror MP4 is connect, the drain electrode of feedback pipe MP3 is grounded after resistance R6, and the drain electrode of feedback pipe MP3 is also connected with comparatorReverse input end, the output end of positive temperature coefficient electric current Iptat connect simultaneously comparator noninverting input and resistance R4 oneThe output end at end, the other end ground connection of resistance R4, comparator is the output end for being lightly loaded detection.
Term is explained：
Power domain：Chip interior uses the circuit of same power supplies and ground, power domain referred to as having the same.
Internal electric source and ground：Produced by converter of the input voltage by inside, the used power supply of internal circuit workThe ground and；
The clock signal of difference：That is opposite in phase, a pair of of clock signal with same common mode level.
Voltage bias input signal：The voltage signal exported by current mirror generative circuit usually can be connected to other metal-oxide-semiconductorsGrid generates different electric currents.
The operation principle of the present invention is that：When the source output SW of NMOS tube be low level when, linear voltage regulator it is defeatedGo out power supply to charge to bootstrap capacitor C1, bootstrap capacitor C1 two-plates is made to generate enough voltage differences.When the source electrode of NMOS tube exportsWhen signal SW is high level, bootstrap voltage mode BS will be raised by bootstrap capacitor C1 stored charges, obtain comparing supply voltageHigher voltage, the power supply as driving circuit.Diode D1 prevents bootstrap charge circuit current flowing backwards.In some applications, ifWhen the time deficiency that SW cannot be lower or be lower at work, linear voltage regulator is had no chance to charging bootstrap capacitor, or chargingWhen very little is insufficient to support the operating current of BS, the voltage of BS will be reduced slowly.At this point, when under-voltage protecting circuit detects BSVoltage between SW is less than setting value, will export high level, and pull-down circuit is touched by the rising edge that under-voltage protecting circuit exportsHair can pull down SW and be allowed to the one section of set time that is persistently lower, and linear voltage regulator will fill within this time to bootstrap capacitorElectricity.As long as the given threshold for setting under-voltage protecting circuit is more than the high-side switch tube well required gate source voltage of conducting, canEnsure that grid has sufficiently high voltage that it is made well to be connected when next high-side switch is opened, and obtains high power-efficient.
Beneficial effects of the present invention are summarized as：High-side switch output SW do not have enough time be it is low when, also can guarantee drivingThe supply voltage of circuit is sufficiently high, ensures conduction property when follow-up high-side switch is opened, obtains high power-efficient.
Description of the drawings
Fig. 1 is traditional boostrap circuit and its application drawing；
Fig. 2 is the boostrap circuit and its application drawing of the present invention；
Fig. 3 is the circuit diagram of the under-voltage protecting circuit and pull-down circuit in first embodiment of the invention boostrap circuit；
Fig. 4 is the realization figure of under-voltage protecting circuit in Fig. 3；
Fig. 5 is second embodiment of the invention boostrap circuit and its application drawing；
Fig. 6 is boostrap circuit used in the non-isolated high voltage direct current of third embodiment of the invention-dc switch buck converterAnd its application drawing；
Fig. 7 is the realization figure of duty detection circuit in Fig. 6 boostrap circuits；
Fig. 8 is the realization figure that detection circuit is lightly loaded in Fig. 6 boostrap circuits.
Specific implementation mode
Such as the boostrap circuit and its application drawing that Fig. 2 is the present invention, present invention is contemplated that：In the bootstrapping of the prior artIncrease under-voltage protecting circuit and pull-down circuit on the basis of circuit, which does not have enough time to certainly in linear voltage regulatorIn the case of lifting capacitor charging, set when under-voltage protecting circuit detects that the voltage between bootstrap voltage mode and high-side switch output is less thanDefinite value, will export high level, and pull-down circuit can be pulled down high-side switch by the rising edge triggering that under-voltage protecting circuit exports and be exportedIt is allowed to the one section of set time that is persistently lower, and linear voltage regulator will give charging bootstrap capacitor within this time.As long as settingThe given threshold of under-voltage protecting circuit is more than the high-side switch tube well required gate source voltage of conducting, can ensure next high sideGrid has sufficiently high voltage that it is made well to be connected when switch is opened, and obtains high power-efficient.
In order to enable those skilled in the art more fully understands that present invention is conceived, implement below in conjunction with specificExample is described in detail.
First embodiment
The functional block diagram that first embodiment of the invention uses is identical as Fig. 2, wherein under-voltage protecting circuit and pull-down circuitPhysical circuit is as shown in Figure 3.
Under-voltage protecting circuit by V/I convert (Chinese is Voltage-current conversion), comparator, resistance R1, resistance R2 andSwitching tube MN2 compositions, the both ends two input terminals connection capacitance C1 (distinguishing input voltage BS and voltage SW) of V/I conversions, V/IThe output end of conversion connects one end of resistance R1 and the reverse input end of comparator simultaneously, and the other end of resistance R1 is after resistance R2Ground connection, the noninverting input of comparator are used to input setting value VREF, and the output end of comparator is the output of under-voltage protecting circuitEnd.The other end of the drain electrode connection resistance R1 of switching tube MN2, the source electrode ground connection of switching tube MN2, the grid connection of switching tube MN2The output end of comparator.
Pull-down circuit is made of constant time lag circuit, NMOS tube MNPD and current-limiting resistance RPD, the input of constant time lag circuitThe grid of the output end of end connection under-voltage protecting circuit, MNPD is connected and fixed the output end of delay circuit, and the source electrode of MNPD is grounded,The drain electrode of MNPD is connected with one end of resistance RPD, the source electrode of the other end connection NMOS tube MNHS of resistance RPD.
The operation principle of the present embodiment is：V/I conversions change the voltage signal (voltage difference of BS and SW) of input detectionFor current signal, this current signal flows through voltage signal caused by resistance R1 (and R2) and reference voltage VREF (i.e. comparatorsNoninverting input input setting value) compare, when the voltage difference between BS and SW is lower than reference voltage VREF, comparator outputHigh level represents bootstrap voltage mode and needs to increase.The output high level rising edge of comparator generates one by constant time lag circuitThe high impulse of set time, which controls MNPD conductings, drop-down SW is low level.The effect of resistance RPD is current limliting, is ensuredThe reliability of drop-down.
The present embodiment can also remove resistance R2 and switching tube MN2, and the advantageous effect for increasing resistance R2 and switching tube MN2 existsOpen circuit and the short circuit that resistance R2 can effectively be controlled when under-voltage protection exports different conditions in switching tube MN2, are produced using positive feedbackThe raw retarding window compared, prevents the noise near threshold limit value or other interference.
The circuit of under-voltage protecting circuit specific implementation in Fig. 3 is referring to Fig. 4.In Fig. 4 VI conversion by PMOS tube MP1,PMOS tube MP2, high pressure NMOS pipe MN1, resistance R3 and capacitance C2 compositions；Izc is zero-temperature coefficient electric current, and stream is joined on resistance R4Examine voltage VREF.MP1 and resistance R3 concatenates two input terminals that latter two endpoint is V/I conversions, can be by the voltage BS of inputVoltage difference between the two is converted to current signal with voltage SW, and obtained current signal is carried out by current mirror MP1 and MP2Mirror image, you can the output current Is for obtaining Voltage-current conversion has
V in formula (1)GS1For the gate source voltage of MP1, K is the mirroring ratios of current mirror MP2 and MP1.Current-voltage is convertedOutput current flow into the both ends of voltage signal and reference voltage VREF input comparators caused by resistance R1 (and R2).ResistanceThe purpose of R2 is to generate the hesitation compared, and MN1 is high-voltage MOS pipe, plays a part of that high-low pressure is isolated in circuit.Due toVoltage SW at work can beating heart become, in order to reduce its coupled interference to comparator negative terminal input signal, in input plusThe filter circuit being made of resistance R5 and capacitance C3 is entered.When voltage is relatively low between BS and SW, comparator exports high level, generationTable bootstrap voltage mode is relatively low.
Second embodiment
The more real first embodiment of the present embodiment boostrap circuit and its is answered the difference is that increase under-voltage protection enabledWith as shown in Figure 5.
Under-voltage protection is enabled to be made of several logic gates, output enable signal to under-voltage protecting circuit, control under-voltage guarantorWhen the working condition of protection circuit, only output signal are high level, under-voltage protecting circuit could work normally.When without under-voltage guarantorIt, can be by closing the enabled saving power consumption of under-voltage protection when protection circuit works.
3rd embodiment
The present embodiment is compared with first embodiment the difference is that increasing duty ratio detection, underloading detection and nor gate X1；Duty ratio detection exports high level when duty ratio is greater than the set value for the switching signal duty ratio of detection switch power supply；GentlyLoad of the detection for detection switch power supply is carried, high level is exported when load is less than setting value；The output letter of duty ratio detectionNumber and underloading detection output signal the enable signal of under-voltage protecting circuit is obtained by nor gate X1 operations.The present embodiment fromIt lifts circuit and its application is as shown in Figure 6.
The present embodiment is mainly used in the design of non-isolated high voltage direct current-dc switch buck converter integrated circuitIn, the master power switch pipe of non-isolated high voltage direct current-dc switch buck converter is high-side switch tube MNHS, because highPress NMOS device that there is smaller conducting resistance than high voltage PMOS under the conditions of identical area, so more and more output mastersPower tube is integrated using high pressure NMOS part, is also therefore needed to utilize boostrap circuit, is generated a drive more higher than power supplyDynamic voltage removes driving grid, ensures that main power tube is operated in deep linear zone, reduces conduction loss, obtain higher power-efficient.
Such as Fig. 6, wherein MNHS is the main power tube of converter, is integrated among chip, is usually managed by the NDMOS of high pressureIt realizes, the output of grid circuit driven controls, and the input signal of driving circuit is by logic control circuit through over levelConversion circuit obtains, and wherein logic control circuit usually compares signal and part protection signal by clock signal, pulse widthIt is formed by digital logic gate composition, generates digital output signal, and the function of level shifting circuit is this numeral outputThe power domain of signal internal electric source caused by linear voltage regulator and ground are converted into bootstrap voltage mode BS and power tube source electrode and exportSW。
When the converter be operated in input and output voltage close under conditions of, i.e. the prodigious situation of duty ratio of switch change-overWhen lower, the time that each periodic voltage SW is pulled low is extremely short, and linear voltage regulator is caused not have enough time to charging bootstrap capacitor,And bootstrap capacitor, so bootstrap voltage mode can slowly be lower, influences the on state characteristic of output power pipe always in power consumption.
Separately have, when the converter is operated in light-load mode, in order to improve light-load efficiency, reduces chip operation electric current, becomeParallel operation can enter energy-saving mode, can close output power pipe under the pattern and compare device including oscillator, pulse width, error is putMost of circuit such as big device, voltage SW meeting free oscillations, when output voltage is higher, can equally cause linear close to output voltageVoltage-stablizer can not give charging bootstrap capacitor, bootstrap capacitor slowly power consumption to directly affect performance when exiting light-load mode.
As described above, in big space rate or light-load mode, all there is the insurmountable BS of traditional circuit institute in the converterPower consumption is lower the problem of leading to inefficiency or influence other performance, and can be good if using the boostrap circuit of the present inventionSolve the problems, such as this, physical circuit realizes that framework is as shown in Figure 6.
Boostrap circuit used in the present embodiment converter is similar with invention circuit above, includes linear voltage regulator, two polesPipe D1, bootstrap capacitor C1, under-voltage protecting circuit and pull-down circuit.The difference is that in this embodiment, under-voltage protection is enabledIt is extended to duty ratio detection, underloading detection and nor gate X1.Duty ratio detection is the switch for detection switch power conversionSignal dutyfactor exports high level when duty ratio is more than a certain setting value (such as 90%).Underloading detection is used for detecting the transformationThe load of device exports high level when load is less than a certain setting value (such as 100mA).The output signal and underloading of duty ratio detectionThe output signal of detection obtains the enable signal of under-voltage protecting circuit by nor gate X1 operations.In this way, when converter is operated inWhen big space rate or light-load mode, under-voltage protecting circuit just enables normal work, when bootstrap voltage mode is lower automatically by drop-downCircuit drags down SW, and bootstrap capacitor is made to have time enough charging, ensures that bootstrap voltage mode is in higher level.Conversely, working as converterBe operated in other patterns or under the conditions of when, then under-voltage protecting circuit be not necessarily to work, save circuit power consumption.
The specific implementation of the present embodiment duty detection circuit as shown in fig. 7, by level shifting circuit, it is single-ended turn both-end,Level detection and comparator composition.
The input of duty detection circuit is the source output voltage SW of converter main power tube, and voltage SW is through level conversionIts power domain is converted to internal electric source and ground by circuit, and the signal after level conversion is converted to difference by Single-to-differenticonversion conversion circuitClock signal, this differential clock signal detects its high level and low duration by level sensitive circuit, generatesThis is sent into comparator to voltage analog signal and compared by the voltage analog signal for representing high level and low level effective timeCompared with, you can generate the duty ratio detection output signal for representing the whether big Mr. Yu's setting value of duty ratio.Pay attention in design level detectionWhen circuit, need to set to reach the duty ratio of duty detection circuit by the ratio of bias current charge and discharge or the ratio of capacitanceDefinite value.
The physical circuit that detection is lightly loaded in the present embodiment is realized as shown in Figure 8.Be lightly loaded detection circuit mainly by power tube andPeripheral components, sample circuit and underloading comparison circuit composition.
L1 is energy storage inductor, C1 is output capacitance, D1 is fly-wheel diode, they are the peripheral device of convertor icPart collectively forms a complete switching power converters with chip.In IC interior, MNHS is the high side of EmbeddedMain power tube is generally formed in parallel by many large-sized high pressure NDMOS, and effect is improved to obtain smaller conducting resistanceRate.
The sample circuit for being integrated in chip interior includes voltage sample pipe MNS, current sample pipe MPS1 and MPS2, current mirrorMP4 and MP5, bias current MP1 and MP2 and feedback pipe MP3.Voltage sample pipe MNS breadth length ratios are much smaller than main power tube, andIt is controlled with main power tube output signal DRVH all driven, when DRVH is high, MNHS conductings, input voltage VIN is deposited to inductanceEnergy storage capacity, while MNS is also opened, and SW voltages are conducted to source electrode by its drain electrode.VB is the internal voltage bias generated, connectionMN1 and MN2 constitutes the bias current of sample circuit.MPS1, MPS2 are current sample pipe, and size is identical, grounded-grid, workIn linear zone.MP4 and MP5 equally constitutes one group of current mirror, works in saturation region, since grid voltage is equal, source electrode electricityPressure is that 2 voltages of P, Q are equal.The electric current for flowing through MP3 is sample rate current Isens, while MP3 constitutes backfeed loop so thatCircuit is enable to respond quickly the voltage difference of P, Q and stablizes loop.
It includes resistance R1 and R2, positive temperature coefficient electric current Iptat and comparator to be lightly loaded comparison circuit.Sample rate current flows intoResistance R1 generates sampled voltage signal VSENS, positive temperature current Iptat and flows into resistance R2 generation underloading reference voltages VREF.ThanCompare sampled voltage signal and underloading reference voltage, output underloading detection output signal compared with device.
When DRVH is high, MNHS, MNS conducting, inductive current, at this time can be by electricity with certain slope linear riseInducing current is sampled, to judge whether the load of converter is underloading.Since the electric current for flowing through MNS is relatively small, streamInductive current can be approximately equal to by crossing the electric current of MNHS, then the voltage of Q points and P points is respectively
VQ=VIN- (IMN2+ISENS)RMPS2Formula (2)
VP=(VIN-ILRMNHS)-IMN1(RMNS+RMPS1) formula (3)
I in formula (2)MN1With the I in formula (1)MN2It is bias current to flow through MN1 and MN2, because designing its sizeIt is identical, therefore electric current is equal.ILFor inductive current, ISENSFor drain current, that is, sample rate current of M5.RMPS1With RMPS2It is online to workThe conducting resistance of current sample the pipe MPS1 and MPS2 in property area, since its size design is identical, therefore conducting resistance is equal.RMHS isThe conducting resistance of main power tube, usual very little.RMNSFor the conducting resistance of voltage sample pipe MHS (W/ is taken in actual circuit designL)MNS》(W/L)MPS1=(W/L)MPS2, then have RMPS1=RMPS2《RMNS.In view of VP=VQ, in summary can obtain：
As it can be seen that the ratio of sample rate current and inductive current, i.e. oversampling ratio are by current sample pipe MPS1 and main power tubeThe conducting resistance ratio of MNHS determines, if in laying out pattern so that both matching it is preferable, so that it may to obtain and inductive currentAt the sample rate current I of fixed proportionSENS, that is to say, that it can identify the big of converter load by the size of sample rate currentIt is small.Sample rate current ISENSIt flows into resistance R1 and generates sampled voltage signal VSENS, be compared with reference voltage VREF, so that it may withOutput underloading detection output signal.Wherein reference voltage is to compensate for main main power tube conducting using the electric current of positive temperature coefficientThe temperature characterisitic of resistance.
The above is the preferred embodiment of the present invention, it is noted that those skilled in the art are comeIt says, without departing from the principle of the present invention, several improvements and modifications made also should be regarded as protection scope of the present invention.