技术领域technical field
本发明涉及高速信号技术领域，特别是一种高速链路信号完整性快速评估方法与系统。The invention relates to the technical field of high-speed signals, in particular to a method and system for quickly evaluating high-speed link signal integrity.
背景技术Background technique
在传统数字系统设计中，高速互联现象常常可以忽略不计，因为在传统数字系统中，其对系统性能的影响非常微弱。然而，随着计算机技术的不断发展，在众多决定系统性能的因素里，高速互联现象正起着主导作用，常常导致一些不可预见的问题的出现，极大的增加了系统设计的复杂性。因此，在高速链路设计中，要尽量优化各个模块，借助仿真工具提前评估设计可行性以及风险点，并依据仿真结果优化设计，提高系统设计成功率，缩短研发周期。在服务器系统高速信号链路设计过程中，往往需要基于仿真结果及时调整方案，项目前期的SI评估阶段越早的发现和避免高速信号问题，就能为系统设计争取更多的时间和裕量，具有极强的时效性。High-speed interconnect phenomena are often negligible in traditional digital system designs because their impact on system performance is minimal in traditional digital systems. However, with the continuous development of computer technology, high-speed interconnection is playing a leading role among many factors that determine system performance, which often leads to some unforeseen problems and greatly increases the complexity of system design. Therefore, in the design of high-speed links, it is necessary to optimize each module as much as possible, evaluate the design feasibility and risk points in advance with the help of simulation tools, and optimize the design based on the simulation results to improve the success rate of system design and shorten the development cycle. In the design process of high-speed signal links in server systems, it is often necessary to adjust the scheme in a timely manner based on simulation results. The earlier the SI evaluation stage of the project is to discover and avoid high-speed signal problems, the more time and margin can be gained for system design. Extremely time-sensitive.
现今针对高速链路信号完整性评估，大部分都是基于当前设计找到设计的最差情况，通过仿真最差情况的损耗、反射和眼参数等指标，与工业规范进行对比，若最差情况能够满足设计要求，则链路评估低风险。Nowadays, most of the evaluation of high-speed link signal integrity is based on the current design to find the worst case of the design. By simulating the worst-case loss, reflection and eye parameters and other indicators, and comparing them with industry specifications, if the worst case can If the design requirements are met, the link assessment is low risk.
虽然这种评估思想能够保证评估的准确性，但是在实际操作中却很难实现。在寻找设计最差情况时，需要考虑的因素较多。比如：链路设计长度，PCB板厂制作公差、芯片性能、环境影响等。其中，有些因素很难用精确模型表示，只能近似处理。而且，这种评估方法耗时较长，大大降低了链路评估的时效性。Although this evaluation idea can guarantee the accuracy of evaluation, it is difficult to realize in actual operation. There are many factors to consider when looking for the worst case for a design. For example: link design length, PCB board manufacturing tolerance, chip performance, environmental impact, etc. Among them, some factors are difficult to express with precise models, and can only be approximated. Moreover, this evaluation method takes a long time, which greatly reduces the timeliness of link evaluation.
发明内容Contents of the invention
本发明的目的是提供一种高速链路信号完整性快速评估方法与系统，旨在解决现有技术中对于高速链路信号完整性仿真评估时效性差的问题，实现在较短时间内完成对高速链路的仿真评估，最大程度为链路设计和优化争取时间，提高时效性。The purpose of the present invention is to provide a method and system for fast evaluation of high-speed link signal integrity, which aims to solve the problem of poor timeliness in the simulation evaluation of high-speed link signal integrity in the prior art, and realize the completion of high-speed link signal integrity evaluation in a relatively short period of time. The simulation evaluation of the link maximizes the time for link design and optimization and improves timeliness.
为达到上述技术目的，本发明提供了一种高速链路信号完整性快速评估方法，包括：In order to achieve the above technical purpose, the present invention provides a method for fast evaluation of high-speed link signal integrity, including:
S1、选择经过测验校正的相似类型拓扑作为参考拓扑；S1. Select a similar type of topology that has been tested and corrected as a reference topology;
S2、基于当前拓扑和参考拓扑分别进行建模仿真；S2. Perform modeling and simulation based on the current topology and the reference topology respectively;
S3、分析对比当前拓扑和参考拓扑的仿真结果。S3. Analyzing and comparing the simulation results of the current topology and the reference topology.
优选地，所述相似类型拓扑具体为组成结构相同，但链路长度、过孔位置和PCB材料不同。Preferably, the topologies of the similar type specifically have the same composition structure, but different link lengths, via positions and PCB materials.
优选地，所述建模仿真基于典型条件下，走线的阻抗、loss标准、芯片的驱动特性、外接环境参数均为典型值。Preferably, the modeling and simulation is based on typical conditions, and the impedance of the wiring, the loss standard, the driving characteristics of the chip, and the external environment parameters are all typical values.
优选地，所述建模仿真包括无源仿真和有源仿真。Preferably, the modeling simulation includes passive simulation and active simulation.
优选地，所述有源仿真过程中，链路长度按固定步长在一定区间内遍历，当遍历结果均满足要求时，才可评估通过。Preferably, in the active simulation process, the link length is traversed in a certain interval according to a fixed step size, and the evaluation can only be passed when the traversed results meet the requirements.
本发明还提供了一种高速链路信号完整性快速评估系统，包括：The present invention also provides a high-speed link signal integrity rapid evaluation system, including:
参考拓扑选择模块，用于选择经过测验校正的相似类型拓扑作为参考拓扑；A reference topology selection module, configured to select a test-corrected topology of a similar type as a reference topology;
建模仿真模块，用于基于当前拓扑和参考拓扑分别进行建模仿真；A modeling and simulation module is used to perform modeling and simulation based on the current topology and the reference topology respectively;
仿真结果分析模块，用于分析对比当前拓扑和参考拓扑的仿真结果。The simulation result analysis module is used to analyze and compare the simulation results of the current topology and the reference topology.
优选地，所述相似类型拓扑具体为组成结构相同，但链路长度、过孔位置和PCB材料不同。Preferably, the topologies of the similar type specifically have the same composition structure, but different link lengths, via positions and PCB materials.
优选地，所述建模仿真基于典型条件下，走线的阻抗、loss标准、芯片的驱动特性、外接环境参数均为典型值。Preferably, the modeling and simulation is based on typical conditions, and the impedance of the wiring, the loss standard, the driving characteristics of the chip, and the external environment parameters are all typical values.
优选地，所述建模仿真模块包括：Preferably, the modeling simulation module includes:
无源仿真单元，用于基于当前拓扑和参考拓扑进行无源仿真；Passive simulation unit for passive simulation based on current topology and reference topology;
有源仿真单元，用于基于当前拓扑和参考拓扑进行有源仿真。Active simulation unit for active simulation based on current and reference topologies.
发明内容中提供的效果仅仅是实施例的效果，而不是发明所有的全部效果，上述技术方案中的一个技术方案具有如下优点或有益效果：The effects provided in the summary of the invention are only the effects of the embodiments, rather than all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects:
与现有技术相比，本发明通过将当前设计链路拓扑与经过测试验证的类似参考拓扑相比较，基于各自链路的典型参数进行对比仿真，通过两者的结果进行对比分析，进而快速评估链路风险。解决了现有技术中对于高速链路信号完整性仿真评估时效性差的问题，实现在较短时间内完成对高速链路的仿真评估，最大程度为链路设计和优化争取时间，提高时效性。该方法充分利用了历史积累的数据，能够快速评估相似链路设计风险，提高了高速链路评估效率，为项目设计优化争取了更多的时间。Compared with the prior art, the present invention compares the current design link topology with the similar reference topology that has been tested and verified, performs comparative simulation based on the typical parameters of the respective links, conducts comparative analysis through the results of the two, and then quickly evaluates Link risk. It solves the problem of poor timeliness in the simulation evaluation of high-speed link signal integrity in the prior art, realizes the simulation evaluation of high-speed links in a relatively short period of time, buys time for link design and optimization to the greatest extent, and improves timeliness. This method makes full use of historically accumulated data, can quickly evaluate similar link design risks, improves the efficiency of high-speed link evaluation, and buys more time for project design optimization.
附图说明Description of drawings
图1为本发明实施例中所提供的一种高速链路信号完整性快速评估方法流程图；FIG. 1 is a flow chart of a method for quickly evaluating high-speed link signal integrity provided in an embodiment of the present invention;
图2为本发明实施例中所提供的一种当前设计链路拓扑结构示意图；FIG. 2 is a schematic diagram of a currently designed link topology provided in an embodiment of the present invention;
图3为本发明实施例中所提供的一种参考链路拓扑结构示意图；FIG. 3 is a schematic diagram of a reference link topology structure provided in an embodiment of the present invention;
图4为本发明实施例中所提供的链路信号无源仿真结果示意图；FIG. 4 is a schematic diagram of a passive simulation result of a link signal provided in an embodiment of the present invention;
图5为本发明实施例中所提供的一种高速链路信号完整性快速评估系统结构框图。Fig. 5 is a structural block diagram of a high-speed link signal integrity rapid evaluation system provided in an embodiment of the present invention.
具体实施方式Detailed ways
为了能清楚说明本方案的技术特点，下面通过具体实施方式，并结合其附图，对本发明进行详细阐述。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。应当注意，在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。In order to clearly illustrate the technical features of the present solution, the present invention will be described in detail below through specific implementation methods and in conjunction with the accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. It should be noted that components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted herein to avoid unnecessarily limiting the present invention.
下面结合附图对本发明实施例所提供的一种高速链路信号完整性快速评估方法与系统进行详细说明。A method and system for quickly evaluating high-speed link signal integrity provided by embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
如图1所示，本发明实施例公开了一种高速链路信号完整性快速评估方法，包括以下步骤：As shown in Figure 1, an embodiment of the present invention discloses a method for quickly evaluating signal integrity of a high-speed link, including the following steps:
S1、选择经过测验校正的相似类型拓扑作为参考拓扑；S1. Select a similar type of topology that has been tested and corrected as a reference topology;
根据当前高速链路的拓扑结构，从前期项目中选择经过测试验证的较为相似的拓扑中，选择相似类型的拓扑结构作为参考拓扑。According to the topological structure of the current high-speed link, select a similar type of topology from the relatively similar topologies that have been tested and verified in the previous project as the reference topology.
如图2所示，某PCIE简化链路中，主板发射芯片经主板走线到连接器，再通过转接板连接到背板，最终到达终端硬盘，图中标出了各段的走线长度以及过孔分布情况。As shown in Figure 2, in a simplified PCIE link, the motherboard transmitter chip is routed to the connector through the motherboard, and then connected to the backplane through the adapter board, and finally reaches the terminal hard disk. Via distribution.
通过对比拓扑结构，从前期项目中找到经过测试验证的较为相似的拓扑中，选择相同类型的拓扑结构作为参考拓扑，所选参考拓扑的组成结构相同。参考拓扑如图3所示，该参考拓扑也是由主板、转接板、背板和硬盘组成，不同点在于链路长度、过孔位置和PCB材料等。By comparing the topologies, from the similar topologies that have been tested and verified in the previous projects, select the same type of topology as the reference topology, and the composition of the selected reference topology is the same. The reference topology is shown in Figure 3. This reference topology is also composed of a mainboard, an adapter board, a backplane, and a hard disk. The differences lie in link length, via location, and PCB material.
S2、基于当前拓扑和参考拓扑分别进行建模仿真；S2. Perform modeling and simulation based on the current topology and the reference topology respectively;
将参考拓扑和当前高速链路的拓扑在各自典型条件下进行仿真。将走线的阻抗以及loss标准、芯片的驱动特性、外接环境参数等都选择典型值，设置好后进行建模仿真。The reference topology and the topology of the current high-speed link are simulated under their respective typical conditions. Select typical values for the impedance and loss standards of the traces, the driving characteristics of the chip, and the external environmental parameters, and then perform modeling and simulation after setting them.
以PCB走线为例，当前设计选择材料的典型loss指标为0.58db/inch@4G Hz,而参考拓扑设计选用材料的典型loss指标为0.65db/inch@4G Hz，分别按照对应的指标分别建立当前拓扑和参考拓扑的PCB走线模型。链路中的各部分模型(过孔以及连接器等)建立完成后就可以进行无源和有源仿真。Taking PCB traces as an example, the typical loss index of the material selected for the current design is 0.58db/inch@4G Hz, while the typical loss index of the material selected for the reference topology design is 0.65db/inch@4G Hz, respectively established according to the corresponding index PCB trace models for the current topology and the reference topology. Passive and active simulations can be performed after the model of each part in the link (via hole and connector, etc.) is established.
S3、分析对比当前拓扑和参考拓扑的仿真结果；S3. Analyzing and comparing the simulation results of the current topology and the reference topology;
无源仿真如图4所示，从图中可以看出，当前设计的拓扑的无源特性优于参考拓扑。The passive simulation is shown in Figure 4. It can be seen from the figure that the passive characteristics of the currently designed topology are better than the reference topology.
有源仿真如表1所示，在进行有源仿真时，为了避免谐振对仿真结果的影响，建议将链路长度在合适区间内遍历，按照0.1inch的步长，从原始长度L遍历至L-0.5inch，当遍历结果都满足设计要求时才能认为评估结果可靠。在遍历区间内，当前设计均优于参考拓扑，而参考拓扑在前期测试中满足设计要求，因此可以基于上述仿真结果评估链路风险较低。Active simulation is shown in Table 1. During active simulation, in order to avoid the influence of resonance on the simulation results, it is recommended to traverse the link length within a suitable interval, from the original length L to L according to the step size of 0.1inch. -0.5inch, when the traversal results meet the design requirements, the evaluation results can be considered reliable. In the traversal interval, the current design is better than the reference topology, and the reference topology meets the design requirements in the previous test, so it can be estimated that the link risk is low based on the above simulation results.
表1Table 1
本发明实施例通过将当前设计链路拓扑与经过测试验证的类似参考拓扑相比较，基于各自链路的典型参数进行对比仿真，通过两者的结果进行对比分析，进而快速评估链路风险。解决了现有技术中对于高速链路信号完整性仿真评估时效性差的问题，实现在较短时间内完成对高速链路的仿真评估，最大程度为链路设计和优化争取时间，提高时效性。该方法充分利用了历史积累的数据，能够快速评估相似链路设计风险，提高了高速链路评估效率，为项目设计优化争取了更多的时间。The embodiment of the present invention compares the currently designed link topology with a similar reference topology that has been tested and verified, performs comparative simulation based on typical parameters of the respective links, and conducts a comparative analysis of the results of the two, thereby quickly assessing link risks. It solves the problem of poor timeliness in the simulation evaluation of high-speed link signal integrity in the prior art, realizes the simulation evaluation of high-speed links in a relatively short time, buys time for link design and optimization to the greatest extent, and improves timeliness. This method makes full use of historically accumulated data, can quickly evaluate similar link design risks, improves the efficiency of high-speed link evaluation, and buys more time for project design optimization.
如图5所示，本发明实施例还公开了一种高速链路信号完整性快速评估系统，包括：As shown in Figure 5, the embodiment of the present invention also discloses a high-speed link signal integrity rapid evaluation system, including:
参考拓扑选择模块，用于选择经过测验校正的相似类型拓扑作为参考拓扑；A reference topology selection module, configured to select a test-corrected topology of a similar type as a reference topology;
通过对比拓扑结构，从前期项目中找到经过测试验证的较为相似的拓扑中，选择相同类型的拓扑结构作为参考拓扑，所选参考拓扑的组成结构相同。By comparing the topologies, from the similar topologies that have been tested and verified in the previous projects, select the same type of topology as the reference topology, and the composition of the selected reference topology is the same.
建模仿真模块，用于基于当前拓扑和参考拓扑分别进行建模仿真；A modeling and simulation module is used to perform modeling and simulation based on the current topology and the reference topology respectively;
将参考拓扑和当前高速链路的拓扑在各自典型条件下进行仿真。将走线的阻抗以及loss标准、芯片的驱动特性、外接环境参数等都选择典型值。The reference topology and the topology of the current high-speed link are simulated under their respective typical conditions. Select typical values for the impedance and loss standards of the traces, the driving characteristics of the chip, and the external environmental parameters.
仿真结果分析模块，用于分析对比当前拓扑和参考拓扑的仿真结果。The simulation result analysis module is used to analyze and compare the simulation results of the current topology and the reference topology.
所述建模仿真模块包括：The modeling simulation module includes:
无源仿真单元，用于基于当前拓扑和参考拓扑进行无源仿真；Passive simulation unit for passive simulation based on current topology and reference topology;
有源仿真单元，用于基于当前拓扑和参考拓扑进行有源仿真。Active simulation unit for active simulation based on current and reference topologies.
在进行有源仿真时，为了避免谐振对仿真结果的影响，建议将链路长度在合适区间内遍历，按照0.1inch的步长，从原始长度L遍历至L-0.5inch，当遍历结果都满足设计要求时才能认为评估结果可靠。When performing active simulation, in order to avoid the influence of resonance on the simulation results, it is recommended to traverse the link length in a suitable range, according to the step size of 0.1inch, traverse from the original length L to L-0.5inch, when the traverse results meet Evaluation results are considered reliable only when required by the design.
所述相似类型拓扑具体为组成结构相同，但链路长度、过孔位置和PCB材料不同。The topologies of similar types specifically have the same composition and structure, but different link lengths, via positions and PCB materials.
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.
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| CN201810496734.1ACN108763717A (en) | 2018-05-22 | 2018-05-22 | A kind of high speed link signal integrality fast evaluation method and system |
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