CN108646483B - Array substrate, display panel and display device - Google Patents

Abstract

Translated fromChinese

本发明公开了一种阵列基板、显示面板和显示装置。该阵列基板包括：多条信号线，多条信号线包括第一信号线和第二信号线，第一信号线的负载大于第二信号线的负载；测试引线；控制引线；多个测试开关，测试开关包括输出端、输入端和控制端，每个测试开关的输出端均与一条不同的信号线电连接，每个测试开关的输入端均与一条测试引线电连接，每个测试开关的控制端均与一条控制引线电连接；多个测试开关包括第一测试开关和第二测试开关，第一测试开关的输出端与第一信号线电连接，第二测试开关的输出端与第二信号线电连接；其中，第一测试开关的开态电流大于第二测试开关的开态电流。通过本发明，能够提高测试的准确度。

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises: a plurality of signal lines, the plurality of signal lines include a first signal line and a second signal line, the load of the first signal line is greater than the load of the second signal line; a test lead; a control lead; a plurality of test switches, The test switch includes an output end, an input end and a control end. The output end of each test switch is electrically connected with a different signal line, and the input end of each test switch is electrically connected with a test lead. The control of each test switch The terminals are all electrically connected to a control lead; the plurality of test switches include a first test switch and a second test switch, the output terminal of the first test switch is electrically connected to the first signal line, and the output terminal of the second test switch is connected to the second signal line. The wires are electrically connected; wherein, the on-state current of the first test switch is greater than the on-state current of the second test switch. Through the present invention, the accuracy of the test can be improved.

Description

Array substrate, display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

After the display panel is packaged, before a chip (IC) or a Flexible Printed Circuit (FPC) is pressed onto the display panel, the display panel needs to be tested, and the test in a Switch (SW) manner is common. During testing, an external test signal is transmitted to a data signal line of the display panel through the switch to provide a data signal for the pixel, and the display effect of the pixel is tested. In addition, for a touch display panel in which a touch function is integrated in the display panel, the touch function needs to be tested in addition to testing the display effect of the pixels. When the touch control function is tested, similar to the display effect of the test pixels, the external test signal is transmitted to the touch control electrode wire through the switch to provide an input signal for the touch control electrode, and the touch control detection function of the touch control electrode is tested.

With the development of display panels, the shapes of display panels are gradually diversified, and the traditional rectangle is gradually developed into various shapes, for example, a display panel with a corner in an arc shape or a display panel in a circular shape, and when the special-shaped display panel is tested in an SW manner, the display difference or the touch difference caused by the special shape of the special-shaped display panel is easily misjudged as the abnormality of the display panel, so that the test accuracy of the display panel is reduced.

Therefore, it is an urgent need to solve the problem in the art to provide an array substrate, a display panel and a display device, so as to improve the accuracy of testing a special-shaped display panel.

Disclosure of Invention

In view of this, the invention provides an array substrate, a display panel and a display device, which solve the technical problem of low test accuracy of a special-shaped display panel in the prior art.

In order to solve the above technical problems, the present invention provides an array substrate.

The array substrate includes: a plurality of signal lines including a first signal line and a second signal line, a load of the first signal line being greater than a load of the second signal line; testing a lead; a control lead; the test switch comprises an output end, an input end and a control end, the output end of each test switch is electrically connected with a different signal wire, the input end of each test switch is electrically connected with one test lead, and the control end of each test switch is electrically connected with one control lead; the plurality of test switches comprise a first test switch and a second test switch, the output end of the first test switch is electrically connected with the first signal line, and the output end of the second test switch is electrically connected with the second signal line; wherein the on-state current of the first test switch is greater than the on-state current of the second test switch.

On the other hand, based on the same inventive concept, the invention also provides a display panel.

The display panel provided by the invention comprises any one array substrate provided by the invention.

On the other hand, based on the same inventive concept, the invention also provides a display device.

The display device provided by the invention comprises any one display panel provided by the invention.

Compared with the prior art, the array substrate, the display panel and the display device have the advantages that:

for a first signal line with a larger load and a second signal line with a smaller load on the array substrate, the on-state current of the test switch connected with the first signal line is set to be larger than the on-state current of the test switch connected with the second signal line, namely the on-state current of the first test switch is larger than the on-state current of the second test switch, so that the driving capability of the first test switch is larger than that of the second test switch, the load difference between the first signal line and the second signal line can be compensated, and therefore when testing is carried out, poor display caused by the load difference of the signal lines can be improved, and the testing accuracy can be improved.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic structural diagram of an array substrate according to the prior art;

fig. 2 is a schematic circuit diagram of an array substrate according to an embodiment of the invention;

fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the invention;

fig. 4 is a schematic structural diagram of a touch portion of an array substrate according to an embodiment of the invention;

fig. 5 is a schematic structural diagram of a touch portion of another array substrate according to an embodiment of the invention;

fig. 6 is a schematic structural diagram of a touch portion of another array substrate according to an embodiment of the invention;

fig. 7 is a schematic structural diagram of a touch portion of another array substrate according to an embodiment of the invention;

fig. 8 is a schematic structural diagram of a mutual capacitance type touch electrode according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another mutual capacitance type touch electrode according to an embodiment of the present invention;

fig. 10 is a schematic diagram of a test switch in an array substrate according to an embodiment of the invention;

fig. 11 is a schematic diagram of a first test switch and a second test switch in an array substrate according to an embodiment of the invention;

fig. 12 is a schematic diagram of another first test switch and a second test switch in the array substrate according to the embodiment of the invention;

fig. 13 is a schematic structural view of another array substrate according to an embodiment of the invention;

fig. 14 is a schematic structural diagram of a display device according to an embodiment of the invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

The inventors have conducted the following studies on the array substrate in the related art: fig. 1 is a schematic structural diagram of an array substrate according to the related art, and as shown in fig. 1, the array substrate includes a plurality of data signal lines 10 'extending in a first direction y' for transmitting data signals, i.e., voltage signals for displaying gray scales, to pixels SP ', and normally, the plurality of pixels SP' are sequentially arranged in the first direction y 'to form a pixel column PY', and one data signal line 10 'is connected to each pixel SP' of the pixel column PY ', i.e., a load of one data signal line 10' includes all the pixels SP 'of the pixel column PY'. The array substrate further includes a test switch SW ' connected to the data signal line 10', receiving an external test signal, and transmitting the external test signal to the pixel SP ' through the data signal line 10', so as to test the pixel SP '. It should be noted that the test switch SW ' in the figure is only used for schematically showing the connection relationship with the data signal line 10', and it is not limited that all thedata signal lines 10 can only be connected to the same test switch SW '.

For the irregular-shaped display panel as shown in fig. 1, the number of pixels SP ' included in each pixel column PY ' is not equal in the first direction y ', and in the array substrate of the display panel having the arc-shaped corners as shown in fig. 1, the number of pixels SP ' included in the pixel column PY ' in the area close to the edge of the array substrate in the second direction x ' is reduced compared to the pixel column PY ' in the central area of the array substrate, so that the load of the data signal line 10' driving the central area of the array substrate is greater than the load of the data signal line 10' driving the edge of the array substrate.

When the driving capability of each test switch SW 'connected to the data signal lines 10' with different loads is the same, a display difference, specifically, a display failure, occurs when the pixels SP 'in the central region and the pixels SP' in the edge region are displayed during the test. The quality problem of the display panel itself may also cause the difference between the pixels SP 'in the central area and the pixels SP' in the edge area. Therefore, in the test process, when the difference occurs between the display of the pixel SP 'in the central area and the display of the pixel SP' in the area close to the edge, the real reason causing the difference cannot be accurately determined, and if the difference is ignored, the display panel with quality problem may be missed; if the quality problem of the display panel is directly judged, the misjudgment can occur.

Therefore, in the prior art, when the special-shaped display panel adopting the array substrate is used for testing the display pixels, the testing accuracy is low. Meanwhile, for the special-shaped display panel with the touch function, when the touch function or the display function is tested, due to different loads on different touch signal lines, a problem similar to the test process of the display pixels can occur, and the test accuracy is reduced. In addition, with the conventional display panel, a similar problem occurs when the loads of the signal lines to be tested are different.

Based on the above research, in order to improve the accuracy of the display panel test, the present application provides an array substrate, a display panel and a display device, and the following detailed descriptions are respectively provided for embodiments of the array substrate, the display panel and the display device provided by the present application.

Fig. 2 is a schematic circuit connection diagram of an array substrate according to an embodiment of the present invention, and as shown in fig. 2, the array substrate includes a plurality ofsignal lines 10, test leads 20, control leads 30, and a plurality of test switches SW.

Thesignal line 10 is a trace for transmitting signals of a peripheral circuit or an integrated circuit chip to a driven load in the array substrate, such as a data signal line, a touch signal line, or other signal lines. The plurality ofsignal lines 10 include afirst signal line 11 and asecond signal line 12, and a load of thefirst signal line 11 is larger than a load of thesecond signal line 12. The load of thefirst signal line 11 includes a resistive load, and the load of thesecond signal line 12 includes a resistive load, and at this time, the resistance value of the resistive load of thefirst signal line 11 is greater than the resistance value of the resistive load of thesecond signal line 12. And/or the load of thefirst signal line 11 comprises a capacitive load, and the load of thesecond signal line 12 comprises a capacitive load, and at this time, the capacitance value of the capacitive load of thefirst signal line 11 is greater than that of the capacitive load of thesecond signal line 12. The specific form of the load of thefirst signal line 11 and thesecond signal line 12 is not limited in this embodiment.

The test switch SW includes an output terminal O, an input terminal I, and a control terminal C. Thetest lead 20 is connected to an external test signal generating device, the number of the test leads 20 on the array substrate may be one or more, the input terminal I of each test switch SW is electrically connected to onetest lead 20, the input terminal I of each test switch SW may be connected todifferent test leads 20, or as shown in fig. 2, may also be connected to thesame test lead 20, and the test switches SW receive the test signal generated by the test signal generating device through the input terminals I; thecontrol lead 30 is connected, for example, to an external control signal generator, thecontrol lead 30 on the array substrate may be one or more, the control end C of each test switch SW is electrically connected to onecontrol lead 30, the control end C of each test switch SW may be connected to different control leads 30, or as shown in fig. 2, may also be connected to thesame control lead 30, and the test switch SW receives a control signal generated by the control signal generator through the control end C, so that the input end I and the output end O are turned on or off, wherein the test signal generator and the control signal generator may be integrated in the same test fixture, or may be separately disposed in different test fixtures; the output end O of each test switch SW is electrically connected to onesignal line 10, and when the input end I of the test switch is conducted with the output end O, a test signal is supplied to thesignal line 10, so that the test of the load function is realized.

The plurality of test switches SW include a first test switch SW1 and a second test switch SW2, an output end O1 of the first test switch SW1 is electrically connected to thefirst signal line 11, an output end O2 of the second test switch SW2 is electrically connected to thesecond signal line 12, and an on-state current of the first test switch SW1 is greater than an on-state current of the secondtest switch SW 2. The charging time of the test switch SW is influenced by the on-state current of the test switch SW, and the larger the on-state current is, the more sufficient the charging is in a limited time, and the stronger the driving capability of the test switch SW is.

In the present application, for the first test switch SW1 and the second test switch SW2, the on-state current of the first test switch SW1 is set to be greater than the on-state current of the second test switch SW2, so that the driving capability of the first test switch SW1 is greater than the driving capability of the second test switch SW2, and the load difference between thefirst signal line 11 and thesecond signal line 12 can be compensated, so that when a test is performed, the display defect caused by the load difference of the signal lines can be improved, and the accuracy of the test can be further improved.

It should be noted that, among the plurality of test switches SW of the array substrate, at least the first test switch SW1 and the second test switch SW2 are connected todifferent signal lines 10, for example, different test switches SW are connected todifferent signal lines 10 in fig. 1, alternatively, one test switch SW may be connected todifferent signal lines 10, but the loads of thesignal lines 10 connected to the same test switch SW are the same, so as to reduce the number of test switches SW and reduce the frame of the array substrate.

Optionally, fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and as shown in fig. 3, the array substrate includes a plurality ofdata lines 10a and a plurality of gate lines 40, and the plurality ofdata lines 10a and the plurality of gate lines 40 are insulated and crossed to define a plurality of pixel units SP. The plurality ofsignal lines 10 include a plurality ofdata lines 10a, and eachdata line 10a is electrically connected to at least one pixel unit SP. Among them, the gate line 40 supplies a scan signal to the pixel unit SP, and thedata line 10a supplies a data signal to the pixel unit SP.

With this embodiment, when testing the pixel units SP on the display panel, the test switch SW receives the test signal, i.e., the data signal, generated by the test signal generating device through the input terminal I, and when the input terminal I and the output terminal O of the test switch SW are turned on, the data signal is supplied to thedata line 10a, so that the test of the display function of the pixel units SP can be realized. When the number of the pixel units SP connected todifferent data lines 10a is different, that is, the load of thedata lines 10a is different, the on-state currents of the corresponding test switches SW are set to be different, and the difference in the number of the pixel units SP connected to thedata lines 10a is compensated through the difference in the on-state currents of the test switches SW, so that when a display test is performed, the display difference of the display panel caused by the difference in the number of the pixel units SP connected to thedata lines 10a is reduced, when the display difference is generated on the display panel, and the quality problem of the display panel is directly determined, the misjudgment can be reduced, and the accuracy of the test is improved.

In a specific embodiment, as shown in fig. 3, each pixel unit SP includes a pixel transistor Ta and a pixel electrode P, the pixel transistor Ta has a gate, a source and a drain, wherein the gate line 40 is electrically connected to the gate of the thin film transistor, thedata line 10a is electrically connected to the pixel unit SP, specifically, thedata line 10a is electrically connected to the source of the pixel transistor Ta, the drain of the pixel transistor Ta is electrically connected to the pixel electrode P, the array substrate may further have a common electrode thereon, or a substrate opposite to the array substrate has a common electrode thereon, and an electric field for deflecting liquid crystal molecules is formed between the pixel electrode and the common electrode. The plurality of pixel units SP are arranged in the first direction y to form a plurality of pixel columns py, in the second direction x to form a plurality of pixel rows px, one pixel row px being connected to each gate line 40, and one pixel column py being connected to eachdata line 10 a. The plurality ofdata lines 10a include afirst data line 11a (i.e., a first signal line) and asecond data line 12a (i.e., a second signal line), a first pixel column connected to thefirst data line 11a includes M pixel units SP, and a second pixel column connected to thesecond data line 12a includes N pixel units SP, where M > N ≧ 1, i.e., the number of pixel units SP connected to thefirst data line 11a is greater than the number of pixel units SP connected to thesecond data line 12a, where the greater the number of pixel units connected to the data line, the greater the load of the data line, and thus the greater the load of thefirst data line 11a is than the load of thesecond data line 12 a. For example, in fig. 3, the first pixel column connected by thefirst data line 11a includes 4 pixel units SP, and the second pixel column connected by thesecond data line 12a includes 2 pixel units SP, and it should be noted that the number of pixels in the pixel column and the pixel row in fig. 3 does not constitute a limitation on the array substrate, and is only a schematic illustration of the arrangement of the pixel units. Thefirst data line 11a is electrically connected to the first test switch SW1, and thesecond data line 12a is electrically connected to the second test switch SW2, at this time, since the on-state current of the first test switch SW1 is greater than the on-state current of the second test switch SW2, so that the driving capability of the first test switch SW1 is greater than that of the second test switch SW2, it is possible to compensate for the difference in the number of the pixel cells SP connected to thefirst data line 11a and thesecond data line 12a, and thus, when performing the display test, it is possible to reduce the display difference caused by the difference in the number, that is, the display difference between the display cells SP connected to thefirst data line 11a and the display cells SP connected to thesecond data line 12 a. Therefore, on the basis of reducing the display difference caused by the number difference, when the display difference is determined as the display problem in the test process, compared with the prior art, the misjudgment is reduced, and the test accuracy of the display unit of the display panel is improved.

Optionally, fig. 4 is a schematic structural diagram of a touch portion of an array substrate according to an embodiment of the present invention, fig. 5 is a schematic structural diagram of a touch portion of another array substrate according to an embodiment of the present invention, fig. 6 is a schematic structural diagram of a touch portion of another array substrate according to an embodiment of the present invention, and fig. 7 is a schematic structural diagram of a touch portion of another array substrate according to an embodiment of the present invention, as shown in fig. 4 to fig. 7, the array substrate is provided with a touch portion, specifically, the array substrate includes a touch electrode layer, the touch electrode layer includes a plurality of touch electrodes TP, each touch electrode TP is electrically connected to onetouch signal line 10b, and the plurality ofsignal lines 10 includetouch signal lines 10 b. Thetouch signal line 10b provides a touch driving signal to the touch electrode TP.

By adopting the embodiment, when the touch electrode TP integrated on the display panel is tested, the test switch SW receives the test signal, i.e. the touch driving signal, generated by the test signal generating device through the input terminal I, and when the input terminal I and the output terminal O of the test switch SW are conducted, the touch driving signal is fed to thetouch signal line 10b, so that the test of the touch function of the touch electrode TP can be realized. When the areas of the touch electrodes TP connected to differenttouch signal lines 10b are different, that is, the loads of thetouch signal lines 10b are different, the on-state currents of the corresponding test switches SW are set to be different, and the area difference of the touch electrodes TP connected to thetouch signal lines 10b is compensated through the on-state current difference of the test switches SW, so that the touch difference of the display panel caused by the area difference of the touch electrodes TP connected to thetouch signal lines 10b is reduced during touch test, and when the touch difference is generated on the display panel and the quality problem of the display panel is directly determined, the misjudgment can be reduced, and the test accuracy is improved. It should be noted that, during the touch test, eachtouch signal line 10b is electrically connected to only one different test switch SW.

Alternatively, in an embodiment, the touch electrode is reused as a common electrode in the display stage, so that, in the display stage, thetouch signal line 10b provides a common voltage signal to the touch electrode TP, and in the touch stage, thetouch signal line 10b provides a touch driving signal to the touch electrode TP.

By adopting the embodiment, when testing the touch electrode TP integrated on the display panel, the test for the touch function includes the above-mentioned test for the touch function, and also includes the test for the display function as the common electrode, and for the test for the touch function as the touch electrode, the details are not repeated here. For the test of the display function as the common electrode, the test switch SW receives the test signal, i.e., the common voltage signal, generated by the test signal generating device through the input terminal I, and when the input terminal I and the output terminal O of the test switch SW are turned on, the common voltage signal is supplied to thetouch signal line 10b, so that the test of the touch electrode TP as the common electrode can be realized. When the areas of the touch electrodes TP connected to differenttouch signal lines 10b are different, that is, the loads of thetouch signal lines 10b are different, the on-state currents of the corresponding test switches SW are set to be different, and the area difference of the touch electrodes TP connected to thetouch signal lines 10b is compensated through the on-state current difference of the test switches SW, so that when a display function test is performed, the display difference of the display panel caused by the area difference of the touch electrodes TP connected to thetouch signal lines 10b is reduced, when the display difference is generated on the display panel, and the quality problem of the display panel can be directly determined, the misjudgment can be reduced, and the test accuracy is improved.

In an embodiment, with reference to fig. 4 and fig. 5, the touch electrode TP is a first electrode TP1 extending in a first direction y, and the plurality of first electrodes TP1 are sequentially arranged in a second direction x, wherein the first direction y intersects the second direction x. Fig. 4 and 5 illustrate two cases where the touch electrodes TP on the array substrate have different areas, and the array substrate illustrated in fig. 4 directly forms the touch electrodes TP having different sizes when the pattern of the touch electrodes TP is formed. When the pattern of the touch electrodes TP is formed on the array substrate shown in fig. 5, the touch electrodes TP with the same size are formed, and the touch electrodes TP at the cut edge are smaller than the touch electrodes TP at other positions when the display panel is cut.

The first electrode TP1 is used as one side electrode in mutual capacitance type touch detection, and the other side electrode in mutual capacitance type touch detection is further disposed on the array substrate or the substrate opposite to the array substrate, specifically, fig. 8 is a schematic structural diagram of a mutual capacitance type touch electrode according to an embodiment of the present invention, fig. 8 illustrates that a third electrode TP3 is disposed on the array substrate BS1, fig. 9 is a schematic structural diagram of another mutual capacitance type touch electrode according to an embodiment of the present invention, fig. 9 illustrates that a third electrode TP3 is disposed on the substrate BS2 opposite to the array substrate BS1, and the third electrode TP3 extends in the second direction y and is sequentially arranged in the first direction x. The first electrode TP1 and the third electrode TP3 are used for implementing mutual capacitive touch detection. The first electrode TP1 and the third electrode TP3 may be grid-shaped electrodes formed by using a metal material, or stripe-shaped electrodes formed by using a thin film conductive material as shown in fig. 8 and 9, or electrodes having other shapes and structures in the prior art, which is not limited in this embodiment.

Eachtouch signal line 10b is electrically connected to one first electrode TP1, provides a touch driving signal to each first electrode TP1, wherein the plurality oftouch signal lines 10b include a firsttouch signal line 11b (i.e., a first signal line) and a secondtouch signal line 12b (i.e., a second signal line), the area of the first electrode TP1 connected to the firsttouch signal line 11b is S1, the area of the first electrode TP1 connected to the secondtouch signal line 12b is S2, wherein S1 > S2 > 0, that is, the area of the first electrode TP1 connected to the firsttouch signal line 11b is larger than the area of the first electrode TP1 connected to the secondtouch signal line 12b, the larger the area of the electrode connected to the touch signal line is, the larger the load of the touch signal line is, and thus, the load of the firsttouch signal line 11b is greater than the load of the secondtouch signal line 12 b. The firsttouch signal line 11b is electrically connected to the first test switch SW1, and the secondtouch signal line 12b is electrically connected to the second test switch SW2, at this time, since the on-state current of the first test switch SW1 is greater than the on-state current of the second test switch SW2, so that the driving capability of the first test switch SW1 is greater than that of the second test switch SW2, the area difference of the first electrode TP1 connected to the firsttouch signal line 11b and the secondtouch signal line 12b can be compensated, and thus, when performing a touch test, the touch difference caused by the area difference, that is, the touch difference between the first electrode TP1 connected to the firsttouch signal line 11b and the first electrode TP1 connected to the secondtouch signal line 12b, can be reduced. Therefore, on the basis of reducing the touch control difference caused by the area difference, when the touch control difference is determined as the touch control problem in the test process, compared with the prior art, the misjudgment is reduced, and the test accuracy of the touch control function of the display panel is improved.

In another specific embodiment, as shown in fig. 6 and 7, the touch electrode TP is a second electrode TP2, and a plurality of second electrodes TP2 are arranged in a matrix array for implementing self-capacitance touch detection. Fig. 6 and 7 show two cases where the touch electrodes TP on the array substrate have different areas, and the array substrate shown in fig. 6 directly forms the touch electrodes TP having different sizes when the pattern of the touch electrodes TP is formed. When the pattern of the touch electrodes TP is formed on the array substrate shown in fig. 7, the touch electrodes TP with the same size are formed, and the touch electrodes TP at the cut edge are smaller than the touch electrodes TP at other positions when the display panel is cut.

Eachtouch signal line 10b is electrically connected to one second electrode TP2, and provides a touch driving signal to each second electrode TP2, wherein the plurality oftouch signal lines 10b include a firsttouch signal line 11b (i.e., a first signal line) and a secondtouch signal line 12b (i.e., a second signal line), the area of the second electrode TP2 connected to the firsttouch signal line 11b is S1, the area of the second electrode TP2 connected to the secondtouch signal line 12b is S2, wherein S1 > S2 > 0, that is, the area of the second electrode TP2 connected to the firsttouch signal line 11b is larger than the area of the second electrode TP2 connected to the secondtouch signal line 12b, the larger the area of the electrode connected to the touch signal line is, the larger the load of the touch signal line is, and thus, the load of the firsttouch signal line 11b is greater than the load of the secondtouch signal line 12 b. The firsttouch signal line 11b is electrically connected to the first test switch SW1, and the secondtouch signal line 12b is electrically connected to the second test switch SW2, at this time, since the on-state current of the first test switch SW1 is greater than the on-state current of the second test switch SW2, so that the driving capability of the first test switch SW1 is greater than that of the second test switch SW2, the area difference of the second electrode TP2 connected to the firsttouch signal line 11b and the secondtouch signal line 12b can be compensated, and thus, when performing a touch test, the touch difference caused by the area difference, that is, the touch difference between the second electrode TP2 connected to the firsttouch signal line 11b and the second electrode TP2 connected to the secondtouch signal line 12b, can be reduced. Therefore, on the basis of reducing the touch control difference caused by the area difference, when the touch control difference is determined as the touch control problem in the test process, compared with the prior art, the misjudgment is reduced, and the test accuracy of the touch control function of the display panel is improved.

Alternatively, fig. 10 is a schematic diagram of a test switch in an array substrate according to an embodiment of the present invention, as shown in fig. 10, the test switch SW includes a switch transistor Tb, the switch transistor Tb includes an active layer a, a gate G, a source S, and a drain D, where a connection end of the gate G of the switch transistor Tb is a control end of the test switch SW and is electrically connected to thecontrol lead 30, a connection end of the source S of the switch transistor Tb is an input end of the test switch SW and is electrically connected to the test lead, a connection end of the drain of the switch transistor Tb is an output end of the test switch SW and is electrically connected to the signal line, a channel for moving carriers is formed between the source S and the drain D at a portion where the active layer a overlaps the gate G, L1 shown in fig. 10 is a channel length, and L2 is a channel width.

Specifically, fig. 11 is a schematic diagram of a first test switch and a second test switch in an array substrate according to an embodiment of the present invention, and fig. 12 is a schematic diagram of another first test switch and another second test switch in an array substrate according to an embodiment of the present invention, as shown in fig. 11 and 12, the first test switch includes a first switch transistor Tb1, the first switch transistor Tb1 includes a first active layer a1, a gate G1 of the first switch transistor Tb1 is electrically connected to a control lead 30, a source S1 of the first switch transistor Tb1 is electrically connected to a test lead 20, and a drain D1 of the first switch transistor Tb1 is electrically connected to a first signal line 11; the second test switch comprises a second switch transistor Tb2, the second switch transistor Tb2 comprises a second active layer A2, the gate G2 of the second switch transistor Tb2 is electrically connected with the control lead 10, the source S2 of the second switch transistor Tb2 is electrically connected with the test lead 20, the drain D2 of the second switch transistor Tb2 is electrically connected with the second signal line 12, and the difference of the on-state currents of the first switch transistor and the second switch transistor is realized by arranging the first switch transistor Tb1 and the second switch transistor Tb2 to be different in structure.

By adopting the array substrate provided by the embodiment, the test switch has a simple structure, occupies a small area of a frame area of the array substrate, and can be prepared with a pixel transistor of a display unit in the same process, so that the process of the array substrate is reduced.

In particular, when the on-state currents of the first switching transistor and the second switching transistor are different, the on-state currents can be realized by one or more of the following methods.

In one approach, the width-to-length ratio of the first switching transistor channel is set to be greater than the width-to-length ratio of the second switching transistor channel.

As shown in fig. 11, the width-to-length ratio L21/L11 of the channel of the first switching transistor Tb1 is greater than the width-to-length ratio L22/L12 of the channel of the second switching transistor Tb2, and it can be achieved by setting and adjusting the source S1 of the first switching transistor Tb1 and the source S2 of the second switching transistor Tb2, and/or the drain D1 of the first switching transistor Tb1 and the drain D2 of the secondswitching transistor Tb 2.

Specifically, the width-to-length ratio L21/L11 of the channel of the first switching transistor Tb1 is greater than the width-to-length ratio L22/L12 of the channel of the second switching transistor Tb2, including the following several possible embodiments:

the channel length L11 of the first switching transistor Tb1 is equal to the channel length L12 of the second switching transistor Tb2, and the channel width L21 of the first switching transistor Tb1 is greater than the channel width L22 of the secondswitching transistor Tb 2;

the channel width L21 of the first switching transistor Tb1 is equal to the channel width L22 of the second switching transistor Tb2, and the channel length L11 of the first switching transistor Tb1 is less than the channel length L12 of the secondswitching transistor Tb 2;

the channel lengths and widths of the first switching transistor Tb1 and the second switching transistor Tb2 are different.

Whichever of the above embodiments is adopted, the aspect ratio L21/L11 of the channel of the first switch transistor Tb1 is larger than the aspect ratio L22/L12 of the channel of the second switch transistor Tb2 by adjusting the source and/or drain of the first switch transistor Tb1 and/or the secondswitch transistor Tb 2.

In another method, the projection area of the first active layer on the plane of the array substrate is larger than the projection area of the secondactive layer 2 on the plane of the array substrate.

As shown in fig. 12, the projected area of the first active layer a1 on the plane of the array substrate is larger than the projected area of the second active layer a2 on the plane of the array substrate, when the switching transistor is turned on, electrons pass through the center and the edge of the active layer, so that the on-state current of the switching transistor can be adjusted by adjusting the size of the active layer, the larger the size of the active layer is, the larger the on-state current of the switching transistor is, and the channel width-to-length ratios of the first switching transistor Tb1 and the second switching transistor Tb2 can be set to be equal.

In the third method, any one or more of the following methods can also be adjusted simultaneously, including: the area, source or drain of the active layer of the first switching transistor, or the area, source or drain of the active layer of the second switching transistor, the on-state current reaching the channel of the first switching transistor Tb1 is greater than the on-state current of the secondswitching transistor Tb 2.

In a fourth method, the doping concentration of the first active layer is set to be greater than the doping concentration of the second active layer. The larger the doping concentration of the active layer is, the larger the on-state current of the switching transistor is, and the stronger the driving capability of the switching transistor is.

In the fifth method, the crystallization degree of the first active layer is set to be greater than the crystallization degree of the second active layer. The larger the crystallization degree of the active layer is, the larger the on-state current of the switching transistor is, and the stronger the driving capability of the switching transistor is.

Optionally, fig. 13 is a schematic structural diagram of another array substrate according to an embodiment of the present invention, as shown in fig. 13, the array substrate includes a display area AA and a non-display area BA surrounding the display area AA, where thesignal line 10 extends in a first direction Y in the display area AA, the display area AA includes a specially-shaped display area AA1, the specially-shaped display area AA1 includes at least one specially-shaped edge Y, an extending direction of the specially-shaped edge Y is not perpendicular to the first direction Y, and thesecond signal line 12 is located in the specially-shapeddisplay area AA 1.

In this embodiment, thesignal line 10 of the AA1 in the special-shaped display area, that is, the load of thesecond signal line 12 is different from the load of thefirst signal line 11, the on-state current of the test switch SW connected to thefirst signal line 11 is set to be different from the on-state current of the test switch SW connected to thesecond signal line 11, and the difference between the loads of thesecond signal line 12 and thefirst signal line 11 is compensated, so that the display defect caused by the difference between the loads of the signal lines can be improved during the test, and the test accuracy can be improved.

The above is each embodiment of the array substrate provided by the present application, and the present application further provides a display panel, which has any one of the above array substrates, has the characteristics of any one of the above array substrates and the corresponding technical effects, and is not repeated here. The display panel can be a liquid crystal display panel, an organic light emitting display panel, an electronic paper and other display panels.

In addition, the present application further provides a display device, fig. 14 is a schematic structural diagram of the display device according to the embodiment of the present invention, as shown in fig. 14, exemplarily, the display device has ahousing 01 with an arc corner, and a display area AA of a display panel also has an arc boundary Y to form an R corner of the display area, and the display panel includes any one of the display panels, and has the features and corresponding technical effects of any one of the array substrates, which are not repeated herein.

According to the embodiment, the array substrate, the display panel and the display device of the invention have the following beneficial effects:

for a first signal line with a larger load and a second signal line with a smaller load on the array substrate, the on-state current of the test switch connected with the first signal line is set to be larger than the on-state current of the test switch connected with the second signal line, namely the on-state current of the first test switch is larger than the on-state current of the second test switch, so that the driving capability of the first test switch is larger than that of the second test switch, the load difference between the first signal line and the second signal line can be compensated, and therefore when testing is carried out, poor display caused by the load difference of the signal lines can be improved, and the testing accuracy can be improved.

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims (13)

Translated fromChinese

1.一种阵列基板，其特征在于，包括：1. An array substrate, characterized in that, comprising:多条信号线，所述多条信号线包括第一信号线和第二信号线，所述第一信号线的负载大于所述第二信号线的负载；a plurality of signal lines, the plurality of signal lines include a first signal line and a second signal line, the load of the first signal line is greater than the load of the second signal line;测试引线；test leads;控制引线；control lead;多个测试开关，所述测试开关包括输出端、输入端和控制端，每个所述测试开关的输出端均与一条不同的所述信号线电连接，每个所述测试开关的输入端均与一条所述测试引线电连接，每个所述测试开关的控制端均与一条所述控制引线电连接；A plurality of test switches, the test switches include an output end, an input end and a control end, the output end of each test switch is electrically connected with a different signal line, and the input end of each test switch is is electrically connected to one of the test leads, and the control end of each of the test switches is electrically connected to one of the control leads;所述多个测试开关包括第一测试开关和第二测试开关，所述第一测试开关的输出端与所述第一信号线电连接，所述第二测试开关的输出端与所述第二信号线电连接；其中，The plurality of test switches include a first test switch and a second test switch, the output end of the first test switch is electrically connected to the first signal line, and the output end of the second test switch is connected to the second test switch. Signal lines are electrically connected; wherein,所述第一测试开关的开态电流大于所述第二测试开关的开态电流。The on-state current of the first test switch is greater than the on-state current of the second test switch.2.根据权利要求1所述的阵列基板，其特征在于，2. The array substrate according to claim 1, wherein,所述第一信号线的负载包括电阻负载，所述第二信号线的负载包括电阻负载；和/或，The load of the first signal line includes a resistive load, and the load of the second signal line includes a resistive load; and/or,所述第一信号线的负载包括电容负载，所述第二信号线的负载包括电容负载。The load of the first signal line includes a capacitive load, and the load of the second signal line includes a capacitive load.3.根据权利要求1所述的阵列基板，其特征在于，包括：3. The array substrate of claim 1, comprising:多条数据线和多条栅极线，所述多条数据线和所述多条栅极线绝缘交叉限定多个像素单元；a plurality of data lines and a plurality of gate lines, the plurality of data lines and the plurality of gate lines are insulated and intersected to define a plurality of pixel units;所述多条信号线包括所述多条数据线，每条所述数据线至少与一个所述像素单元电连接。The plurality of signal lines include the plurality of data lines, and each of the data lines is electrically connected to at least one of the pixel units.4.根据权利要求3所述的阵列基板，其特征在于，4. The array substrate according to claim 3, wherein,所述第一信号线与M个所述像素单元电连接，所述第二信号线与N个所述像素单元电连接，其中M＞N≥1。The first signal line is electrically connected to the M pixel units, and the second signal line is electrically connected to the N pixel units, wherein M>N≥1.5.根据权利要求1所述的阵列基板，其特征在于，还包括：5. The array substrate according to claim 1, further comprising:触控电极层，所述触控电极层包括多个触控电极，每个所述触控电极均与一条触控信号线电连接；a touch electrode layer, the touch electrode layer includes a plurality of touch electrodes, and each of the touch electrodes is electrically connected to a touch signal line;所述多条信号线包括所述触控信号线。The plurality of signal lines include the touch signal lines.6.根据权利要求5所述的阵列基板，其特征在于，6. The array substrate according to claim 5, wherein,与所述第一信号线电连接的所述触控电极的面积为S1，与所述第二信号线电连接的所述触控电极的面积为S2，其中S1＞S2＞0。The area of the touch electrodes electrically connected to the first signal line is S1, and the area of the touch electrodes electrically connected to the second signal line is S2, where S1>S2>0.7.根据权利要求1所述的阵列基板，其特征在于，7. The array substrate according to claim 1, wherein,所述第一测试开关包括第一开关晶体管，所述第一开关晶体管包括第一有源层，所述第一开关晶体管的栅极与所述第一测试开关的控制端电连接，所述第一开关晶体管的源极与所述第一测试开关的输入端电连接，所述第一开关晶体管的漏极与所述第一测试开关的输出端电连接；The first test switch includes a first switch transistor, the first switch transistor includes a first active layer, the gate of the first switch transistor is electrically connected to the control terminal of the first test switch, and the first switch transistor is electrically connected to the control terminal of the first test switch. The source of a switch transistor is electrically connected to the input terminal of the first test switch, and the drain of the first switch transistor is electrically connected to the output terminal of the first test switch;所述第二测试开关包括第二开关晶体管，所述第二开关晶体管包括第二有源层，所述第二开关晶体管的栅极与所述第二测试开关的控制端电连接，所述第二开关晶体管的源极与所述第二测试开关的输入端电连接，所述第二开关晶体管的漏极与所述第二测试开关电连接。The second test switch includes a second switch transistor, the second switch transistor includes a second active layer, the gate of the second switch transistor is electrically connected to the control terminal of the second test switch, the first The sources of the two switch transistors are electrically connected to the input terminals of the second test switch, and the drains of the second switch transistors are electrically connected to the second test switch.8.根据权利要求7所述的阵列基板，其特征在于，8. The array substrate according to claim 7, wherein,所述第一开关晶体管沟道的宽长比大于所述第二开关晶体沟道的宽长比；和/或，The width to length ratio of the channel of the first switching transistor is greater than the width to length ratio of the channel of the second switching transistor; and/or,所述第一有源层在所述阵列基板所在平面的投影面积大于所述第二有源层在所述阵列基板所在平面的投影面积。The projected area of the first active layer on the plane where the array substrate is located is larger than the projected area of the second active layer on the plane where the array substrate is located.9.根据权利要求7所述的阵列基板，其特征在于，9. The array substrate according to claim 7, wherein,所述第一有源层的掺杂浓度大于所述第二有源层的掺杂浓度。The doping concentration of the first active layer is greater than the doping concentration of the second active layer.10.根据权利要求7所述的阵列基板，其特征在于，10. The array substrate according to claim 7, wherein,所述第一有源层的晶化程度大于所述第二有源层的晶化程度。The degree of crystallization of the first active layer is greater than that of the second active layer.11.根据权利要求1所述的阵列基板，其特征在于，11. The array substrate according to claim 1, wherein,所述阵列基板包括显示区和围绕所述显示区的非显示区；The array substrate includes a display area and a non-display area surrounding the display area;所述信号线在所述显示区内沿第一方向延伸；the signal line extends along a first direction in the display area;所述显示区包括异形显示区，所述异形显示区至少包括一条异形边，所述异形边的延伸方向与所述第一方向非垂直相交；The display area includes a special-shaped display area, the special-shaped display area includes at least one special-shaped side, and the extension direction of the special-shaped side intersects the first direction non-perpendicularly;所述第二信号线位于所述异形显示区内。The second signal line is located in the special-shaped display area.12.一种显示面板，其特征在于，包括权利要求1至11中任一项所述的阵列基板。12. A display panel, comprising the array substrate according to any one of claims 1 to 11.13.一种显示装置，其特征在于，包括权利要求12所述的显示面板。13. A display device, comprising the display panel of claim 12.

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