技术领域technical field
本发明涉及一种半导体器件制造方法，特别是涉及一种精细图形的刻蚀方法。The invention relates to a method for manufacturing a semiconductor device, in particular to an etching method for fine patterns.
背景技术Background technique
为了改善存储器件的密度，业界已经广泛致力于研发减小二维布置的存储器单元的尺寸的方法。随着二维(2D)存储器件的存储器单元尺寸持续缩减，信号冲突和干扰会显著增大，以至于难以执行多电平单元(MLC)操作。为了克服2D存储器件的限制，业界已经研发了具有三维(3D)结构的存储器件，通过将存储器单元三维地布置在衬底之上来提高集成密度。这些三维存储器单元之间的互联需要精细的图形刻蚀工艺。In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. The interconnection between these three-dimensional memory cells requires fine pattern etching process.
现有的一种精细图形的光刻/刻蚀工艺如图1a至图1e所示。如图1a所示，在衬底1上沉积多晶硅、金属等待刻蚀的材料层2；在材料层2上沉积牺牲层3，通常其材质较软、密度较低，例如为低k材料、SOC(spin-on-carbon自旋对碳)等；在牺牲层3上沉积硬掩模层或抗反射层4，例如氮化硅、氮氧化硅；在层4上形成光刻胶图形5。如图1b所示，以光刻胶图形5为掩模，各向异性干法刻蚀硬掩模层或抗反射层4形成图形4。如图1c所示，以图形4为掩模，各向异性干法刻蚀形成牺牲层3的图形。为了保证后续的图形传输不会出现图形闭合、刻蚀停止等问题，所需求的刻蚀后的牺牲层3的形貌为理想状态下的90°的完全规则的矩形，如图1c所示。然而，由于SOC等低k材料相对于其他材料来说致密度较低，材质较软，而其线宽又比较窄，很容易出现刻蚀线断掉的问题，因此，现有的技术一般会在刻蚀气体里加入少量的COS等类似的钝化气体(聚合物生成气体，例如碳含量较大的卤代烃，或者含C和S的化合物)来进行侧墙保护。虽然此种工艺可以对牺牲层3的图形进行很好的保护，如图2a所示，使刻蚀后的牺牲层为梯形形貌，角度较低，有助于线条的站立，不会出现线条倒掉以及断掉的情况。但是，这种刻蚀工艺下的牺牲层图形，对后续的图形传输则有很多不好的影响。An existing photolithography/etching process for fine patterns is shown in Figures 1a to 1e. As shown in Figure 1a, polysilicon and metal material layer 2 waiting to be etched are deposited on the substrate 1; a sacrificial layer 3 is deposited on the material layer 2, usually with a softer material and lower density, such as low-k material, SOC (spin-on-carbon spin on carbon), etc.; deposit a hard mask layer or an anti-reflection layer 4 on the sacrificial layer 3 , such as silicon nitride, silicon oxynitride; form a photoresist pattern 5 on the layer 4 . As shown in FIG. 1 b , using the photoresist pattern 5 as a mask, the hard mask layer or the anti-reflection layer 4 is anisotropically dry-etched to form a pattern 4 . As shown in FIG. 1c, using the pattern 4 as a mask, the pattern of the sacrificial layer 3 is formed by anisotropic dry etching. In order to ensure that there will be no problems such as pattern closure and etching stop in the subsequent pattern transmission, the desired shape of the sacrificial layer 3 after etching is a completely regular rectangle with 90° in an ideal state, as shown in FIG. 1c. However, compared with other materials, low-k materials such as SOC have lower density and softer materials, and their line width is relatively narrow, which is prone to the problem of broken etching lines. Therefore, the existing technologies generally Add a small amount of COS and other similar passivation gases (polymer-forming gases, such as halogenated hydrocarbons with a large carbon content, or compounds containing C and S) to the etching gas for sidewall protection. Although this process can well protect the pattern of the sacrificial layer 3, as shown in Figure 2a, the etched sacrificial layer has a trapezoidal shape with a low angle, which helps the lines to stand up and no lines will appear. A case to be drained and broken. However, the pattern of the sacrificial layer under this etching process has many adverse effects on the subsequent pattern transmission.
接着，如图1d的理想情况所示，在硬掩模层4和牺牲层图形3的顶部和侧壁以及材料层2的顶部上共形地均匀地沉积绝缘层6，例如氮化硅、氧化硅、氮氧化硅等。通过控制沉积工艺参数，可以严格控制层6的厚度，特别是在牺牲层3侧壁上的厚度。图2b的情形为实际工艺条件下图1d所对应的情形。Next, as shown in the ideal case of Fig. 1d, an insulating layer 6, such as silicon nitride, oxide Silicon, silicon oxynitride, etc. By controlling the parameters of the deposition process, the thickness of the layer 6 can be strictly controlled, especially the thickness on the sidewall of the sacrificial layer 3 . The situation in Figure 2b is the situation corresponding to Figure 1d under actual process conditions.
此后，如图1e的理想情况所示，刻蚀去除硬掩模层4、牺牲层3，仅在材料层2顶部上留下由绝缘层6的垂直侧壁部分所构成的精细线条，此后可以以该精细线条为掩模刻蚀材料层2从而获得所需的精细结构。如此，这种自对准双沟槽(SADP)工艺利用牺牲层侧壁的绝缘层作为掩模，实现了比光刻工艺的最小分辨率更加精细的图形。Thereafter, as shown in the ideal case of FIG. 1e, the hard mask layer 4 and the sacrificial layer 3 are removed by etching, leaving only the fine lines formed by the vertical sidewall portions of the insulating layer 6 on the top of the material layer 2, after which the The material layer 2 is etched using the fine lines as a mask to obtain the desired fine structure. In this way, this self-aligned double trench (SADP) process utilizes the insulating layer on the sidewall of the sacrificial layer as a mask to achieve a finer pattern than the minimum resolution of the photolithography process.
然而，由于图2a所示牺牲层实际刻蚀过程中通常难以实现90度直角，这种倾斜侧壁将使得出现图2c所示的情况，绝缘层6的侧壁图形无法垂直，降低了后续刻蚀的工艺窗口。严重时甚至会导致侧墙6相互粘合，粘合区域下方的图形无法被刻蚀或填充，造成器件短路或断路。However, since it is usually difficult to achieve a 90-degree right angle during the actual etching process of the sacrificial layer shown in FIG. 2a, this inclined sidewall will cause the situation shown in FIG. etched process window. In severe cases, it may even cause the sidewalls 6 to adhere to each other, and the pattern below the adhesive area cannot be etched or filled, resulting in short circuit or open circuit of the device.
发明内容Contents of the invention
因此，本发明的目的在于克服上述缺陷，改良传统的刻蚀工艺，提高牺牲层图形的侧壁垂直度，保证后续侧墙刻蚀工艺中侧墙线条不会因为牺牲层图形的侧壁角度较低而闭合。Therefore, the purpose of the present invention is to overcome the above-mentioned defects, improve the traditional etching process, improve the verticality of the sidewall of the sacrificial layer pattern, and ensure that the sidewall lines in the subsequent sidewall etching process will not be due to the relatively large angle of the sidewall of the sacrificial layer pattern. low and closed.
为此，本发明提供了一种刻蚀方法，包括：For this reason, the invention provides a kind of etching method, comprising:
步骤a，在衬底上依次形成材料层、牺牲层和硬掩模层；Step a, sequentially forming a material layer, a sacrificial layer and a hard mask layer on the substrate;
步骤b，以光刻胶图形为掩模，刻蚀硬掩模层形成硬掩模图形；Step b, using the photoresist pattern as a mask, etching the hard mask layer to form a hard mask pattern;
步骤c，以硬掩模图形为掩模，刻蚀部分牺牲层，剩余的牺牲层具有水平部分，以及在水平部分上的垂直部分；Step c, using the hard mask pattern as a mask to etch part of the sacrificial layer, and the remaining sacrificial layer has a horizontal part and a vertical part on the horizontal part;
步骤d，分解硬掩模图形，在牺牲层的垂直部分的侧壁上形成保护层；Step d, decomposing the hard mask pattern, forming a protective layer on the sidewall of the vertical portion of the sacrificial layer;
步骤e，重复步骤c和步骤d，直至暴露材料层，留下垂直的牺牲层图形。In step e, step c and step d are repeated until the material layer is exposed, leaving a vertical sacrificial layer pattern.
其中，硬掩模层为单层或多层结构；任选地，硬掩模层用作抗反射层，或者包含抗反射层；任选地，硬掩模层包括至少一个第一层和至少一个第二层，其中第二层的硬度大于第一层。Wherein, the hard mask layer is a single-layer or multilayer structure; optionally, the hard mask layer is used as an anti-reflection layer, or contains an anti-reflection layer; optionally, the hard mask layer includes at least one first layer and at least one A second layer, where the second layer is harder than the first layer.
其中，步骤b和/或步骤c的刻蚀为各向异性干法刻蚀；任选地，刻蚀气体选自SF6、NF3、COS、Cl2、HBr、CF4、CHF3。Wherein, the etching in step b and/or step c is anisotropic dry etching; optionally, the etching gas is selected from SF6 , NF3 , COS, Cl2 , HBr, CF4 , CHF3 .
其中，步骤d的分解包括等离子体轰击；任选地，工作气体为惰性气体及其氟化物；优选地，工作气体中进一步包括氧化性气体。Wherein, the decomposition in step d includes plasma bombardment; optionally, the working gas is an inert gas and its fluoride; preferably, the working gas further includes an oxidizing gas.
其中，牺牲层的材料选自BSG、PSG、BPSG、SOG、多孔材料、SOC。Wherein, the material of the sacrificial layer is selected from BSG, PSG, BPSG, SOG, porous material, and SOC.
其中，步骤e之后进一步包括，在牺牲层图形两侧形成侧墙图形，以侧墙图形为掩模刻蚀材料层形成所需的精细线条。Wherein, after step e, it further includes forming sidewall patterns on both sides of the sacrificial layer pattern, using the sidewall patterns as a mask to etch the material layer to form required fine lines.
其中，侧墙图形的材料的硬度大于牺牲层图形的材料的硬度。Wherein, the hardness of the material of the side wall pattern is greater than that of the material of the sacrificial layer pattern.
其中，第一次执行步骤c时，牺牲层垂直部分的厚度大于等于牺牲层原始厚度的1/2。Wherein, when step c is performed for the first time, the thickness of the vertical portion of the sacrificial layer is greater than or equal to 1/2 of the original thickness of the sacrificial layer.
其中，材料层的材质选自导体、半导体、绝缘体。Wherein, the material of the material layer is selected from conductors, semiconductors, and insulators.
依照本发明的刻蚀方法，物理轰击硬掩模层图形使其分解而附着在牺牲层侧壁上作为保护层，获得了垂直度良好的牺牲层图形，提高了刻蚀的精细度，减少了器件缺陷、提高了良率。According to the etching method of the present invention, the pattern of the hard mask layer is physically bombarded to decompose and adhere to the sidewall of the sacrificial layer as a protective layer, thereby obtaining a sacrificial layer pattern with good verticality, improving the fineness of etching, and reducing Device defects, improved yield.
本发明所述目的，以及在此未列出的其他目的，在本申请独立权利要求的范围内得以满足。本发明的实施例限定在独立权利要求中，具体特征限定在其从属权利要求中。The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claim and specific features are defined in its dependent claims.
附图说明Description of drawings
以下参照附图来详细说明本发明的技术方案，其中：Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:
图1a至图1e分别显示了现有技术刻蚀工艺步骤的剖面示意图；Figures 1a to 1e respectively show a schematic cross-sectional view of the etching process steps in the prior art;
图2a至图2c分别显示了现有技术刻蚀工艺的局部放大图；Figures 2a to 2c respectively show partial enlarged views of the etching process in the prior art;
图3a至图3g分别显示了根据本发明实施例的刻蚀工艺的剖视图；以及3a to 3g respectively show cross-sectional views of etching processes according to embodiments of the present invention; and
图4显示了根据本发明实施例的刻蚀工艺的示意性流程图。FIG. 4 shows a schematic flowchart of an etching process according to an embodiment of the present invention.
具体实施方式Detailed ways
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了可有效提高精度和良率的刻蚀工艺。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with schematic embodiments, and an etching process that can effectively improve precision and yield is disclosed. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures. These modifications do not imply a spatial, sequential or hierarchical relationship of the modified device structures unless specifically stated.
如图4所示，描述了根据本发明一个实施例的刻蚀工艺的示意性流程图。提供衬底，在衬底上依次沉积材料层、牺牲层、硬掩模层；光刻/刻蚀硬掩模层形成硬掩模图形；以硬掩模图形为掩模刻蚀牺牲层的一部分，此时牺牲层具有垂直的侧壁以及水平的底部，而顶部的硬掩模图形也被刻蚀去除了一部分；随后利用硬掩模层图形在牺牲层侧壁上形成保护层，例如通过物理过程诸如等离子体轰击，使得一部分硬掩模层图形分解并沉积在牺牲层侧壁上作为保护层；重复上述过程直至暴露材料层，在材料层上留下竖直的牺牲层图形。此后，可以在牺牲层图形侧壁上形成绝缘材料的侧墙，去除牺牲层图形留下侧墙图形，以侧墙图形为掩模刻蚀材料层而形成所需的精细图形。As shown in FIG. 4 , a schematic flowchart of an etching process according to an embodiment of the present invention is described. Provide a substrate, deposit a material layer, a sacrificial layer, and a hard mask layer sequentially on the substrate; photolithography/etch the hard mask layer to form a hard mask pattern; use the hard mask pattern as a mask to etch a part of the sacrificial layer At this time, the sacrificial layer has vertical sidewalls and horizontal bottoms, and a part of the hard mask pattern on the top is also etched away; then a protective layer is formed on the sidewalls of the sacrificial layer using the hard mask layer pattern, for example, by physical A process such as plasma bombardment causes a part of the hard mask layer pattern to be decomposed and deposited on the sidewall of the sacrificial layer as a protective layer; repeating the above process until the material layer is exposed, leaving a vertical sacrificial layer pattern on the material layer. Thereafter, sidewalls of insulating material can be formed on the sidewalls of the sacrificial layer pattern, the sacrificial layer pattern is removed to leave the sidewall pattern, and the material layer is etched using the sidewall pattern as a mask to form the desired fine pattern.
如此，图4所示的基本流程通过物理轰击硬掩模层图形使其分解而附着在牺牲层侧壁上作为保护层，获得了垂直度良好的牺牲层图形，提高了刻蚀的精细度，减少了器件缺陷、提高了良率。In this way, the basic process shown in Figure 4 decomposes the pattern of the hard mask layer by physical bombardment and attaches it to the sidewall of the sacrificial layer as a protective layer, thereby obtaining a pattern of the sacrificial layer with good verticality and improving the fineness of etching. Device defects are reduced and the yield rate is improved.
以下结合图3a-图3g来详细描述参照图4所述的具体工艺流程。The specific process flow described with reference to FIG. 4 will be described in detail below in conjunction with FIGS. 3a-3g.
如图3a所示，在衬底10上形成依次形成材料层20、牺牲层30、硬掩模层40、光刻胶图形50。提供衬底10，其材质可以包括体硅(bulk Si)、体锗(bulk Ge)、绝缘体上硅(SOI)、绝缘体上锗(GeOI)或者是其他化合物半导体衬底，例如SiGe、Si:C、SIGeC、GaN、GaAs、InP等等，以及这些物质的组合。为了与现有的IC制造工艺兼容，衬底10优选地为含硅材质的衬底，例如Si、SOI、SiGe、Si:C、SiGeC等。As shown in FIG. 3 a , a material layer 20 , a sacrificial layer 30 , a hard mask layer 40 , and a photoresist pattern 50 are sequentially formed on a substrate 10 . A substrate 10 is provided, and its material may include bulk silicon (bulk Si), bulk germanium (bulk Ge), silicon-on-insulator (SOI), germanium-on-insulator (GeOI) or other compound semiconductor substrates, such as SiGe, Si:C , SIGeC, GaN, GaAs, InP, etc., and combinations of these substances. In order to be compatible with the existing IC manufacturing process, the substrate 10 is preferably a substrate containing silicon, such as Si, SOI, SiGe, Si:C, SiGeC and the like.
采用包括LPCVD、PECVD、HDPCVD、UHVCVD、MOCVD、MBE、ALD、蒸发、溅射、热氧化、化学氧化等常规工艺，在衬底10上形成材料层20，可以用作半导体器件的栅极堆叠，可以用作半导体器件的源漏接触，可以用作器件之间的层间互联线，也可以用作3D存储器件的介质堆叠或栅极堆叠。因此，材料层20的材料包括但不限于，导体、半导体、绝缘体，导体例如Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La等金属单质、或这些金属的合金以及这些金属的导电氮化物或导电氧化物，半导体例如掺杂或不掺杂的Si、Ge、SiGe、SiC、SiGeC、SiGeSn、SiGaN、SiGaP、SiGaAs、InSiN、InSiP、InSiAs、InSiSb、GaN、InSb、InP、InAs、GaAs、SiInGaAs，绝缘体例如氧化硅、氮化硅、氮氧化硅、DLC、SiOC、SiOF、SiNC、SiNF、高K材料(其中高k材料选自HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOx的铪基材料，或是包括选自ZrO2、La2O3、LaAlO3、Ta2O5、TiO2、Y2O3、CeO2的稀土基高K介质材料，或是包括SiN、AlSiN、AlN、Al2O3，以其上述材料的复合层)。在本发明一个优选实施例中，材料层20是用作栅极的掺杂多晶硅。Using conventional processes including LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, thermal oxidation, chemical oxidation, etc., the material layer 20 is formed on the substrate 10, which can be used as a gate stack of a semiconductor device, It can be used as a source-drain contact of a semiconductor device, as an interlayer interconnection line between devices, or as a dielectric stack or a gate stack of a 3D storage device. Therefore, the material of the material layer 20 includes, but is not limited to, conductors, semiconductors, insulators, conductors such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La and other metals, or alloys of these metals and conductive nitrides or conductive oxides of these metals, semiconductors such as doped or undoped Si, Ge, SiGe, SiC, SiGeC, SiGeSn, SiGaN , SiGaP, SiGaAs, InSiN, InSiP, InSiAs, InSiSb, GaN, InSb, InP, InAs, GaAs, SiInGaAs, insulators such as silicon oxide, silicon nitride, silicon oxynitride, DLC, SiOC, SiOF, SiNC, SiNF, high K Materials (wherein the high-k material is selected from HfO2 , HfSiOx , HfSiON, HfAlOx , HfTaOx , HfLaOx , HfAlSiOx , HfLaSiOx hafnium-based materials, or includes hafnium-based materials selected from ZrO2 , La2 O3 , LaAlO3 , Ta2 O5 , TiO2 , Y2 O3 , CeO2 rare earth-based high-K dielectric material, or a composite layer including SiN, AlSiN, AlN, Al2 O3 , and the above materials). In a preferred embodiment of the invention, material layer 20 is doped polysilicon used as a gate.
在材料层20上通过旋涂、喷涂、丝网印刷、CVD沉积等工艺，形成材质较软也即硬度较低、致密度较低的牺牲层30，用作自对准双沟槽刻蚀(SADP)工艺中最终侧墙掩模图形的支撑体。这种较软的材质能够很好地吸收侧墙图形刻蚀过程中的应力，能够避免局部应力过于集中导致的超细线条断裂的缺陷。牺牲层30的图形例如为BSG(掺B氧化硅)、PSG(掺P氧化硅)、BPSG(掺BP氧化硅)、SOG(旋涂玻璃)、多孔材料、自旋对碳(SOC)等，并优选SOC。牺牲层30的厚度需要较大，例如30～200nm，以便于侧墙沉积过程中利用沉积工艺保形性良好的特性拉伸而形成均匀厚度的线条。On the material layer 20, a sacrificial layer 30 with a softer material, that is, a lower hardness and lower density is formed by spin coating, spray coating, screen printing, CVD deposition, etc., for self-aligned double trench etching ( The support for the final sidewall mask pattern in the SADP) process. This kind of soft material can well absorb the stress during the etching process of the side wall pattern, and can avoid the defect of ultra-thin line breakage caused by excessive concentration of local stress. The pattern of the sacrificial layer 30 is, for example, BSG (B-doped silicon oxide), PSG (P-doped silicon oxide), BPSG (BP-doped silicon oxide), SOG (spin-on-glass), porous material, spin on carbon (SOC), etc. And preferably SOC. The thickness of the sacrificial layer 30 needs to be relatively large, for example, 30-200 nm, so that lines with uniform thickness can be formed by stretching during the deposition process of the sidewall by utilizing the good conformal property of the deposition process.
在牺牲层30上通过LPCVD、PECVD等常规工艺，形成硬掩模层40。层40的材质较硬，例如氮化硅、氮氧化硅、掺氮碳化硅、掺氧碳化硅、掺硫氮化硅、掺硫碳化硅、掺氟氮化硅、掺氟碳化硅等。层40的厚度不能太大，避免硬掩模图形失真，其厚度又不能太小，后续需要其分解形成保护层。在本发明一个优选实施例中，硬掩模层40的厚度为20～100nm。层40可以为单层也可以为多个子层的堆叠。在本发明另一优选实施例中，硬掩模层40的材料可以吸收光刻工艺中的光辐射，避免辐射被反射穿透光刻胶造成光刻胶图形失真，也即硬掩模层40可以用作抗反射层或者包含了抗反射层的子层。在本发明一个优选实施例中，硬掩模层40包含下方较软的至少一个第一层与上方较硬的至少一个第二层的交替堆叠(也即第二层硬度大于第一层)，硬质第一层用于提供良好的顶部保护，而软质的第二层用于在牺牲层刻蚀过程中快速分解以形成侧壁保护层。A hard mask layer 40 is formed on the sacrificial layer 30 by conventional processes such as LPCVD and PECVD. The material of layer 40 is relatively hard, such as silicon nitride, silicon oxynitride, nitrogen-doped silicon carbide, oxygen-doped silicon carbide, sulfur-doped silicon nitride, sulfur-doped silicon carbide, fluorine-doped silicon nitride, fluorine-doped silicon carbide, and the like. The thickness of the layer 40 should not be too large to avoid distortion of the hard mask pattern, and the thickness should not be too small, as it needs to be decomposed to form a protective layer later. In a preferred embodiment of the present invention, the thickness of the hard mask layer 40 is 20-100 nm. Layer 40 may be a single layer or a stack of multiple sub-layers. In another preferred embodiment of the present invention, the material of the hard mask layer 40 can absorb the light radiation in the photolithography process, so as to prevent the radiation from being reflected and penetrating the photoresist to cause distortion of the photoresist pattern, that is, the hard mask layer 40 Can be used as an anti-reflection layer or as a sub-layer comprising an anti-reflection layer. In a preferred embodiment of the present invention, the hard mask layer 40 comprises an alternate stack of at least one first layer that is softer below and at least one second layer that is harder above (that is, the hardness of the second layer is greater than that of the first layer), The hard first layer is used to provide good top protection, while the soft second layer is used to quickly decompose during the etching process of the sacrificial layer to form a sidewall protection layer.
在牺牲层40顶部通过已有的光刻工艺形成光刻胶图形50。A photoresist pattern 50 is formed on the top of the sacrificial layer 40 through an existing photolithography process.
接着，如图3b所示，以光刻胶图形50为掩模，刻蚀硬掩模层40，形成硬掩模层图形40。刻蚀优选各向异性的干法刻蚀工艺，刻蚀气体例如SF6、NF3、COS、Cl2、HBr、以及碳氟比较小的氟代烃(CF4、CHF3)等，刻蚀速率大于聚合物沉积速率，刻蚀线条垂直度较好。Next, as shown in FIG. 3 b , the hard mask layer 40 is etched using the photoresist pattern 50 as a mask to form the hard mask layer pattern 40 . An anisotropic dry etching process is preferred for etching. Etching gases such as SF6 , NF3 , COS, Cl2 , HBr, and fluorocarbons (CF4 , CHF3 ), etc. The rate is greater than the polymer deposition rate, and the verticality of the etching lines is better.
随后，如图3c所示，以硬掩模层图形40为掩模，刻蚀牺牲层30的一部分，留下的牺牲层30具有水平的部分，以及在水平部分之上的垂直部分30f。其中牺牲层剩余的垂直部分具有垂直度较好的侧壁，例如底部角度为90±0.5度。刻蚀为各向异性的干法刻蚀，例如等离子体干法刻蚀或反应离子刻蚀(RIE)，刻蚀气体类似图3b对应的工艺。在本发明的一个优选实施例中，垂直部分30f具有牺牲层30原始厚度的至少1/2，也即牺牲层30的刻蚀至少被分成两个部分。在本发明的其他优选实施例中，垂直部分30f的厚度大于等于牺牲层30原始厚度的90％、85％、80％、75％、70％、65％、60％、55％、50％，以便于执行多次图3c和图3d的工艺。Subsequently, as shown in FIG. 3c, a part of the sacrificial layer 30 is etched using the hard mask layer pattern 40 as a mask, and the remaining sacrificial layer 30 has a horizontal part and a vertical part 30f above the horizontal part. Wherein the remaining vertical portion of the sacrificial layer has sidewalls with good verticality, for example, the bottom angle is 90±0.5 degrees. The etching is anisotropic dry etching, such as plasma dry etching or reactive ion etching (RIE), and the etching gas is similar to the process corresponding to FIG. 3b. In a preferred embodiment of the present invention, the vertical portion 30f has at least 1/2 the original thickness of the sacrificial layer 30, that is, the etching of the sacrificial layer 30 is at least divided into two parts. In other preferred embodiments of the present invention, the thickness of the vertical portion 30f is greater than or equal to 90%, 85%, 80%, 75%, 70%, 65%, 60%, 55%, 50% of the original thickness of the sacrificial layer 30, In order to carry out the process of Fig. 3c and Fig. 3d multiple times.
接着，如图3d所示，停止通入化学性刻蚀气体，主要通过物理性工艺分解硬掩模层图形40的一部分，在牺牲层30的垂直部分30f侧壁上形成保护层40s，而在垂直部分30f的顶部上留下剩余的硬掩模层图形40t。分解工艺例如采用等离子体轰击(溅射)，工艺气体优选Ar、Kr、Xe等重原子数的惰性气体或其氟化物(例如ArF2、KrF2、XeF2)，利用高频高能电磁场加速气体分子轰击硬掩模层40，使其顶部的一部分被物理分解而沉积在牺牲层垂直部分30f的侧壁上聚集成为保护层40s。在本发明一个优选实施例中，分解工艺的工作气体中含有O2、CO等氧化性气体以加速分解过程，并促使在侧壁形成氧化物基的保护层。优选地，前述氧化性气体与工艺气体的流量配比范围为1:20至1:10并优选1:15，例如O2/Ar具体流量为20/200sccm至15/300sccm，优选20/300sccm，用于有效地加速分解同时避免侧壁上过多氧化物堆积而阻挡工艺气体向下轰击。进一步优选地，工艺腔内等离子体的偏压功率(轰击功率)与解离功率的配比为1:5至1:3，优选1:4至1:3.6，最佳3:11，用于提高工艺气体的轰击能量而同时避免对材料层深处造成过度损伤而出现不必要的非晶化。在图3d所示过程中，避免采用化学性刻蚀气体继续刻蚀牺牲层30f侧壁或水平部分的顶部，防止出现图2a所示的倾斜侧壁情形。Next, as shown in FIG. 3d, stop feeding the chemical etching gas, mainly decompose a part of the hard mask layer pattern 40 through a physical process, and form a protective layer 40s on the sidewall of the vertical portion 30f of the sacrificial layer 30, and The remaining hard mask layer pattern 40t is left on top of the vertical portion 30f. The decomposition process, for example, adopts plasma bombardment (sputtering), and the process gas is preferably inert gas with heavy atomic number such as Ar, Kr, Xe or its fluoride (such as ArF2 , KrF2 , XeF2 ), and the gas is accelerated by high-frequency high-energy electromagnetic field Molecules bombard the hard mask layer 40, causing a portion of its top to be physically decomposed and deposited on the sidewalls of the vertical portion 30f of the sacrificial layer to aggregate as the protective layer 40s. In a preferred embodiment of the present invention, the working gas of the decomposition process contains oxidizing gases such as O2 and CO to accelerate the decomposition process and promote the formation of an oxide-based protective layer on the sidewall. Preferably, the flow ratio of the oxidizing gas to the process gas ranges from 1:20 to 1:10 and preferably 1:15, for example, the specific flow rate of O2 /Ar is 20/200 sccm to 15/300 sccm, preferably 20/300 sccm, It is used to effectively accelerate the decomposition while avoiding excessive oxide accumulation on the side wall and blocking the downward bombardment of the process gas. Further preferably, the ratio of the bias power (bombardment power) of the plasma in the process chamber to the dissociation power is 1:5 to 1:3, preferably 1:4 to 1:3.6, and optimally 3:11, for Increase the bombardment energy of the process gas while avoiding unnecessary amorphization due to excessive damage deep in the material layer. In the process shown in FIG. 3d, avoid using chemical etching gas to continuously etch the sidewall or the top of the horizontal part of the sacrificial layer 30f, so as to prevent the sloped sidewall situation shown in FIG. 2a.
优选地，图3c和图3d所示的工艺步骤重复迭代多次，如图4所示，直至如图3e所示，刻蚀暴露材料层20，此时顶部的硬掩模层40t减薄至接近0，而留下了垂直度良好的牺牲层图形30f。Preferably, the process steps shown in FIG. 3c and FIG. 3d are repeated multiple times, as shown in FIG. 4, until the exposed material layer 20 is etched as shown in FIG. 3e, and the hard mask layer 40t on the top is thinned to close to 0, leaving a sacrificial layer pattern 30f with good perpendicularity.
随后，如图3f所示，采用HDPCVD、UHVCVD、MOCVD、MBE、ALD等保形性良好的沉积工艺，在牺牲层图形30f顶部、侧壁以及材料层20顶部上形成绝缘层60。绝缘层60的硬度高于牺牲层30，以提高侧墙线条的硬度，避免后续刻蚀过程中倾倒、软化。绝缘层60例如为氮化硅、氮氧化硅、掺碳氮化硅、DLC(类金刚石无定形碳)等。Subsequently, as shown in FIG. 3f, an insulating layer 60 is formed on the top, sidewall and top of the material layer 20 of the sacrificial layer pattern 30f by using a deposition process with good conformality such as HDPCVD, UHVCVD, MOCVD, MBE, and ALD. The hardness of the insulating layer 60 is higher than that of the sacrificial layer 30, so as to increase the hardness of the sidewall lines, and avoid toppling and softening during the subsequent etching process. The insulating layer 60 is, for example, silicon nitride, silicon oxynitride, carbon-doped silicon nitride, DLC (diamond-like amorphous carbon), or the like.
最后，如图3g所示，各向异性刻蚀去除牺牲层图形30f顶部和材料层20顶部的绝缘层60，留下了垂直的、精细的线条图形60。图形60的宽度取决于图3f所示工艺的沉积厚度，例如仅1～10nm，远远小于图3a光刻工艺所能实现的分辨率，由此大幅提高了器件的集成度。Finally, as shown in FIG. 3 g , the anisotropic etching removes the insulating layer 60 on the top of the sacrificial layer pattern 30 f and the top of the material layer 20 , leaving a vertical, fine line pattern 60 . The width of the pattern 60 depends on the deposition thickness of the process shown in FIG. 3f, for example, only 1-10 nm, which is much smaller than the resolution achieved by the photolithography process in FIG. 3a, thereby greatly improving the integration of the device.
此后，可以以侧墙图形60为掩模继续刻蚀材料层20，获得所需的最终精细线条图形。Thereafter, the material layer 20 can be continuously etched using the side wall pattern 60 as a mask to obtain the desired final fine line pattern.
依照本发明的刻蚀方法，物理轰击硬掩模层图形使其分解而附着在牺牲层侧壁上作为保护层，获得了垂直度良好的牺牲层图形，提高了刻蚀的精细度，减少了器件缺陷、提高了良率。According to the etching method of the present invention, the pattern of the hard mask layer is physically bombarded to decompose and adhere to the sidewall of the sacrificial layer as a protective layer, thereby obtaining a sacrificial layer pattern with good verticality, improving the fineness of etching, and reducing Device defects, improved yield.
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。While the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structures that do not depart from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .
| Application Number | Priority Date | Filing Date | Title |
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| CN201810231889.2ACN108615681B (en) | 2018-03-20 | 2018-03-20 | Etching method |
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| CN201810231889.2ACN108615681B (en) | 2018-03-20 | 2018-03-20 | Etching method |
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| CN108615681Atrue CN108615681A (en) | 2018-10-02 |
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| CN111725062A (en)* | 2019-03-20 | 2020-09-29 | 东京毅力科创株式会社 | Film etching method and plasma processing apparatus |
| CN115831721A (en)* | 2022-11-18 | 2023-03-21 | 中国科学院光电技术研究所 | Hard mask etching method based on side wall protection |
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