本申请是中国申请号为201610081525.1、申请日为2016年2月5日、题为“像素结构、其制作方法与薄膜晶体管”的申请的分案申请。This application is a divisional application of the Chinese application number 201610081525.1, the filing date is February 5, 2016, and the title is "Pixel Structure, Its Fabrication Method and Thin Film Transistor".
【技术领域】【Technical field】
本发明是有关于一种像素结构、其制作方法与薄膜晶体管。The invention relates to a pixel structure, a manufacturing method thereof and a thin film transistor.
【背景技术】【Background technique】
家用电器设备的各式电子产品之中。其中，应用薄膜晶体管(thin filmtransistor；TFT)的液晶显示器已经被广泛地使用。薄膜晶体管式的液晶显示器主要是由薄膜晶体管阵列基板、彩色滤光阵列基板和液晶层所构成，其中，薄膜晶体管阵列基板上设置有多个以阵列排列的薄膜晶体管，以及，与每一个薄膜晶体管对应配置的像素电极(pixel electrode)，以构成像素结构。对于所设置的薄膜晶体管中，薄膜晶体管包含栅极、漏极、源极与通道层，以构成像素结构中的开关组件。Among all kinds of electronic products in household appliances. Among them, a liquid crystal display using a thin film transistor (thin film transistor; TFT) has been widely used. A thin-film transistor liquid crystal display is mainly composed of a thin-film transistor array substrate, a color filter array substrate and a liquid crystal layer, wherein a plurality of thin-film transistors arranged in an array are arranged on the thin-film transistor array substrate, and each thin-film transistor The pixel electrodes are arranged correspondingly to form a pixel structure. For the provided thin film transistor, the thin film transistor includes a gate, a drain, a source and a channel layer to form a switch component in the pixel structure.
然而，于薄膜晶体管的结构之中，由于会有寄生电容产生于其中的问题，像素结构的效能将可能会受到此寄生电容的影响。进一步而言，当薄膜晶体管结构中有寄生电容产生时，液晶显示器的画面品质将可能会受影响，例如，寄生电容将可能造成液晶显示画面有亮暗不均的问题。However, in the thin film transistor structure, due to the problem of parasitic capacitance generated therein, the performance of the pixel structure may be affected by the parasitic capacitance. Furthermore, when there is parasitic capacitance in the thin film transistor structure, the picture quality of the liquid crystal display may be affected. For example, the parasitic capacitance may cause uneven brightness and darkness of the liquid crystal display picture.
【发明内容】【Content of invention】
本发明的一实施方式提供一种像素结构，于此像素结构中，可通过第二绝缘层的设置而降低源极与漏极的其中之一与栅极之间所产生的寄生电容，借以降低馈通电压与栅极负载，以使应用像素结构的显示面板可以有更佳的品质。One embodiment of the present invention provides a pixel structure. In this pixel structure, the parasitic capacitance generated between one of the source and the drain and the gate can be reduced by setting the second insulating layer, so as to reduce Feedthrough voltage and gate load, so that the display panel with pixel structure can have better quality.
本发明的一实施方式提供一种像素结构，包含基板、栅极、通道层、第一绝缘层、源极、漏极与第二绝缘层。栅极设置于基板上。通道层设置于基板上。第一绝缘层设置于栅极与通道层之间。源极电性连接于通道层。漏极电性连接于通道层。第二绝缘层设置于垂直投影落于通道层内的源极与漏极的其中之一的一部分与栅极之间，其中，垂直投影落于通道层内的源极与漏极的其中之一的一部分与栅极之间的垂直距离为第一距离，而垂直投影落于通道层内的源极与漏极的其中另一者的一部分与栅极之间的垂直距离为第二距离，其中，第一距离至少包含第二绝缘层的厚度，且第一距离大于第二距离。An embodiment of the present invention provides a pixel structure, including a substrate, a gate, a channel layer, a first insulating layer, a source, a drain, and a second insulating layer. The grid is disposed on the substrate. The channel layer is disposed on the substrate. The first insulating layer is disposed between the gate and the channel layer. The source is electrically connected to the channel layer. The drain is electrically connected to the channel layer. The second insulating layer is disposed between a part of one of the source and the drain falling in the channel layer in a vertical projection and one of the drain in the channel layer, wherein the vertical projection falls in one of the source and the drain in the channel layer The vertical distance between a part of the gate and the gate is the first distance, and the vertical distance between a part of the other of the source and the drain that is vertically projected into the channel layer and the gate is the second distance, wherein , the first distance includes at least the thickness of the second insulating layer, and the first distance is greater than the second distance.
于部分实施方式中，信道层至栅极的垂直投影落于栅极之内。In some embodiments, the vertical projection of the channel layer to the gate falls within the gate.
于部分实施方式中，第一绝缘层覆盖栅极背向基板的表面，且第二绝缘层设置于垂直投影落于通道层内的源极与漏极的其中之一的一部分与部分通道层之间。In some embodiments, the first insulating layer covers the surface of the gate facing away from the substrate, and the second insulating layer is disposed between a part of one of the source and the drain falling in the channel layer and part of the channel layer in a vertical projection between.
于部分实施方式中，第二绝缘层设置于部分漏极与部分通道层之间，且第二绝缘层的相对两表面分别被部分漏极与部分通道层完全覆盖。In some embodiments, the second insulating layer is disposed between the part of the drain and the part of the channel layer, and the opposite two surfaces of the second insulating layer are completely covered by the part of the drain and the part of the channel layer respectively.
于部分实施方式中，信道层、源极、漏极与第二绝缘层位于基板与第一绝缘层之间，且栅极设置于第一绝缘层背向基板的表面。In some embodiments, the channel layer, the source, the drain and the second insulating layer are located between the substrate and the first insulating layer, and the gate is disposed on the surface of the first insulating layer facing away from the substrate.
于部分实施方式中，像素结构更包含遮蔽层。遮蔽层位于基板与通道层之间，其中，通道层至遮蔽层的垂直投影落于遮蔽层之内。In some embodiments, the pixel structure further includes a shielding layer. The shielding layer is located between the substrate and the channel layer, wherein the vertical projection from the channel layer to the shielding layer falls within the shielding layer.
于部分实施方式中，第二绝缘层设置于第一绝缘层朝向源极与漏极的其中之一与朝向通道层的表面上，且第二绝缘层至通道层的垂直投影落于源极与漏极的其中之一至通道层的垂直投影内。In some embodiments, the second insulating layer is disposed on the surface of the first insulating layer facing one of the source electrode and the drain electrode and facing the channel layer, and the vertical projection of the second insulating layer to the channel layer falls on the source electrode and the channel layer. One of the drains is within the vertical projection of the channel layer.
于部分实施方式中，第二绝缘层设置于第一绝缘层背向源极与漏极的其中之一与背向通道层的表面上，且第二绝缘层至通道层的垂直投影落于源极与漏极的其中之一至通道层的垂直投影内。In some embodiments, the second insulating layer is disposed on the surface of the first insulating layer facing away from one of the source electrode and the drain electrode and facing away from the channel layer, and the vertical projection of the second insulating layer to the channel layer falls on the source In the vertical projection of one of the electrode and the drain to the channel layer.
于部分实施方式中，第二绝缘层的厚度为300纳米(nm)至400纳米(nm)。In some embodiments, the thickness of the second insulating layer is 300 nanometers (nm) to 400 nanometers (nm).
于部分实施方式中，像素结构更包含栅极驱动电路(gate on array；GOA)单元。栅极驱动电路包含第一导电单元与第二导电单元。第一导电单元设置于基板上，并电性连接至栅极。第二导电单元设置于第一导电单元之上。In some embodiments, the pixel structure further includes a gate on array (GOA) unit. The gate driving circuit includes a first conductive unit and a second conductive unit. The first conductive unit is disposed on the substrate and electrically connected to the grid. The second conductive unit is disposed on the first conductive unit.
于部分实施方式中，像素结构更包含钝化层与像素电极。钝化层位于第一绝缘层、通道层、第二绝缘层、源极与漏极之上。钝化层具有通孔，以至少暴露部分漏极。像素电极位于钝化层上，并通过通孔与漏极电性连接。像素电极、漏极、钝化层与栅极于基板的垂直投影至少部分重叠。In some embodiments, the pixel structure further includes a passivation layer and a pixel electrode. The passivation layer is located on the first insulating layer, the channel layer, the second insulating layer, the source and the drain. The passivation layer has a through hole to expose at least part of the drain. The pixel electrode is located on the passivation layer and electrically connected to the drain through the through hole. The vertical projection of the pixel electrode, the drain electrode, the passivation layer and the gate on the substrate at least partially overlaps.
本发明的一实施方式提供一种像素结构的制作方法，包含以下步骤。形成栅极于基板上。形成第一绝缘层于基板与栅极上。形成半导体层于第一绝缘层上，并图案化半导体层成信道层，其中，信道层具有源极连接部与漏极连接部。形成第二绝缘层，并图案化第二绝缘层，以使图案化的第二绝缘层至通道层的垂直投影落于源极连接部与漏极连接部的其中之一之内。形成金属层于第一绝缘层、通道层与第二绝缘层上，并将金属层图案化为源极与漏极，其中，源极电性连接源极连接部，漏极电性连接漏极连接部，且第二绝缘层位于源极与漏极的其中之一与栅极之间。An embodiment of the present invention provides a method for manufacturing a pixel structure, including the following steps. A gate is formed on the substrate. A first insulating layer is formed on the substrate and the grid. A semiconductor layer is formed on the first insulating layer, and the semiconductor layer is patterned into a channel layer, wherein the channel layer has a source connecting portion and a drain connecting portion. A second insulating layer is formed, and the second insulating layer is patterned so that a vertical projection of the patterned second insulating layer to the channel layer falls within one of the source connecting portion and the drain connecting portion. forming a metal layer on the first insulating layer, the channel layer and the second insulating layer, and patterning the metal layer into a source and a drain, wherein the source is electrically connected to the source connection part, and the drain is electrically connected to the drain The connection part, and the second insulating layer is located between one of the source and the drain and the gate.
于部分实施方式中，图案化半导体层与图案化第二绝缘层为通过同一道半阶式光罩(half-tone mask)制程完成，且图案化半导体层与图案化第二绝缘层的步骤包含以下步骤。形成第二绝缘层于半导体层上，并形成光阻层于第二绝缘层上。通过半阶式光罩曝光光阻层，并对光阻层进行显影制程。进行第一蚀刻制程，以图案化半导体层与第二绝缘层，并移除部分光阻层，以暴露图案化的第二绝缘层。进行第二蚀刻制程，以移除部分图案化的第二绝缘层，并暴露部分通道层。In some embodiments, the patterned semiconductor layer and the patterned second insulating layer are completed through the same half-tone mask process, and the steps of patterning the semiconductor layer and patterning the second insulating layer include The following steps. A second insulating layer is formed on the semiconductor layer, and a photoresist layer is formed on the second insulating layer. The photoresist layer is exposed through a half-step photomask, and a development process is performed on the photoresist layer. A first etching process is performed to pattern the semiconductor layer and the second insulating layer, and part of the photoresist layer is removed to expose the patterned second insulating layer. A second etching process is performed to remove part of the patterned second insulating layer and expose part of the channel layer.
于部分实施方式中，像素结构的制作方法更包含以下步骤。形成钝化层于第一绝缘层、通道层、第二绝缘层、源极与漏极之上。形成通孔于钝化层之中，以至少暴露部分漏极。形成像素电极于钝化层上，并将像素电极通过通孔与漏极电性连接，其中，像素电极、漏极、钝化层与栅极于基板的垂直投影至少部分重叠。In some embodiments, the manufacturing method of the pixel structure further includes the following steps. A passivation layer is formed on the first insulating layer, the channel layer, the second insulating layer, the source and the drain. A via hole is formed in the passivation layer to expose at least part of the drain. A pixel electrode is formed on the passivation layer, and the pixel electrode is electrically connected to the drain through the through hole, wherein the vertical projection of the pixel electrode, the drain, the passivation layer and the gate on the substrate at least partially overlaps.
于部分实施方式中，像素结构的制作方法更包含形成栅极驱动电路单元，其中，形成栅极驱动电路单元的步骤包含以下步骤。形成第一导电单元于基板上，其中，第一导电单元与栅极为通过同一道光罩制程形成。形成第二导电单元于第二绝缘层上，其中，第二导电单元、源极与漏极为通过同一道光罩制程形成。In some embodiments, the manufacturing method of the pixel structure further includes forming a gate driving circuit unit, wherein the step of forming the gate driving circuit unit includes the following steps. A first conductive unit is formed on the substrate, wherein the first conductive unit and the gate are formed through the same photomask process. A second conductive unit is formed on the second insulating layer, wherein the second conductive unit, the source and the drain are formed through the same photomask process.
本发明的一实施方式提供一种像素结构的制作方法，包含以下步骤。形成金属层于基板上，并将金属层图案化为源极与漏极。形成半导体层于源极与漏极上，并图案化半导体层成通道层。形成第一绝缘层，其中，第一绝缘层至通道层的垂直投影与源极与漏极的其中之一的一部分至通道层的垂直投影重叠。形成第二绝缘层于源极、漏极、通道层与第一绝缘层上。形成栅极于第二绝缘层上。An embodiment of the present invention provides a method for manufacturing a pixel structure, including the following steps. A metal layer is formed on the substrate, and the metal layer is patterned as source and drain. forming a semiconductor layer on the source and the drain, and patterning the semiconductor layer into a channel layer. A first insulating layer is formed, wherein a vertical projection of the first insulating layer to the channel layer overlaps with a vertical projection of a part of one of the source and the drain to the channel layer. A second insulating layer is formed on the source electrode, the drain electrode, the channel layer and the first insulating layer. A gate is formed on the second insulating layer.
于部分实施方式中，像素结构的制作方法更包含于形成金属层于基板上的步骤前，形成遮蔽层于基板上，其中，通道层至遮蔽层的垂直投影落于遮蔽层之内。In some embodiments, the manufacturing method of the pixel structure further includes forming a shielding layer on the substrate before the step of forming the metal layer on the substrate, wherein the vertical projection from the channel layer to the shielding layer falls within the shielding layer.
本发明的一实施方式提供一种薄膜晶体管，包含基板、栅极、通道层、第一绝缘层、第一电极与第二电极。栅极设置于基板上。通道层设置于基板上。第一绝缘层设置于栅极与通道层之间。第一电极以及第二电极电性连接于通道层，其中，第一电极与栅极间形成第一电容，第二电极与栅极间形成第二电容，且第一电容大于第二电容。One embodiment of the present invention provides a thin film transistor, including a substrate, a gate, a channel layer, a first insulating layer, a first electrode and a second electrode. The grid is disposed on the substrate. The channel layer is disposed on the substrate. The first insulating layer is disposed between the gate and the channel layer. The first electrode and the second electrode are electrically connected to the channel layer, wherein a first capacitance is formed between the first electrode and the gate, a second capacitance is formed between the second electrode and the gate, and the first capacitance is greater than the second capacitance.
于部分实施方式中，第一电容与第二电容的差值约为10pF至100pF。In some embodiments, the difference between the first capacitor and the second capacitor is about 10 pF to 100 pF.
本发明的一实施方式提供一种薄膜晶体管，包含基板、栅极、通道层、第一绝缘层、第一电极与第二电极。栅极设置于基板上。通道层设置于基板上。第一绝缘层设置于栅极与通道层之间。第一电极以及第二电极电性连接于通道层，其中，第一电极与栅极间的最大垂直距离和第二电极与栅极间的最大垂直距离的差值约为300埃至约10000埃。One embodiment of the present invention provides a thin film transistor, including a substrate, a gate, a channel layer, a first insulating layer, a first electrode and a second electrode. The grid is disposed on the substrate. The channel layer is disposed on the substrate. The first insulating layer is disposed between the gate and the channel layer. The first electrode and the second electrode are electrically connected to the channel layer, wherein the difference between the maximum vertical distance between the first electrode and the gate and the maximum vertical distance between the second electrode and the gate is about 300 angstroms to about 10000 angstroms .
【附图说明】【Description of drawings】
图1绘示本发明第一实施方式的像素结构的剖面图。FIG. 1 is a cross-sectional view of a pixel structure according to a first embodiment of the present invention.
图2A至图2K绘示图1的像素结构于制作流程的不同阶段的剖面图。2A to 2K are cross-sectional views of the pixel structure in FIG. 1 at different stages of the manufacturing process.
图3绘示本发明第二实施方式的像素结构的剖面图。FIG. 3 is a cross-sectional view of a pixel structure according to a second embodiment of the present invention.
图4绘示本发明第三实施方式的像素结构的剖面图。FIG. 4 is a cross-sectional view of a pixel structure according to a third embodiment of the present invention.
图5绘示本发明第四实施方式的像素结构的剖面图。FIG. 5 is a cross-sectional view of a pixel structure according to a fourth embodiment of the present invention.
图6绘示本发明第五实施方式的像素结构的剖面图。FIG. 6 is a cross-sectional view of a pixel structure according to a fifth embodiment of the present invention.
图7A至图7G绘示图6的像素结构于制作流程的不同阶段的剖面图。7A to 7G are cross-sectional views of the pixel structure in FIG. 6 at different stages of the manufacturing process.
图8绘示本发明第六实施方式的像素结构的剖面图。FIG. 8 is a cross-sectional view of a pixel structure according to a sixth embodiment of the present invention.
图9A至图9D绘示图8的像素结构于制作流程的不同阶段的剖面图。9A to 9D are cross-sectional views of the pixel structure in FIG. 8 at different stages of the manufacturing process.
【符号说明】【Symbol Description】
100A、100B、100C、100D、100E、100F 像素结构100A, 100B, 100C, 100D, 100E, 100F pixel structure
102 基板102 Substrate
104 栅极104 grid
106 第一绝缘层106 First insulating layer
107 半导体层107 semiconductor layer
108 通道层108 channel layer
108d 漏极连接部108d Drain connection part
108s 源极连接部108s Source connection part
109 辅助层109 auxiliary layer
110 源极110 source
112 漏极112 drain
113、113a、113a1、113a2、113b、113b1、113b2 光阻层113, 113a, 113a1, 113a2, 113b, 113b1, 113b2 photoresist layer
114、114a、114a1、114a2、114b、114c 第二绝缘层114, 114a, 114a1, 114a2, 114b, 114c second insulating layer
115 半阶式光罩115 half-step mask
116 第一钝化保护层116 first passivation protective layer
118 钝化层118 passivation layer
120 通孔120 through holes
122 共享电极122 shared electrodes
124 第二钝化保护层124 second passivation protective layer
126 像素电极126 pixel electrodes
130 栅极驱动电路单元130 gate drive circuit unit
132 第一导电单元132 The first conductive unit
134 第二导电单元134 Second conductive unit
140 遮蔽层140 masking layer
D1 第一距离D1 first distance
D2 第二距离D2 second distance
T1、T2 厚度T1, T2 Thickness
【具体实施方式】【Detailed ways】
以下将以图式揭露本发明的多个实施方式，为明确说明起见，许多实务上的细节将在以下叙述中一并说明。然而，应了解到，该多个实务上的细节不应用以限制本发明。也就是说，在本发明部分实施方式中，该多个实务上的细节是非必要的。此外，为简化图式起见，一些已知惯用的结构与组件在图式中将以简单示意的方式绘示的。A number of embodiments of the present invention will be disclosed in the following figures. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these various practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some known and commonly used structures and components will be shown in a simple and schematic manner in the drawings.
有鉴于寄生电容将可能造成液晶显示画面有亮暗不均的问题。有鉴于此，于本发明的像素结构中，可通过第二绝缘层的设置而降低源极与漏极的其中之一与栅极之间所产生的寄生电容，借以降低馈通电压与栅极负载，以使应用像素结构的显示面板可以有更佳的品质，并改善亮暗不均的问题。In view of the fact that the parasitic capacitance may cause the problem of uneven brightness and darkness of the liquid crystal display screen. In view of this, in the pixel structure of the present invention, the parasitic capacitance generated between one of the source and the drain and the gate can be reduced by setting the second insulating layer, so as to reduce the feed-through voltage and the gate Load, so that the display panel with pixel structure can have better quality, and improve the problem of uneven brightness and darkness.
图1绘示本发明第一实施方式的像素结构100A的剖面图。像素结构100A包含基板102、栅极104、第一绝缘层106、通道层108、源极110、漏极112、第二绝缘层114b、第一钝化保护层116、钝化层118、共享电极122、第二钝化保护层124与像素电极126。此外，基板102、栅极104、通道层108、第一绝缘层106、源极110、漏极112与第二绝缘层114b的组合至少可视为构成一个薄膜晶体管。FIG. 1 is a cross-sectional view of a pixel structure 100A according to a first embodiment of the present invention. The pixel structure 100A includes a substrate 102, a gate 104, a first insulating layer 106, a channel layer 108, a source 110, a drain 112, a second insulating layer 114b, a first passivation protection layer 116, a passivation layer 118, a shared electrode 122 . The second passivation protection layer 124 and the pixel electrode 126 . In addition, the combination of the substrate 102 , the gate 104 , the channel layer 108 , the first insulating layer 106 , the source 110 , the drain 112 and the second insulating layer 114 b can at least be regarded as forming a thin film transistor.
栅极104设置于基板102上。通道层108设置于基板102上。第一绝缘层106设置于栅极104与通道层108之间。图1中，自基板102向上层叠的组件依序为栅极104、第一绝缘层106与通道层108，其中，第一绝缘层106覆盖栅极104背向基板102的表面(即栅极104之上表面)。亦即，图1所绘的像素结构100A显示了底栅极(bottom gate)薄膜晶体管结构。此外，源极110电性连接于通道层108，且漏极112也电性连接于通道层108。The gate 104 is disposed on the substrate 102 . The channel layer 108 is disposed on the substrate 102 . The first insulating layer 106 is disposed between the gate 104 and the channel layer 108 . In FIG. 1, the components stacked upwards from the substrate 102 are the gate 104, the first insulating layer 106 and the channel layer 108 in sequence, wherein the first insulating layer 106 covers the surface of the gate 104 facing away from the substrate 102 (ie, the gate 104 above the surface). That is, the pixel structure 100A depicted in FIG. 1 shows a bottom gate TFT structure. In addition, the source 110 is electrically connected to the channel layer 108 , and the drain 112 is also electrically connected to the channel layer 108 .
本实施方式中，第二绝缘层114b设置于垂直投影落于通道层108内的漏极112与栅极104之间。于其他的实施方式中，第二绝缘层114b为设置于垂直投影落于通道层108内的源极110与栅极104的一部分之间。In this embodiment, the second insulating layer 114b is disposed between the drain 112 and the gate 104 whose vertical projection falls in the channel layer 108 . In other embodiments, the second insulating layer 114b is disposed between a part of the source electrode 110 and the gate electrode 104 whose vertical projection falls in the channel layer 108 .
换言之，第二绝缘层114b可设置于垂直投影落于通道层108内的源极110与漏极112的其中之一的一部分与栅极104之间。此外，于第二绝缘层114b设置于漏极112与栅极104之间的实施方式中，源极110与栅极104之间可以不设置第二绝缘层114b。同样地，于第二绝缘层114b设置于源极110与栅极104之间的实施方式中，漏极112与栅极104之间可以不设置第二绝缘层114b。In other words, the second insulating layer 114 b may be disposed between a portion of one of the source 110 and the drain 112 that falls within the channel layer 108 in a vertical projection and the gate 104 . In addition, in the embodiment where the second insulating layer 114b is disposed between the drain 112 and the gate 104 , the second insulating layer 114b may not be disposed between the source 110 and the gate 104 . Likewise, in the embodiment where the second insulating layer 114b is disposed between the source 110 and the gate 104 , the second insulating layer 114b may not be disposed between the drain 112 and the gate 104 .
进一步而言，第二绝缘层114b设置于垂直投影落于通道层108内的部分漏极112的一部分与部分通道层108之间。亦即，对漏极112朝向栅极104的表面而言，其一部分为连接通道层108，而其另一部分为连接第二绝缘层114b。换言之，第二绝缘层114b设置于部分漏极112与部分通道层108之间，且第二绝缘层114b的相对两表面分别被部分漏极112与部分通道层108完全覆盖。Further, the second insulating layer 114b is disposed between a portion of the drain electrode 112 whose vertical projection falls within the channel layer 108 and a portion of the channel layer 108 . That is, for the surface of the drain 112 facing the gate 104 , a part thereof is connected to the channel layer 108 , and the other part thereof is connected to the second insulating layer 114 b. In other words, the second insulating layer 114b is disposed between the part of the drain 112 and the part of the channel layer 108 , and the opposite surfaces of the second insulating layer 114b are completely covered by the part of the drain 112 and the part of the channel layer 108 respectively.
于此配置下，垂直投影落于通道层108内的漏极112的一部分与栅极104之间的垂直距离为第一距离D1，而垂直投影落于通道层108内的源极110的一部分与栅极104之间的垂直距离为第二距离D2，其中，第一距离D1至少包含第二绝缘层114b的厚度，第二距离D2举例是不包含第二绝缘层114b的厚度。以上所述的「第一距离D1至少包含第二绝缘层114b的厚度」的意思为，第二绝缘层114b的厚度会被列入第一距离D1的范围之中。例如，本实施方式中，第一距离D1至少包含第二绝缘层114b的厚度、通道层108的厚度与第一绝缘层106的厚度。此外，第二距离D2至少包含通道层108的厚度与第一绝缘层106的厚度。进一步而言，图1中，第一距离D1为漏极112朝向栅极104与第二绝缘层114b的表面与栅极104朝向漏极112与第二绝缘层114b的表面之间的垂直距离，第二距离D2为源极110朝向栅极104与通道层108的表面与栅极104朝向通道层108与源极110的表面之间的垂直距离。Under this configuration, the vertical distance between a part of the drain electrode 112 that falls in the channel layer 108 and the gate 104 is the first distance D1, and a part of the source electrode 110 that falls in the channel layer 108 and the vertical distance The vertical distance between the gates 104 is the second distance D2, wherein the first distance D1 includes at least the thickness of the second insulating layer 114b, and the second distance D2 is, for example, the thickness not including the second insulating layer 114b. The aforementioned "the first distance D1 includes at least the thickness of the second insulating layer 114b" means that the thickness of the second insulating layer 114b will be included in the range of the first distance D1. For example, in this embodiment, the first distance D1 at least includes the thickness of the second insulating layer 114 b , the thickness of the channel layer 108 and the thickness of the first insulating layer 106 . In addition, the second distance D2 at least includes the thickness of the channel layer 108 and the thickness of the first insulating layer 106 . Further, in FIG. 1, the first distance D1 is the vertical distance between the surface of the drain 112 facing the gate 104 and the second insulating layer 114b and the surface of the gate 104 facing the drain 112 and the second insulating layer 114b, The second distance D2 is the vertical distance between the surface of the source 110 facing the gate 104 and the channel layer 108 and the surface of the gate 104 facing the channel layer 108 and the source 110 .
由于第一距离D1相对第二距离D2更进一步将第二绝缘层114b的厚度列入其中，因此第一距离D1会大于第二距离D2。借由此第一距离D1大于第二距离D2的配置，可以降低漏极112与栅极104之间所产生的寄生电容，借以降低馈通(feed through)电压与栅极负载(gate loading)。因此，通过此配置降低漏极112与栅极104之间所产生的馈通电压与栅极负载后，应用此像素结构100A的显示面板可以有更佳的品质。Since the first distance D1 further includes the thickness of the second insulating layer 114b relative to the second distance D2, the first distance D1 is greater than the second distance D2. With the configuration that the first distance D1 is greater than the second distance D2, the parasitic capacitance generated between the drain 112 and the gate 104 can be reduced, thereby reducing the feed through voltage and gate loading. Therefore, after reducing the feed-through voltage and gate load generated between the drain 112 and the gate 104 through this configuration, the display panel using the pixel structure 100A can have better quality.
换言之，若源极110与栅极104间形成第一电容，漏极112与栅极104间形成第二电容，其中，第一电容例如是栅极/源极电容(CGS)，而第二电容例如是栅极/漏极电容(CGD)，借由设置于漏极112与栅极104之间的第二绝缘层114b，可以降低第二电容，使得第一电容大于第二电容，进而降低馈通电压与栅极负载。另一方面，于部分实施方式中，第二绝缘层114b的厚度举例为300纳米(nm)至400纳米(nm)。通过调整第二绝缘层114b的厚度，可以调整第一距离D1的大小，使得第二电容(栅极/漏极电容)具有可调性。In other words, if a first capacitance is formed between the source 110 and the gate 104, a second capacitance is formed between the drain 112 and the gate 104, wherein the first capacitance is, for example, a gate/source capacitance (CGS), and the second capacitance For example, the gate/drain capacitance (CGD), through the second insulating layer 114b arranged between the drain 112 and the gate 104, can reduce the second capacitance, so that the first capacitance is greater than the second capacitance, thereby reducing the feed pass voltage and gate load. On the other hand, in some embodiments, the thickness of the second insulating layer 114 b is, for example, 300 nanometers (nm) to 400 nanometers (nm). By adjusting the thickness of the second insulating layer 114b, the size of the first distance D1 can be adjusted, so that the second capacitance (gate/drain capacitance) is adjustable.
除此之外，通道层108至栅极104的垂直投影落于栅极104之内。换言之，通道层108至基板102的垂直投影面积小于或等于栅极104至基板102的垂直投影面积，且通道层108至基板102的垂直投影落于栅极104至基板102的垂直投影的范围内或与其一致。于此配置下，由于栅极104可遮蔽自基板102背向通道层108的一侧射向通道层108的光线，因此，可避免通道层108因光照而产生的光电流，进而防止有漏电产生。Besides, the vertical projection of the channel layer 108 to the gate 104 falls within the gate 104 . In other words, the vertical projection area of the channel layer 108 to the substrate 102 is less than or equal to the vertical projection area of the gate 104 to the substrate 102, and the vertical projection of the channel layer 108 to the substrate 102 falls within the range of the vertical projection of the gate 104 to the substrate 102 or consistent with it. Under this configuration, since the gate 104 can shield the light emitted from the side of the substrate 102 facing away from the channel layer 108 to the channel layer 108, the photocurrent generated by the channel layer 108 due to light irradiation can be avoided, thereby preventing leakage. .
另一方面，第一钝化保护层116与钝化层118位于第一绝缘层106、通道层108、第二绝缘层114b、源极110与漏极112之上，其中，钝化层118位于第一钝化保护层116上表面并覆盖第一钝化保护层116。第一钝化保护层116与钝化层118具有通孔120，以至少暴露部分漏极112。第二钝化保护层124位于钝化层118上，且共享电极122位于第二钝化保护层124与钝化层118之间。On the other hand, the first passivation protection layer 116 and the passivation layer 118 are located on the first insulating layer 106, the channel layer 108, the second insulating layer 114b, the source electrode 110 and the drain electrode 112, wherein the passivation layer 118 is located on The upper surface of the first passivation protection layer 116 covers and covers the first passivation protection layer 116 . The first passivation protection layer 116 and the passivation layer 118 have a through hole 120 to expose at least part of the drain electrode 112 . The second passivation protection layer 124 is located on the passivation layer 118 , and the common electrode 122 is located between the second passivation protection layer 124 and the passivation layer 118 .
像素电极126位于钝化层118、共享电极122与第二钝化保护层124上，其中，像素电极126通过通孔120与漏极112电性连接。像素电极126、漏极112、钝化层118与栅极104于基板102的垂直投影至少部分重叠。同样地，由于像素电极126、漏极112、钝化层118与栅极104于基板102的垂直投影至少部分重叠，栅极104可用以遮蔽来自基板102背向通道层108的一侧射向像素电极126的光线，以避免像素电极126产生光电流而产生漏电。The pixel electrode 126 is located on the passivation layer 118 , the common electrode 122 and the second passivation protection layer 124 , wherein the pixel electrode 126 is electrically connected to the drain 112 through the through hole 120 . The vertical projection of the pixel electrode 126 , the drain electrode 112 , the passivation layer 118 and the gate 104 on the substrate 102 at least partially overlaps. Similarly, since the vertical projection of the pixel electrode 126, the drain electrode 112, the passivation layer 118 and the gate 104 on the substrate 102 at least partially overlaps, the gate 104 can be used to shield the pixel from the side of the substrate 102 facing away from the channel layer 108. The light from the electrode 126 is used to prevent the photocurrent generated by the pixel electrode 126 from causing leakage.
综上所述，像素结构100A中，通过设置第二绝缘层114b，可以降低漏极112与栅极104之间所产生的寄生电容，借以降低馈通电压与栅极负载，以使应用此像素结构100A的显示面板可以有更佳的品质，并改善亮暗不均的问题。另一方面，像素结构100A中的栅极104可用以作为遮蔽自基板102背向通道层108的一侧射入像素结构100A的光线，以避免通道层108产生光电流而产生漏电。To sum up, in the pixel structure 100A, by setting the second insulating layer 114b, the parasitic capacitance generated between the drain 112 and the gate 104 can be reduced, so as to reduce the feed-through voltage and gate load, so that the application of this pixel The display panel of the structure 100A can have better quality and improve the problem of uneven brightness and darkness. On the other hand, the gate 104 in the pixel structure 100A can be used to shield the light entering the pixel structure 100A from the side of the substrate 102 facing away from the channel layer 108 , so as to prevent the channel layer 108 from generating photocurrent and causing leakage.
此外，图1所绘的像素结构100A可通过图2A至图2K所绘示的制作流程完成，其中，图2A至图2K绘示图1的像素结构100A于制作流程的不同阶段的剖面图。以下将对像素结构的制作方法的各流程作说明。In addition, the pixel structure 100A shown in FIG. 1 can be completed through the manufacturing process shown in FIGS. 2A to 2K , wherein FIGS. 2A to 2K show cross-sectional views of the pixel structure 100A in FIG. 1 at different stages of the manufacturing process. Each flow of the manufacturing method of the pixel structure will be described below.
图2A中，形成栅极104于基板102上。于此步骤中，可以先形成金属层(未绘示)于基板102上，接着，图案化此金属层，以形成栅极104。In FIG. 2A , a gate 104 is formed on a substrate 102 . In this step, a metal layer (not shown) may be formed on the substrate 102 first, and then the metal layer is patterned to form the gate 104 .
图2B中，依序形成第一绝缘层106、半导体层107与第二绝缘层114，其中，第一绝缘层106形成于基板102与栅极104上，半导体层107形成于第一绝缘层106上，第二绝缘层114形成于半导体层107上。当依序形成第一绝缘层106、半导体层107与第二绝缘层114之后，再形成光阻层113于第二绝缘层114上，其中，光阻层113举例为正型光阻。In FIG. 2B, the first insulating layer 106, the semiconductor layer 107 and the second insulating layer 114 are formed in sequence, wherein the first insulating layer 106 is formed on the substrate 102 and the gate 104, and the semiconductor layer 107 is formed on the first insulating layer 106. Above, the second insulating layer 114 is formed on the semiconductor layer 107 . After forming the first insulating layer 106 , the semiconductor layer 107 and the second insulating layer 114 in sequence, a photoresist layer 113 is formed on the second insulating layer 114 , wherein the photoresist layer 113 is, for example, a positive photoresist.
图2C中，使用半阶式光罩115对光阻层113进行曝光。于曝光结束后，再接着对光阻层113进行显影制程。由于对光阻层113所进行的曝光制程是通过半阶式光罩115完成，因此位于第二绝缘层114a上的光阻层113a会有两种厚度(如图2D所示)。In FIG. 2C , a half-step mask 115 is used to expose the photoresist layer 113 . After the exposure, the photoresist layer 113 is then developed. Since the exposure process of the photoresist layer 113 is completed through the half-step mask 115, the photoresist layer 113a on the second insulating layer 114a has two thicknesses (as shown in FIG. 2D).
图2D中，以光阻层113a为屏蔽，进行第一蚀刻制程，以图案化半导体层107与第二绝缘层114b，其中，半导体层107于图案化之后形成通道层108，并具有源极连接部108s与漏极连接部108d，其中，第二绝缘层114于图案化之后形成第二绝缘层114a。源极连接部108s与漏极连接部108d分别为通道层108的相对两端部，其用于连接后续制程中所形成的源极与漏极(如图1的源极110与漏极112)。In FIG. 2D, the photoresist layer 113a is used as a mask to perform a first etching process to pattern the semiconductor layer 107 and the second insulating layer 114b, wherein the semiconductor layer 107 forms a channel layer 108 after patterning and has a source connection part 108s and the drain connection part 108d, wherein the second insulating layer 114 forms the second insulating layer 114a after patterning. The source connecting portion 108s and the drain connecting portion 108d are opposite ends of the channel layer 108 respectively, which are used to connect the source and the drain formed in the subsequent process (such as the source 110 and the drain 112 in FIG. 1 ) .
图2E中，移除光阻层113a中较薄的部分而形成光阻层113b，以暴露部分图案化的第二绝缘层114a，其中，移除光阻层113a中较薄的部分的步骤包含减薄光阻层113a的厚度，例如通过灰化(ashing)制程。由于第二绝缘层114a上的光阻层113a具有两种厚度，因此，光阻层113a中较薄的部分会先被移除，而光阻层113a中较厚的部分可以于减薄后留存于第二绝缘层114a上。In FIG. 2E, the photoresist layer 113b is formed by removing a thinner part of the photoresist layer 113a to expose a part of the patterned second insulating layer 114a, wherein the step of removing the thinner part of the photoresist layer 113a includes The thickness of the photoresist layer 113a is reduced, for example, by an ashing process. Since the photoresist layer 113a on the second insulating layer 114a has two thicknesses, the thinner part of the photoresist layer 113a will be removed first, and the thicker part of the photoresist layer 113a can remain after being thinned. on the second insulating layer 114a.
请参考图2E至图2F，通过留存于第二绝缘层114a上的光阻层113b(请见图2E)来进行第二蚀刻制程，以移除部分图案化的第二绝缘层114a，并暴露部分通道层108。接着，于移除部分图案化的第二绝缘层114a后形成第二绝缘层114b，再将光阻层113b移除。此外，图案化的第二绝缘层114b至通道层108的垂直投影落于漏极连接部108d之内。亦即，图案化的第二绝缘层114b至通道层108的垂直投影落于预计形成漏极的范围内，以使第二绝缘层114b可位于栅极104与后续制程中所形成的漏极之间。然而，于其他实施方式中，图案化的第二绝缘层114b至通道层108的垂直投影可落于源极连接部108s之内，即落于预计形成源极的范围内，以使第二绝缘层114b可位于栅极104与后续制程中所形成的源极之间。2E to 2F, a second etching process is performed through the photoresist layer 113b (see FIG. 2E) remaining on the second insulating layer 114a to remove part of the patterned second insulating layer 114a and expose Part of the channel layer 108 . Next, the second insulating layer 114b is formed after removing part of the patterned second insulating layer 114a, and then the photoresist layer 113b is removed. In addition, the vertical projection of the patterned second insulating layer 114b onto the channel layer 108 falls within the drain connection portion 108d. That is, the vertical projection of the patterned second insulating layer 114b to the channel layer 108 falls within the range where the drain is expected to be formed, so that the second insulating layer 114b can be located between the gate 104 and the drain formed in the subsequent process. between. However, in other implementations, the vertical projection of the patterned second insulating layer 114b to the channel layer 108 may fall within the source connection portion 108s, that is, within the range where the source is expected to be formed, so that the second insulating The layer 114b may be located between the gate 104 and a source formed in a subsequent process.
图2G中，形成金属层(未绘示)于第一绝缘层106、通道层108与第二绝缘层114b上，接着，将金属层图案化为源极110与漏极112。源极110与漏极112电性连接于通道层108，其中，源极110位于源极连接部108s上，漏极112位于漏极连接部108d上，且第二绝缘层114b位于漏极112与栅极104之间。In FIG. 2G , a metal layer (not shown) is formed on the first insulating layer 106 , the channel layer 108 and the second insulating layer 114 b, and then, the metal layer is patterned into the source 110 and the drain 112 . The source 110 and the drain 112 are electrically connected to the channel layer 108, wherein the source 110 is located on the source connecting portion 108s, the drain 112 is located on the drain connecting portion 108d, and the second insulating layer 114b is located between the drain 112 and the drain 112. Between the gates 104.
图2H中，形成第一钝化保护层116与钝化层118于第一绝缘层106、通道层108、第二绝缘层114b、源极110与漏极112之上，其中，钝化层118位于第一钝化保护层116上表面并覆盖第一钝化保护层116。接着，于钝化层118形成通孔120，并暴露部分第一钝化保护层116。In FIG. 2H, a first passivation protection layer 116 and a passivation layer 118 are formed on the first insulating layer 106, the channel layer 108, the second insulating layer 114b, the source electrode 110 and the drain electrode 112, wherein the passivation layer 118 Located on the upper surface of the first passivation protection layer 116 and covering the first passivation protection layer 116 . Next, a via hole 120 is formed in the passivation layer 118 to expose a portion of the first passivation protection layer 116 .
图2I中，形成共享电极122于钝化层118上。其中共享电极122的材料包含透明金属氧化物，例如铟锡氧化物(Indium Tin Oxide；ITO)。In FIG. 2I , the common electrode 122 is formed on the passivation layer 118 . The material of the common electrode 122 includes a transparent metal oxide, such as Indium Tin Oxide (ITO).
图2J中，形成第二钝化保护层124于钝化层118上，其中，共享电极122位于第二钝化保护层124与钝化层118之间。接着，移除部分第一钝化保护层116与部分第二钝化保护层124，使得通孔120至少贯穿第一钝化保护层116与钝化层118，以暴露部分漏极112。In FIG. 2J , a second passivation protection layer 124 is formed on the passivation layer 118 , wherein the common electrode 122 is located between the second passivation protection layer 124 and the passivation layer 118 . Next, part of the first passivation protection layer 116 and part of the second passivation protection layer 124 are removed, so that the via hole 120 at least penetrates through the first passivation protection layer 116 and the passivation layer 118 to expose part of the drain electrode 112 .
图2K中，形成像素电极126于钝化层118、共享电极122与第二钝化保护层124上，其中，像素电极126通过通孔120与漏极112电性连接。此外，同前所述，像素电极126、漏极112、钝化层118与栅极104于基板102的垂直投影至少部分重叠。当像素电极126形成后，即可得到如图1所示的像素结构100A。In FIG. 2K , the pixel electrode 126 is formed on the passivation layer 118 , the common electrode 122 and the second passivation protection layer 124 , wherein the pixel electrode 126 is electrically connected to the drain 112 through the through hole 120 . In addition, as mentioned above, the vertical projection of the pixel electrode 126 , the drain electrode 112 , the passivation layer 118 and the gate 104 on the substrate 102 at least partially overlaps. After the pixel electrode 126 is formed, the pixel structure 100A as shown in FIG. 1 can be obtained.
综合以上，通过使用半阶式光罩制程，可以在不增加光罩制程数量的情况下，于同一道光罩制程中形成通道层108与第二绝缘层114b。然而，于其他的实施方式中，信道层108与第二绝缘层114b也可以分别通过两道光罩制程形成。In summary, by using the half-step mask process, the channel layer 108 and the second insulating layer 114b can be formed in the same mask process without increasing the number of mask processes. However, in other implementation manners, the channel layer 108 and the second insulating layer 114b may also be formed through two photomask processes respectively.
此外，由于半阶式光罩制程可使所形成的绝缘层具有多个厚度。于部分实施方式中，所形成的第一绝缘层可通过半阶式光罩制程图案化，以使其具有至少两个厚度，借以使源极与栅极之间的垂直距离与漏极与栅极之间的垂直距离不相同。In addition, due to the half-step photomask process, the formed insulating layer can have multiple thicknesses. In some embodiments, the formed first insulating layer can be patterned by a half-step photomask process so that it has at least two thicknesses, so that the vertical distance between the source and the gate is the same as that between the drain and the gate. The vertical distance between the poles is not the same.
例如，请看到图3，其中，图3绘示本发明第二实施方式的像素结构100B的剖面图。为了不使图式过于复杂，图3无绘示第一钝化保护层、钝化层、共享电极、第二钝化保护层与像素电极，然而，本实施方式可参照第一实施方式配置第一钝化保护层、钝化层、共享电极、第二钝化保护层与像素电极。For example, please see FIG. 3 , wherein FIG. 3 shows a cross-sectional view of a pixel structure 100B according to a second embodiment of the present invention. In order not to make the drawing too complicated, FIG. 3 does not show the first passivation protection layer, the passivation layer, the common electrode, the second passivation protection layer and the pixel electrode. However, this embodiment can refer to the configuration of the first embodiment. A passivation protection layer, a passivation layer, a common electrode, a second passivation protection layer and a pixel electrode.
本实施方式与第一实施方式的差异在于，本实施方式的第一绝缘层106具有至少两个厚度，以使得源极110与栅极104之间的垂直距离与漏极112与栅极104之间的垂直距离不相同。具体而言，垂直投影落于通道层108内的源极110与栅极104之间的垂直距离和垂直投影落于通道层108内的漏极112与栅极104之间的垂直距离不相同。The difference between this embodiment and the first embodiment is that the first insulating layer 106 in this embodiment has at least two thicknesses, so that the vertical distance between the source 110 and the gate 104 is the same as the distance between the drain 112 and the gate 104 The vertical distance between them is different. Specifically, the vertical distance between the source 110 and the gate 104 in the channel layer 108 is different from the vertical distance between the drain 112 and the gate 104 in the channel layer 108 .
换言之，通过半阶式光罩制程，第一绝缘层106位于栅极104与源极110之间的厚度T1可小于第一绝缘层106位于栅极104与漏极112之间的厚度T2。进一步而言，源极110与栅极104之间的最大垂直距离小于漏极112与栅极104之间的最大垂直距离，其中，源极110与栅极104之间的最大垂直距离为源极110朝向栅极104的表面与栅极104朝向源极110的表面之间的垂直距离中的最大者，而漏极112与栅极104之间的最大垂直距离为漏极112朝向栅极104的表面与栅极104朝向漏极112的表面之间的垂直距离中的最大者。此外，源极110与栅极104之间的最大垂直距离和漏极112与栅极104之间的最大垂直距离的差值约为300埃至约10000埃。In other words, through the half-step photomask process, the thickness T1 of the first insulating layer 106 between the gate 104 and the source 110 may be smaller than the thickness T2 of the first insulating layer 106 between the gate 104 and the drain 112 . Further, the maximum vertical distance between the source 110 and the gate 104 is smaller than the maximum vertical distance between the drain 112 and the gate 104, wherein the maximum vertical distance between the source 110 and the gate 104 is the source 110 is the largest of the vertical distances between the surface of the gate 104 facing the gate 104 and the surface of the gate 104 facing the source 110 , and the maximum vertical distance between the drain 112 and the gate 104 is the maximum vertical distance between the drain 112 facing the gate 104 The largest of the vertical distances between the surface and the surface of the gate 104 facing the drain 112 . In addition, the difference between the maximum vertical distance between the source 110 and the gate 104 and the maximum vertical distance between the drain 112 and the gate 104 is about 300 Angstroms to about 10,000 Angstroms.
于此配置下，当源极110与栅极104间形成第一电容，漏极112与栅极104间形成第二电容，其中，第一电容例如是栅极/源极电容(CGS)，而第二电容例如是栅极/漏极电容(CGD)，借由源极110与栅极104之间的最大垂直距离小于漏极112与栅极104之间的最大垂直距离，可以降低第二电容，使得第一电容可大于第二电容。例如，第一电容与第二电容的差值约为10pF至100pF。同前所述，通过降低第二电容，可以降低馈通电压与栅极负载。Under this configuration, when a first capacitance is formed between the source 110 and the gate 104, a second capacitance is formed between the drain 112 and the gate 104, wherein the first capacitance is, for example, a gate/source capacitance (CGS), and The second capacitance is, for example, a gate/drain capacitance (CGD). By virtue of the maximum vertical distance between the source 110 and the gate 104 being smaller than the maximum vertical distance between the drain 112 and the gate 104, the second capacitance can be reduced. , so that the first capacitance can be larger than the second capacitance. For example, the difference between the first capacitor and the second capacitor is about 10 pF to 100 pF. As mentioned above, by reducing the second capacitance, the feedthrough voltage and gate load can be reduced.
也就是说，于本实施方式的像素结构100B中，省略了第一实施方式中的第二绝缘层，而基板102、栅极104、第一绝缘层106、通道层108、源极110与漏极112所成的薄膜晶体管可通过具有两种厚度的第一绝缘层106达到降低栅极/漏极电容的效果。That is to say, in the pixel structure 100B of this embodiment, the second insulating layer in the first embodiment is omitted, and the substrate 102, the gate 104, the first insulating layer 106, the channel layer 108, the source 110 and the drain The thin film transistor formed by the electrode 112 can achieve the effect of reducing the gate/drain capacitance through the first insulating layer 106 having two kinds of thicknesses.
此外，本实施方式的像素结构100B是以第一绝缘层106位于栅极104与源极110之间的厚度小于第一绝缘层106位于栅极104与漏极112之间的厚度为例，于其他实施方式中，也可以是第一绝缘层106位于栅极104与漏极112之间的厚度小于第一绝缘层106位于栅极104与源极110之间的厚度，使得源极110与栅极104之间的最大垂直距离会大于漏极112与栅极104之间的最大垂直距离。In addition, in the pixel structure 100B of this embodiment, the thickness of the first insulating layer 106 between the gate 104 and the source 110 is smaller than the thickness of the first insulating layer 106 between the gate 104 and the drain 112 as an example. In other embodiments, the thickness of the first insulating layer 106 between the gate 104 and the drain 112 may be smaller than the thickness of the first insulating layer 106 between the gate 104 and the source 110, so that the source 110 and the gate The maximum vertical distance between electrodes 104 will be greater than the maximum vertical distance between drain 112 and gate 104 .
图4绘示本发明第三实施方式的像素结构100C的剖面图。为了不使图式过于复杂，图4无绘示第一钝化保护层、钝化层、共享电极、第二钝化保护层与像素电极，然而，本实施方式可参照第一实施方式配置第一钝化保护层、钝化层、共享电极、第二钝化保护层与像素电极。FIG. 4 is a cross-sectional view of a pixel structure 100C according to a third embodiment of the present invention. In order not to make the drawing too complicated, FIG. 4 does not show the first passivation protection layer, the passivation layer, the common electrode, the second passivation protection layer and the pixel electrode. However, this embodiment can refer to the configuration of the first embodiment. A passivation protection layer, a passivation layer, a common electrode, a second passivation protection layer and a pixel electrode.
请参照图4，本实施方式与第一实施方式的差异在于，本实施方式的第二绝缘层114b设置于第一绝缘层106朝向漏极112与通道层108的表面上，且第二绝缘层114b至通道层108的垂直投影例如落于漏极112至通道层108的垂直投影内。具体而言，第二绝缘层114b为设置于通道层108与第一绝缘层106之间。图4中，第一距离D1为漏极112朝向栅极104与第二绝缘层114b的表面与栅极104朝向漏极112与第二绝缘层114的表面之间的最大垂直距离，第二距离D2为源极110朝向栅极104与通道层108的表面与栅极104朝向通道层108与源极110的表面之间的最大垂直距离，其中，第一距离D1大于第二距离D2。于此配置下，由于第一距离D1通过第二绝缘层114b的设置而增加，因此可降低漏极112与栅极104之间所产生的寄生电容，借以降低馈通电压与栅极负载，以使应用此像素结构100C的显示面板可以有更佳的品质。Please refer to FIG. 4, the difference between this embodiment and the first embodiment is that the second insulating layer 114b of this embodiment is disposed on the surface of the first insulating layer 106 facing the drain 112 and the channel layer 108, and the second insulating layer The vertical projection of 114 b to the channel layer 108 falls within the vertical projection of the drain electrode 112 to the channel layer 108 , for example. Specifically, the second insulating layer 114 b is disposed between the channel layer 108 and the first insulating layer 106 . In FIG. 4, the first distance D1 is the maximum vertical distance between the surface of the drain 112 facing the gate 104 and the second insulating layer 114b and the surface of the gate 104 facing the drain 112 and the second insulating layer 114, and the second distance D2 is the maximum vertical distance between the surface of the source 110 facing the gate 104 and the channel layer 108 and the surface of the gate 104 facing the channel layer 108 and the source 110 , wherein the first distance D1 is greater than the second distance D2 . Under this configuration, since the first distance D1 is increased by the setting of the second insulating layer 114b, the parasitic capacitance generated between the drain 112 and the gate 104 can be reduced, so as to reduce the feed-through voltage and the gate load, so as to The display panel using the pixel structure 100C can have better quality.
此外，本实施方式是以第二绝缘层114b至通道层108的垂直投影落于漏极112至通道层108的垂直投影内为例，然而，于其他实施方式中，第二绝缘层114b至通道层108的垂直投影也可以是落于源极110至通道层108的垂直投影内，以降低源极110与栅极104之间所产生的寄生电容。In addition, in this embodiment, the vertical projection of the second insulating layer 114b to the channel layer 108 falls within the vertical projection of the drain electrode 112 to the channel layer 108 as an example, however, in other embodiments, the second insulating layer 114b to the channel The vertical projection of the layer 108 may also fall within the vertical projection from the source 110 to the channel layer 108 to reduce the parasitic capacitance generated between the source 110 and the gate 104 .
图5绘示本发明第四实施方式的像素结构100D的剖面图。为了不使图式过于复杂，图5无绘示第一钝化保护层、钝化层、共享电极、第二钝化保护层与像素电极，然而，本实施方式可参照第一实施方式配置第一钝化保护层、钝化层、共享电极、第二钝化保护层与像素电极。FIG. 5 is a cross-sectional view of a pixel structure 100D according to a fourth embodiment of the present invention. In order not to make the drawing too complicated, FIG. 5 does not show the first passivation protection layer, the passivation layer, the common electrode, the second passivation protection layer and the pixel electrode. However, this embodiment can refer to the configuration of the first embodiment. A passivation protection layer, a passivation layer, a common electrode, a second passivation protection layer and a pixel electrode.
请参照图5，本实施方式与第一实施方式的差异在于，本实施方式的第二绝缘层114b设置于第一绝缘层106背向漏极112与通道层108的表面上，且第二绝缘层114b至通道层108的垂直投影落于漏极112至通道层108的垂直投影内。具体而言，第二绝缘层114b是设置于第一绝缘层106与栅极104之间，且第一绝缘层106覆盖于第二绝缘层114b之上。图5中，第一距离D1为漏极112朝向栅极104与第二绝缘层114b的表面与栅极104朝向漏极112与第二绝缘层114b的表面之间的最大垂直距离，第二距离D2为源极110朝向栅极104与通道层108的表面与栅极104朝向通道层108与源极110的表面之间的最大垂直距离，其中，第一距离D1大于第二距离D2。于此配置下，由于第一距离D1通过第二绝缘层114b的设置而增加，因此可降低漏极112与栅极104之间所产生的寄生电容，借以降低馈通电压与栅极负载，以使应用此像素结构100D的显示面板可以有更佳的品质。Please refer to FIG. 5, the difference between this embodiment and the first embodiment is that the second insulating layer 114b of this embodiment is disposed on the surface of the first insulating layer 106 facing away from the drain electrode 112 and the channel layer 108, and the second insulating layer 114b The vertical projection of layer 114b to channel layer 108 falls within the vertical projection of drain 112 to channel layer 108 . Specifically, the second insulating layer 114b is disposed between the first insulating layer 106 and the gate 104, and the first insulating layer 106 covers the second insulating layer 114b. In FIG. 5, the first distance D1 is the maximum vertical distance between the surface of the drain 112 facing the gate 104 and the second insulating layer 114b and the surface of the gate 104 facing the drain 112 and the second insulating layer 114b, and the second distance D2 is the maximum vertical distance between the surface of the source 110 facing the gate 104 and the channel layer 108 and the surface of the gate 104 facing the channel layer 108 and the source 110 , wherein the first distance D1 is greater than the second distance D2 . Under this configuration, since the first distance D1 is increased by the setting of the second insulating layer 114b, the parasitic capacitance generated between the drain 112 and the gate 104 can be reduced, so as to reduce the feed-through voltage and the gate load, so as to The display panel using the pixel structure 100D can have better quality.
此外，本实施方式是以第二绝缘层114b至通道层108的垂直投影落于漏极112至通道层108的垂直投影内为例，然而，于其他实施方式中，第二绝缘层114b至通道层108的垂直投影也可以是落于源极110至通道层108的垂直投影内，以降低源极110与栅极104之间所产生的寄生电容。In addition, in this embodiment, the vertical projection of the second insulating layer 114b to the channel layer 108 falls within the vertical projection of the drain electrode 112 to the channel layer 108 as an example, however, in other embodiments, the second insulating layer 114b to the channel The vertical projection of the layer 108 may also fall within the vertical projection from the source 110 to the channel layer 108 to reduce the parasitic capacitance generated between the source 110 and the gate 104 .
图6绘示本发明第五实施方式的像素结构100E的剖面图。本实施方式与第一实施方式的差异在于，本实施方式的像素结构100E更包含栅极驱动电路(gate on array；GOA)单元130。栅极驱动电路单元130包含第一导电单元132与第二导电单元134。第一导电单元132设置于基板102上，并电性连接至栅极104。第二导电单元134设置于第一导电单元132之上，其中，第一绝缘层106、半导体层107与第二绝缘层114c位于第一导电单元132与第二导电单元134之间。FIG. 6 is a cross-sectional view of a pixel structure 100E according to a fifth embodiment of the present invention. The difference between this embodiment and the first embodiment is that the pixel structure 100E of this embodiment further includes a gate on array (GOA) unit 130 . The gate driving circuit unit 130 includes a first conductive unit 132 and a second conductive unit 134 . The first conductive unit 132 is disposed on the substrate 102 and electrically connected to the gate 104 . The second conductive unit 134 is disposed on the first conductive unit 132 , wherein the first insulating layer 106 , the semiconductor layer 107 and the second insulating layer 114 c are located between the first conductive unit 132 and the second conductive unit 134 .
由于第一绝缘层106与第二绝缘层114c可增加栅极驱动电路单元130的第一导电单元132与第二导电单元134之间的距离，因此可以降低第一导电单元132与第二导电单元134之间的寄生电容。Since the first insulating layer 106 and the second insulating layer 114c can increase the distance between the first conductive unit 132 and the second conductive unit 134 of the gate drive circuit unit 130, the distance between the first conductive unit 132 and the second conductive unit 134 can be reduced. The parasitic capacitance between 134.
另一方面，通过第二绝缘层114b，栅极104与漏极112之间的第一距离D1仍大于栅极104与源极110之间的第二距离D2。此外，于本实施方式的像素结构100E中，漏极112与通道层108之间的第二绝缘层114b和第一导电单元132与第二导电单元134之间的第二绝缘层114c可通过同一道制程完成，请见以下说明。On the other hand, through the second insulating layer 114b, the first distance D1 between the gate 104 and the drain 112 is still greater than the second distance D2 between the gate 104 and the source 110 . In addition, in the pixel structure 100E of this embodiment, the second insulating layer 114b between the drain electrode 112 and the channel layer 108 and the second insulating layer 114c between the first conductive unit 132 and the second conductive unit 134 can pass through the same The process is completed, please see the following instructions.
图7A至图7G绘示图6的像素结构100E于制作流程的不同阶段的剖面图。本实施方式与图2A至图2K所绘示的制作流程剖面图的差异在于，像素结构100E的制作方法更包含形成栅极驱动电路单元130(请见图6)。7A to 7G are cross-sectional views of the pixel structure 100E in FIG. 6 at different stages of the fabrication process. The difference between this embodiment and the cross-sectional fabrication process shown in FIGS. 2A to 2K is that the fabrication method of the pixel structure 100E further includes forming a gate driving circuit unit 130 (see FIG. 6 ).
图7A中，形成栅极104与第一导电单元132于基板102上。于此步骤中，可以先形成金属层(未绘示)于基板102上，接着图案化此金属层成栅极104与第一导电单元132。亦即，栅极104与第一导电单元132可通过同一道光罩制程图案化同一金属层而形成。In FIG. 7A , the gate 104 and the first conductive unit 132 are formed on the substrate 102 . In this step, a metal layer (not shown) may be formed on the substrate 102 first, and then the metal layer is patterned to form the gate 104 and the first conductive unit 132 . That is, the gate 104 and the first conductive unit 132 can be formed by patterning the same metal layer through the same photomask process.
图7B中，依序形成第一绝缘层106、半导体层107与第二绝缘层114，其中，第一绝缘层106形成于基板102、栅极104与第一导电单元132上，半导体层107形成于第一绝缘层106上，第二绝缘层114形成于半导体层107上。当依序形成第一绝缘层106、半导体层107与第二绝缘层114之后，再形成光阻层113于第二绝缘层114上。In FIG. 7B, the first insulating layer 106, the semiconductor layer 107 and the second insulating layer 114 are sequentially formed, wherein the first insulating layer 106 is formed on the substrate 102, the gate 104 and the first conductive unit 132, and the semiconductor layer 107 is formed. On the first insulating layer 106 , a second insulating layer 114 is formed on the semiconductor layer 107 . After forming the first insulating layer 106 , the semiconductor layer 107 and the second insulating layer 114 sequentially, a photoresist layer 113 is formed on the second insulating layer 114 .
图7C中，同图2C所述，图案化半导体层107与图案化第二绝缘层114可通过半阶式光罩制程完成。此外，由于光阻层113举例为正型光阻，因此半阶式光罩115遮蔽第一导电单元132上方的光线，以使第一导电单元132上方的光阻层113可于显影之后留存于第一导电单元132上方的第二绝缘层114上。此时便形成位于栅极104上方的光阻层113a1及位于第一导电单元132上方的光阻层113a2(如图7D所示)。In FIG. 7C , as described in FIG. 2C , the patterning of the semiconductor layer 107 and the patterning of the second insulating layer 114 can be completed through a half-step photomask process. In addition, since the photoresist layer 113 is, for example, a positive photoresist, the half-step photomask 115 shields the light above the first conductive unit 132 so that the photoresist layer 113 above the first conductive unit 132 can remain on the surface after development. On the second insulating layer 114 above the first conductive unit 132 . At this time, a photoresist layer 113a1 located above the gate 104 and a photoresist layer 113a2 located above the first conductive unit 132 are formed (as shown in FIG. 7D ).
图7D中，进行第一蚀刻制程，以图案化半导体层107与第二绝缘层114，其中，半导体层107于图案化之后形成位于栅极104上方的通道层108以及位于第一导电单元132上方的辅助层109，第二绝缘层114于图案化之后形成位于栅极104上方的第二绝缘层114a1以及位于第一导电单元132上方的第二绝缘层114a2，而第一导电单元132上方的辅助层109仍位于第一绝缘层106与第二绝缘层114a2之间。此外，由于图7C对光阻层所进行的曝光制程是通过半阶式光罩115完成，因此位于通道层108上方的第二绝缘层114a1上的光阻层113a1会有两种厚度，其中，第二绝缘层114a1上的光阻层113a1的厚度较大的一者与第一导电单元132上方的第二绝缘层114a2举例具有相同厚度。In FIG. 7D, a first etching process is performed to pattern the semiconductor layer 107 and the second insulating layer 114, wherein the semiconductor layer 107 is patterned to form the channel layer 108 above the gate 104 and above the first conductive unit 132. After the second insulating layer 114 is patterned, a second insulating layer 114a1 located above the gate 104 and a second insulating layer 114a2 located above the first conductive unit 132 are formed, and the auxiliary layer 114a2 located above the first conductive unit 132 Layer 109 is still located between first insulating layer 106 and second insulating layer 114a2. In addition, since the exposure process of the photoresist layer in FIG. 7C is completed through the half-step mask 115, the photoresist layer 113a1 on the second insulating layer 114a1 above the channel layer 108 has two thicknesses, wherein, The thicker one of the photoresist layer 113a1 on the second insulating layer 114a1 is, for example, the same thickness as the second insulating layer 114a2 above the first conductive unit 132 .
图7E中，减薄光阻层113a1及光阻层113a2，以移除光阻层113a1中较薄的部分，以形成位于第二绝缘层114a1上的光阻层113b1及位于辅助层109上的光阻层113b2，并暴露部分的第二绝缘层114a1。另一方面，请同时参照图7D及图7E，第一导电单元132上方的光阻层113b2的厚度小于光阻层113a2的厚度。In FIG. 7E, the photoresist layer 113a1 and the photoresist layer 113a2 are thinned to remove the thinner part of the photoresist layer 113a1 to form the photoresist layer 113b1 on the second insulating layer 114a1 and the photoresist on the auxiliary layer 109. layer 113b2, and expose a portion of the second insulating layer 114a1. On the other hand, please refer to FIG. 7D and FIG. 7E at the same time, the thickness of the photoresist layer 113b2 above the first conductive unit 132 is smaller than the thickness of the photoresist layer 113a2.
图7F中，通过留存的光阻层113b1(请见图7E)进行第二蚀刻制程，以移除通道层108上方的部分的第二绝缘层114a1，并暴露部分通道层108。接着，于移除第二绝缘层114a1的一部分以形成第二绝缘层114b后，再移除光阻层113b1及光阻层113b2。In FIG. 7F , a second etching process is performed through the remaining photoresist layer 113b1 (see FIG. 7E ) to remove part of the second insulating layer 114a1 above the channel layer 108 and expose part of the channel layer 108 . Next, after removing a part of the second insulating layer 114a1 to form the second insulating layer 114b, the photoresist layer 113b1 and the photoresist layer 113b2 are removed.
图7G中，形成金属层(未绘示)于第一绝缘层106、信道层108、信道层108上方的第二绝缘层114b与第一导电单元132上方的第二绝缘层114a2上，接着，将金属层图案化为源极110、漏极112与第二导电单元134，其中，第二导电单元134、源极110与漏极112为可通过同一道光罩制程形成。In FIG. 7G, a metal layer (not shown) is formed on the first insulating layer 106, the channel layer 108, the second insulating layer 114b above the channel layer 108, and the second insulating layer 114a2 above the first conductive unit 132, and then, The metal layer is patterned into the source 110 , the drain 112 and the second conductive unit 134 , wherein the second conductive unit 134 , the source 110 and the drain 112 can be formed through the same photomask process.
所形成的源极110与漏极112连接于通道层108，且第二绝缘层114b位于漏极112与栅极104之间。另一方面，于栅极驱动电路单元130中，第二导电单元134位于第一导电单元132上方，且第二绝缘层114a2至少位于第一导电单元132与第二导电单元134之间。The formed source 110 and drain 112 are connected to the channel layer 108 , and the second insulating layer 114 b is located between the drain 112 and the gate 104 . On the other hand, in the gate driving circuit unit 130 , the second conductive unit 134 is located above the first conductive unit 132 , and the second insulating layer 114a2 is at least located between the first conductive unit 132 and the second conductive unit 134 .
当第二导电单元134形成后，形成栅极驱动电路单元130的步骤也随的完成。接着，后续所进行的制程可如图2H至图2K所绘的流程完成。亦即，图6所绘的第一钝化保护层116、钝化层118、通孔120、共享电极122、第二钝化保护层124与像素电极126可通过图2H至图2K所绘的流程形成，以完成图6所示的像素结构100E。After the second conductive unit 134 is formed, the step of forming the gate driving circuit unit 130 is also completed. Then, subsequent manufacturing processes can be completed as shown in FIG. 2H to FIG. 2K . That is, the first passivation protection layer 116, the passivation layer 118, the via hole 120, the common electrode 122, the second passivation protection layer 124 and the pixel electrode 126 depicted in FIG. The process is formed to complete the pixel structure 100E shown in FIG. 6 .
图8绘示本发明第六实施方式的像素结构100F的剖面图。本实施方式与第一实施方式的差异在于，本实施方式的像素结构100F包含顶栅极(top gate)薄膜晶体管结构，其中，栅极104与漏极112之间的第一距离D1仍大于栅极104与源极110之间的第二距离D2。FIG. 8 is a cross-sectional view of a pixel structure 100F according to a sixth embodiment of the present invention. The difference between this embodiment and the first embodiment is that the pixel structure 100F of this embodiment includes a top gate (top gate) thin film transistor structure, wherein the first distance D1 between the gate 104 and the drain 112 is still larger than the gate 104 . The second distance D2 between the pole 104 and the source 110 .
于本实施方式中，信道层108、源极110、漏极112与第二绝缘层114b位于基板102与第一绝缘层106之间，且栅极104设置于第一绝缘层106背向基板102的表面。换言之，位于基板102上的通道层108、源极110、漏极112与第二绝缘层114b被第一绝缘层106覆盖。第二绝缘层114b位于漏极112上方并位于通道层108与第一绝缘层106之间，且第二绝缘层114b于基板102的垂直投影举例是落于漏极112于基板102的垂直投影之中。In this embodiment, the channel layer 108 , the source 110 , the drain 112 and the second insulating layer 114 b are located between the substrate 102 and the first insulating layer 106 , and the gate 104 is disposed on the first insulating layer 106 facing away from the substrate 102 s surface. In other words, the channel layer 108 , the source 110 , the drain 112 and the second insulating layer 114 b on the substrate 102 are covered by the first insulating layer 106 . The second insulating layer 114b is located above the drain 112 and between the channel layer 108 and the first insulating layer 106, and the vertical projection of the second insulating layer 114b on the substrate 102 is for example falling on the vertical projection of the drain 112 on the substrate 102. middle.
图8中，第一距离D1为漏极112朝向栅极104与第二绝缘层114b的表面与栅极104朝向漏极112与第二绝缘层114b的表面之间的最大垂直距离，第二距离D2为源极110朝向栅极104与通道层108的表面与栅极104朝向通道层108与源极110的表面之间的最大垂直距离，其中，第一距离D1大于第二距离D2。借由第二绝缘层114b的设置，由于第一距离D1可大于第二距离D2，因此降低了漏极112与栅极104之间所产生的寄生电容，并也降低馈通电压与栅极负载。也因此，应用像素结构100F的显示面板也可以有较佳的品质。In FIG. 8, the first distance D1 is the maximum vertical distance between the surface of the drain 112 facing the gate 104 and the second insulating layer 114b and the surface of the gate 104 facing the drain 112 and the second insulating layer 114b, and the second distance D2 is the maximum vertical distance between the surface of the source 110 facing the gate 104 and the channel layer 108 and the surface of the gate 104 facing the channel layer 108 and the source 110 , wherein the first distance D1 is greater than the second distance D2 . With the arrangement of the second insulating layer 114b, since the first distance D1 can be greater than the second distance D2, the parasitic capacitance generated between the drain 112 and the gate 104 is reduced, and the feedthrough voltage and gate load are also reduced. . Therefore, the display panel using the pixel structure 100F can also have better quality.
除此之外，像素结构100F更包含遮蔽层140。遮蔽层140位于基板102与通道层108之间，其中，通道层108至遮蔽层140的垂直投影落于遮蔽层140之内。换言之，通道层108至遮蔽层140的垂直投影落于遮蔽层140至基板102的垂直投影内。于此配置下，由于遮蔽层140可遮蔽自基板102背向通道层108的一侧射入像素结构100F的光线，因此可以避免通道层108因照射而产生光电流，进而防止漏电产生。遮蔽层140的材料举例是为金属或黑色树脂等等遮光材料。Besides, the pixel structure 100F further includes a shielding layer 140 . The shielding layer 140 is located between the substrate 102 and the channel layer 108 , wherein the vertical projection of the channel layer 108 to the shielding layer 140 falls within the shielding layer 140 . In other words, the vertical projection of the channel layer 108 to the shielding layer 140 falls within the vertical projection of the shielding layer 140 to the substrate 102 . Under this configuration, since the shielding layer 140 can shield the light entering the pixel structure 100F from the side of the substrate 102 facing away from the channel layer 108 , it can prevent the channel layer 108 from generating photocurrent due to irradiation, thereby preventing leakage. The material of the shielding layer 140 is, for example, light-shielding materials such as metal or black resin.
除此之外，图8所绘的像素结构100F是以将第二绝缘层114b设置于通道层108与于第一绝缘层106之间，且第二绝缘层114b于基板102的垂直投影是落于漏极112于基板102的垂直投影之中为例。然而，在其他的实施方式中，第二绝缘层114b也可以设置于通道层108与漏极112之间，且第二绝缘层114于基板102的垂直投影是落于源极110于基板102的垂直投影之中，以至少增加栅极104与源极110的距离，进而降低栅极104与源极110之间的寄生电容。此外，在其他的实施方式中，两个第二绝缘层114b也可以分别设置于通道层108与漏极112之间和通道层108与于第一绝缘层106之间，进一步增加栅极104与源极110的距离。In addition, the pixel structure 100F depicted in FIG. 8 is based on disposing the second insulating layer 114b between the channel layer 108 and the first insulating layer 106, and the vertical projection of the second insulating layer 114b on the substrate 102 is to fall Take the vertical projection of the drain electrode 112 on the substrate 102 as an example. However, in other embodiments, the second insulating layer 114b can also be disposed between the channel layer 108 and the drain 112, and the vertical projection of the second insulating layer 114 on the substrate 102 falls on the source 110 on the substrate 102. In the vertical projection, at least the distance between the gate 104 and the source 110 is increased, thereby reducing the parasitic capacitance between the gate 104 and the source 110 . In addition, in other implementation manners, the two second insulating layers 114b can also be respectively disposed between the channel layer 108 and the drain 112 and between the channel layer 108 and the first insulating layer 106, further increasing the gate 104 and the first insulating layer 106. source 110 distance.
图8所绘的像素结构100F可通过图9A至图9D所绘示的制作流程完成，其中，图9A至图9D绘示图8的像素结构100F于制作流程的不同阶段的剖面图。以下将对图8的像素结构100F的制作方法的各流程作说明。The pixel structure 100F shown in FIG. 8 can be completed through the manufacturing process shown in FIGS. 9A to 9D , wherein FIGS. 9A to 9D show cross-sectional views of the pixel structure 100F in FIG. 8 at different stages of the manufacturing process. Each flow of the manufacturing method of the pixel structure 100F in FIG. 8 will be described below.
图9A中，形成遮蔽层140于基板102上，接着，形成金属层(未绘示)于基板102上，并将金属层图案化为源极110与漏极112。In FIG. 9A , a shielding layer 140 is formed on the substrate 102 , and then, a metal layer (not shown) is formed on the substrate 102 , and the metal layer is patterned into the source 110 and the drain 112 .
图9B中，形成半导体层(未绘示)于遮蔽层140、源极110与漏极112上，并图案化半导体层成通道层108，其中，所形成的通道层108电性连接源极110与漏极112，且通道层108至遮蔽层140的垂直投影落于遮蔽层140之内。In FIG. 9B, a semiconductor layer (not shown) is formed on the shielding layer 140, the source 110 and the drain 112, and the semiconductor layer is patterned into a channel layer 108, wherein the formed channel layer 108 is electrically connected to the source 110. and the drain electrode 112 , and the vertical projection from the channel layer 108 to the shielding layer 140 falls within the shielding layer 140 .
图9C中，形成第二绝缘层114b于通道层108上，其中，第二绝缘层114b至通道层108的垂直投影举例是落于漏极112至通道层108的垂直投影内。亦即，部分的通道层108会位于第二绝缘层114b与部分的漏极112之间。In FIG. 9C , the second insulating layer 114 b is formed on the channel layer 108 , wherein the vertical projection of the second insulating layer 114 b to the channel layer 108 falls within the vertical projection of the drain electrode 112 to the channel layer 108 . That is, part of the channel layer 108 is located between the second insulating layer 114 b and part of the drain 112 .
图9D中，形成第一绝缘层106，并覆盖源极110、漏极112、通道层108与第二绝缘层114b，接着，形成栅极104于第一绝缘层106上。由于图9C所形成的第二绝缘层114b的垂直投影是落于漏极112至通道层108的垂直投影内，因此，所形成的栅极104与漏极112的垂直距离会大于其与源极110的垂直距离，借以降低栅极104与漏极112之间的寄生电容。In FIG. 9D , the first insulating layer 106 is formed to cover the source 110 , the drain 112 , the channel layer 108 and the second insulating layer 114 b, and then the gate 104 is formed on the first insulating layer 106 . Since the vertical projection of the second insulating layer 114b formed in FIG. 9C falls within the vertical projection from the drain 112 to the channel layer 108, the vertical distance between the formed gate 104 and the drain 112 will be greater than that between the source and the drain. 110 to reduce the parasitic capacitance between the gate 104 and the drain 112 .
综上所述，本发明的像素结构通过第二绝缘层的设置，降低源极与漏极的其中之一与栅极之间所产生的寄生电容，借以降低馈通电压与栅极负载，以使应用像素结构的显示面板可以有更佳的品质，并改善亮暗不均的问题。另一方面，像素结构的栅极可用以作为遮蔽射入像素结构内的光线，以避免像素结构中的通道层因产生光电流而导致漏电产生。To sum up, the pixel structure of the present invention reduces the parasitic capacitance generated between one of the source and the drain and the gate through the setting of the second insulating layer, so as to reduce the feedthrough voltage and the gate load, so as to The display panel using the pixel structure can have better quality, and the problem of uneven brightness and darkness can be improved. On the other hand, the gate of the pixel structure can be used to shield light incident into the pixel structure, so as to prevent the channel layer in the pixel structure from generating photocurrent and causing leakage.
虽然本发明已以多种实施方式揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视后附的申请专利范围所界定者为准。Although the present invention has been disclosed above in various embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, The scope of protection of the present invention should be defined by the scope of the appended patent application.
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| TW104143580ATWI593090B (en) | 2015-12-24 | 2015-12-24 | Pixel structure, manufacturing method thereof and thin film transistor |
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| CN201610081525.1ACN105655405B (en) | 2015-12-24 | 2016-02-05 | Pixel structure, manufacturing method thereof and thin film transistor |
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| CN201610081525.1ADivisionCN105655405B (en) | 2015-12-24 | 2016-02-05 | Pixel structure, manufacturing method thereof and thin film transistor |
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| CN201610081525.1AExpired - Fee RelatedCN105655405B (en) | 2015-12-24 | 2016-02-05 | Pixel structure, manufacturing method thereof and thin film transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109560085A (en)* | 2018-12-10 | 2019-04-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and display module |
| CN110262145A (en)* | 2019-06-11 | 2019-09-20 | 惠科股份有限公司 | Array substrate, manufacturing method of array substrate and display panel |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102484185B1 (en)* | 2016-10-31 | 2023-01-04 | 엘지디스플레이 주식회사 | Gate driving circuit and display device using the same |
| CN107342050B (en)* | 2017-08-30 | 2019-08-30 | 上海天马有机发光显示技术有限公司 | A kind of display base plate and display device |
| CN108663863B (en)* | 2018-06-25 | 2021-01-26 | Tcl华星光电技术有限公司 | Array substrate |
| TWI743899B (en)* | 2020-07-22 | 2021-10-21 | 友達光電股份有限公司 | Device array substrate and manufacturing method thereof |
| US20230317633A1 (en)* | 2022-03-30 | 2023-10-05 | Win Semiconductors Corp. | Semiconductor chip |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120193620A1 (en)* | 2011-02-02 | 2012-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and semiconductor device |
| US20130207102A1 (en)* | 2012-02-15 | 2013-08-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN203850306U (en)* | 2014-05-13 | 2014-09-24 | 华映视讯（吴江）有限公司 | Film transistor and pixel structure |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW471182B (en)* | 2001-01-20 | 2002-01-01 | Unipac Optoelectronics Corp | Thin film transistor having light guide material |
| JP2009180981A (en)* | 2008-01-31 | 2009-08-13 | Mitsubishi Electric Corp | Active matrix substrate and manufacturing method thereof |
| KR101600879B1 (en)* | 2010-03-16 | 2016-03-09 | 삼성디스플레이 주식회사 | Thin film transistor, manufacturing method thereof and display substrate using the thin film transistor |
| CN103035734A (en)* | 2011-10-07 | 2013-04-10 | 元太科技工业股份有限公司 | Metal oxide thin film transistor |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120193620A1 (en)* | 2011-02-02 | 2012-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and semiconductor device |
| US20130207102A1 (en)* | 2012-02-15 | 2013-08-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN203850306U (en)* | 2014-05-13 | 2014-09-24 | 华映视讯（吴江）有限公司 | Film transistor and pixel structure |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109560085A (en)* | 2018-12-10 | 2019-04-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and display module |
| CN110262145A (en)* | 2019-06-11 | 2019-09-20 | 惠科股份有限公司 | Array substrate, manufacturing method of array substrate and display panel |
| Publication number | Publication date |
|---|---|
| TWI593090B (en) | 2017-07-21 |
| CN105655405B (en) | 2018-06-08 |
| TW201724475A (en) | 2017-07-01 |
| CN105655405A (en) | 2016-06-08 |
| Publication | Publication Date | Title |
|---|---|---|
| CN105655405B (en) | Pixel structure, manufacturing method thereof and thin film transistor | |
| KR101517528B1 (en) | Method for manufacturing semiconductor device | |
| CN103149760B (en) | Thin film transistor array substrate, manufacturing method and display device | |
| CN104460147B (en) | Thin-film transistor array base-plate, manufacture method and display device | |
| US9711542B2 (en) | Method for fabricating display panel | |
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| WD01 | Invention patent application deemed withdrawn after publication | Application publication date:20180928 | |
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