CN108511450B - Method for forming threshold adjusting layer of memory peripheral circuit and peripheral circuit structure - Google Patents
Method for forming threshold adjusting layer of memory peripheral circuit and peripheral circuit structureDownload PDFInfo
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- CN108511450B CN108511450BCN201810353239.5ACN201810353239ACN108511450BCN 108511450 BCN108511450 BCN 108511450BCN 201810353239 ACN201810353239 ACN 201810353239ACN 108511450 BCN108511450 BCN 108511450B
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
Translated fromChinese
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for forming a threshold adjustment layer of a memory peripheral circuit and a peripheral circuit structure.
Background
In recent years, Flash Memory (Flash Memory) memories have been developed particularly rapidly. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up, and it has the advantages of high integration level, fast access speed, easy erasing and rewriting, so it is widely used in microcomputer, automation control and other fields.
In semiconductor processes, especially in the formation of memory, the reduction of the number of photomasks is a very important issue due to cost considerations, and it is desirable to minimize the number of photomasks and process steps.
In the flash memory formation process, a threshold adjustment implantation is performed on the high-voltage device region of the peripheral circuit region of the flash memory to adjust the threshold voltage of the formed transistor. Because the doping concentration of the threshold adjustment implantation is not high, in the prior art, in order to save a photomask, when the threshold adjustment implantation is performed on a high-voltage device region, the threshold adjustment implantation is usually directly performed on the whole wafer, and a mask layer is not additionally formed by using the photomask for defining the high-voltage device region. But this results in all devices being affected by the threshold adjustment implant, which has some effect on the performance of the memory.
Therefore, it is an urgent need to solve the problem of avoiding the influence of the threshold adjustment implantation on the devices in other regions without increasing the number of photomasks.
Disclosure of Invention
The invention provides a method for forming a threshold adjustment layer of a memory peripheral circuit and a peripheral circuit structure, which can avoid the influence of threshold adjustment injection on devices in other areas without increasing the number of photomasks.
In order to solve the above problems, the present invention provides a method for forming a threshold adjustment layer of a memory peripheral circuit, comprising: providing a substrate, wherein the substrate comprises a high-voltage area of a peripheral circuit; forming a patterned mask layer on the surface of the substrate, wherein at least part of the high-voltage area is exposed by the patterned mask layer; and taking the graphical mask layer as a mask, carrying out threshold adjustment injection on the high-voltage area, and forming a threshold adjustment layer in the high-voltage area and/or forming a gate dielectric layer of a high-voltage device on the surface of the high-voltage area.
Optionally, the patterned mask layer is used as a mask to perform threshold adjustment injection on the high-voltage region, and when a threshold adjustment layer is formed in the high-voltage region and a gate dielectric layer of a high-voltage device is formed on the surface of the high-voltage region, the gate dielectric layer of the high-voltage device is formed behind the threshold adjustment layer.
Optionally, a dielectric layer is arranged on the surface of the high-voltage area; the method for forming the threshold adjustment layer further includes: after the threshold adjusting layer is formed, the dielectric layer is removed.
Optionally, the threshold adjustment implantation uses boron as the implanted ions, the energy range is 10KeV to 80KeV, and the dose range is 5E11/cm2～1E13/cm2。
Optionally, the depth range of the threshold adjustment layer is
The doping concentration range is 5E11/cm3～1E13/cm3。
Optionally, a high-voltage P-well and a high-voltage N-well are formed in the high-voltage region.
In order to solve the above problems, the present invention further provides a memory peripheral circuit structure, including: a substrate including a high voltage region of a peripheral circuit; and the threshold adjusting layer is only positioned in the high-voltage area of the substrate and is used for adjusting the threshold voltage of the high-voltage area device.
Optionally, the method further includes: and the gate dielectric layer is positioned on the surface of the high-voltage area.
Optionally, the depth range of the threshold adjustment layer is
The doping concentration range is 5E11/cm3～1E13/cm3。
Optionally, a high-voltage P-well and a high-voltage N-well are formed in the high-voltage region.
The method for forming the threshold adjusting layer of the memory peripheral circuit utilizes the graphical mask layer as a mask when the gate dielectric layer is formed on the high-voltage area to carry out threshold adjusting injection, thereby forming the threshold adjusting layer only in the high-voltage area and avoiding the influence on other areas. In addition, an additional photomask and an additional photoetching step are not needed, and the performance of the memory can be improved on the premise of not increasing the process cost.
The threshold adjusting layer in the memory peripheral circuit structure is only formed in the high-voltage area, so that the influence on the device performance of other areas is avoided. And the threshold adjusting layer and the gate dielectric layer of the high-voltage device are positioned in the same area, the same graphical mask layer can be adopted, a photomask and a photoetching step are not required to be added, and the performance of the memory is improved on the premise of not increasing the process cost.
Drawings
Fig. 1 to 5 are schematic structural diagrams illustrating a process of forming a threshold adjustment layer of a memory peripheral circuit according to an embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of a method for forming a threshold adjustment layer of a memory peripheral circuit according to the present invention with reference to the accompanying drawings.
Referring to fig. 1, asubstrate 100 is provided, thesubstrate 100 including a high voltage region I of a peripheral circuit.
Thesubstrate 100 may be a semiconductor material, such as a single crystal silicon substrate, a single crystal germanium substrate, an SOI (silicon on insulator) or GOI (germanium on insulator) substrate, etc., and thesubstrate 100 may also be P-type doped or N-type doped. The skilled person can select suitable materials as the substrate according to actual requirements, and the substrate is not limited herein.
Thesubstrate 100 is used to form a memory, and includes a memory region and a peripheral circuit region, where a peripheral circuit is formed to control memory cells in the memory region.
Further, the peripheral circuit includes a high voltage region I on which high voltage devices such as a high voltage MOS transistor operating under a high voltage condition are formed, and a low voltage region (not shown in the figure). The low-voltage region is used for forming low-voltage devices such as a low-voltage MOS tube and the like which work under the low-voltage condition.
And aiming at the type of a high-voltage device to be formed, a high-voltage P well and a high-voltage N well are also formed in the high-voltage region I. And subsequently, threshold adjustment injection is required to be carried out in the high-voltage area I so as to further adjust the concentration of doped ions in the high-voltage area I, so that the threshold voltage of a high-voltage device to be formed is adjusted, and the high-voltage device can normally work in a high-voltage environment.
Referring to fig. 2, a patternedmask layer 200 is formed on the surface of thesubstrate 100, wherein at least a portion of the high voltage region I is exposed by the patternedmask layer 200.
The material of thepatterned mask layer 200 may be a photoresist layer or a hard mask material layer such as silicon oxide, silicon nitride, or silicon carbide. In this embodiment, the material of thepatterned mask layer 200 is a photoresist layer, and specifically, the method for forming thepatterned mask layer 200 includes: after a photoresist layer is formed on the surface of thesubstrate 100 through spin coating, an exposure and development operation is performed on the photoresist layer by adopting a photomask defining the position and the area of a high-voltage area I, a pattern on the photomask is transferred onto the photoresist layer to form thegraphical mask layer 200, and thegraphical mask layer 200 is provided with anopening 201 to expose the high-voltage area I.
Referring to fig. 3, thepatterned mask layer 200 is used as a mask to perform a threshold adjustment implantation on the high voltage region I, so as to form athreshold adjustment layer 103 in the high voltage region I of thesubstrate 100.
Since thepatterned mask layer 200 covers other regions, the threshold adjustment implantation only forms thethreshold adjustment layer 103 in the high voltage region I, and does not affect other regions, such as a low voltage region.
The threshold adjustment implantation may be an N-type or P-type ion implantation according to the requirement of threshold adjustment. Compared with the prior art that the threshold adjustment implantation is performed without adopting a mask layer, the threshold adjustment implantation parameters need to be adjusted correspondingly because the range of the threshold adjustment implantation is changed.
In one embodiment of the present invention, the threshold adjustment implant uses boron as the implant ion, the energy range is 10 KeV-80 KeV, and the dose range is 5E11/cm2～1E13/cm2. Thethreshold adjusting layer 103 is formed above the high-voltage P-well 101 and the high-voltage N-well 102 close to the surface of thesubstrate 100 to change the concentration of doped ions in the channel of the high-voltage device, so as to adjust the threshold voltage of the high-voltage device. In order to achieve better threshold adjustment effect, the depth range of thethreshold adjustment layer 103 is
The doping concentration range is 5E11/cm3～1E13/cm3。
Because a ZMOS structure is formed in the substrate if the substrate of the NMOS device is not doped or has no P well in the semiconductor process, namely the substrate is Psub, the ZMOS structure is a MOS structure with the threshold voltage close to 0, and the ZMOS structure is effectively utilized to be beneficial to the structural design of a peripheral circuit. In the prior art, a mask layer is not adopted for threshold adjustment injection, so that ZMOS structures in all regions including a high-voltage region and a low-voltage region are damaged, and the ZMOS structures cannot be utilized in the design process of a circuit structure. In the invention, only the high-voltage area I is subjected to threshold adjustment injection, only the ZMOS structure in the high-voltage area I is damaged, and the ZMOS structure in the low-voltage area can still be reserved, thus being beneficial to the design of a circuit structure in the low-voltage area.
In other embodiments of the present invention, a silicon oxide layer, a silicon oxide pad layer, or a dielectric layer made of other materials formed in the foregoing steps is further formed on the surface of thesubstrate 100. After thepatterned mask layer 200 is formed, the dielectric layer may be removed prior to performing the threshold adjustment implant. Under the condition that the thickness of the dielectric layer is low, the threshold adjustment injection can be directly carried out, so that injection damage to the surface of thesubstrate 100 caused by the threshold adjustment injection can be avoided, and adverse effects on the injection effect of the threshold adjustment injection caused by removing residual impurities in the dielectric layer process are also avoided.
Referring to fig. 4, the patternedmask layer 200 is continuously used as a mask to remove the silicon nitride and silicon oxide pad layer, and then the photoresist of themask layer 200 is removed, and then a gatedielectric layer 301 of the high-voltage device is formed on the surface of the high-voltage region I.
In this embodiment, the gatedielectric layer 301 is made of silicon oxide, and the gatedielectric layer 301 may be formed by a thermal oxidation process. In other specific embodiments, the gatedielectric layer 301 may also be made of a high-K dielectric material such as hafnium oxide, zirconium oxide, or the like, and the gatedielectric layer 301 may be formed by an atomic layer deposition process or the like.
Thesubstrate 100 is usually formed with a dielectric layer on its surface, which includes a silicon dioxide pad layer and a silicon nitride layer on the surface of the silicon dioxide pad layer. After the patternedmask layer 200 is used as a mask for threshold adjustment injection, the mask is continuously used to remove deposited or grown silicon nitride and silicon dioxide pad layers, and then the gatedielectric layer 301 of the high-voltage region is grown, because the device working voltages of the high-voltage region and the low-voltage region are different, gate dielectric layers with different thicknesses or materials need to be formed, and therefore gate dielectric layers need to be formed on the high-voltage region and the low-voltage region respectively, and therefore, in the process of forming the gatedielectric layer 301 on the high-voltage region I, thepatterned mask layer 200 exposing the high-voltage region I is inevitably required to be formed as a mask.
In the invention, thepatterned mask layer 200 required in the process of forming the gatedielectric layer 301 is used for removing the silicon nitride and silicon dioxide cushion layer, and the threshold adjustment injection is only formed in the high-voltage area I on the premise of not increasing the number of photomasks and photoetching process steps, thereby avoiding influencing devices in other areas. The performance of the memory can be improved on the premise of not increasing the process cost.
In other embodiments of the present invention, thegate dielectric layer 301 may be formed by using only the patternedmask layer 200 as a mask, without performing the threshold adjustment implantation.
Referring to fig. 5, a shallowtrench isolation structure 104, a low voltage P-well 105 and a low voltage N-well 106 are formed in thesubstrate 100.
The shallowtrench isolation structure 104 is used to divide an active region, and after the shallowtrench isolation structure 104 is formed, the low voltage P well 105 and the low voltage N well 106 are formed in a low voltage region of a peripheral circuit. And other process flows of memory manufacturing can be carried out subsequently.
The method for forming the threshold adjusting layer of the memory peripheral circuit utilizes the graphical mask layer as a mask when the gate dielectric layer is formed on the high-voltage area to carry out threshold adjusting injection, thereby forming the threshold adjusting layer only in the high-voltage area and avoiding the influence on other areas. In addition, an additional photomask and an additional photoetching step are not needed, and the performance of the memory can be improved on the premise of not increasing the process cost.
The invention also provides a peripheral circuit structure of the memory.
Fig. 4 is a schematic structural diagram of the memory peripheral circuit structure.
The memory peripheral circuit structure includes: asubstrate 100, thesubstrate 100 including a high voltage region I of a peripheral circuit; and athreshold adjusting layer 103, located only in the high voltage region I of thesubstrate 100, for adjusting the threshold voltage of the high voltage region device.
Thesubstrate 100 may be a semiconductor material, such as a single crystal silicon substrate, a single crystal germanium substrate, an SOI (silicon on insulator) or GOI (germanium on insulator) substrate, and thesubstrate 100 may also be P-type doped or N-type doped. The peripheral circuit includes a high voltage region I on which high voltage devices such as high voltage MOS transistors operating under high voltage are formed, and a low voltage region (not shown in the figure). The low-voltage region is used for forming low-voltage devices such as a low-voltage MOS tube and the like which work under the low-voltage condition.
And aiming at the type of the high-voltage device, a high-voltage P well and a high-voltage N well are also formed in the high-voltage area I. Thethreshold adjusting layer 103 is used to further adjust the concentration of doped ions in the high voltage region I, so as to adjust the threshold voltage of the high voltage device, so that the high voltage device can normally operate in a high voltage environment. The depth range of the threshold adjusting layer is
The doping concentration range is 5E11/cm3～1E13/cm3。
The memory peripheral circuit structure further comprises agate dielectric layer 301 of a high-voltage device positioned on the surface of the high-voltage area I. Thegate dielectric layer 301 and thethreshold adjusting layer 103 are both formed in the high-voltage region I, so that the same patterning mask layer can be adopted in the forming process of thegate dielectric layer 301 and thethreshold adjusting layer 103, and extra photomask and photoetching steps are not required.
Referring to fig. 5, the memory peripheral circuit structure may further include a shallowtrench isolation structure 104, and a low voltage P-well 105 and a low voltage N-well 106. The shallowtrench isolation structure 104 is used to partition an active region, and the low voltage P-well 105 and the low voltage N-well 106 are formed in a low voltage region of a peripheral circuit.
The threshold adjusting layer in the memory peripheral circuit structure is only formed in the high-voltage area, and the influence on the device performance of other areas is avoided. And the threshold adjusting layer and the gate dielectric layer of the high-voltage device are positioned in the same area, the same graphical mask layer can be adopted, a photomask and a photoetching step are not required to be added, and the performance of the memory is improved on the premise of not increasing the process cost.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A method for forming a threshold adjustment layer of a memory peripheral circuit, comprising:
providing a substrate, wherein the substrate comprises a high-voltage area of a peripheral circuit;
forming a patterned mask layer on the surface of the substrate, wherein at least part of the high-voltage area is exposed by the patterned mask layer;
and performing threshold adjustment injection on the high-voltage area by taking the graphical mask layer as a mask, forming a threshold adjustment layer in the high-voltage area, forming a gate dielectric layer of a high-voltage device on the surface of the high-voltage area by taking the graphical mask layer as a mask, and forming the gate dielectric layer of the high-voltage device behind the threshold adjustment layer.
2. The method of claim 1, wherein the surface of the high voltage region has a dielectric layer; the method for forming the threshold adjustment layer further includes: after the threshold adjusting layer is formed, the dielectric layer is removed.
3. The method of claim 1, wherein the threshold adjustment implant is performed with boron as an implant ion, and has an energy ranging from 10KeV to 80KeV and a dose ranging from 5E11/cm2～1E13/cm2。
4. The method of claim 1, wherein the threshold adjustment layer has a depth in a range of
The doping concentration range is 5E11/cm3～1E13/cm3。
5. The method of claim 1, wherein a high voltage P-well and a high voltage N-well are formed in the high voltage region.
6. A memory peripheral circuit structure, comprising:
a substrate including a high voltage region of a peripheral circuit;
the threshold adjusting layer is only positioned in a high-voltage area of the substrate and is used for adjusting the threshold voltage of a high-voltage area device; and the threshold adjusting layer and the gate dielectric layer are formed by adopting the same patterned mask layer.
7. The memory peripheral circuit structure of claim 6, wherein the threshold adjustment layer has a depth range of
The doping concentration range is 5E11/cm3～1E13/cm3。
8. The memory peripheral circuit structure of claim 6, wherein a high voltage P-well and a high voltage N-well are formed within the high voltage region.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1213183A (en)* | 1997-09-10 | 1999-04-07 | 日本电气株式会社 | A threshold voltage level setting method |
| CN1691331A (en)* | 1999-02-01 | 2005-11-02 | 株式会社日立制作所 | Semiconductor integrated circuit device |
| KR20090128915A (en)* | 2008-06-11 | 2009-12-16 | 매그나칩 반도체 유한회사 | Semiconductor integrated circuit device having triple gate insulating film and manufacturing method thereof |
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| US6680230B2 (en)* | 2001-07-25 | 2004-01-20 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| KR100557995B1 (en)* | 2003-07-30 | 2006-03-06 | 삼성전자주식회사 | Semiconductor device having floating trap type nonvolatile memory cell and method of manufacturing same |
| US8999785B2 (en)* | 2011-09-27 | 2015-04-07 | Tower Semiconductor Ltd. | Flash-to-ROM conversion |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1213183A (en)* | 1997-09-10 | 1999-04-07 | 日本电气株式会社 | A threshold voltage level setting method |
| CN1691331A (en)* | 1999-02-01 | 2005-11-02 | 株式会社日立制作所 | Semiconductor integrated circuit device |
| KR20090128915A (en)* | 2008-06-11 | 2009-12-16 | 매그나칩 반도체 유한회사 | Semiconductor integrated circuit device having triple gate insulating film and manufacturing method thereof |
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