CN108511029B - Built-in self-test and repair system and method for dual-port SRAM array in FPGA - Google Patents

Abstract

Translated fromChinese

本发明公开了一种FPGA中双端口SRAM阵列的内建自测和修复系统，包含：检测模块，用于获取内建自测过程的开始信号；自测试模块，包含：测试波形产生单元，用于产生不同的测试波形及读写控制信号；故障检测单元，用于比较从SRAM阵列的端口中读出的数据与预期数据，若不一致，则产生故障指示信号；存储单元，用于记录读出的数据、预期数据以及读出的数据与预期数据的对比结果；切换单元，用于切换测试的端口；还包含自修复模块，用于根据故障指示信号及对比结果对SRAM阵列进行修复。本发明还公开了一种内建自测和修复方法。本发明将双端口SRAM阵列配置成A端口写B端口读或者B端口写A端口读来测试，保证测试故障覆盖率高，并且测试和修复的效率高。

The invention discloses a built-in self-test and repair system of a dual-port SRAM array in an FPGA, comprising: a detection module for acquiring a start signal of the built-in self-test process; and a self-test module, comprising: a test waveform generation unit for It is used to generate different test waveforms and read and write control signals; the fault detection unit is used to compare the data read out from the port of the SRAM array with the expected data. If it is inconsistent, a fault indication signal will be generated; the storage unit is used to record and read The data, the expected data, and the comparison result between the read data and the expected data; the switching unit, which is used to switch the ports of the test; it also includes a self-repair module, which is used to repair the SRAM array according to the fault indication signal and the comparison result. The invention also discloses a built-in self-test and repair method. The invention configures the dual-port SRAM array as A port writes B port read or B port writes A port read for testing, which ensures high test fault coverage and high test and repair efficiency.

Description

Built-in self-test and repair system and method for dual-port SRAM array in FPGA

Technical Field

The invention relates to the technical field of programmable logic devices, in particular to a built-in self-test and repair system and a built-in self-test and repair method for a dual-port SRAM array in an FPGA.

Background

In deep submicron, a Static Random Access Memory (SRAM) is easily affected by process fluctuation, so that a built-in self-test and repair circuit is generally required to be added to the SRAM circuit, thereby improving the yield of chips. In addition, for a dual-port SRAM array (where there are a plurality of SRAM cells in the SRAM array, each SRAM cell has A, B read/write ports), there is a case where two ports access a common SRAM cell at the same time, and at this time, the read/write is more prone to errors than the single-ended read/write, so the test cannot simply test the a port and the B port separately, but the a port is configured as a-write-B-read or B-write-a-read for testing, thereby ensuring the coverage of the test.

The Field-Programmable Gate Array (FPGA) is widely used, and functions of a logic unit and an interconnection unit are controlled by downloading a bit stream to an SRAM Array built in the FPGA, and in addition, the bit stream can be read back from the SRAM of the FPGA.

Some FPGAs have special logic units added, such as a large number of SRAM memory blocks. As the capacity of FPGAs is made larger and larger, SRAM memory blocks are larger and smaller, as well as minimum feature sizes, which all increase the sensitivity of FPGAs to process defects. It is therefore necessary to propose a method for reducing this sensitivity.

The patent document with publication number US7216277B1 discloses a programmable logic device (SELF-REPAIRING REDUNDANCY FOR MEMORY BLOCKS IN PROGRAMMABLE LOGIC DEVICES) for SELF-repairing a redundant memory block, and proposes a built-in SELF-test and repair method for an SRAM memory block in an FPGA, which mainly solves the problems that: before the application date, a fuse wire and a non-volatile storage unit (such as an EEPROM or FLASH unit) are commonly used in an FPGA to store a test result, so that a corresponding redundant column is selected for repairing, the manufacturing cost and complexity are increased, only one factory test can be performed, then a repaired chip is handed to a user, and if some SRAMs are in failure during the use of the user, the test and the repair cannot be performed. However, the method does not involve the test of the dual-port SRAM array, when the SRAM cell is read at two ports simultaneously during the writing at one port and the reading at the other port, in a general SRAM circuit, at this time, four read pipes are all turned on and are easily interfered by the outside, and the read stability at this time becomes poor, so that the situation needs to be taken into consideration during the built-in self-test. In addition, all the memory blocks in the FPGA need built-in self test and repair, which needs a mechanism to ensure the most efficient completion of built-in self test and repair.

Disclosure of Invention

The invention aims to provide a built-in self-test and repair system and a built-in self-test and repair method for a dual-port SRAM array in an FPGA (field programmable gate array). the dual-port SRAM array is configured to be tested by writing in a port A and reading in a port B or writing in a port B and reading in a port A, so that high test fault coverage rate is ensured, and high test and repair efficiency is ensured.

In order to achieve the purpose, the invention is realized by the following technical scheme: a built-in self-test and repair system of a dual-port SRAM array in an FPGA is characterized by comprising:

the detection module is used for acquiring a starting signal of a built-in self-test process;

a self-test module, said self-test module comprising:

the test waveform generating unit is connected with the detection module and used for generating different test waveforms and read-write control signals according to a starting signal of a built-in self-test process;

the fault detection unit is connected with the test waveform generation unit and used for comparing the data read out from the port of the SRAM array with expected data, and if the data are not consistent with the expected data, a fault indication signal is generated;

the storage unit is connected with the fault detection unit and used for recording data read out from a port of the SRAM array, expected data and a comparison result of the read data and the expected data;

the switching unit is connected with the test waveform generating unit and used for switching a test port;

the built-in self-test and repair system also comprises a self-repair module which is respectively connected with the fault detection unit and the storage unit and used for repairing the SRAM array according to the fault indication signal and the comparison result of the read data and the expected data.

A built-in self-test and repair method of a dual-port SRAM array in an FPGA is characterized in that the method is used for carrying out built-in self-test and repair on a single SRAM array, and comprises a built-in self-test subprocess and a self-repair subprocess:

built-in self-test subprocess: when the fact that the redundancy repairing starting signal is valid and the fact that the indication signal of the previous-stage SRAM array for completing the built-in self-test subprocess test is invalid is detected, the built-in self-test subprocess is entered;

step S102: when detecting that an indication signal of the previous-stage SRAM array for completing the built-in self-test subprocess test is valid, writing first test waveform format data into an A port of the SRAM array according to a first test waveform;

step S104: when the write pointer count of the port A is detected to reach a preset value, reading data from the port A and the port B of the SRAM array respectively, comparing the read data with expected data, and if the read data is not consistent with the expected data, generating a fault indication signal;

step S106: resetting the read and write pointers of the port A and the read and write pointers of the port B when detecting that the read pointer count of the port A and the read pointer count of the port B both reach preset values, and executing the step S102 and the step S104 according to a second test waveform;

step S108: when detecting that the read pointer count of the port A and the read pointer count of the port B both reach preset values, executing step S102, step S104 and step S106 on the port B of the SRAM array;

a self-repairing sub-process: when the read pointer count of the port A and the read pointer count of the port B are detected to reach preset values, an indication signal for completing the built-in self-test subprocess test is set to be valid, if the redundancy repair signal is started to be invalid, the built-in self-test subprocess is switched to, the SRAM array is self-repaired according to the fault indication signal, and meanwhile, the indication signal for completing the built-in self-test subprocess test is set to be invalid.

The first test waveform is in a positive checkerboard format; the second test waveform is in an inverse checkerboard format.

The preset value is 511.

The built-in self-test and repair method is used for testing the fixed 0 fault and the fixed 1 fault set bridging fault of the SRAM unit.

A built-in self-test and repair method of a dual-port SRAM array in an FPGA is characterized in that the method is used for carrying out built-in self-test and repair on all SRAM arrays in the FPGA, and comprises a built-in self-test subprocess and a self-repair subprocess:

when detecting that the global signal is effective, entering a built-in self-test subprocess;

and when the indication signal of the last-stage SRAM array for completing the built-in self-test subprocess test is valid, resetting the global signal to 0, and simultaneously resetting the indication signals of all the SRAM arrays in the FPGA for completing the built-in self-test subprocess test to be invalid.

And the built-in self-test subprocess starts the test in sequence according to the frame address.

Compared with the prior art, the built-in self-test and repair system and the method thereof of the dual-port SRAM array in the FPGA have the following advantages: the dual-port SRAM array is configured to be tested by writing port A into port B for reading or writing port B into port A for reading, so that high test fault coverage rate is ensured; the test and repair of all SRAM units of the full chip can be completed with high efficiency.

Drawings

FIG. 1 is a schematic diagram of the overall structure of a built-in self-test and repair system of a dual-port SRAM array in an FPGA according to the present invention;

FIG. 2 is a flow chart of a method for built-in self test and repair of a single SRAM cell;

FIG. 3 is a flow chart of a method for performing built-in self test and repair of all SRAM cells in an SRAM array.

Detailed Description

The present invention will now be further described by way of the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings.

A built-in self test and repair system for a dual port SRAM array in an FPGA, as shown in fig. 1, comprising: thedetection module 10 is used for acquiring a starting signal of a built-in self-test process; a self-test module 20, said self-test module comprising: the testwaveform generating unit 21 is connected with thedetection module 10 and used for generating different test waveforms and read-write control signals according to a start signal of a built-in self-test process; afault detection unit 22 connected to the testwaveform generation unit 21 for comparing the data read from the port of the SRAM array with expected data, and if the data is not consistent with the expected data, generating a fault indication signal; astorage unit 23 connected to thefailure detection unit 22 for recording data read from the ports of the SRAM array, expected data, and a comparison result between the read data and the expected data; aswitching unit 24, connected to the testwaveform generating unit 21, for switching a port for testing; the built-in self-test and repair system further comprises a self-repair module 30, which is respectively connected with thefault detection unit 22 and thestorage unit 23, and is used for repairing the SRAM array according to the fault indication signal and the comparison result between the read data and the expected data.

A built-in self-test and repair method of a dual-port SRAM array in an FPGA is used for testing a fixed 0 fault and a fixed 1 fault set bridging fault of a single SRAM array, and as shown in FIG. 2, the built-in self-test and repair method comprises a built-in self-test subprocess and a self-repair subprocess:

built-in self-test subprocess: entering a built-in self-test subprocess when detecting that a Start redundancy repair signal is valid (Start _ RSR =1, Start redundancy-self-repeat) and an indication signal indicating that a previous-stage SRAM array completes the built-in self-test subprocess test is invalid (bit _ done _ pre = 0);

step S102: when detecting that the indication signal indicating that the previous-stage SRAM array completes the built-in self-test subprocess test is valid (bit _ done _ pre = 1), writing first test waveform format data (0101, 1010, 0101 ….) to the a port of the SRAM array according to a first test waveform (positive checkerboard format).

Step S104: when the write pointer count of the A port is detected to reach a preset value (wptr _ A = 511), data are read from the A port and the B port of the SRAM array respectively, the read data are compared with expected data, and if the read data are inconsistent with the expected data, a fault indication signal is generated (the fault indication signal is written into an SRAM special for an error signal).

Step S106: when detecting that the read pointer count of the a port and the read pointer count of the B port both reach the preset value (Rptr _ a = Rptr _ B = 511), the read and write pointers of the a port and the read and write pointers of the B port are reset, and step S102 and step S104 are performed according to the second test waveform (inverse checkerboard format).

Step S108: when detecting that the read pointer count of the a port (wptr _ a = 511) and the read pointer count of the B port both reach the preset value (wptr _ B = 511), the SRAM cell has been read out at this time, so step S102, step S104, and step S106 are performed on the B port of the SRAM array.

A self-repairing sub-process: when the read pointer count of the port A and the read pointer count of the port B are detected to reach preset values, the writing and reading of ABport and ADDRA/B [8:0] are completed, an indication signal for completing the built-in self-test subprocess test is set to be valid, if a redundancy repair signal is started to be invalid (Start _ RSR = 0), the built-in self-test subprocess is switched to, the SRAM array is self-repaired according to a fault indication signal, and meanwhile, the indication signal for completing the built-in self-test subprocess test is set to be invalid (BIST _ DONE = 0).

A built-in self-test and repair method for a dual-port SRAM array in an FPGA, which is used for performing built-in self-test and repair on all SRAM arrays in the FPGA, as shown in fig. 3, the built-in self-test and repair method includes a built-in self-test subprocess and a self-repair subprocess:

step S202: the global signal is detected to be valid (Start _ rsr = 1), and the built-in self-test subprocess is entered when FPGA TYPE0 is configured.

Since there is a corresponding SRAM (CFG [ N-1:0 ]) controlling the BIST, a built-in self test is initiated if the attribute SRAM of the SRAM _ MEMORY _ BLOCK is configured to be 1.

Step S204: and when the indication signal of the last-stage SRAM array for completing the built-in self-test subprocess test is valid, resetting the global signal to 0, and simultaneously resetting the indication signals of all the SRAM arrays in the FPGA for completing the built-in self-test subprocess test to be invalid.

The FPGA TYPE0 configuration is configured according to the frame address in sequence, so the BIST also starts the test according to the frame address in sequence.

While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.

Claims (8)

1. A built-in self-test and repair method of a dual-port SRAM array in an FPGA is characterized in that the built-in self-test and repair method is used for carrying out built-in self-test and repair on a single SRAM array, and comprises a built-in self-test subprocess and a self-repair subprocess:

built-in self-test subprocess: when the fact that the redundancy repairing starting signal is valid and the fact that the indication signal of the previous-stage SRAM array for completing the built-in self-test subprocess test is invalid is detected, the built-in self-test subprocess is entered;

step S102: when detecting that an indication signal of the previous-stage SRAM array for completing the built-in self-test subprocess test is valid, writing first test waveform format data into an A port of the SRAM array according to a first test waveform;

step S104: when the write pointer count of the port A is detected to reach a preset value, reading data from the port A and the port B of the SRAM array respectively, comparing the read data with expected data, and if the read data is not consistent with the expected data, generating a fault indication signal;

step S106: resetting the read and write pointers of the port A and the read and write pointers of the port B when detecting that the read pointer count of the port A and the read pointer count of the port B both reach preset values, and executing the step S102 and the step S104 according to a second test waveform;

step S108: when detecting that the read pointer count of the port A and the read pointer count of the port B both reach preset values, executing step S102, step S104 and step S106 on the port B of the SRAM array;

a self-repairing sub-process: when the read pointer count of the port A and the read pointer count of the port B are detected to reach preset values, an indication signal for completing the built-in self-test subprocess test is set to be valid, if the redundancy repair signal is started to be invalid, the built-in self-test subprocess is switched to, the SRAM array is self-repaired according to the fault indication signal, and meanwhile, the indication signal for completing the built-in self-test subprocess test is set to be invalid.

2. The method of claim 1, wherein the first test waveform is in a positive checkerboard format; the second test waveform is in an inverse checkerboard format.

3. The method of claim 1, wherein the predetermined value is 511.

4. The built-in self test and repair method of claim 1, wherein the built-in self test and repair method is used for testing of stuck-at 0 faults, stuck-at 1 fault set bridging faults of SRAM cells.

5. A built-in self test and repair system of a dual port SRAM array in an FPGA for implementing the built-in self test and repair method of any one of claims 1-4, comprising:

the detection module is used for acquiring a starting signal of a built-in self-test process;

a self-test module, said self-test module comprising:

the test waveform generating unit is connected with the detection module and used for generating different test waveforms and read-write control signals according to a starting signal of a built-in self-test process;

the fault detection unit is connected with the test waveform generation unit and used for comparing the data read out from the port of the SRAM array with expected data, and if the data are not consistent with the expected data, a fault indication signal is generated;

the storage unit is connected with the fault detection unit and used for recording data read out from a port of the SRAM array, expected data and a comparison result of the read data and the expected data;

the switching unit is connected with the test waveform generating unit and used for switching a test port;

the built-in self-test and repair system also comprises a self-repair module which is respectively connected with the fault detection unit and the storage unit and used for repairing the SRAM array according to the fault indication signal and the comparison result of the read data and the expected data.

6. A built-in self test and repair method for a full array of dual port SRAMs in an FPGA for built-in self test and repair of all SRAM arrays in the FPGA, the built-in self test and repair method comprising the built-in self test subprocess and the self repair subprocess of any one of claims 1 to 4:

when detecting that the global signal is effective, entering a built-in self-test subprocess;

and when the indication signal of the last-stage SRAM array for completing the built-in self-test subprocess test is valid, resetting the global signal to 0, and simultaneously resetting the indication signals of all the SRAM arrays in the FPGA for completing the built-in self-test subprocess test to be invalid.

7. The method of claim 6, wherein the built-in self test subprocess initiates tests in sequence by frame address.

8. A built-in self test and repair system for a dual port SRAM array in an FPGA for implementing the method of claim 7, comprising:

the detection module is used for acquiring a starting signal of a built-in self-test process;

a self-test module, said self-test module comprising:

the test waveform generating unit is connected with the detection module and used for generating different test waveforms and read-write control signals according to a starting signal of a built-in self-test process;

the fault detection unit is connected with the test waveform generation unit and used for comparing the data read out from the port of the SRAM array with expected data, and if the data are not consistent with the expected data, a fault indication signal is generated;

the storage unit is connected with the fault detection unit and used for recording data read out from a port of the SRAM array, expected data and a comparison result of the read data and the expected data;

the switching unit is connected with the test waveform generating unit and used for switching a test port;

the built-in self-test and repair system also comprises a self-repair module which is respectively connected with the fault detection unit and the storage unit and used for repairing the SRAM array according to the fault indication signal and the comparison result of the read data and the expected data.

Images