CN108346616B

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Info

Publication number: CN108346616B
Application number: CN201710056223.3A
Authority: CN
Inventors: 李鸿志; 黄旻暄
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2017-01-25
Filing date: 2017-01-25
Publication date: 2021-03-05
Anticipated expiration: 2037-01-25
Also published as: CN108346616A

Abstract

Translated fromChinese

一种内连线结构，包括基底、介电层、第一导电图案与第二导电图案。介电层设置于基底上，且具有开口。第一导电图案设置于开口中。第二导电图案设置于第一导电图案上，且暴露出第一导电图案的露出部分。第一导电图案的露出部分具有缺口。

An internal connection structure includes a substrate, a dielectric layer, a first conductive pattern and a second conductive pattern. The dielectric layer is disposed on the substrate and has an opening. The first conductive pattern is disposed in the opening. The second conductive pattern is disposed on the first conductive pattern and exposes an exposed portion of the first conductive pattern. The exposed portion of the first conductive pattern has a notch.

Description

Interconnect structure and method of fabricating the same

Technical Field

The present invention relates to a conductive structure and a method for fabricating the same, and more particularly, to an interconnect structure and a method for fabricating the same.

Background

As the semiconductor industry advances, as the integration level of integrated circuits increases and the surface of the chip is unable to provide enough area for the fabrication of the desired interconnects, the multilevel interconnect design is becoming a design of many integrated circuits.

As semiconductor devices are gradually scaled down, the overlap margin (overlay window) between the upper conductive element and the lower conductive element in the multilayer interconnection structure is also reduced, and thus alignment deviation is easily caused. When the alignment deviation occurs between the upper conductive element and the lower conductive element, the upper conductive element exposes the lower conductive element. As a result, the adjacent two upper conductive elements form a bridging path through the exposed lower conductive element, thereby generating a circuit bridging defect.

Disclosure of Invention

The present invention provides an interconnect structure and a method for fabricating the same, which can effectively prevent the occurrence of the defect of circuit bridging.

The invention provides an interconnect structure, which includes a substrate, a dielectric layer, a first conductive pattern and a second conductive pattern. The dielectric layer is disposed on the substrate and has an opening. The first conductive pattern is disposed in the opening. The second conductive pattern is disposed on the first conductive pattern and exposes the exposed portion of the first conductive pattern. The exposed portion of the first conductive pattern has a notch.

According to an embodiment of the present invention, in the interconnect structure, a material of the first conductive pattern is, for example, W, Ti, TiN, Ta, or TaN.

According to an embodiment of the present invention, in the interconnect structure, a material of the second conductive pattern is, for example, AlCu, Al, or W.

According to an embodiment of the present invention, in the interconnect structure, a width of the second conductive pattern may be smaller than a width of the first conductive pattern, and the exposed portion of the first conductive pattern may be located on one side or both sides of the second conductive pattern.

According to an embodiment of the present invention, in the interconnect structure, the opening exposes a portion of the sidewall of the opening.

The present invention provides a method for manufacturing an interconnect structure, which includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric layer has an opening. A first conductive pattern is formed in the opening. A second conductive pattern is formed on the first conductive pattern. The second conductive pattern exposes the exposed portion of the first conductive pattern. A gap is formed in the exposed portion of the first conductive pattern.

According to an embodiment of the present invention, in the method for manufacturing the interconnect structure, the forming method of the notch is, for example, to perform an etching process on the exposed portion of the first conductive pattern by using the second conductive pattern as a mask, so as to partially remove the exposed portion of the first conductive pattern.

According to an embodiment of the present invention, in the method for fabricating the interconnect structure, the etching gas used in the etching process includes chlorine and a shielding gas. The content of chlorine is, for example, 50 to 96% by volume, based on the total amount of chlorine and protective gas.

According to an embodiment of the present invention, in the method for fabricating the interconnect structure, the shielding gas is, for example, nitrogen (N)₂) Boron trichloride (BCl)₃) Trifluoromethane (CHF)₃) Methane (CH)₄) Or a combination thereof.

According to an embodiment of the present invention, in the method for fabricating an interconnect structure, the etching gas further includes an inert gas.

In view of the above, in the interconnect structure and the method for manufacturing the same provided by the present invention, since the exposed portion of the first conductive pattern exposed by the second conductive pattern has the gap, the bridge path between two adjacent second conductive patterns can be cut off. Therefore, the interconnect structure and the method for manufacturing the same provided by the invention can prevent the generation of the defect of circuit bridging, and can effectively increase the overlapping margin of the second conductive pattern and the first conductive pattern.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A to fig. 1D are cross-sectional views illustrating a manufacturing process of an interconnect structure according to an embodiment of the invention.

FIG. 2 is a cross-sectional view of an interconnect structure according to another embodiment of the present invention.

[ notation ] to show

100: substrate

102: dielectric layer

104: opening of the container

106. 110, 114: barrier layer

108. 112, 112: conductive pattern

116: gap

EP: exposed part

Detailed Description

First, referring to fig. 1A, adielectric layer 102 is formed on asubstrate 100, wherein thedielectric layer 102 has anopening 104. Thesubstrate 100 may be a single-layer substrate or a multi-layer substrate, and may have other layers (not shown) or semiconductor devices (not shown) formed thereon. The material of thedielectric layer 102 is, for example, silicon oxide. Thedielectric layer 102 is formed by, for example, chemical vapor deposition. Theopening 104 is, for example, a contact hole (contact hole), a via hole (via hole) or a trench. Theopening 104 is formed by, for example, patterning thedielectric layer 102.

Next, referring to fig. 1B, abarrier layer 106 may be selectively formed on the surface of theopening 104. The material of thebarrier layer 106 is, for example, Ti, TiN, Ta, TaN, or a combination thereof.

Then, aconductive pattern 108 is formed on thebarrier layer 106 in the opening 104. The adhesion between theconductive pattern 108 and other layers can be increased by thebarrier layer 106. Theconductive pattern 108 is, for example, a plug or a conductive line, wherein the plug may be a contact plug or a via plug. The material of theconductive pattern 108 is, for example, W, Ti, TiN, Ta, or TaN.

The formation method of thebarrier layer 106 and theconductive pattern 108 is illustrated as follows, but the invention is not limited thereto. First, a barrier material layer (not shown) is conformally formed on thedielectric layer 102. The barrier material layer is formed by physical vapor deposition or chemical vapor deposition. Next, a conductive pattern material layer (not shown) is formed on the barrier material layer to fill theopening 104. The conductive pattern material layer is formed by, for example, physical vapor deposition or chemical vapor deposition. Then, the conductive pattern material layer and the barrier material layer outside theopening 104 are removed. The conductive pattern material layer and the barrier material layer outside theopening 104 are removed by, for example, chemical mechanical polishing or etch back.

Next, referring to fig. 1C, abarrier layer 110 may be selectively formed on theconductive pattern 108. The material of thebarrier layer 110 is, for example, Ti, TiN, Ta, TaN, or a combination thereof.

Thereafter, aconductive pattern 112 is formed on thebarrier layer 110. Theconductive pattern 112 exposes the exposed portion EP of theconductive pattern 108. The adhesion between theconductive pattern 112 and other layers can be increased by thebarrier layer 110. In this embodiment, the exposed portion EP of theconductive pattern 108 may be located on one side of theconductive pattern 112. The width of theconductive pattern 112 may be greater than, equal to, or less than the width of theconductive pattern 108. Theconductive pattern 112 is, for example, a conductive line or a plug, wherein the plug may be a contact plug or a via plug. The material of theconductive pattern 112 is, for example, AlCu, Al, or W.

Further, abarrier layer 114 may be selectively formed on theconductive pattern 112. The material of thebarrier layer 114 is, for example, Ti, TiN, Ta, TaN, or a combination thereof. Thebarrier layer 114 can be used to increase adhesion between a layer subsequently formed thereon and theconductive pattern 112.

The formation method of thebarrier layer 114, theconductive pattern 112 and thebarrier layer 110 is illustrated as follows, but the invention is not limited thereto. First, a stack structure of a barrier material layer (not shown), a conductive pattern material layer (not shown) and a barrier material layer (not shown) is sequentially formed on thedielectric layer 102. The barrier material layer and the conductive pattern material layer are formed by physical vapor deposition or chemical vapor deposition. Then, a patterning process is performed on the stacked structure of the barrier material layer, the conductive pattern material layer and the barrier material layer.

Next, referring to fig. 1D, agap 116 is formed in the exposed portion EP of theconductive pattern 108. Since thegap 116 can cut off the bridge path between two adjacentconductive patterns 112, the defect of circuit bridging can be prevented, and the overlapping margin between theconductive patterns 112 and theconductive patterns 108 can be effectively increased. Thenotch 116 may expose a portion of the sidewall of theopening 104. The exposed portion EP of theconductive pattern 108 exposed by thenotch 116 may have a slope.

The forming method of thenotch 116 is, for example, to perform an etching process on the exposed portion EP of theconductive pattern 108 by using theconductive pattern 112 as a mask, so as to partially remove the exposed portion EP of theconductive pattern 108. The exposed portions EP of theconductive pattern 108 may be removed by in-situ (in-situ) etching. In the etching process performed on the exposed portion EP of theconductive pattern 108, a portion of thebarrier layer 106 on the sidewall of theopening 104 may be simultaneously removed. In addition, in the etching process, the etching rate of thebarrier layer 106 is, for example, higher than that of the exposed portion EP of theconductive pattern 108.

The etching gas used in the etching process includes chlorine and a protective gas. The content of chlorine is, for example, 50 to 96% by volume, based on the total amount of chlorine and protective gas. The protective gas is, for example, nitrogen, boron trichloride, trifluoromethane, methane, or a combination thereof. In addition, the etching gas may further include an inert gas. The inert gas is, for example, argon or helium.

In one embodiment, in the etching gas used in the etching process, the flow rate of the chlorine gas may be 15sccm to 500sccm, the flow rate of the nitrogen gas may be 5sccm to 20sccm, the flow rate of the boron trichloride may be 0sccm to 100sccm, the flow rate of the trifluoromethane may be 0sccm to 20sccm, the flow rate of the methane may be 0sccm to 15sccm, and the flow rate of the inert gas (e.g., argon or helium) may be 0sccm to 200 sccm. In another embodiment, in the etching gas used in the etching process, the flow rate of the chlorine gas may be 30sccm to 100sccm, the flow rate of the nitrogen gas may be 10sccm to 20sccm, the flow rate of the boron trichloride may be 0sccm to 5sccm, the flow rate of the trifluoromethane may be 0sccm to 3sccm, the flow rate of the methane may be 0sccm to 3sccm, and the flow rate of the inert gas may be 50sccm to 200 sccm.

In addition, in one embodiment, the process pressure may be 2mTorr to 30mTorr, the RF power source may be 30W to 1500W, and the RF bias power may be 15W to 850W during the etching process. In another embodiment, the process pressure may be 2mTorr to 8mTorr, the RF power source may be 300W to 1000W, and the RF bias power may be 100W to 250W when performing the etching process.

As can be seen from the above, in the method for manufacturing an interconnect structure in the above embodiment, since the exposed portion EP of theconductive pattern 108 exposed by theconductive pattern 112 has thenotch 116, the bridge path between two adjacentconductive patterns 112 can be cut. Thus, the method for manufacturing the interconnect structure of the above embodiment can prevent the occurrence of the defect of circuit bridging, and can effectively increase the overlapping margin between the

conductive patterns

112 and 108.

The interconnect structure of the present embodiment will be described with reference to fig. 1D. In addition, although the method for manufacturing the interconnect structure of the present embodiment is described as an example, the method for manufacturing the interconnect structure of the present invention is not limited thereto.

Referring to fig. 1D, the interconnect structure includes asubstrate 100, adielectric layer 102, aconductive pattern 108, and aconductive pattern 112. Thedielectric layer 102 is disposed on thesubstrate 100 and has anopening 104. Theconductive pattern 108 is disposed in theopening 104. Theconductive pattern 112 is disposed on theconductive pattern 108, and exposes the exposed portion EP of theconductive pattern 108. The exposed portion EP of theconductive pattern 108 has anotch 116. In this embodiment, the exposed portion EP of theconductive pattern 108 may be located on one side of theconductive pattern 112. In addition, the interconnect structure may optionally include at least one ofbarrier layer 106,barrier layer 110, andbarrier layer 114. Thebarrier layer 106 is disposed between theconductive pattern 108 and thedielectric layer 102, and may also be disposed between theconductive pattern 108 and thesubstrate 100. Thebarrier layer 110 is disposed between theconductive pattern 112 and theconductive pattern 108 and between theconductive pattern 112 and thedielectric layer 102. Thebarrier layer 114 is disposed on theconductive pattern 112. In addition, the materials, arrangement, forming method and effects of the components in the interconnect structure are described in detail in the manufacturing method of fig. 1A to 1D, and thus are not described herein again.

As can be seen from the above, in the interconnect structure of the above embodiment, since the exposed portion EP of theconductive pattern 108 exposed by theconductive pattern 112 has thenotch 116, the bridge path between two adjacentconductive patterns 112 can be cut. Thus, the interconnect structure of the above embodiment can prevent the occurrence of the defect of circuit bridging, and can effectively increase the overlapping margin between the

conductive patterns

112 and 108.

Referring to fig. 1D and fig. 2, the difference between the interconnect structure of fig. 1D and the interconnect structure of fig. 2 is as follows. In the interconnect structure of fig. 2, due to process variation, the width of theconductive pattern 108a is greater than the width of theconductive pattern 108, so that the width of theconductive pattern 112 is smaller than the width of theconductive pattern 108a, and the exposed portions EP of theconductive pattern 108a are located on two sides of theconductive pattern 112. In addition, the exposed portion EP of theconductive pattern 108a may havenotches 116 on both sides of theconductive pattern 112, respectively. In addition, the forming method and the effect of the interconnect structure of fig. 2 are similar to those of the interconnect structure of fig. 1D, and the same reference numerals are used for the same components, so the description thereof is omitted.

In summary, in the interconnect structure and the method for fabricating the same of the above embodiments, since the exposed portion of the lower conductive pattern exposed by the upper conductive pattern has the gap, the bridge path between two adjacent upper conductive patterns can be cut off. Therefore, the interconnect structure and the method for manufacturing the same of the above embodiments can prevent the occurrence of the defect of circuit bridging, and can effectively increase the overlapping margin between the upper conductive pattern and the lower conductive pattern.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.