技术领域technical field
本发明是有关于一种导电结构及其制造方法，且特别是有关于一种内连线结构及其制造方法。The present invention relates to a conductive structure and its manufacturing method, and in particular to an interconnect structure and its manufacturing method.
背景技术Background technique
随着半导体产业的发展，当集成电路的集成度增加，芯片的表面无法提供足够的面积来制作所需的内连线时，多层的内连线设计便逐渐地成为许多集成电路所必须采用的设计方式。With the development of the semiconductor industry, when the integration of integrated circuits increases and the surface of the chip cannot provide enough area to make the required interconnection, the multi-layer interconnection design has gradually become a must for many integrated circuits. way of design.
随着半导体组件逐渐缩小，多层内连线结构中的上层导电组件与其下方的下层导电组件的重迭裕度(overlay window)也会变小，因此容易发生对准偏差。当多层内连线结构中的上层导电组件与其下方的下层导电组件发生对准偏差时，上层导电组件会暴露出其下方的下层导电组件。如此一来，相邻的两个上层导电组件会通过所暴露出的下层导电组件而产生桥接路径(bridging path)，进而产生电路桥接(circuit bridging)的缺陷。As the semiconductor device shrinks gradually, the overlay window between the upper layer conductive device and the lower layer conductive device below it in the multilayer interconnection structure will also become smaller, so misalignment is prone to occur. When misalignment occurs between the upper layer conductive component and the lower layer conductive component in the multilayer interconnection structure, the upper layer conductive component will expose the lower layer conductive component below it. In this way, two adjacent upper-layer conductive components will generate bridging paths through the exposed lower-layer conductive components, thereby causing circuit bridging defects.
发明内容Contents of the invention
本发明提供一种内连线结构及其制造方法，其可有效地防止产生电路桥接的缺陷。The invention provides an interconnection structure and a manufacturing method thereof, which can effectively prevent circuit bridging defects.
本发明提出一种内连线结构，包括基底、介电层、第一导电图案与第二导电图案。介电层设置于基底上，且具有开口。第一导电图案设置于开口中。第二导电图案设置于第一导电图案上，且暴露出第一导电图案的露出部分。第一导电图案的露出部分具有缺口。The present invention provides an interconnection structure, including a substrate, a dielectric layer, a first conductive pattern and a second conductive pattern. The dielectric layer is disposed on the base and has an opening. The first conductive pattern is disposed in the opening. The second conductive pattern is disposed on the first conductive pattern and exposes an exposed portion of the first conductive pattern. The exposed portion of the first conductive pattern has a gap.
依照本发明的一实施例所述，在上述内连线结构中，第一导电图案的材料例如是W、Ti、TiN、Ta或TaN。According to an embodiment of the present invention, in the above interconnection structure, the material of the first conductive pattern is, for example, W, Ti, TiN, Ta or TaN.
依照本发明的一实施例所述，在上述内连线结构中，第二导电图案的材料例如是AlCu、Al或W。According to an embodiment of the present invention, in the above interconnection structure, the material of the second conductive pattern is, for example, AlCu, Al or W.
依照本发明的一实施例所述，在上述内连线结构中，第二导电图案的宽度可小于第一导电图案的宽度，且第一导电图案的露出部分可位于第二导电图案的一侧或两侧。According to an embodiment of the present invention, in the above interconnection structure, the width of the second conductive pattern may be smaller than the width of the first conductive pattern, and the exposed portion of the first conductive pattern may be located on one side of the second conductive pattern or sides.
依照本发明的一实施例所述，在上述内连线结构中，缺口可暴露出开口的部分侧壁。According to an embodiment of the present invention, in the above interconnection structure, the notch may expose part of the sidewall of the opening.
本发明提出一种内连线结构的制造方法，包括下列步骤。在基底上形成介电层，其中介电层具有开口。在开口中形成第一导电图案。在第一导电图案上形成第二导电图案。第二导电图案暴露出第一导电图案的露出部分。在第一导电图案的露出部分中形成缺口。The invention proposes a method for manufacturing an interconnection structure, which includes the following steps. A dielectric layer is formed on the substrate, wherein the dielectric layer has openings. A first conductive pattern is formed in the opening. A second conductive pattern is formed on the first conductive pattern. The second conductive pattern exposes the exposed portion of the first conductive pattern. A notch is formed in the exposed portion of the first conductive pattern.
依照本发明的一实施例所述，在上述内连线结构的制造方法中，缺口的形成方法例如是以第二导电图案为掩模，对第一导电图案的露出部分进行蚀刻工艺，以部分地移除第一导电图案的露出部分。According to an embodiment of the present invention, in the above method of manufacturing the interconnection structure, the notch is formed, for example, by using the second conductive pattern as a mask to etch the exposed portion of the first conductive pattern to partially The exposed portion of the first conductive pattern is removed.
依照本发明的一实施例所述，在上述内连线结构的制造方法中，蚀刻工艺所使用的蚀刻气体包括氯气与保护气体。以氯气与保护气体的总量计，氯气的含量例如是50体积％至96体积％。According to an embodiment of the present invention, in the manufacturing method of the interconnect structure, the etching gas used in the etching process includes chlorine gas and shielding gas. Based on the total amount of chlorine gas and protective gas, the content of chlorine gas is, for example, 50% by volume to 96% by volume.
依照本发明的一实施例所述，在上述内连线结构的制造方法中，保护气体例如是氮气(N2)、三氯化硼(BCl3)、三氟甲烷(CHF3)、甲烷(CH4)或其组合。According to an embodiment of the present invention, in the manufacturing method of the above-mentioned interconnection structure, the protective gas is, for example, nitrogen (N2 ), boron trichloride (BCl3 ), trifluoromethane (CHF3 ), methane ( CH4 ) or a combination thereof.
依照本发明的一实施例所述，在上述内连线结构的制造方法中，蚀刻气体还包括惰性气体。According to an embodiment of the present invention, in the above method of manufacturing the interconnection structure, the etching gas further includes an inert gas.
基于上述，在本发明所提出的内连线结构及其制造方法中，由于第二导电图案所暴露出的第一导电图案的露出部分具有缺口，因此可切断相邻两个第二导电图案之间的桥接路径。如此一来，本发明所提出的内连线结构及其制造方法可防止产生电路桥接的缺陷，且可有效地增加第二导电图案与第一导电图案的重迭裕度。Based on the above, in the interconnection structure and its manufacturing method proposed by the present invention, since the exposed portion of the first conductive pattern exposed by the second conductive pattern has a gap, it is possible to cut off the gap between two adjacent second conductive patterns. bridge paths between. In this way, the interconnection structure and its manufacturing method proposed by the present invention can prevent circuit bridging defects, and can effectively increase the overlap margin between the second conductive pattern and the first conductive pattern.
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.
附图说明Description of drawings
图1A至图1D为本发明一实施例的内连线结构的制造流程剖面图。1A to 1D are cross-sectional views of the manufacturing process of an interconnection structure according to an embodiment of the present invention.
图2为本发明另一实施例的内连线结构的剖面图。FIG. 2 is a cross-sectional view of an interconnection structure according to another embodiment of the present invention.
【符号说明】【Symbol Description】
100：基底100: base
102：介电层102: Dielectric layer
104：开口104: opening
106、110、114：阻障层106, 110, 114: barrier layer
108、112：导电图案108, 112: conductive pattern
116：缺口116: Gap
EP：露出部分EP: exposed part
具体实施方式Detailed ways
图1A至图1D为本发明一实施例的内连线结构的制造流程剖面图。1A to 1D are cross-sectional views of the manufacturing process of an interconnection structure according to an embodiment of the present invention.
首先，请参照图1A，在基底100上形成介电层102，其中介电层102具有开口104。基底100可为单层基底或多层基底，且可形成有其他膜层(未绘示)或半导体组件(未绘示)于其上。介电层102的材料例如是氧化硅。介电层102的形成方法例如是化学气相沉积法。开口104例如是接触窗开口(contact hole)、介层窗开口(via hole)或沟渠。开口104的形成方法例如是对介电层102进行图案化工艺。First, please refer to FIG. 1A , a dielectric layer 102 is formed on a substrate 100 , wherein the dielectric layer 102 has an opening 104 . The substrate 100 can be a single-layer substrate or a multi-layer substrate, and other film layers (not shown) or semiconductor devices (not shown) can be formed thereon. The material of the dielectric layer 102 is, for example, silicon oxide. The method for forming the dielectric layer 102 is, for example, chemical vapor deposition. The opening 104 is, for example, a contact hole, a via hole or a trench. A method for forming the opening 104 is, for example, performing a patterning process on the dielectric layer 102 .
接着，请参照图1B，可选择性地在开口104的表面形成阻障层106。阻障层106的材料例如是Ti、TiN、Ta、TaN或其组合。Next, please refer to FIG. 1B , a barrier layer 106 may be optionally formed on the surface of the opening 104 . The material of the barrier layer 106 is, for example, Ti, TiN, Ta, TaN or a combination thereof.
然后，在开口104中的阻障层106上形成导电图案108。可通过阻障层106来增加导电图案108与其他膜层的黏着力。导电图案108例如是插塞或导线，其中插塞可为接触窗插塞或介层窗插塞。导电图案108的材料例如是W、Ti、TiN、Ta或TaN。Then, a conductive pattern 108 is formed on the barrier layer 106 in the opening 104 . The adhesion between the conductive pattern 108 and other film layers can be increased by the barrier layer 106 . The conductive pattern 108 is, for example, a plug or a wire, wherein the plug can be a contact plug or a via plug. The material of the conductive pattern 108 is, for example, W, Ti, TiN, Ta or TaN.
阻障层106与导电图案108的形成方法举例说明如下，但本发明并不以此为限。首先，在介电层102上共形地形成阻障材料层(未绘示)。阻障材料层的形成方法例如是物理气相沉积法或化学气相沉积法。接着，在阻障材料层上形成填满开口104的导电图案材料层(未绘示)。导电图案材料层的形成方法例如是物理气相沉积法或化学气相沉积法。然后，移除开口104以外的导电图案材料层与阻障材料层。开口104以外的导电图案材料层与阻障材料层的移除方法例如是化学机械研磨法或回蚀刻法。The methods for forming the barrier layer 106 and the conductive pattern 108 are illustrated as follows, but the invention is not limited thereto. First, a barrier material layer (not shown) is conformally formed on the dielectric layer 102 . The formation method of the barrier material layer is, for example, physical vapor deposition or chemical vapor deposition. Next, a conductive pattern material layer (not shown) filling the opening 104 is formed on the barrier material layer. The method for forming the conductive pattern material layer is, for example, physical vapor deposition or chemical vapor deposition. Then, the conductive pattern material layer and barrier material layer outside the opening 104 are removed. The removal method of the conductive pattern material layer and the barrier material layer outside the opening 104 is, for example, a chemical mechanical polishing method or an etch-back method.
接下来，请参照图1C，可选择性地在导电图案108上形成阻障层110。阻障层110的材料例如是Ti、TiN、Ta、TaN或其组合。Next, referring to FIG. 1C , a barrier layer 110 may be optionally formed on the conductive pattern 108 . The material of the barrier layer 110 is, for example, Ti, TiN, Ta, TaN or a combination thereof.
之后，在阻障层110上形成导电图案112。导电图案112暴露出导电图案108的露出部分EP。可通过阻障层110来增加导电图案112与其他膜层的黏着力。在此实施例中，导电图案108的露出部分EP可位于导电图案112的一侧。导电图案112的宽度可大于、等于或小于导电图案108的宽度。导电图案112例如是导线或插塞，其中插塞可为接触窗插塞或介层窗插塞。导电图案112的材料例如是AlCu、Al或W。Afterwards, a conductive pattern 112 is formed on the barrier layer 110 . The conductive pattern 112 exposes the exposed portion EP of the conductive pattern 108 . The adhesion between the conductive pattern 112 and other film layers can be increased through the barrier layer 110 . In this embodiment, the exposed portion EP of the conductive pattern 108 may be located at one side of the conductive pattern 112 . The width of the conductive pattern 112 may be greater than, equal to, or smaller than the width of the conductive pattern 108 . The conductive pattern 112 is, for example, a wire or a plug, wherein the plug can be a contact plug or a via plug. The material of the conductive pattern 112 is, for example, AlCu, Al or W.
再者，可选择性地在导电图案112上形成阻障层114。阻障层114的材料例如是Ti、TiN、Ta、TaN或其组合。阻障层114可用以增加后续形成于其上的膜层与导电图案112之间的黏着力。Furthermore, a barrier layer 114 can be optionally formed on the conductive pattern 112 . The material of the barrier layer 114 is, for example, Ti, TiN, Ta, TaN or a combination thereof. The barrier layer 114 can be used to increase the adhesion between the subsequently formed film layer and the conductive pattern 112 .
阻障层114、导电图案112与阻障层110的形成方法举例说明如下，但本发明并不以此为限。首先，在介电层102上依序形成阻障材料层(未绘示)、导电图案材料层(未绘示)与阻障材料层(未绘示)的堆栈结构。阻障材料层与导电图案材料层的形成方法例如是物理气相沉积法或化学气相沉积法。接着，对阻障材料层、导电图案材料层与阻障材料层的堆栈结构进行图案化工艺。The methods for forming the barrier layer 114 , the conductive pattern 112 and the barrier layer 110 are illustrated as follows, but the invention is not limited thereto. Firstly, a stack structure of a barrier material layer (not shown), a conductive pattern material layer (not shown) and a barrier material layer (not shown) is sequentially formed on the dielectric layer 102 . The method for forming the barrier material layer and the conductive pattern material layer is, for example, physical vapor deposition or chemical vapor deposition. Next, a patterning process is performed on the stacked structure of the barrier material layer, the conductive pattern material layer and the barrier material layer.
接着，请参照图1D，在导电图案108的露出部分EP中形成缺口116。由于缺口116可切断相邻两个导电图案112之间的桥接路径，因此可防止产生电路桥接的缺陷，且可有效地增加导电图案112与导电图案108的重迭裕度。缺口116可暴露出开口104的部分侧壁。缺口116所暴露出的导电图案108的露出部分EP可具有斜面。Next, referring to FIG. 1D , a gap 116 is formed in the exposed portion EP of the conductive pattern 108 . Since the gap 116 can cut off the bridging path between two adjacent conductive patterns 112 , it can prevent circuit bridging defects and effectively increase the overlap margin between the conductive patterns 112 and the conductive patterns 108 . The notch 116 can expose a portion of the sidewall of the opening 104 . The exposed portion EP of the conductive pattern 108 exposed by the notch 116 may have a slope.
缺口116的形成方法例如是以导电图案112为掩模，对导电图案108的露出部分EP进行蚀刻工艺，以部分地移除导电图案108的露出部分EP。导电图案108的露出部分EP可通过原位(in-situ)蚀刻移除。在对导电图案108的露出部分EP所进行蚀刻工艺中，可同时移除开口104侧壁上的部分阻障层106。此外，在上述蚀刻工艺中，对阻障层106的蚀刻速度例如是大于对导电图案108的露出部分EP的蚀刻速度。The forming method of the gap 116 is, for example, using the conductive pattern 112 as a mask to perform an etching process on the exposed portion EP of the conductive pattern 108 to partially remove the exposed portion EP of the conductive pattern 108 . The exposed portion EP of the conductive pattern 108 can be removed by in-situ etching. During the etching process on the exposed portion EP of the conductive pattern 108 , part of the barrier layer 106 on the sidewall of the opening 104 can be removed simultaneously. In addition, in the above etching process, the etching rate for the barrier layer 106 is, for example, greater than the etching rate for the exposed portion EP of the conductive pattern 108 .
蚀刻工艺所使用的蚀刻气体包括氯气与保护气体。以氯气与保护气体的总量计，氯气的含量例如是50体积％至96体积％。保护气体例如是氮气、三氯化硼、三氟甲烷、甲烷或其组合。此外，蚀刻气体还包括惰性气体。惰性气体例如是氩气或氦气。The etching gas used in the etching process includes chlorine gas and shielding gas. Based on the total amount of chlorine gas and protective gas, the content of chlorine gas is, for example, 50% by volume to 96% by volume. The shielding gas is, for example, nitrogen, boron trichloride, trifluoromethane, methane or a combination thereof. In addition, the etching gas also includes an inert gas. Inert gases are, for example, argon or helium.
在一实施例中，在蚀刻工艺所使用的蚀刻气体中，氯气的流量可为15sccm至500sccm，氮气的流量可为5sccm至20sccm，三氯化硼的流量可为0sccm至100sccm，三氟甲烷的流量可为0sccm至20sccm，甲烷的流量可为0sccm至15sccm，惰性气体(如，氩气或氦气)的流量可为0sccm至200sccm。在另一实施例中，在蚀刻工艺所使用的蚀刻气体中，氯气的流量可为30sccm至100sccm，氮气的流量可为10sccm至20sccm，三氯化硼的流量可为0sccm至5sccm，三氟甲烷的流量可为0sccm至3sccm，甲烷的流量可为0sccm至3sccm，惰性气体的流量可为50sccm至200sccm。In one embodiment, in the etching gas used in the etching process, the flow rate of chlorine gas can be 15 sccm to 500 sccm, the flow rate of nitrogen gas can be 5 sccm to 20 sccm, the flow rate of boron trichloride can be 0 sccm to 100 sccm, and the flow rate of trifluoromethane can be 0 sccm to 100 sccm. The flow rate may be 0 sccm to 20 sccm, the flow rate of methane may be 0 sccm to 15 sccm, and the flow rate of inert gas (eg, argon or helium) may be 0 sccm to 200 sccm. In another embodiment, in the etching gas used in the etching process, the flow rate of chlorine gas can be 30 sccm to 100 sccm, the flow rate of nitrogen gas can be 10 sccm to 20 sccm, the flow rate of boron trichloride can be 0 sccm to 5 sccm, trifluoromethane The flow rate of the gas can be 0sccm to 3sccm, the flow rate of methane can be 0sccm to 3sccm, and the flow rate of the inert gas can be 50sccm to 200sccm.
此外，在一实施例中，在进行蚀刻工艺时，工艺压力可为2mTorr至30mTorr，射频电源功率可为30W至1500W，且射频偏压功率可为15W至850W。在另一实施例中，在进行蚀刻工艺时，工艺压力可为2mTorr至8mTorr，射频电源功率可为300W至1000W，且射频偏压功率可为100W至250W。In addition, in one embodiment, when performing the etching process, the process pressure may be 2 mTorr to 30 mTorr, the RF power may be 30 W to 1500 W, and the RF bias power may be 15 W to 850 W. In another embodiment, when performing the etching process, the process pressure may be 2 mTorr to 8 mTorr, the RF power may be 300W to 1000W, and the RF bias power may be 100W to 250W.
基于上述可知，在上述实施例的内连线结构的制造方法中，由于导电图案112所暴露出的导电图案108的露出部分EP具有缺口116，因此可切断相邻两个导电图案112之间的桥接路径。如此一来，上述实施例的内连线结构的制造方法可防止产生电路桥接的缺陷，且可有效地增加导电图案112与导电图案108的重迭裕度。Based on the above, in the method for manufacturing the interconnect structure of the above embodiment, since the exposed portion EP of the conductive pattern 108 exposed by the conductive pattern 112 has a gap 116, the connection between two adjacent conductive patterns 112 can be cut off. bridge path. In this way, the manufacturing method of the interconnection structure of the above-mentioned embodiment can prevent circuit bridging defects, and can effectively increase the overlapping margin of the conductive pattern 112 and the conductive pattern 108 .
以下，通过图1D来说明本实施例的内连线结构。此外，本实施例的内连线结构的制造方法虽然是上述制造方法为例进行说明，但本发明的内连线结构的制造方法并不以此为限。Hereinafter, the interconnection structure of this embodiment will be described with reference to FIG. 1D. In addition, although the manufacturing method of the interconnection structure in this embodiment is described by taking the above-mentioned manufacturing method as an example, the manufacturing method of the interconnection structure of the present invention is not limited thereto.
请参照图1D，内连线结构包括基底100、介电层102、导电图案108与导电图案112。介电层102设置于基底100上，且具有开口104。导电图案108设置于开口104中。导电图案112设置于导电图案108上，且暴露出导电图案108的露出部分EP。导电图案108的露出部分EP具有缺口116。在此实施例中，导电图案108的露出部分EP可位于导电图案112的一侧。此外，内连线结构还可选择性地包括阻障层106、阻障层110与阻障层114中的至少之一。阻障层106设置于导电图案108与介电层102之间，且还可设置于导电图案108与基底100之间。阻障层110设置于导电图案112与导电图案108之间且设置于导电图案112与介电层102之间。阻障层114设置于导电图案112上。另外，内连线结构中的各构件的材料、设置方式、形成方法与功效已于上述图1A至图1D的制造方法中进行详尽地说明，故于此不再赘述。Referring to FIG. 1D , the interconnect structure includes a substrate 100 , a dielectric layer 102 , a conductive pattern 108 and a conductive pattern 112 . The dielectric layer 102 is disposed on the substrate 100 and has an opening 104 . The conductive pattern 108 is disposed in the opening 104 . The conductive pattern 112 is disposed on the conductive pattern 108 and exposes the exposed portion EP of the conductive pattern 108 . The exposed portion EP of the conductive pattern 108 has a gap 116 . In this embodiment, the exposed portion EP of the conductive pattern 108 may be located at one side of the conductive pattern 112 . In addition, the interconnect structure can optionally include at least one of the barrier layer 106 , the barrier layer 110 and the barrier layer 114 . The barrier layer 106 is disposed between the conductive pattern 108 and the dielectric layer 102 , and may also be disposed between the conductive pattern 108 and the substrate 100 . The barrier layer 110 is disposed between the conductive pattern 112 and the conductive pattern 108 and between the conductive pattern 112 and the dielectric layer 102 . The barrier layer 114 is disposed on the conductive pattern 112 . In addition, the materials, arrangement methods, forming methods and functions of each component in the interconnection structure have been described in detail in the above-mentioned manufacturing method of FIG. 1A to FIG. 1D , so details are not repeated here.
基于上述可知，在上述实施例的内连线结构中，由于导电图案112所暴露出的导电图案108的露出部分EP具有缺口116，因此可切断相邻两个导电图案112之间的桥接路径。如此一来，上述实施例的内连线结构可防止产生电路桥接的缺陷，且可有效地增加导电图案112与导电图案108的重迭裕度。Based on the above, in the interconnect structure of the above embodiment, since the exposed portion EP of the conductive pattern 108 exposed by the conductive pattern 112 has a gap 116 , the bridging path between two adjacent conductive patterns 112 can be cut off. In this way, the interconnection structure of the above-mentioned embodiment can prevent circuit bridging defects, and can effectively increase the overlapping margin of the conductive pattern 112 and the conductive pattern 108 .
图2为本发明另一实施例的内连线结构的剖面图。FIG. 2 is a cross-sectional view of an interconnection structure according to another embodiment of the present invention.
请同时参照图1D与图2，图1D的内连线结构与图2的内连线结构的差异如下。在图2的内连线结构中，由于工艺变异的原因，造成导电图案108a的宽度大于导电图案108的宽度，而使得导电图案112的宽度小于导电图案108a的宽度，且导电图案108a的露出部分EP位于导电图案112两侧。此外，导电图案108a的露出部分EP在导电图案112的两侧可分别具有缺口116。此外，图2的内连线结构与图1D的内连线结构的形成方法与功效相似，且相同的构件使用相同的标号表示，故于此不再赘述。Please refer to FIG. 1D and FIG. 2 at the same time. The differences between the interconnection structure in FIG. 1D and the interconnection structure in FIG. 2 are as follows. In the interconnection structure of FIG. 2 , due to process variations, the width of the conductive pattern 108a is greater than the width of the conductive pattern 108, so that the width of the conductive pattern 112 is smaller than the width of the conductive pattern 108a, and the exposed portion of the conductive pattern 108a EP is located on both sides of the conductive pattern 112 . In addition, the exposed portion EP of the conductive pattern 108 a may have notches 116 on both sides of the conductive pattern 112 . In addition, the formation method and effect of the interconnection structure in FIG. 2 and the interconnection structure in FIG. 1D are similar, and the same components are denoted by the same reference numerals, so details are not repeated here.
综上所述，在上述实施例的内连线结构及其制造方法中，由于上层导电图案所暴露出的下层导电图案的露出部分具有缺口，因此可切断相邻两个上层导电图案之间的桥接路径。如此一来，上述实施例的内连线结构及其制造方法可防止产生电路桥接的缺陷，且可有效地增加上层导电图案与下层导电图案的重迭裕度。To sum up, in the interconnection structure and its manufacturing method of the above embodiment, since the exposed portion of the lower conductive pattern exposed by the upper conductive pattern has a gap, the connection between two adjacent upper conductive patterns can be cut off. bridge path. In this way, the interconnection structure and the manufacturing method thereof in the above embodiments can prevent circuit bridging defects, and can effectively increase the overlap margin between the upper conductive pattern and the lower conductive pattern.
虽然本发明已以实施例公开如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视后附的申请专利范围所界定者为准。Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined in the scope of the appended patent application.
| Application Number | Priority Date | Filing Date | Title |
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| CN201710056223.3ACN108346616B (en) | 2017-01-25 | 2017-01-25 | Interconnect structure and method of fabricating the same |
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| CN201710056223.3ACN108346616B (en) | 2017-01-25 | 2017-01-25 | Interconnect structure and method of fabricating the same |
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| CN108346616Atrue CN108346616A (en) | 2018-07-31 |
| CN108346616B CN108346616B (en) | 2021-03-05 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201710056223.3AActiveCN108346616B (en) | 2017-01-25 | 2017-01-25 | Interconnect structure and method of fabricating the same |
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