Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of BUCK converters and its inputsOutput control circuit, for solve in the prior art BUCK converters can not effectively expand to greatest extent wide scope input it is defeatedThe application gone out, and load can not be jumped to greatest extent from underloading and asked when overloaded what output voltage was quickly adjustedTopic.
In order to achieve the above objects and other related objects, the present invention provides a kind of input and output control electricity of BUCK convertersRoad, the BUCK converters include：Include the adaptive turn-on time generation circuit of turn-on time comparator, pulsewidth modulation is comparedDevice, rest-set flip-flop, closed loop control logic and are opened power switch driver circuit including PMOS power switch and NMOS powerThe power stage output circuit of pass；The input/output control circuit of the BUCK converters includes：Duty ratio logic control circuit andInductance peak-to-valley value logic control circuit；The duty ratio logic control circuit includes：First input end, with the pulsewidth modulation ratioOutput end compared with device is connected；Second input terminal is connected with the output end of the inductance peak-to-valley value logic control circuit；Third inputsEnd, is connected with the output end of the turn-on time comparator；Logic gates, including it is connected to the first of second input terminalFirst NOT gate output is carried out first and door of logic and operation by NOT gate with the output of the pulse width modulated comparator, withThe output of second NOT gate and the turn-on time comparator is carried out logical AND fortune by the second NOT gate of first input end connectionSecond calculated carries out logic or fortune with door and by the output of described second and door and the inductance peak-to-valley value logic control circuitFirst or the door calculated；Wherein, described first is connected with door with the ends S of the rest-set flip-flop, described first or door and the RS touchThe ends R for sending out device are connected.
In one embodiment of the invention, the inductance peak-to-valley value logic control circuit includes：Inductance peak detection logicCircuit, inductor valley detect logic circuit and respectively by the output of the inductance peak detection logic circuit and the inductor valleysThe output for detecting logic circuit carries out second or door of logic or operation；Described second or the output end of door be the inductance peakThe output end of valley logic control circuit.
In one embodiment of the invention, the phase is turned off in PMOS power switch conducting and the NMOS power switchBetween, the inductance peak detection logic circuit is detected inductive current；The NMOS power switch conducting and it is describedDuring PMOS power switch turns off, the inductor valley detection logic circuit is detected inductive current.
In one embodiment of the invention, the inductance peak detection logic circuit includes peak value Current-Limiting Comparator and peak valueLogic circuit；The inductor valley detection logic circuit includes valley Current-Limiting Comparator and valley logic circuit.
In one embodiment of the invention, the NMOS power switch conducting starts to the valley Current-Limiting Comparator to exportFrom it is logically high be turned to logic low during, it is height that the valley logic circuit, which forces the output of valley Current-Limiting Comparator output,Level.
In one embodiment of the invention, when inductive current is reduced to cut-off current or less, the valley current limliting ratio is controlledOutput compared with device is low level.
In one embodiment of the invention, the rest-set flip-flop is by two nor gate input, output end interconnection groupsAt.
The embodiment of the present invention also provides a kind of BUCK converters, and the BUCK converters include that BUCK as described above becomesThe input/output control circuit of parallel operation.
In one embodiment of the invention, the adaptive turn-on time generation circuit includes：It is connected to described lead in turnThe controlled current source of logical time comparator in-phase input end, timing capacitor and time switch；The turn-on time comparator it is anti-Output voltage terminal is connected to input terminal.
In one embodiment of the invention, the in-phase input end of the pulse width modulated comparator connects error amplifier, insteadOutput voltage sampling and synchronous slope generating circuit are connected to input terminal.
As described above, the BUCK converters and its input/output control circuit of the present invention, have the advantages that：
BUCK converters in the present invention can keep fast transient response possessed by ACOT frameworks always, and negativeWhen carrying transmission short circuit exception, BUCK converters, which can also stablize inductive current, be limited between peak value and valley, reach wide modelThe purpose of input and output is enclosed, and the transient response performance and security reliability of BUCK converters can be promoted to greatest extent,Extend practical ranges.
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific exampleDisclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realitiesThe mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing fromVarious modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the absence of conflict, following embodiment and implementationFeature in example can be combined with each other.
It please refers to Fig.1 to Fig. 7, it should be noted that the diagram provided in following embodiment only illustrates in a schematic wayThe basic conception of the present invention, package count when only display is with related component in the present invention rather than according to actual implementation in schema thenMesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and itsAssembly layout kenel may also be increasingly complex.
The purpose of the present embodiment is that a kind of BUCK converters and its input/output control circuit are provided, it is existing for solvingBUCK converters can not effectively expand to the application of wide scope input and output to greatest extent in technology, and can not be to greatest extentThe problem of quickly being adjusted to output voltage when overloaded is jumped to loading from underloading.The present invention's described in detail belowThe principle and embodiment of BUCK converters and its input/output control circuit makes those skilled in the art not need creative laborThe dynamic BUCK converters and its input/output control circuit for being appreciated that the present invention.
The BUCK transformation that the BUCK converters and its input/output control circuit of the present embodiment are controlled based on traditional ACOTDevice integrated circuit introduces 100% Duty ratio control and the minimum turn-on time (Min-off- comprising valley current limliting CL Compare LogicTime it) control and peak inductive current current limliting and valley inductor current current limliting and deposits, BUCK converters can be made to adapt to wide modelEnclose the application demand of input and output.The BUCK converters and its input/output control circuit of the present embodiment are carried out specifically belowIt is bright.
The present embodiment provides a kind of BUCK converters, as shown in Figure 1, the BUCK converters 1 include：Including turn-on timeThe adaptive turn-on time generation circuit 11 of comparator A1 (Cycle by Cycle compares frequency locking error Vferr and timing voltage Vct), pulsewidthModulate comparator A2 (Cycle by Cycle relative error voltage Vea and synchronous slope Vramp), rest-set flip-flop 12 (rest-set flip-flop 12 it is defeatedGo out the power switch work of logic Duty closed-loop control BUCK converters 1, when Duty is logically high, power power PMOS are ledLogical, power power NMOS are closed；When Duty logics are low, power power PMOS are closed, power power NMOS conductings.Duty logics are the duty ratio that logically high time accounting is BUCK converters 1 within the period), closed loop control logic 13(closed loop control logic 13 and power switch driver circuit 14 control BUCK converters 1 with power switch driver circuit 14The working condition of closed-loop control and power switch and generate the non-overlapping power power PMOS of two-phase driving voltage GH andThe driving voltage GL of power power NMOS), including PMOS power switch (PMOS shown in Fig. 1) and NMOS power switchPower stage output circuit.Power stage output circuit includes mainly PMOS power switch (PMOS shown in Fig. 1), NMOS powerSwitch (NMOS shown in Fig. 1), filter inductance L, filter capacitor C and output loading, power stage output circuit undertake BUCK1 power of converter and energy output.
Wherein, the adaptive turn-on time generation circuit 11 includes：It is connected to the turn-on time comparator A1 in turnThe controlled current source A of in-phase input end0(generating the electric current gm*Vin directly proportional to Vin), timing capacitor Ct and time switch Q；The reverse input end of the turn-on time comparator A1 connects output voltage terminal.The homophase input of the pulse width modulated comparator A2End connection error amplifier A3 (by detecting output feedback reference Vref and output feedback signal Vfb in real time, is obtained amplifiedError voltage Vea, as loop pulsewidth modulation foundation), reverse input end connects output voltage sampling and is generated with synchronous slopeCircuit 15 is (for generating output voltage feedback signal Vfb and the slope synchronous with inductive current letter needed for ACOT control modelsNumber Vramp).
In this present embodiment, the BUCK converters 1 further include input/output control circuit 10, as depicted in figs. 1 and 2,The input/output control circuit 10 includes：Duty ratio logic control circuit 110 and inductance peak-to-valley value logic control circuit 120.
In this present embodiment, as shown in figure 3, the rest-set flip-flop 12 intersects company by two nor gate input, output endsConnect composition.100% duty ratio and Min-off-time control logics used in the present embodiment is as shown in figure 3, rest-set flip-flop 12Output logic Q be DUTY CYCLE, for control power switch conducting turn off.When PWM mode is run, DUTYCYCLE=H (high level), PMOS power switch (PMOS shown in Fig. 1) conducting and NMOS power switch are (shown in Fig. 1NMOS it) turns off；DUTY CYCLE=L (low level), NMOS power switch (NMOS shown in Fig. 1) conducting and PMOS power are openedClose (PMOS shown in Fig. 1) shutdown.
Specifically, in this present embodiment, as shown in figure 3, the duty ratio logic control circuit 110 includes：First inputIt holds at (ends Vset shown in Fig. 3), is connected with the output end of the pulse width modulated comparator A2；Second input terminal is (shown in Fig. 3The ends OCP), be connected with the output end of the inductance peak-to-valley value logic control circuit 120；Third input terminal is (shown in Fig. 3The ends Vrset), it is connected with the output end of the turn-on time comparator A1；Logic gates 111, including it is connected to described secondFirst NOT gate 111a of input terminal (ends OCP shown in Fig. 3), by the first NOT gate 111a outputs and the pulsewidth modulation ratioOutput compared with device A2 carries out first and door 111b of logic and operation, is connect with first input end (ends Vset shown in Fig. 3)The second NOT gate 111c, the output of the second NOT gate 111c and the turn-on time comparator A1 are subjected to logic and operationSecond patrols with door 111d and by described second and door 111d and the output of the inductance peak-to-valley value logic control circuit 120Volume or operation first or door 111e；Wherein, described first is connected with door 111b with the ends S of the rest-set flip-flop 12, and describedOne or door 111e is connected with the ends R of the rest-set flip-flop 12.
The duty ratio logic control circuit 110 is by the inverted signal of the output logic Vset of pulse width modulated comparator A2 and leadsThe output logic Vrset of logical time comparator A1 does logical AND.When the mistake that output voltage Vout and input voltage vin move closer toThe output logic Vset of Cheng Zhong, pulse width modulated comparator A2 are logically high by the maintenance for stepping into 100% duty ratio, shield and leadLogical time comparator A1 exports the control to rest-set flip-flop 12R so that BUCK converters 1 step into the operation of 100% duty ratio.The duty ratio logic control circuit 110 can not only be such that BUCK converters 1 are transported automatically into 100% duty ratio in stable stateRow keeps input Vin and output Vout straight-through, is also beneficial to accelerate load response.Load jump signal occurs for BUCK converters 1 such asShown in Fig. 4, when BUCK converters 1 are when occurring to load upper saltus step, output voltage Vout declines lead to that error amplifier A3's is defeatedGo out Vea raisings.When synchronizing ramp signal Vramp by than stable state at this time later be increased beyond Vea, during which pulse width modulated comparatorThe output Vset of A2 just remains always logically high, and BUCK converters 1 enter 100% duty ratio and run, and maximally reduce defeatedThe shake for going out voltage, improves transient response performance.
In order to adapt to wide scope input and output operation, need to design inductance peak value current limliting and inductor valley current limliting simultaneouslyIt deposits, and is also the monitoring inductive current of Cycle by Cycle.The Current limited Control that the present embodiment is used is as shown in Figure 5.
In this present embodiment, the inductance peak-to-valley value logic control circuit 120 includes：Inductance peak detection logic circuit121, inductor valley detects logic circuit 122 and respectively by the output of the inductance peak detection logic circuit 121 and the electricityThe output for feeling valley detection logic circuit 122 carries out second or the door 123 of logic or operation.
In this present embodiment, the inductance peak detection logic circuit 121 includes peak value Current-Limiting Comparator CMP1 and peak valueLogic circuit 121a；The inductor valley detection logic circuit 122 includes valley Current-Limiting Comparator CMP2 and valley logic circuit122a。
Specifically, in the PMOS power switch (PMOS shown in Fig. 1) conducting and described NMOS power switch (Fig. 1Shown in NMOS) shutdown during, the inductance peak detection logic circuit 121 is detected inductive current；DescribedDuring NMOS power switch (NMOS shown in Fig. 1) is connected and the PMOS power switch (PMOS shown in Fig. 1) turns off,The inductor valley detection logic circuit 122 is detected inductive current.
Described second or door 123 output end be the inductance peak-to-valley value logic control circuit 120 output end.Current limlitingLogic export OCP be peak value current limliting logic POCP and valley current limliting logic VOCP logic or.As long as monitor inductance short circuit orOverload, OCP will be set to logically high, force set the input S of rest-set flip-flop 12 as logic low, R is logically high, closing PMOS work(Rate switchs (PMOS shown in Fig. 1), conducting NMOS power switch (NMOS shown in Fig. 1) so that inductive current declines.MostWhole inductive current will be controlled between peak value current limliting and valley current limliting.
In this present embodiment, NMOS power switch (NMOS shown in Fig. 1) conducting starts to the valley current limlitingComparator CMP2 output from it is logically high be turned to logic low during, the valley logic circuit 122a forces the valley current limliting ratioOutput compared with device CMP2 outputs is high level.When inductive current is reduced to cut-off current or less, controls the valley current limliting and compareThe output of device CMP2 is low level.
Specifically, minimum turn-on time (Min-off-time) the control sequential such as Fig. 6 for the Cycle by Cycle that the present embodiment is usedIt is shown.Cycle by Cycle is detected by DUTY CYCLE and NMOS power switch (NMOS shown in Fig. 1) grid voltage GD_LIn DUTY CYCLE=H, (PMOS power switch (PMOS shown in Fig. 1) is connected the output VCMP of valley Current-Limiting Comparator CMP2Turned off with NMOS power switch (NMOS shown in Fig. 1)) during, pressure is preset as logically high (detected in normal valley current limlitingWhen, it is logically high to show that inductive current has been more than valley current limliting).And in DUTY CYCLE=L, (NMOS power switch is (shown in Fig. 1NMOS) conducting and PMOS power switch (PMOS shown in Fig. 1) shutdown) after, just discharge to valley Current-Limiting ComparatorCMP2 exports the pressure control of VCMP, so that it is started normal valley current limliting and judges.When basic Cycle by Cycle valley current limliting detectsSequence from DUTY CYCLE are logically high as shown in fig. 6, be turned to logic low, i.e. NMOS power switch (NMOS shown in Fig. 1) is ledThe beginning is opened up, to valley Current-Limiting Comparator CMP2 outputs from the logically high this period for being turned to logic low, valley current limliting is forced to be patrolledIt is height to collect VOCP so that it is logically high that rest-set flip-flop 12, which exports R, and S is logic low, and holding NMOS power switch is (shown in Fig. 1NMOS it) is connected.
If inductive current is less than valley current limliting at this time, after a valley Current-Limiting Comparator CMP2 operating lag,It exports VCMP and becomes logic low, and then valley current limliting logic VOCP is made to become logic low, discharge the control for PWM loops.If at this timeInductive current is higher than valley current limliting, then is only reduced to cut-off current hereinafter, the CMP2 outputs of valley Current-Limiting Comparator in inductive currentLogic VCMP just becomes logic low, and otherwise valley current limliting logic VOCP will control rest-set flip-flop 12 and input S maintenance logic lows and R maintenancesIt is logically high, pressure make NMOS power switch (NMOS shown in Fig. 1) conducting until inductive current be reduced to valley current limliting hereinafter,Realize the Cycle by Cycle Min-off-time controls comprising valley current limliting information.Fig. 7 is used to be produced from for what the present embodiment was usedTurn-on time (Ton) comparator control of turn-on time is adapted to, output logic Vrset is in stable state as reset rest-set flip-flop 12One of control condition of output.
The input/output control circuit 10 of BUCK converters 1 realizes answering for from 0% to 100% duty ratio in the present inventionWith.VOUT=0.5V-3.4V is exported, answering for IOUT=0A-3A is loaded in input VIN=2.5V-5.5V by simulating, verifyingIn the case of, BUCK converters 1 can keep fast transient response possessed by ACOT frameworks always, and short in load transmissionWhen the exception of road, BUCK converters 1 also can by inductive current stablize be limited between peak value and valley reach wide scope input it is defeatedThe purpose gone out.
In conclusion the BUCK converters in the present invention can keep fast transient possessed by ACOT frameworks to ring alwaysAnswer, and load send short circuit it is abnormal when, BUCK converters inductive current can also be stablized be limited in peak value and valley itBetween, achieve the purpose that wide scope input and output, and can be promoted to greatest extent BUCK converters transient response performance andSecurity reliability extends practical ranges.So the present invention effectively overcomes various shortcoming in the prior art and has heightIndustrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripeThe personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.CauseThis, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such asAt all equivalent modifications or change, should by the present invention claim be covered.