技术领域technical field
本发明涉及半导体器件设计及制造领域，特别涉及一种集成电路转接板及其制备方法。The invention relates to the field of design and manufacture of semiconductor devices, in particular to an integrated circuit adapter board and a preparation method thereof.
背景技术Background technique
目前为止集成电路的特征尺寸已经低至7nm，在单个芯片上集成的晶体管数量已经到达百亿级别，伴随百亿级别的晶体管数量的要求，片上资源和互连线长度问题成为现今集成电路领域发展的瓶颈，3D集成电路被认为是未来集成电路的发展方向，它原有电路的基础上，在Z轴上层叠，以求在最小的面积上集成更多的功能，这种方法克服了原有集成度的限制，采用新兴技术硅片通孔(Through Silicon Vias，简称TSV)，大幅度的提高了集成电路的性能，降低线上延迟，减小芯片功耗。So far, the feature size of integrated circuits has been as low as 7nm, and the number of transistors integrated on a single chip has reached tens of billions. With the requirement of tens of billions of transistors, the problem of on-chip resources and the length of interconnection lines has become the development of today's integrated circuit field. The bottleneck of 3D integrated circuits is considered to be the development direction of future integrated circuits. On the basis of the original circuit, it is stacked on the Z axis in order to integrate more functions in the smallest area. This method overcomes the original Due to the limitation of integration level, the emerging technology of Through Silicon Vias (TSV for short) is adopted, which greatly improves the performance of integrated circuits, reduces online delay, and reduces chip power consumption.
在半导体行业里面，随着集成电路集成度的提高以及器件特征尺寸的减小，集成电路中静电放电引起的潜在性损坏已经变得越来越明显。据有关报道，集成电路领域的故障中有近35％的故障是由静电释放(Electro-Static discharge，简称ESD)所引发的，因此芯片内部都设计有ESD保护结构来提高器件的可靠性。然而不同芯片的的抗静电能力不同，在三维堆叠时抗静电能力弱的芯片会影响到封装后整个系统的抗静电能力，因此如何提高基于TSV工艺的3D集成电路的抗静电能力成为半导体行业亟待解决的问题。In the semiconductor industry, with the increase of integrated circuit integration and the reduction of device feature size, the potential damage caused by electrostatic discharge in integrated circuits has become more and more obvious. According to related reports, nearly 35% of the faults in the field of integrated circuits are caused by Electro-Static discharge (ESD). Therefore, ESD protection structures are designed inside the chip to improve the reliability of the device. However, different chips have different antistatic capabilities. Chips with weak antistatic capabilities during three-dimensional stacking will affect the antistatic capabilities of the entire system after packaging. Therefore, how to improve the antistatic capabilities of 3D integrated circuits based on TSV technology has become an urgent need in the semiconductor industry. solved problem.
发明内容Contents of the invention
为解决现有技术存在的技术缺陷和不足，本发明提出一种集成电路转接板及其制备方法。该制备方法包括：In order to solve the technical defects and deficiencies existing in the prior art, the present invention proposes an integrated circuit adapter board and a preparation method thereof. The preparation method includes:
(a)选取硅基衬底；(a) selecting a silicon-based substrate;
(b)在所述硅基衬底上制作TSV孔、隔离沟槽及器件沟槽，其中，所述隔离沟槽位于所述TSV孔与所述器件沟槽之间；(b) making a TSV hole, an isolation trench, and a device trench on the silicon-based substrate, wherein the isolation trench is located between the TSV hole and the device trench;
(c)利用二氧化硅材料填充所述隔离沟槽；(c) filling the isolation trenches with a silicon dioxide material;
(d)利用多晶硅材料填充所述TSV孔，并引入掺杂气体对所述多晶硅材料进行原位掺杂；(d) filling the TSV hole with a polysilicon material, and introducing a dopant gas to perform in-situ doping on the polysilicon material;
(e)在所述器件沟槽中制作二极管；(e) fabricating a diode in the device trench;
(f)在所述多晶硅材料上表面及所述二极管的阳极表面制作金属互连线以使所述多晶硅材料与所述二极管相连接；(f) making a metal interconnection line on the upper surface of the polysilicon material and the anode surface of the diode so that the polysilicon material is connected to the diode;
(g)去除所述硅基衬底底部部分材料，使所述硅基衬底底部露出所述TSV孔与所述隔离沟槽；(g) removing part of the material at the bottom of the silicon-based substrate, exposing the TSV hole and the isolation trench at the bottom of the silicon-based substrate;
(h)在所述多晶硅材料与所述N型区域底部制作铜凸点。(h) making copper bumps on the polysilicon material and the bottom of the N-type region.
在本发明的一个实施例中，步骤(b)包括：In one embodiment of the invention, step (b) includes:
(b1)利用热氧化工艺，在所述硅基衬底上生长二氧化硅层；(b1) using a thermal oxidation process to grow a silicon dioxide layer on the silicon-based substrate;
(b2)利用光刻工艺，在所述二氧化硅层上制作第一待刻蚀区域、第二待刻蚀区域及第三待刻蚀区域；(b2) using a photolithography process to form a first region to be etched, a second region to be etched and a third region to be etched on the silicon dioxide layer;
(b3)利用深度反应离子刻蚀工艺，在所述第一待刻蚀区域、所述第二待刻蚀区域及所述第三待刻蚀区域刻蚀所述硅基衬底，分别形成所述TSV孔、所述隔离沟槽及所述器件沟槽。(b3) Etching the silicon-based substrate in the first to-be-etched region, the second to-be-etched region, and the third to-be-etched region by using a deep reactive ion etching process to respectively form the The TSV hole, the isolation trench and the device trench.
在本发明的一个实施例中，在步骤(c)之前还包括：In one embodiment of the present invention, before step (c), also include:
(x1)利用热氧化工艺，在所述TSV孔、所述隔离沟槽及所述器件沟槽的内壁形成氧化层；(x1) forming an oxide layer on the inner walls of the TSV hole, the isolation trench, and the device trench by using a thermal oxidation process;
(x2)利用湿法刻蚀工艺，选择性刻蚀所述氧化层以使所述TSV孔、所述隔离沟槽及所述器件沟槽的内壁平整。(x2) Using a wet etching process, selectively etching the oxide layer to make inner walls of the TSV hole, the isolation trench and the device trench flat.
在本发明的一个实施例中，步骤(c)包括：In one embodiment of the invention, step (c) comprises:
(c1)利用光刻工艺，在所述硅基衬底表面形成隔离沟槽填充区域；(c1) forming an isolation trench filling region on the surface of the silicon-based substrate by using a photolithography process;
(c2)利用化学气相淀积工艺，通过所述隔离沟槽填充区域在所述隔离沟槽内淀积二氧化硅。(c2) Depositing silicon dioxide in the isolation trench through the isolation trench filling region by using a chemical vapor deposition process.
在本发明的一个实施例中，步骤(d)包括：In one embodiment of the invention, step (d) includes:
(d1)利用光刻工艺，在所述硅基衬底表面形成TSV孔填充区域；(d1) forming a TSV hole filling region on the surface of the silicon-based substrate by using a photolithography process;
(d2)利用化学气相淀积工艺，通过所述TSV孔填充区域在所述TSV孔内淀积多晶硅材料，并引入掺杂气体对所述多晶硅材料进行原位掺杂。(d2) Depositing a polysilicon material in the TSV hole through the TSV hole filling region by using a chemical vapor deposition process, and introducing a doping gas to perform in-situ doping on the polysilicon material.
在本发明的一个实施例中，步骤(e)包括：In one embodiment of the invention, step (e) includes:
(e1)利用光刻工艺，在所述硅基衬底表面形成器件沟槽填充区域；(e1) forming a device trench filling region on the surface of the silicon-based substrate by using a photolithography process;
(e2)利用CVD工艺与离子掺杂工艺，通过所述器件沟槽填充区域在所述器件沟槽底部淀积厚度为20μm～40μm、掺杂浓度为5×1018cm-3的N+区；(e2) Depositing an N+ region with a thickness of 20 μm to 40 μm and a doping concentration of 5×1018 cm−3 at the bottom of the device trench through the device trench filling region by using a CVD process and an ion doping process;
(e3)利用CVD工艺与离子掺杂工艺，通过所述器件沟槽填充区域在所述N+区上淀积厚度为40μm～80μm、掺杂浓度为2×1014cm-3的N-区；(e3) Depositing an N- region with a thickness of 40 μm to 80 μm and a doping concentration of 2×1014 cm−3 on the N+ region through the device trench filling region by using a CVD process and an ion doping process;
(e4)利用CVD工艺与离子掺杂工艺，通过所述器件沟槽填充区域在所述N-区上淀积厚度为20μm～40μm、掺杂浓度为5×1018cm-3的P+区，其中，所述N+区、所述N-区及所述P+区形成所述二极管。(e4) Depositing a P+ region with a thickness of 20 μm to 40 μm and a doping concentration of 5×1018 cm−3 on the N- region through the device trench filling region by using a CVD process and an ion doping process, Wherein, the N+ region, the N- region and the P+ region form the diode.
在本发明的另一个实施例中，步骤(f)包括：In another embodiment of the present invention, step (f) includes:
(f1)在所述多晶硅材料与所述P+区表面制作上钨插塞；(f1) making an upper tungsten plug on the surface of the polysilicon material and the P+ region;
(f2)在所述上钨插塞表面制作所述金属互连线以使所述多晶硅材料与所述二极管相连接。(f2) forming the metal interconnection line on the surface of the upper tungsten plug to connect the polysilicon material to the diode.
在本发明的一个实施例中，步骤(g)包括：In one embodiment of the invention, step (g) comprises:
(g1)利用机械磨削工艺，去除所述硅基衬底下部部分材料；(g1) using a mechanical grinding process to remove the material at the lower part of the silicon-based substrate;
(g2)利用化学机械抛光工艺，对所述硅基衬底下表面进行平整化处理，使所述硅基衬底底部露出所述TSV孔、所述隔离沟槽及所述N+区。(g2) Using a chemical mechanical polishing process to planarize the lower surface of the silicon-based substrate, so that the bottom of the silicon-based substrate exposes the TSV hole, the isolation trench and the N+ region.
在本发明的一个实施例中，步骤(h)包括：In one embodiment of the invention, step (h) comprises:
(h1)在所述多晶硅材料与所述N+区下表面制作下钨插塞；(h1) making a lower tungsten plug on the lower surface of the polysilicon material and the N+ region;
(h2)在所述下钨插塞表面制作所述铜凸点。(h2) forming the copper bumps on the surface of the lower tungsten plug.
在本发明的另一个实施例中，提供了一种集成电路转接板，该集成电路转接板包括硅基衬底、TSV孔、隔离槽、二极管、钨插塞、金属互连线、铜凸点及隔离层；其中，所述集成电路转接板由上述任一项所述的方法制备形成。In another embodiment of the present invention, an integrated circuit interposer is provided. The integrated circuit interposer includes a silicon substrate, TSV holes, isolation grooves, diodes, tungsten plugs, metal interconnections, copper Bumps and isolation layers; wherein, the integrated circuit adapter board is prepared by any one of the methods described above.
与现有技术相比，本发明至少具有以下有益效果：Compared with the prior art, the present invention has at least the following beneficial effects:
1、本发明提供的集成电路转接板的制备工艺，其工艺步骤简单，可行性高；1. The preparation process of the integrated circuit adapter board provided by the present invention has simple process steps and high feasibility;
2、本发明提供的集成电路转接板，通过在TSV转接板上加工ESD防护器件——二极管，增强了层叠封装芯片的抗静电能力；此外，上述二极管周围采用上下贯通的隔离沟槽，具有较小的漏电流和寄生电容。2. The integrated circuit adapter board provided by the present invention enhances the antistatic ability of stacked packaging chips by processing the ESD protection device—diode on the TSV adapter board; in addition, the above-mentioned diodes are surrounded by isolation grooves that penetrate up and down, Has a small leakage current and parasitic capacitance.
附图说明Description of drawings
下面将结合附图，对本发明的具体实施方式进行详细的说明。The specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings.
图1为本发明实施例提供的一种集成电路转接板的制备方法流程图；Fig. 1 is a flow chart of a method for preparing an integrated circuit adapter board provided by an embodiment of the present invention;
图2a-图2i为本发明实施例提供的一种集成电路转接板的制备方法示意图；2a-2i are schematic diagrams of a method for preparing an integrated circuit adapter board provided by an embodiment of the present invention;
图3为本发明实施例提供的一种集成电路转接板的结构示意图。FIG. 3 is a schematic structural diagram of an integrated circuit adapter board provided by an embodiment of the present invention.
具体实施方式Detailed ways
下面结合具体实施例对本发明做进一步详细的描述，但本发明的实施方式不限于此。The present invention will be described in further detail below in conjunction with specific examples, but the embodiments of the present invention are not limited thereto.
实施例一Embodiment one
请参见图1，图1为本发明实施例提供的一种集成电路转接板的制备方法流程图，该制备方法包括：Please refer to FIG. 1. FIG. 1 is a flow chart of a method for preparing an integrated circuit adapter board provided by an embodiment of the present invention. The method includes:
(a)选取硅基衬底；(a) selecting a silicon-based substrate;
(b)在所述硅基衬底上制作TSV孔、隔离沟槽及器件沟槽，其中，所述隔离沟槽位于所述TSV孔与所述器件沟槽之间；(b) making a TSV hole, an isolation trench, and a device trench on the silicon-based substrate, wherein the isolation trench is located between the TSV hole and the device trench;
(c)利用二氧化硅材料填充所述隔离沟槽；(c) filling the isolation trenches with a silicon dioxide material;
(d)利用多晶硅材料填充所述TSV孔，并引入掺杂气体对所述多晶硅材料进行原位掺杂；(d) filling the TSV hole with a polysilicon material, and introducing a dopant gas to perform in-situ doping on the polysilicon material;
(e)在所述器件沟槽中制作二极管；(e) fabricating a diode in the device trench;
(f)在所述多晶硅材料上表面及所述二极管的阳极表面制作金属互连线以使所述多晶硅材料与所述二极管相连接；(f) making a metal interconnection line on the upper surface of the polysilicon material and the anode surface of the diode so that the polysilicon material is connected to the diode;
(g)去除所述硅基衬底底部部分材料，使所述硅基衬底底部露出所述TSV孔与所述隔离沟槽；(g) removing part of the material at the bottom of the silicon-based substrate, exposing the TSV hole and the isolation trench at the bottom of the silicon-based substrate;
(h)在所述多晶硅材料与所述N型区域底部制作铜凸点。(h) making copper bumps on the polysilicon material and the bottom of the N-type region.
优选地，所述硅基衬底的晶向可以是(100)或者(110)或者(111)，此处不做任何限制，另外，衬底的掺杂类型可以为N型，也可以是为P型，掺杂浓度例如为1014～1017cm-3，厚度例如为450～550μm。Preferably, the crystal orientation of the silicon-based substrate may be (100) or (110) or (111), without any limitation here. In addition, the doping type of the substrate may be N-type, or For P type, the doping concentration is, for example, 1014 to 1017 cm-3 , and the thickness is, for example, 450 to 550 μm.
进一步地，在上述实施例的基础上，步骤(b)包括：Further, on the basis of the foregoing embodiments, step (b) includes:
(b1)在1050℃～1100℃温度下，利用热氧化工艺，在所述硅基衬底上生长厚度为800nm～1000nm二氧化硅层；(b1) growing a silicon dioxide layer with a thickness of 800 nm to 1000 nm on the silicon-based substrate by using a thermal oxidation process at a temperature of 1050°C to 1100°C;
(b2)利用光刻工艺，在所述二氧化硅层上制作第一待刻蚀区域、第二待刻蚀区域及第三待刻蚀区域；(b2) using a photolithography process to form a first region to be etched, a second region to be etched and a third region to be etched on the silicon dioxide layer;
(b3)利用深度反应离子刻蚀工艺，在所述第一待刻蚀区域、所述第二待刻蚀区域及所述第三待刻蚀区域刻蚀所述硅基衬底，分别形成所述TSV孔、所述隔离沟槽及所述器件沟槽。(b3) Etching the silicon-based substrate in the first to-be-etched region, the second to-be-etched region, and the third to-be-etched region by using a deep reactive ion etching process to respectively form the The TSV hole, the isolation trench and the device trench.
进一步地，在上述实施例的基础上，在步骤(c)之前还包括：Further, on the basis of the foregoing embodiments, before step (c), it also includes:
(x1)在1050℃～1100℃温度下，利用热氧化工艺，在所述TSV孔、所述隔离沟槽及所述器件沟槽的内壁形成厚度为200nm～300nm的氧化层；(x1) using a thermal oxidation process at a temperature of 1050°C to 1100°C to form an oxide layer with a thickness of 200nm to 300nm on the inner walls of the TSV hole, the isolation trench, and the device trench;
(x2)利用湿法刻蚀工艺，选择性刻蚀所述氧化层以使所述TSV孔、所述隔离沟槽及所述器件沟槽的内壁平整。该步骤是为了防止TSV孔、所述隔离沟槽及所述器件沟槽侧壁的突起形成电场集中区域。(x2) Using a wet etching process, selectively etching the oxide layer to make inner walls of the TSV hole, the isolation trench and the device trench flat. This step is to prevent the TSV hole, the isolation trench and the protrusion of the side wall of the device trench from forming an electric field concentration area.
进一步地，在上述实施例的基础上，步骤(c)包括：Further, on the basis of the foregoing embodiments, step (c) includes:
(c1)利用光刻工艺，在所述硅基衬底表面形成隔离沟槽填充区域；(c1) forming an isolation trench filling region on the surface of the silicon-based substrate by using a photolithography process;
(c2)在690℃～710℃温度下，利用化学气相淀积工艺，通过所述隔离沟槽填充区域在所述隔离沟槽内淀积二氧化硅。在本步骤中，二氧化硅主要起隔离器件的作用，也可用其他隔离材料代替。(c2) Depositing silicon dioxide in the isolation trench through the filling region of the isolation trench by using a chemical vapor deposition process at a temperature of 690° C. to 710° C. In this step, silicon dioxide mainly functions as an isolation device, and other isolation materials can also be used instead.
进一步地，在上述实施例的基础上，步骤(d)包括：Further, on the basis of the foregoing embodiments, step (d) includes:
(d1)利用光刻工艺，在所述硅基衬底表面形成TSV孔填充区域；(d1) forming a TSV hole filling region on the surface of the silicon-based substrate by using a photolithography process;
(d2)在600～620℃温度下，利用化学气相淀积工艺，在所述TSV孔填充区域淀积多晶硅材料以对所述TSV孔进行填充，并引入掺杂气体以对所述多晶硅材料进行原位掺杂；其中，多晶硅材料掺杂浓度优选为2×1021cm-3，掺杂杂质优选磷。本步骤的目的是为了在TSV孔中形成杂质分布均匀、且高掺杂浓度的导电材料填充，利于减小TSV孔的电阻。(d2) at a temperature of 600-620° C., using a chemical vapor deposition process, deposit polysilicon material in the TSV hole filling region to fill the TSV hole, and introduce a doping gas to treat the polysilicon material. In-situ doping; wherein, the doping concentration of the polysilicon material is preferably 2×1021 cm-3 , and the doping impurity is preferably phosphorus. The purpose of this step is to fill the TSV holes with uniform impurity distribution and high doping concentration of conductive material, which is beneficial to reduce the resistance of the TSV holes.
进一步地，在上述实施例的基础上，步骤(e)包括：Further, on the basis of the foregoing embodiments, step (e) includes:
(e1)利用光刻工艺，在所述硅基衬底表面形成器件沟槽填充区域；(e1) forming a device trench filling region on the surface of the silicon-based substrate by using a photolithography process;
(e2)利用CVD工艺与离子掺杂工艺，通过所述器件沟槽填充区域在所述器件沟槽底部淀积厚度为20μm～40μm、掺杂浓度为5×1018cm-3的N+区；(e2) Depositing an N+ region with a thickness of 20 μm to 40 μm and a doping concentration of 5×1018 cm−3 at the bottom of the device trench through the device trench filling region by using a CVD process and an ion doping process;
(e3)利用CVD工艺与离子掺杂工艺，通过所述器件沟槽填充区域在所述N+区上淀积厚度为40μm～80μm、掺杂浓度为2×1014cm-3的N-区；(e3) Depositing an N- region with a thickness of 40 μm to 80 μm and a doping concentration of 2×1014 cm−3 on the N+ region through the device trench filling region by using a CVD process and an ion doping process;
(e4)利用CVD工艺与离子掺杂工艺，通过所述器件沟槽填充区域在所述N-区上淀积厚度为20μm～40μm、掺杂浓度为5×1018cm-3的P+区。(e4) Depositing a P+ region with a thickness of 20 μm to 40 μm and a doping concentration of 5×1018 cm−3 on the N − region through the device trench filling region by using a CVD process and an ion doping process.
其中，所述N+区、所述N-区及所述P+区形成所述二极管。Wherein, the N+ region, the N- region and the P+ region form the diode.
进一步地，在上述实施例的基础上，步骤(f)包括：Further, on the basis of the foregoing embodiments, step (f) includes:
(f1)在所述多晶硅材料与所述P+区表面制作上钨插塞；(f1) making an upper tungsten plug on the surface of the polysilicon material and the P+ region;
(f2)在所述上钨插塞表面制作所述金属互连线以使所述多晶硅材料与所述二极管相连接。(f2) forming the metal interconnection line on the surface of the upper tungsten plug to connect the polysilicon material to the diode.
进一步地，在上述实施例的基础上，步骤(g)包括：Further, on the basis of the foregoing embodiments, step (g) includes:
(g1)利用机械磨削工艺，去除所述硅基衬底下部部分材料；剩余部分的硅基衬底的厚度略大于目标尺寸10μm；(g1) Using a mechanical grinding process to remove the lower part of the silicon-based substrate material; the thickness of the remaining silicon-based substrate is slightly greater than the target size of 10 μm;
(g2)利用化学机械抛光工艺，对所述硅基衬底下表面进行平整化处理，使所述硅基衬底底部露出所述TSV孔、所述隔离沟槽及所述N+区。经该步骤处理后，硅基衬底的厚度达到目标厚度，优选为80μm～120μm。(g2) Using a chemical mechanical polishing process to planarize the lower surface of the silicon-based substrate, so that the bottom of the silicon-based substrate exposes the TSV hole, the isolation trench and the N+ region. After this step, the thickness of the silicon-based substrate reaches the target thickness, preferably 80 μm˜120 μm.
进一步地，在上述实施例的基础上，步骤(h)包括：Further, on the basis of the foregoing embodiments, step (h) includes:
(h1)在所述多晶硅材料与所述N+区下表面制作下钨插塞；(h1) making a lower tungsten plug on the lower surface of the polysilicon material and the N+ region;
(h2)在所述下钨插塞表面制作所述铜凸点。(h2) forming the copper bumps on the surface of the lower tungsten plug.
本实施例提供的集成电路转接板，通过在TSV转接板上加工二极管作为ESD防护器件，增强了层叠封装芯片的抗静电能力；另外，上述二极管周围采用上下贯通的隔离沟槽，具有较小的漏电流和寄生电容。The integrated circuit adapter board provided in this embodiment enhances the antistatic capability of stacked package chips by processing diodes on the TSV adapter board as ESD protection devices; in addition, the upper and lower through-through isolation trenches are used around the above diodes, which has a relatively Small leakage current and parasitic capacitance.
实施例二Embodiment two
请参照图2a-图2i，图2a-图2i为本发明实施例提供的一种集成电路转接板的制备方法示意图，该制备方法包括如下步骤：Please refer to Figure 2a-Figure 2i, Figure 2a-Figure 2i is a schematic diagram of a preparation method of an integrated circuit adapter board provided by an embodiment of the present invention, the preparation method includes the following steps:
第1步、选取硅基衬底21；所述硅基衬底21的晶向可以是(100)或者(110)或者(111)，此处不做任何限制，另外，衬底的掺杂类型可以为N型，也可以是为P型，掺杂浓度例如为1014～1017cm-3，厚度例如为450～550μm。如图2a所示。Step 1, select the silicon-based substrate 21; the crystal orientation of the silicon-based substrate 21 can be (100) or (110) or (111), without any limitation here, in addition, the doping type of the substrate It can be N-type or P-type, the doping concentration is, for example, 1014 -1017 cm-3, and the thickness is, for example, 450-550 μm. As shown in Figure 2a.
第2步、在1050℃～1100℃温度下，利用热氧化工艺，在所述硅基衬底21上生长厚度为800nm～1000nm二氧化硅层；利用光刻工艺，在所述二氧化硅层上制作第一待刻蚀区域、第二待刻蚀区域及第三待刻蚀区域；利用深度反应离子刻蚀工艺，在所述第一待刻蚀区域、所述第二待刻蚀区域及所述第三待刻蚀区域刻蚀所述硅基衬底21，分别形成所述TSV孔22、所述隔离沟槽23及所述隔离沟槽24，如图2b所示。Step 2: At a temperature of 1050°C to 1100°C, use a thermal oxidation process to grow a silicon dioxide layer with a thickness of 800nm to 1000nm on the silicon-based substrate 21; Fabricate a first region to be etched, a second region to be etched and a third region to be etched; using a deep reactive ion etching process, in the first region to be etched, the second region to be etched and the The silicon-based substrate 21 is etched in the third region to be etched to form the TSV hole 22 , the isolation trench 23 and the isolation trench 24 , as shown in FIG. 2 b .
第3步、在1050℃～1100℃温度下，利用热氧化工艺，在所述TSV孔22、所述隔离沟槽23及所述隔离沟槽24的内壁形成氧化层；利用湿法刻蚀工艺，选择性刻蚀所述氧化层以使所述TSV孔22、所述隔离沟槽23及所述隔离沟槽24的内壁平整，如图2c所示。该步骤是为了防止TSV孔22、所述隔离沟槽23及所述隔离沟槽24侧壁的突起形成电场集中区域。Step 3: Form an oxide layer on the inner walls of the TSV hole 22, the isolation trench 23, and the isolation trench 24 by using a thermal oxidation process at a temperature of 1050° C. to 1100° C.; use a wet etching process , selectively etching the oxide layer to make inner walls of the TSV hole 22 , the isolation trench 23 and the isolation trench 24 flat, as shown in FIG. 2 c . This step is to prevent the TSV hole 22 , the protrusions on the sidewalls of the isolation trench 23 and the isolation trench 24 from forming an electric field concentration area.
第4步、利用光刻工艺，在所述硅基衬底21表面形成隔离沟槽23填充区域；在690℃～710℃温度下，利用化学气相淀积工艺，通过所述隔离沟槽23填充区域在所述隔离沟槽23内淀积二氧化硅。在本步骤中，二氧化硅主要起隔离器件的作用，也可用其他隔离材料代替，如图2d所示。Step 4: Using a photolithography process, form an isolation trench 23 filling area on the surface of the silicon-based substrate 21; at a temperature of 690°C to 710°C, use a chemical vapor deposition process to fill the area through the isolation trench 23 Silicon dioxide is deposited in the isolation trench 23. In this step, silicon dioxide mainly plays the role of isolating devices, and can also be replaced by other isolating materials, as shown in Figure 2d.
第5步、利用光刻工艺，在所述硅基衬底21表面形成TSV孔22填充区域；在600～620℃温度下，利用化学气相淀积工艺，在所述TSV孔22填充区域淀积多晶硅材料以对所述TSV孔22进行填充，并引入掺杂气体以对所述多晶硅材料进行原位掺杂；其中，多晶硅材料掺杂浓度优选为2×1021cm-3，掺杂杂质优选磷。本步骤的目的是为了在TSV孔22中形成杂质分布均匀、且高掺杂浓度的导电材料填充，利于减小TSV孔22的电阻，如图2e所示。Step 5: Form a TSV hole 22 filling area on the surface of the silicon-based substrate 21 by photolithography; at a temperature of 600-620° C., use a chemical vapor deposition process to deposit Polysilicon material is used to fill the TSV hole 22, and doping gas is introduced to perform in-situ doping on the polysilicon material; wherein, the doping concentration of the polysilicon material is preferably 2×1021 cm-3 , and the doping impurities are preferably phosphorus. The purpose of this step is to fill the TSV hole 22 with uniform impurity distribution and high doping concentration of conductive material, which is beneficial to reduce the resistance of the TSV hole 22 , as shown in FIG. 2 e .
第6步、利用光刻工艺，在所述硅基衬底21表面形成隔离沟槽24填充区域；利用CVD工艺与离子掺杂工艺，通过所述隔离沟槽24填充区域在所述隔离沟槽24底部淀积厚度为20μm～40μm、掺杂浓度为5×1018cm-3的N+区25；利用CVD工艺与离子掺杂工艺，通过所述隔离沟槽24填充区域在所述N+区上淀积厚度为40μm～80μm、掺杂浓度为2×1014cm-3的N-区26；利用CVD工艺与离子掺杂工艺，通过所述隔离沟槽24填充区域在所述N-区上淀积厚度为20μm～40μm、掺杂浓度为5×1018cm-3的P+区27。其中，所述N+区25、所述N-区26及所述P+区27形成所述二极管，如图2f所示。Step 6: Form the filling area of the isolation trench 24 on the surface of the silicon-based substrate 21 by photolithography; use the CVD process and the ion doping process to form the filling area of the isolation trench 24 in the isolation trench Deposit the N+ region 25 at the bottom of 24 with a thickness of 20 μm to 40 μm and a doping concentration of 5×1018 cm−3 ; use the CVD process and ion doping process to fill the region on the N+ region through the isolation trench 24 Depositing an N-region 26 with a thickness of 40 μm to 80 μm and a doping concentration of 2×1014 cm−3 ; using CVD technology and ion doping technology, filling the region on the N-region through the isolation trench 24 A P+ region 27 with a thickness of 20 μm˜40 μm and a doping concentration of 5×1018 cm−3 is deposited. Wherein, the N+ region 25, the N-region 26 and the P+ region 27 form the diode, as shown in FIG. 2f.
第7步、在所述多晶硅材料与所述P+区27表面制作上钨插塞28；在所述上钨插塞28表面制作所述金属互连线29以使所述多晶硅材料与所述二极管相连接，如图2g所示；其中，同时可利用金属互连线围绕成螺旋状而使其具有电感的特性以更好用于射频集成电路的静电防护。Step 7, making an upper tungsten plug 28 on the surface of the polysilicon material and the P+ region 27; making the metal interconnection line 29 on the surface of the upper tungsten plug 28 so that the polysilicon material and the diode are connected, as shown in FIG. 2g; wherein, at the same time, metal interconnection wires can be used to wrap around in a spiral shape to make it have an inductive characteristic, so as to be better used for electrostatic protection of radio frequency integrated circuits.
第8步、利用机械磨削工艺，去除所述硅基衬底21下部部分材料；剩余部分的硅基衬底21的厚度略大于目标尺寸10μm；利用化学机械抛光工艺，对所述硅基衬底21下表面进行平整化处理，使所述硅基衬底21底部露出所述TSV孔22、所述隔离沟槽23及所述N+区25。经该步骤处理后，硅基衬底21的厚度达到目标厚度，优选为80μm～120μm，如图2h所示。Step 8, using mechanical grinding process, remove the material of the lower part of the silicon base substrate 21; the thickness of the remaining part of the silicon base substrate 21 is slightly larger than the target size of 10 μm; using chemical mechanical polishing process, the silicon base substrate 21 The lower surface of the bottom 21 is planarized, so that the bottom of the silicon-based substrate 21 exposes the TSV hole 22 , the isolation trench 23 and the N+ region 25 . After this step, the thickness of the silicon-based substrate 21 reaches the target thickness, preferably 80 μm˜120 μm, as shown in FIG. 2h.
第9步、在所述多晶硅材料与所述N+区25下表面制作下钨插塞30；在所述下钨插塞30表面制作所述铜凸点31，如图2i所示。Step 9: Fabricate a lower tungsten plug 30 on the lower surface of the polysilicon material and the N+ region 25; fabricate the copper bump 31 on the surface of the lower tungsten plug 30, as shown in FIG. 2i.
需要说明的是，隔离沟槽是为了隔断二极管与转接板中其他结构的连接，故隔离沟槽可以制作为封闭结构(例如环状结构)并贯穿衬底材料，二极管位于该封闭结构内部。It should be noted that the isolation trench is to isolate the connection between the diode and other structures in the adapter board, so the isolation trench can be made as a closed structure (such as a ring structure) and penetrate the substrate material, and the diode is located inside the closed structure.
实施例三Embodiment three
请参照图3，图3为本发明实施例提供的一种集成电路转接板的结构示意图。该集成电路转接板采用上述实施例所述的制备方法制备形成。具体地，所述集成电路转接板包括：硅基衬底31、TSV孔32、隔离槽33、二极管34、钨插塞35、金属互连线36、铜凸点37及隔离层38；其中，TSV孔32中填充多晶硅材料，隔离槽33中填充二氧化硅材料。Please refer to FIG. 3 . FIG. 3 is a schematic structural diagram of an integrated circuit adapter board provided by an embodiment of the present invention. The integrated circuit adapter board is prepared by the preparation method described in the above embodiments. Specifically, the integrated circuit adapter board includes: a silicon-based substrate 31, a TSV hole 32, an isolation groove 33, a diode 34, a tungsten plug 35, a metal interconnection line 36, a copper bump 37, and an isolation layer 38; , the TSV hole 32 is filled with polysilicon material, and the isolation groove 33 is filled with silicon dioxide material.
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
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| CN201711351066.5ACN108321145A (en) | 2017-12-15 | 2017-12-15 | Integral circuit keyset and preparation method thereof |
| Application Number | Priority Date | Filing Date | Title |
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| CN201711351066.5ACN108321145A (en) | 2017-12-15 | 2017-12-15 | Integral circuit keyset and preparation method thereof |
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| CN108321145Atrue CN108321145A (en) | 2018-07-24 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201711351066.5APendingCN108321145A (en) | 2017-12-15 | 2017-12-15 | Integral circuit keyset and preparation method thereof |
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| CN (1) | CN108321145A (en) |
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