技术领域technical field
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置、薄膜晶体管的制备方法。The invention relates to the field of display technology, in particular to an array substrate and a preparation method thereof, a display device, and a preparation method of a thin film transistor.
背景技术Background technique
目前，常将栅极驱动电路(Gate On Array，简称GOA)制作在阵列基板上，这样不仅可以减少制作程序，降低成本，且由于不需要栅极驱动芯片(Integrate Circuit，简称IC)，因而可以提高阵列基板的集成度。At present, the gate drive circuit (Gate On Array, GOA for short) is often manufactured on the array substrate, which can not only reduce the production process, but also reduce the cost, and because the gate drive chip (Integrate Circuit, short for IC) is not required, it can The integration degree of the array substrate is improved.
现有技术中，栅极驱动电路包括电容和薄膜晶体管(Thin Film Transistor，简称TFT)，通过设置在GOA区(设置栅极驱动电路的区域)的电容和薄膜晶体管来控制显示区域(A-A区)的栅线(Gate)逐行扫描。其中，如图1(a)所示，GOA区包括层叠设置在衬底基板10上的第一金属图案201、第一绝缘图案301和第二金属图案401，通过第一金属图案201和第二金属图案401形成电容。如图1(b)所示，GOA区的电容C＝C1。In the prior art, the gate drive circuit includes capacitors and thin film transistors (Thin Film Transistor, TFT for short), and the display area (A-A area) is controlled by the capacitors and thin film transistors arranged in the GOA area (the area where the gate drive circuit is installed) The grid lines (Gate) are scanned line by line. Wherein, as shown in FIG. 1(a), the GOA region includes a first metal pattern 201, a first insulating pattern 301, and a second metal pattern 401 stacked on the base substrate 10. Through the first metal pattern 201 and the second The metal pattern 401 forms a capacitor. As shown in FIG. 1( b ), the capacitance C=C1 in the GOA region.
然而，由于GOA区中第一金属图案201和第二金属图案401形成的电容较小，因而会延长显示区域TFT的打开和关闭时间，从而影响了显示画面快速准确地输出。However, since the capacitance formed by the first metal pattern 201 and the second metal pattern 401 in the GOA area is small, the turn-on and turn-off time of the TFT in the display area will be prolonged, thereby affecting the fast and accurate output of the display image.
发明内容Contents of the invention
本发明的实施例提供一种阵列基板及其制备方法、显示装置、薄膜晶体管的制备方法，可解决GOA区设置的电容较小的问题。Embodiments of the present invention provide an array substrate and a manufacturing method thereof, a display device, and a manufacturing method of a thin film transistor, which can solve the problem of a small capacitance in the GOA region.
为达到上述目的，本发明的实施例采用如下技术方案：In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:
第一方面，提供一种阵列基板，包括显示区域和GOA区，其特征在于，所述GOA区包括依次层叠设置的半导体图案、第一绝缘图案、第一金属图案、第二绝缘图案和第二金属图案；其中，所述第一金属图案穿过所述第一绝缘图案上的过孔与所述半导体图案电连接，或者所述第二金属图案穿过所述第一绝缘图案和所述第二绝缘图案上的过孔与所述半导体图案电连接。In a first aspect, an array substrate is provided, including a display area and a GOA area, wherein the GOA area includes a semiconductor pattern, a first insulating pattern, a first metal pattern, a second insulating pattern, and a second A metal pattern; wherein, the first metal pattern is electrically connected to the semiconductor pattern through a via hole on the first insulating pattern, or the second metal pattern passes through the first insulating pattern and the first insulating pattern. The via holes on the two insulating patterns are electrically connected with the semiconductor pattern.
优选的，所述显示区域包括薄膜晶体管；所述薄膜晶体管包括依次设置的有源层图案、栅绝缘层、栅极、层间介电层和源漏极，所述源漏极穿过所述层间介电层和所述栅绝缘层上的过孔与所述有源层图案电连接；其中，所述有源层图案与所述半导体图案、所述栅绝缘层和所述第一绝缘图案、所述栅极与所述第一金属图案、所述层间介电层与所述第二绝缘图案以及所述源漏极与所述第二金属图案中的至少一组同层同材料。Preferably, the display area includes a thin film transistor; the thin film transistor includes an active layer pattern, a gate insulating layer, a gate, an interlayer dielectric layer, and a source and drain arranged in sequence, and the source and drain pass through the The interlayer dielectric layer and the via hole on the gate insulating layer are electrically connected to the active layer pattern; wherein, the active layer pattern is connected to the semiconductor pattern, the gate insulating layer and the first insulating layer. pattern, the gate and the first metal pattern, the interlayer dielectric layer and the second insulating pattern, and at least one group of the source and drain electrodes and the second metal pattern are of the same layer and the same material .
优选的，所述半导体图案为被掺杂的半导体图案。Preferably, the semiconductor pattern is a doped semiconductor pattern.
第二方面，提供一种显示装置，包括上述的阵列基板。In a second aspect, a display device is provided, including the above-mentioned array substrate.
第三方面，提供一种阵列基板的制备方法，包括：在衬底基板上形成半导体层，所述半导体层包括位于显示区域的有源层图案和位于GOA区的半导体图案；在所述半导体层上依次形成第一绝缘层、第一金属层、第二绝缘层和第二金属层；所述第一金属层包括位于所述显示区域的栅极和位于所述GOA区的第一金属图案；所述第二金属层包括位于所述显示区域的源漏极和位于所述GOA区域的第二金属图案；所述第一绝缘层包括位于所述显示区域的栅绝缘层和位于所述GOA区的第一绝缘图案；所述第二绝缘层包括位于所述显示区域的层间介电层和位于所述GOA区的第二绝缘图案；其中，所述源漏极穿过所述栅绝缘层和所述层间介电层上的过孔与所述有源层图案电连接；所述第一金属图案穿过所述第一绝缘图案上的过孔与所述半导体图案电连接，或者所述第二金属图案穿过所述第二绝缘图案和所述第一绝缘图案上的过孔与所述半导体图案电连接。In a third aspect, a method for preparing an array substrate is provided, including: forming a semiconductor layer on a base substrate, the semiconductor layer including an active layer pattern located in a display area and a semiconductor pattern located in a GOA region; Forming a first insulating layer, a first metal layer, a second insulating layer and a second metal layer in sequence; the first metal layer includes a gate located in the display area and a first metal pattern located in the GOA area; The second metal layer includes a source and drain electrode located in the display area and a second metal pattern located in the GOA area; the first insulating layer includes a gate insulating layer located in the display area and a second metal pattern located in the GOA area. The first insulating pattern; the second insulating layer includes an interlayer dielectric layer located in the display area and a second insulating pattern located in the GOA region; wherein the source and drain pass through the gate insulating layer The via hole on the interlayer dielectric layer is electrically connected to the active layer pattern; the first metal pattern is electrically connected to the semiconductor pattern through the via hole on the first insulating pattern, or the The second metal pattern is electrically connected to the semiconductor pattern through the via hole on the second insulating pattern and the first insulating pattern.
优选的，所述制备方法还包括：在所述半导体层上形成所述第一金属层之前，对所述半导体图案进行掺杂。Preferably, the preparation method further includes: before forming the first metal layer on the semiconductor layer, doping the semiconductor pattern.
优选的，所述制备方法还包括：在形成半导体层之后，形成第二绝缘层之前，对所述有源层图案的源极接触区和漏极接触区进行第一次掺杂；在对所述有源层图案的源极接触区和漏极接触区进行第一次掺杂之前，所述制备方法还包括：在所述有源层图案上形成光刻胶图案；沿栅极的宽度方向，所述栅极在所述有源层图案上正投影的边界位于所述光刻胶图案在所述有源层图案上正投影的边界以内，且所述光刻胶图案在所述有源层图案上的正投影与所述有源层图案的源极接触区和漏极接触区无重叠区域；在对所述有源层图案的源极接触区和漏极接触区进行第一次掺杂之后，所述制备方法还包括：剥离所述光刻胶图案；在形成所述第一金属层之后，形成所述第二绝缘层之前，所述制备方法还包括：以所述栅极为掩膜，对所述有源层图案进行第二次掺杂，所述第二次掺杂的掺杂浓度小于所述第一次掺杂的掺杂浓度。Preferably, the preparation method further includes: after forming the semiconductor layer and before forming the second insulating layer, doping the source contact region and the drain contact region of the active layer pattern for the first time; Before the source contact region and the drain contact region of the active layer pattern are doped for the first time, the preparation method further includes: forming a photoresist pattern on the active layer pattern; , the boundary of the orthographic projection of the gate on the active layer pattern is located within the boundary of the orthographic projection of the photoresist pattern on the active layer pattern, and the photoresist pattern is on the active layer pattern The orthographic projection on the layer pattern has no overlapping area with the source contact region and the drain contact region of the active layer pattern; After the impurity, the preparation method further includes: stripping the photoresist pattern; after forming the first metal layer and before forming the second insulating layer, the preparation method further includes: using the gate as a mask film, performing second doping on the active layer pattern, the doping concentration of the second doping is lower than the doping concentration of the first doping.
优选的，对所述有源层图案的源极接触区和漏极接触区进行第一次掺杂的步骤是在形成所述第一绝缘层之前完成的。Preferably, the first doping step of the source contact region and the drain contact region of the active layer pattern is completed before forming the first insulating layer.
优选的，在形成所述半导体层之后，形成所述第一绝缘层之前，所述制备方法还包括：对所述有源层图案进行第三次掺杂，所述第三次掺杂的掺杂浓度小于所述第二次掺杂的掺杂浓度。Preferably, after forming the semiconductor layer and before forming the first insulating layer, the preparation method further includes: performing a third doping on the active layer pattern, the doping of the third doping The impurity concentration is less than the doping concentration of the second doping.
第四方面，提供一种薄膜晶体管的制备方法，包括：在衬底基板上形成有源层图案；在所述有源层图案上形成栅绝缘层和栅极；以所述栅极为掩膜，对所述有源层图案进行第二次掺杂；在所述栅极上依次形成层间介电层和源漏极，所述源漏极穿过所述层间介电层和所述栅绝缘层上的过孔与所述有源层图案电连接；所述制备方法还包括：在形成所述有源层图案之后，形成所述层间介电层之前，在所述有源层图案上形成光刻胶图案；沿所述栅极的宽度方向，所述栅极在所述有源层图案上正投影的边界位于所述光刻胶图案在所述有源层图案上正投影的边界以内，且所述光刻胶图案在所述有源层图案上的正投影与所述有源层图案的源极接触区和漏极接触区无重叠区域；以所述光刻胶图案为掩膜，对所述有源层图案进行第一次掺杂，所述第一次掺杂的掺杂浓度大于所述第二次掺杂的掺杂浓度；剥离所述光刻胶图案。In a fourth aspect, a method for manufacturing a thin film transistor is provided, comprising: forming an active layer pattern on a base substrate; forming a gate insulating layer and a gate on the active layer pattern; using the gate as a mask, Doping the active layer pattern for the second time; forming an interlayer dielectric layer and a source-drain in sequence on the gate, and the source-drain passes through the interlayer dielectric layer and the gate The via hole on the insulating layer is electrically connected to the active layer pattern; the preparation method further includes: after forming the active layer pattern and before forming the interlayer dielectric layer, forming the active layer pattern A photoresist pattern is formed on it; along the width direction of the gate, the boundary of the positive projection of the gate on the active layer pattern is located at the front projection of the photoresist pattern on the active layer pattern within the boundary, and the orthographic projection of the photoresist pattern on the active layer pattern has no overlapping area with the source contact region and the drain contact region of the active layer pattern; the photoresist pattern is a mask, performing first doping on the active layer pattern, the doping concentration of the first doping is greater than the doping concentration of the second doping; stripping the photoresist pattern.
优选的，以所述光刻胶图案为掩膜，对所述有源层图案进行第一次掺杂的步骤是在形成所述栅绝缘层之前完成的。Preferably, using the photoresist pattern as a mask, the step of doping the active layer pattern for the first time is completed before forming the gate insulating layer.
优选的，所述制备方法还包括：在形成所述有源层图案之后，形成所述栅绝缘层之前，对所述有源层图案进行第三次掺杂；所述第三次掺杂的掺杂浓度小于所述第二次掺杂的掺杂浓度。Preferably, the preparation method further includes: after forming the active layer pattern and before forming the gate insulating layer, doping the active layer pattern for a third time; the third doping The doping concentration is less than the doping concentration of the second doping.
本发明实施例提供一种阵列基板及其制备方法、显示装置、薄膜晶体管的制备方法，阵列基板的GOA区包括依次层叠设置的半导体图案、第一绝缘图案、第一金属图案、第二绝缘图案和第二金属图案，由于第一金属图案与半导体图案电连接或者第二金属图案与半导体图案电连接，因而不仅第一金属图案和第二金属图案可以形成电容，而且在第一金属图案与半导体图案电连接的情况下，第二金属图案和半导体图案还可以形成电容，或者在第二金属图案与半导体图案电连接的情况下，第一金属图案和半导体图案还可以形成电容，因此相对于现有技术中GOA区仅有第一金属图案和第二金属图案形成电容，本发明实施例GOA区的电容增加，从而使得显示区域的TFT可以快速打开或关闭，进而确保了显示画面能够准确快速地输出。Embodiments of the present invention provide an array substrate and its preparation method, a display device, and a preparation method of a thin film transistor. The GOA region of the array substrate includes a semiconductor pattern, a first insulating pattern, a first metal pattern, and a second insulating pattern that are sequentially stacked. and the second metal pattern, since the first metal pattern is electrically connected to the semiconductor pattern or the second metal pattern is electrically connected to the semiconductor pattern, not only the first metal pattern and the second metal pattern can form a capacitor, but also the first metal pattern and the semiconductor pattern When the pattern is electrically connected, the second metal pattern and the semiconductor pattern can also form a capacitor, or when the second metal pattern is electrically connected to the semiconductor pattern, the first metal pattern and the semiconductor pattern can also form a capacitor, so compared with the existing In the prior art, only the first metal pattern and the second metal pattern form capacitance in the GOA area. The capacitance of the GOA area in the embodiment of the present invention is increased, so that the TFT in the display area can be quickly turned on or off, thereby ensuring that the display screen can be accurately and quickly output.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1(a)为现有技术提供的一种GOA区电容的结构示意图；Fig. 1 (a) is the structural schematic diagram of a kind of GOA region capacitor provided by the prior art;
图1(b)为现有技术提供的一种GOA区电容的电路结构示意图；Fig. 1 (b) is the schematic diagram of the circuit structure of a kind of GOA region capacitor provided by the prior art;
图2(a)为本发明实施例提供的一种GOA区电容的结构示意图一；Fig. 2 (a) is the structural schematic diagram 1 of a kind of GOA region capacitance provided by the embodiment of the present invention;
图2(b)为本发明实施例提供的一种GOA区电容的结构示意图二；Fig. 2 (b) is the structural schematic diagram 2 of a kind of GOA region capacitance provided by the embodiment of the present invention;
图2(c)为本发明实施例提供的一种GOA区电容的电路结构示意图；Fig. 2 (c) is the schematic diagram of the circuit structure of a kind of GOA region capacitance provided by the embodiment of the present invention;
图3(a)为本发明实施例提供的一种阵列基板的结构示意图一；FIG. 3(a) is a first structural schematic diagram of an array substrate provided by an embodiment of the present invention;
图3(b)为本发明实施例提供的一种阵列基板的结构示意图二；FIG. 3(b) is a second structural schematic diagram of an array substrate provided by an embodiment of the present invention;
图4为本发明实施例提供的一种阵列基板的结构示意图三；FIG. 4 is a schematic structural diagram III of an array substrate provided by an embodiment of the present invention;
图5为本发明实施例提供的一种阵列基板的制备方法的流程示意图；FIG. 5 is a schematic flowchart of a method for preparing an array substrate provided by an embodiment of the present invention;
图6为本发明实施例提供的一种在衬底基板上形成半导体层的结构示意图；FIG. 6 is a schematic structural diagram of forming a semiconductor layer on a base substrate according to an embodiment of the present invention;
图7为本发明实施例提供的一种在有源层图案上形成光刻胶图案的结构示意图；7 is a schematic structural diagram of forming a photoresist pattern on an active layer pattern according to an embodiment of the present invention;
图8为剥离图7中光刻胶图案后的结构示意图；FIG. 8 is a schematic view of the structure after peeling off the photoresist pattern in FIG. 7;
图9为本发明实施例提供的一种在栅绝缘层上形成栅极的结构示意图；FIG. 9 is a schematic structural diagram of forming a gate on a gate insulating layer according to an embodiment of the present invention;
图10为本发明实施例提供的一种阵列基板的结构示意图四；FIG. 10 is a fourth structural schematic diagram of an array substrate provided by an embodiment of the present invention;
图11为本发明实施例提供的一种薄膜晶体管的制备方法的流程示意图。FIG. 11 is a schematic flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the present invention.
附图标记：Reference signs:
10-衬底基板；201-第一金属图案；301-第一绝缘图案；401-第二金属图案；501-半导体图案；601-第二绝缘图案；701-有源层图案；702-栅绝缘层；703-栅极；704-层间介电层；705-源漏极；80-光阻挡图案；90-缓冲层；100-光刻胶图案。10-substrate substrate; 201-first metal pattern; 301-first insulating pattern; 401-second metal pattern; 501-semiconductor pattern; 601-second insulating pattern; 701-active layer pattern; 702-gate insulation layer; 703-gate; 704-interlayer dielectric layer; 705-source-drain; 80-light blocking pattern; 90-buffer layer; 100-photoresist pattern.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明实施例提供一种阵列基板，包括显示区域和GOA区，如图2(a)和图2(b)所示，GOA区包括依次层叠设置的半导体图案501、第一绝缘图案301、第一金属图案201、第二绝缘图案601和第二金属图案401；其中，如图2(a)所示，第一金属图案201穿过第一绝缘图案301上的过孔与半导体图案501电连接，或者如图2(b)所示，第二金属图案401穿过第一绝缘图案301和第二绝缘图案601上的过孔与半导体图案501电连接。An embodiment of the present invention provides an array substrate, including a display area and a GOA region. As shown in FIG. 2(a) and FIG. 2(b), the GOA region includes a semiconductor pattern 501, a first insulating pattern 301, A metal pattern 201, a second insulating pattern 601 and a second metal pattern 401; wherein, as shown in FIG. , or as shown in FIG. 2( b ), the second metal pattern 401 is electrically connected to the semiconductor pattern 501 through the via holes on the first insulating pattern 301 and the second insulating pattern 601 .
需要说明的是，第一，对于半导体图案501的材料不进行限定，例如可以是单晶硅、多晶硅(P-Si)或非晶硅(α-Si)。由于多晶硅的电子迁移率快，稳定性较高，因而本发明实施例优选，半导体图案501的材料为多晶硅。It should be noted that, first, the material of the semiconductor pattern 501 is not limited, for example, it may be single crystal silicon, polycrystalline silicon (P-Si) or amorphous silicon (α-Si). Since polysilicon has fast electron mobility and high stability, it is preferable in this embodiment of the present invention that the material of the semiconductor pattern 501 is polysilicon.
第二，当半导体图案501与第一金属图案201电连接时，此时半导体图案501和第二金属图案401可以形成电容；当半导体图案501与第二金属图案401电连接时，此时半导体图案501和第一金属图案201可以形成电容。Second, when the semiconductor pattern 501 is electrically connected to the first metal pattern 201, the semiconductor pattern 501 and the second metal pattern 401 can form a capacitor at this time; when the semiconductor pattern 501 is electrically connected to the second metal pattern 401, the semiconductor pattern 501 and the first metal pattern 201 may form a capacitor.
基于此，参考图2(c)，以半导体图案501与第二金属图案401电连接为例，在GOA区，第一金属图案201和第二金属图案401形成第一电容C1，半导体图案501和第一金属图案201形成第二电容C2，因此GOA区的电容C＝C1+C2。Based on this, referring to FIG. 2(c), taking the electrical connection between the semiconductor pattern 501 and the second metal pattern 401 as an example, in the GOA region, the first metal pattern 201 and the second metal pattern 401 form a first capacitor C1, and the semiconductor pattern 501 and the second metal pattern 401 form a first capacitor C1. The first metal pattern 201 forms the second capacitor C2, so the capacitor C in the GOA region=C1+C2.
第三，第一金属图案201和第二金属图案401的材料可以选自但不限于铝(Al)、钛(Ti)、钼(Mo)、银(Ag)、铬(Cr)或其合金中的一种或多种的组合。本发明实施例优选第一金属图案201和第二金属图案401的材料为依次层叠设置的Mo/Al/Mo。Third, the materials of the first metal pattern 201 and the second metal pattern 401 can be selected from but not limited to aluminum (Al), titanium (Ti), molybdenum (Mo), silver (Ag), chromium (Cr) or alloys thereof one or a combination of more. In the embodiment of the present invention, the materials of the first metal pattern 201 and the second metal pattern 401 are preferably Mo/Al/Mo which are stacked in sequence.
第一绝缘图案301和第二绝缘图案601的材料可以选自但不限于氧化硅(SiOx)、氮化硅(SiNx)或氮氧化硅(SiOxNy)中的至少一种。Materials of the first insulating pattern 301 and the second insulating pattern 601 may be selected from at least one of, but not limited to, silicon oxide (SiOx ), silicon nitride (SiNx ) or silicon oxynitride (SiOx Ny ).
第四，如图2(a)和图2(b)所示，半导体图案501、第一绝缘图案301、第一金属图案201、第二绝缘图案601和第二金属图案401可以设置在衬底基板10上。衬底基板10例如可以为玻璃。Fourth, as shown in Figure 2(a) and Figure 2(b), the semiconductor pattern 501, the first insulating pattern 301, the first metal pattern 201, the second insulating pattern 601 and the second metal pattern 401 can be arranged on the substrate on the substrate 10. The base substrate 10 may be, for example, glass.
本发明实施例提供一种阵列基板，阵列基板的GOA区包括依次层叠设置的半导体图案501、第一绝缘图案301、第一金属图案201、第二绝缘图案601和第二金属图案401，由于第一金属图案201与半导体图案501电连接或者第二金属图案401与半导体图案501电连接，因而不仅第一金属图案201和第二金属图案401可以形成电容，而且在第一金属图案201与半导体图案501电连接的情况下，第二金属图案401和半导体图案501还可以形成电容，或者在第二金属图案401与半导体图案501电连接的情况下，第一金属图案201和半导体图案501还可以形成电容，因此相对于现有技术中GOA区仅有第一金属图案201和第二金属图案401形成电容，本发明实施例GOA区的电容增加，从而使得显示区域的TFT可以快速打开或关闭，进而确保了显示画面能够准确快速地输出。An embodiment of the present invention provides an array substrate. The GOA region of the array substrate includes a semiconductor pattern 501, a first insulating pattern 301, a first metal pattern 201, a second insulating pattern 601, and a second metal pattern 401 that are sequentially stacked. A metal pattern 201 is electrically connected to the semiconductor pattern 501 or the second metal pattern 401 is electrically connected to the semiconductor pattern 501, so that not only the first metal pattern 201 and the second metal pattern 401 can form a capacitor, but also between the first metal pattern 201 and the semiconductor pattern 501 is electrically connected, the second metal pattern 401 and the semiconductor pattern 501 can also form a capacitor, or in the case of the second metal pattern 401 and the semiconductor pattern 501 are electrically connected, the first metal pattern 201 and the semiconductor pattern 501 can also form Capacitance, so compared with the GOA region in the prior art, only the first metal pattern 201 and the second metal pattern 401 form capacitance, the capacitance of the GOA region in the embodiment of the present invention is increased, so that the TFT in the display region can be quickly turned on or off, and then It ensures that the display screen can be output accurately and quickly.
优选的，如图3(a)和图3(b)所示，显示区域包括薄膜晶体管；薄膜晶体管包括依次设置的有源层图案701、栅绝缘层702、栅极703、层间介电层704和源漏极705，源漏极705穿过层间介电层704和栅绝缘层702上的过孔与有源层图案701电连接；其中，有源层图案701与半导体图案501、栅绝缘层702和第一绝缘图案301、栅极703与第一金属图案201、层间介电层704与第二绝缘图案601以及源漏极705与第二金属图案401中的至少一组同层同材料。Preferably, as shown in Fig. 3(a) and Fig. 3(b), the display area includes a thin film transistor; the thin film transistor includes an active layer pattern 701, a gate insulating layer 702, a gate 703, an interlayer dielectric layer arranged in sequence 704 and the source and drain electrodes 705, the source and drain electrodes 705 are electrically connected to the active layer pattern 701 through the via hole on the interlayer dielectric layer 704 and the gate insulating layer 702; wherein, the active layer pattern 701 is connected to the semiconductor pattern 501, the gate At least one group of the insulating layer 702 and the first insulating pattern 301, the gate 703 and the first metal pattern 201, the interlayer dielectric layer 704 and the second insulating pattern 601, and the source and drain 705 and the second metal pattern 401 are in the same layer Same material.
此处，本发明实施例提供的薄膜晶体管可以如图3(b)所示为单栅薄膜晶体管，也可以如图3(a)所示为双栅(Dual gate)薄膜晶体管。由于双栅极结构可以抑制漏电流，因而本发明实施例优选薄膜晶体管为双栅薄膜晶体管。Here, the thin film transistor provided by the embodiment of the present invention may be a single gate thin film transistor as shown in FIG. 3( b ), or may be a dual gate (Dual gate) thin film transistor as shown in FIG. 3( a ). Since the double-gate structure can suppress leakage current, it is preferred that the thin film transistor in the embodiment of the present invention be a double-gate thin film transistor.
此外，当源漏极705与第二金属图案401同层同材料时，本发明实施例优选第二金属图案401与半导体图案501电连接。这是因为由于源漏极705穿过层间介电层704和栅绝缘层702上的过孔与有源层图案701电连接，因而可以在层间介电层704和栅绝缘层702上的形成过孔的同时在第二绝缘图案601和第一绝缘图案301上形成过孔，相对于第一金属图案201与半导体图案501电连接，这样便可以节省一张掩膜板(Mask)，简化阵列基板的制备工艺。In addition, when the source and drain electrodes 705 and the second metal pattern 401 have the same layer and material, it is preferred that the second metal pattern 401 is electrically connected to the semiconductor pattern 501 in the embodiment of the present invention. This is because the source and drain electrodes 705 are electrically connected to the active layer pattern 701 through the via holes on the interlayer dielectric layer 704 and the gate insulating layer 702, and thus can be formed on the interlayer dielectric layer 704 and the gate insulating layer 702. While forming the via hole, the via hole is formed on the second insulating pattern 601 and the first insulating pattern 301, and is electrically connected to the semiconductor pattern 501 with respect to the first metal pattern 201, so that a mask board (Mask) can be saved, simplifying Fabrication process of array substrate.
需要说明的是，当有源层图案701的材料为多晶硅时，薄膜晶体管为低温多晶硅(Low Temperature Poly-silicon，简称LTPS)薄膜晶体管，低温多晶硅薄膜晶体管具有反应速度快、高开口率等优点。It should be noted that when the material of the active layer pattern 701 is polysilicon, the thin film transistor is a low temperature polysilicon (LTPS) thin film transistor, and the low temperature polysilicon thin film transistor has advantages such as fast response speed and high aperture ratio.
本发明实施例，当有源层图案701与半导体图案501同层同材料，可以在制备有源层图案701的同时制备半导体图案501；当栅绝缘层702和第一绝缘图案301同层同材料，可以在制备栅绝缘层702的同时制备第一绝缘图案301；当栅极703与第一金属图案201同层同材料时，可以在制备栅极703的同时制备第一金属图案201；当层间介电层704与第二绝缘图案601同层同材料时，可以在制备层间介电层704的同时制备第二绝缘图案601；当源漏极705与第二金属图案401同层同材料时，可以在制备源漏极705的同时制备第二金属图案401，从而简化了阵列基板的制作工艺。In the embodiment of the present invention, when the active layer pattern 701 and the semiconductor pattern 501 are of the same layer and material, the semiconductor pattern 501 can be prepared at the same time as the active layer pattern 701; when the gate insulating layer 702 and the first insulating pattern 301 are of the same layer and material , the first insulating pattern 301 can be prepared while the gate insulating layer 702 is being prepared; when the gate 703 and the first metal pattern 201 are of the same layer and material, the first metal pattern 201 can be prepared while the gate 703 is being prepared; when the layer When the interlayer dielectric layer 704 and the second insulating pattern 601 are of the same layer and material, the second insulating pattern 601 can be prepared at the same time as the interlayer dielectric layer 704 is prepared; when the source and drain electrodes 705 and the second metal pattern 401 are of the same layer and material When the source and drain electrodes 705 are prepared, the second metal pattern 401 can be prepared simultaneously, thereby simplifying the manufacturing process of the array substrate.
由于半导体图案501被掺杂后，半导体图案501的导电性能会提高，进而使得半导体图案501和第一金属图案201或第二金属图案401形成的电容的电容值会增大，因而本发明实施例优选半导体图案501为被掺杂的半导体图案501。After the semiconductor pattern 501 is doped, the conductivity of the semiconductor pattern 501 will be improved, and the capacitance value of the capacitor formed by the semiconductor pattern 501 and the first metal pattern 201 or the second metal pattern 401 will increase, so the embodiment of the present invention Preferably, the semiconductor pattern 501 is a doped semiconductor pattern 501 .
此处，对于半导体图案501的掺杂浓度不进行限定，可以根据需要进行相应的掺杂。由于掺杂的浓度越大，半导体图案501的导电性能提高的越大，因而发明实施例优选对半导体图案501的掺杂为重掺杂。Here, the doping concentration of the semiconductor pattern 501 is not limited, and corresponding doping can be performed as required. Since the greater the doping concentration, the greater the improvement of the conductivity of the semiconductor pattern 501 , and thus the embodiment of the invention preferably heavily doping the semiconductor pattern 501 .
在此基础上，对于半导体图案501的掺杂类型不进行限定，可以是N型掺杂，也可以是P型掺杂。当半导体图案501的掺杂为N型掺杂时，可以掺入磷元素或锑元素；当半导体图案501的掺杂为P型掺杂时，可以掺入硼元素或铟元素。On this basis, the doping type of the semiconductor pattern 501 is not limited, it may be N-type doping or P-type doping. When the doping of the semiconductor pattern 501 is N-type doping, phosphorus element or antimony element can be doped; when the doping of the semiconductor pattern 501 is P-type doping, boron element or indium element can be doped.
基于上述，优选的，如图4所示，阵列基板的显示区域还包括层叠设置的光阻挡图案80和缓冲层90，缓冲层90靠近有源层图案701；其中，光阻挡图案80和栅极703在有源层图案701上的正投影具有重叠区域。Based on the above, preferably, as shown in FIG. 4 , the display area of the array substrate further includes a stacked light blocking pattern 80 and a buffer layer 90, and the buffer layer 90 is close to the active layer pattern 701; wherein, the light blocking pattern 80 and the gate The orthographic projection of 703 on the active layer pattern 701 has an overlapping area.
其中，对于缓冲层的材料不进行限定，例如可以是氧化硅、氮化硅或氮氧化硅中的至少一种。此外，缓冲层可以通过化学气相沉积工艺制备。Wherein, the material of the buffer layer is not limited, for example, it may be at least one of silicon oxide, silicon nitride, or silicon oxynitride. In addition, the buffer layer can be prepared by a chemical vapor deposition process.
有源层图案701中与栅极703正对的区域为沟道区域，当沟道区域受到光的照射时，沟道区域的性能会发生变化，从而会影响薄膜晶体管的开关性能，造成漏电流，因而本发明实施例在显示区域设置光阻挡图案80，且光阻挡图案80和栅极703在有源层图案701上的正投影具有重叠区域，从而可以减少沟道区域受到的光照。为了使沟道区域受到的光照尽可能地少，因而本发明实施例优选，光阻挡图案80和栅极703在有源层图案701上的正投影完全重叠。The area of the active layer pattern 701 facing the gate 703 is the channel area. When the channel area is irradiated by light, the performance of the channel area will change, which will affect the switching performance of the thin film transistor and cause leakage current. Therefore, in the embodiment of the present invention, the light blocking pattern 80 is provided in the display area, and the orthographic projection of the light blocking pattern 80 and the gate 703 on the active layer pattern 701 has an overlapping area, so that the illumination of the channel area can be reduced. In order to make the channel region receive as little light as possible, it is preferred in this embodiment of the present invention that the orthographic projections of the light blocking pattern 80 and the gate 703 on the active layer pattern 701 overlap completely.
在此基础上，本发明实施例，在衬底基板10上设置缓冲层90，不但可以平坦衬底基板10，屏蔽衬底基板10的缺陷，还可以防止杂质离子渗透到衬底基板10中引起器件的各种不良。On this basis, in the embodiment of the present invention, the buffer layer 90 is provided on the base substrate 10, which can not only flatten the base substrate 10, shield the defects of the base substrate 10, but also prevent impurity ions from penetrating into the base substrate 10 to cause Various defects of the device.
本发明实施例提供一种显示装置，包括上述的阵列基板。An embodiment of the present invention provides a display device, including the above-mentioned array substrate.
此处，对于显示装置的类型不进行限定，可以是液晶显示装置(Liquid CrystalDisplay，简化LCD)，也可以有机电致发光显示装置(Organic Light-Emitting Display，简称OLED)或其它类型的显示装置。Here, the type of the display device is not limited, and may be a liquid crystal display (Liquid Crystal Display, simplified LCD), or an organic electroluminescence display (Organic Light-Emitting Display, OLED for short) or other types of display devices.
其中，本发明实施例提供的显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图画的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。此外，显示装置可以是显示面板。Wherein, the display device provided by the embodiments of the present invention may be any device that displays images whether moving (for example, video) or fixed (for example, still images), and regardless of text or pictures. More specifically, it is contemplated that the described embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or Laptop Computers, GPS Receivers/Navigators, Cameras, MP4 Video Players, Camcorders, Game Consoles, Watches, Clocks, Calculators, Television Monitors, Flat Panel Displays, Computer Monitors, Automotive Displays (eg, odometer displays, etc.), navigators, cockpit controls and/or displays, displays for camera views (e.g., displays for rear-view cameras in vehicles), electronic photographs, electronic billboards or signage, projectors, building structures, packaging and aesthetic structures (for example, for a display of an image of a piece of jewelry), etc. Also, the display device may be a display panel.
本发明实施例提供一种显示装置，由于显示装置包括上述的阵列基板，因此本发明实施例提供的显示装置具有与本发明前述实施例提供的阵列基板相同的有益效果，由于阵列基板在前述实施例中已经进行了详细说明，因此此处不再赘述。An embodiment of the present invention provides a display device. Since the display device includes the above-mentioned array substrate, the display device provided by the embodiment of the present invention has the same beneficial effects as the array substrate provided by the foregoing embodiments of the present invention. The example has already been described in detail, so it will not be repeated here.
本发明实施例提供一种阵列基板的制备方法，如图5所示，包括：An embodiment of the present invention provides a method for preparing an array substrate, as shown in FIG. 5 , including:
S100、如图6所示，在衬底基板10上形成半导体层，半导体层包括位于显示区域的有源层图案701和位于GOA区的半导体图案501。S100 , as shown in FIG. 6 , form a semiconductor layer on the base substrate 10 , the semiconductor layer includes an active layer pattern 701 located in the display area and a semiconductor pattern 501 located in the GOA area.
其中，对于半导体层的材料不进行限定，例如可以是单晶硅、多晶硅或非晶硅。由于多晶硅的电子迁移率快，稳定性较高，因而本发明实施例优选，半导体层的材料为多晶硅。当半导体层的材料为多晶硅时，半导体层的制备过程可以是先形成非晶硅层，再采用准分子激光退火(ELA)、固相晶化(SPC)等方法将非晶硅层转换为多晶硅层。Wherein, the material of the semiconductor layer is not limited, for example, it may be single crystal silicon, polycrystalline silicon or amorphous silicon. Since polysilicon has fast electron mobility and high stability, it is preferable in this embodiment of the present invention that the material of the semiconductor layer is polysilicon. When the material of the semiconductor layer is polysilicon, the preparation process of the semiconductor layer can be to form an amorphous silicon layer first, and then convert the amorphous silicon layer into polysilicon by excimer laser annealing (ELA), solid phase crystallization (SPC) and other methods. Floor.
需要说明的是，在衬底基板10上形成半导体层之前，上述制备方法还包括：如图6所示，在衬底基板10上依次形成位于显示区域的光阻挡图案80和缓冲层90；其中，光阻挡图案80和待形成的栅极703在有源层图案701上的正投影具有重叠区域。此处，形成光阻挡图案80的目的是为了减少沟道区域受到的光照，以避免影响薄膜晶体管的开关性能，造成漏电流。形成缓冲层90的目的是为了平坦衬底基板10，屏蔽衬底基板10的缺陷，防止杂质离子渗透到衬底基板10中引起器件的各种不良。It should be noted that, before forming the semiconductor layer on the base substrate 10, the above preparation method further includes: as shown in FIG. , the orthographic projection of the light blocking pattern 80 and the to-be-formed gate 703 on the active layer pattern 701 has an overlapping area. Here, the purpose of forming the light blocking pattern 80 is to reduce the light received by the channel region, so as to avoid affecting the switching performance of the thin film transistor and causing leakage current. The purpose of forming the buffer layer 90 is to flatten the base substrate 10 , shield the defects of the base substrate 10 , and prevent impurity ions from penetrating into the base substrate 10 to cause various defects of the device.
S101、如图4所示，在半导体层上依次形成第一绝缘层、第一金属层、第二绝缘层和第二金属层。第一金属层包括位于显示区域的栅极703和位于GOA区的第一金属图案201；第二金属层包括位于显示区域的源漏极705和位于GOA区域的第二金属图案401；第一绝缘层包括位于显示区域的栅绝缘层702和位于GOA区的第一绝缘图案301；第二绝缘层包括位于显示区域的层间介电层704和位于GOA区的第二绝缘图案601。S101 , as shown in FIG. 4 , sequentially form a first insulating layer, a first metal layer, a second insulating layer and a second metal layer on the semiconductor layer. The first metal layer includes the gate 703 located in the display area and the first metal pattern 201 located in the GOA area; the second metal layer includes the source and drain electrodes 705 located in the display area and the second metal pattern 401 located in the GOA area; the first insulating The layers include a gate insulating layer 702 located in the display area and a first insulating pattern 301 located in the GOA area; the second insulating layer includes an interlayer dielectric layer 704 located in the display area and a second insulating pattern 601 located in the GOA area.
其中，源漏极705穿过栅绝缘层702和层间介电层704上的过孔与有源层图案701电连接；第一金属图案201穿过第一绝缘图案301上的过孔与半导体图案501电连接，或者第二金属图案401穿过第二绝缘图案601和第一绝缘图案301上的过孔与半导体图案501电连接。Wherein, the source and drain electrodes 705 are electrically connected to the active layer pattern 701 through the via holes on the gate insulating layer 702 and the interlayer dielectric layer 704; the first metal pattern 201 is connected to the semiconductor via holes on the first insulating pattern 301. The pattern 501 is electrically connected, or the second metal pattern 401 is electrically connected to the semiconductor pattern 501 through the via holes on the second insulating pattern 601 and the first insulating pattern 301 .
此处，若第一金属图案201穿过第一绝缘图案301上的过孔与半导体图案501电连接，则在形成第一绝缘图案301之后，还需要利用一张掩膜板在第一绝缘图案301上形成过孔。由于源漏极705穿过栅绝缘层702和层间介电层704上的过孔与有源层图案701电连接，因此在形成层间介电层704之后，需利用一张掩膜板在栅绝缘层702和层间介电层704上形成过孔。若第二金属图案401穿过第二绝缘图案601和第一绝缘图案301上的过孔与半导体图案501电连接，此时可以利用一张掩膜板在形成栅绝缘层702和层间介电层704上的过孔的同时，形成第二绝缘图案601和第一绝缘图案301上的过孔。为了简化阵列基板的制作工艺，避免增加掩膜板的数量，因而本发明实施例优选第二金属图案401穿过第二绝缘图案601和第一绝缘图案301上的过孔与半导体图案501电连接Here, if the first metal pattern 201 is electrically connected to the semiconductor pattern 501 through the via hole on the first insulating pattern 301, after the formation of the first insulating pattern 301, it is also necessary to use a mask to cover the first insulating pattern. Vias are formed on 301 . Since the source and drain electrodes 705 are electrically connected to the active layer pattern 701 through the via holes on the gate insulating layer 702 and the interlayer dielectric layer 704, after the formation of the interlayer dielectric layer 704, it is necessary to utilize a mask Vias are formed on the gate insulating layer 702 and the interlayer dielectric layer 704 . If the second metal pattern 401 is electrically connected to the semiconductor pattern 501 through the via holes on the second insulating pattern 601 and the first insulating pattern 301, a mask can be used to form the gate insulating layer 702 and the interlayer dielectric. At the same time as the via holes on the layer 704 are formed, the via holes on the second insulating pattern 601 and the first insulating pattern 301 are formed. In order to simplify the manufacturing process of the array substrate and avoid increasing the number of mask plates, in this embodiment of the present invention, the second metal pattern 401 is preferably electrically connected to the semiconductor pattern 501 through the via holes on the second insulating pattern 601 and the first insulating pattern 301
需要说明的是，显示区域的有源层图案701、栅绝缘层702、栅极703、层间介电层704以及源漏极705构成薄膜晶体管，其中，薄膜晶体管的栅极703可以如图3(b)所示为单栅极，也可以如图4所示为双栅极。由于双栅极结构可以抑制漏电流，因而本发明实施例优选，薄膜晶体管的栅极703为双栅极结构。It should be noted that the active layer pattern 701, the gate insulating layer 702, the gate 703, the interlayer dielectric layer 704, and the source and drain 705 in the display region form a thin film transistor, wherein the gate 703 of the thin film transistor can be as shown in FIG. (b) shows a single gate, but it can also be a double gate as shown in Figure 4. Since the double gate structure can suppress the leakage current, it is preferred in the embodiment of the present invention that the gate 703 of the thin film transistor has a double gate structure.
在此基础上，第一绝缘层和第二绝缘层的材料可以选自但不限于氧化硅、氮化硅或氮氧化硅中的至少一种。On this basis, the materials of the first insulating layer and the second insulating layer may be selected from at least one of, but not limited to, silicon oxide, silicon nitride, or silicon oxynitride.
第一金属层和第二金属层的材料可以选自但不限于铝、钛、钼、银、铬或其合金中的一种或多种的组合。本发明实施例优选第一金属层和第二金属层的材料为依次层叠设置的Mo/Al/Mo。Materials of the first metal layer and the second metal layer may be selected from, but not limited to, one or more combinations of aluminum, titanium, molybdenum, silver, chromium or alloys thereof. In the embodiment of the present invention, the materials of the first metal layer and the second metal layer are preferably Mo/Al/Mo which are sequentially stacked.
本发明实施例提供一种阵列基板的制备方法，阵列基板的GOA区包括依次层叠设置的半导体图案501、第一绝缘图案301、第一金属图案201、第二绝缘图案601和第二金属图案401，由于第一金属图案201与半导体图案501电连接或者第二金属图案401与半导体图案501电连接，因而不仅第一金属图案201和第二金属图案401可以形成电容，而且在第一金属图案201与半导体图案501电连接的情况下，第二金属图案401和半导体图案501还可以形成电容，或者在第二金属图案401与半导体图案501电连接的情况下，第一金属图案201和半导体图案501还可以形成电容，因此相对于现有技术中GOA区仅有第一金属图案201和第二金属图案401形成电容，本发明实施例GOA区的电容增加，从而使得显示区域的TFT可以快速打开或关闭，进而确保了显示画面能够准确快速地输出。An embodiment of the present invention provides a method for preparing an array substrate. The GOA region of the array substrate includes a semiconductor pattern 501, a first insulating pattern 301, a first metal pattern 201, a second insulating pattern 601, and a second metal pattern 401 that are sequentially stacked. , since the first metal pattern 201 is electrically connected to the semiconductor pattern 501 or the second metal pattern 401 is electrically connected to the semiconductor pattern 501, not only the first metal pattern 201 and the second metal pattern 401 can form a capacitor, but also the first metal pattern 201 In the case of being electrically connected to the semiconductor pattern 501, the second metal pattern 401 and the semiconductor pattern 501 can also form a capacitor, or in the case of the second metal pattern 401 being electrically connected to the semiconductor pattern 501, the first metal pattern 201 and the semiconductor pattern 501 Capacitors can also be formed, so compared to the GOA region in the prior art where only the first metal pattern 201 and the second metal pattern 401 form capacitance, the capacitance of the GOA region in the embodiment of the present invention increases, so that the TFTs in the display region can be quickly turned on or Closed, thereby ensuring that the display screen can be output accurately and quickly.
优选的，上述制备方法还包括：在半导体层上形成第一金属层之前，对半导体图案501进行掺杂。Preferably, the above preparation method further includes: before forming the first metal layer on the semiconductor layer, doping the semiconductor pattern 501 .
此处，对于半导体图案501的掺杂浓度不进行限定，可以根据需要进行相应的掺杂。由于掺杂的浓度越大，半导体图案501的导电性能提高的越大，因而发明实施例优选对半导体图案501的掺杂为重掺杂。Here, the doping concentration of the semiconductor pattern 501 is not limited, and corresponding doping can be performed as required. Since the greater the doping concentration, the greater the improvement of the conductivity of the semiconductor pattern 501 , and thus the embodiment of the invention preferably heavily doping the semiconductor pattern 501 .
在此基础上，对于半导体图案501的掺杂类型不进行限定，可以是N型掺杂，也可以是P型掺杂。当半导体图案501的掺杂为N型掺杂时，可以掺入磷元素或锑元素；当半导体图案501的掺杂为P型掺杂时，可以掺入硼元素或铟元素。On this basis, the doping type of the semiconductor pattern 501 is not limited, it may be N-type doping or P-type doping. When the doping of the semiconductor pattern 501 is N-type doping, phosphorus element or antimony element can be doped; when the doping of the semiconductor pattern 501 is P-type doping, boron element or indium element can be doped.
需要说明的是，对半导体图案50进行掺杂的步骤，可以在形成半导体层之后，形成第一绝缘层之前；也可以在形成第一绝缘层之后，第一金属层之前。当在形成第一绝缘层之后，第一金属层之前，对半导体图案501进行掺杂时，由于离子注入需穿过第一绝缘图案301，而第一绝缘图案301的厚度一般达到这样就导致离子注入能量较高，因而本发明实施例优选，在形成第一绝缘层之前，对半导体图案501进行掺杂。It should be noted that the step of doping the semiconductor pattern 50 may be performed after forming the semiconductor layer and before forming the first insulating layer; or after forming the first insulating layer and before forming the first metal layer. When the semiconductor pattern 501 is doped after the formation of the first insulating layer and before the first metal layer, since the ion implantation needs to pass through the first insulating pattern 301, the thickness of the first insulating pattern 301 generally reaches This leads to higher ion implantation energy, and therefore, in the embodiment of the present invention, it is preferable to dope the semiconductor pattern 501 before forming the first insulating layer.
本发明实施例，对半导体图案501进行掺杂后，半导体图案501的导电性能会提高，进而使得半导体图案501和第一金属图案201或第二金属图案401形成的电容的电容值会增大。In the embodiment of the present invention, after the semiconductor pattern 501 is doped, the conductivity of the semiconductor pattern 501 will be improved, so that the capacitance of the capacitor formed by the semiconductor pattern 501 and the first metal pattern 201 or the second metal pattern 401 will increase.
优选的，上述制备方法还包括：在形成半导体层之后，形成第二绝缘层之前，对有源层图案701的源极接触区和漏极接触区进行第一次掺杂。Preferably, the above preparation method further includes: after forming the semiconductor layer and before forming the second insulating layer, doping the source contact region and the drain contact region of the active layer pattern 701 for the first time.
本领域技术人员应该明白，有源层图案701的源极接触区指的是有源层图案701与源极接触的区域，有源层图案701的漏极接触区指的是有源层图案701与漏极接触的区域。Those skilled in the art should understand that the source contact region of the active layer pattern 701 refers to the region where the active layer pattern 701 is in contact with the source, and the drain contact region of the active layer pattern 701 refers to the area of the active layer pattern 701. area in contact with the drain.
本发明实施例，对有源层图案701的源极接触区和漏极接触区进行第一次掺杂，有利于薄膜晶体管的快速打开和关闭。In the embodiment of the present invention, the source contact region and the drain contact region of the active layer pattern 701 are doped for the first time, which is beneficial to the rapid turn-on and turn-off of the thin film transistor.
在对有源层图案701的源极接触区和漏极接触区进行第一次掺杂之前，上述制备方法还包括：如图7所示，在有源层图案701上形成光刻胶图案100；沿栅极703的宽度方向，栅极703在有源层图案701上正投影的边界位于光刻胶图案100在有源层图案701上正投影的边界以内,且光刻胶图案100在有源层图案701上的正投影与有源层图案701的源极接触区和漏极接触区无重叠区域。在对有源层图案701的源极接触区和漏极接触区进行第一次掺杂之后，上述制备方法还包括：如图8所示，剥离光刻胶图案100。Before doping the source contact region and the drain contact region of the active layer pattern 701 for the first time, the above preparation method further includes: as shown in FIG. 7 , forming a photoresist pattern 100 on the active layer pattern 701 ; Along the width direction of the gate 703, the boundary of the positive projection of the gate 703 on the active layer pattern 701 is located within the boundary of the positive projection of the photoresist pattern 100 on the active layer pattern 701, and the photoresist pattern 100 is within the boundary of the positive projection of the photoresist pattern 701 The orthographic projection on the source layer pattern 701 has no overlapping area with the source contact region and the drain contact region of the active layer pattern 701 . After doping the source contact region and the drain contact region of the active layer pattern 701 for the first time, the above preparation method further includes: as shown in FIG. 8 , stripping the photoresist pattern 100 .
在形成第一金属层之后，形成第二绝缘层之前，上述制备方法还包括：如图9所示，以栅极703为掩膜，对有源层图案701进行第二次掺杂，第二次掺杂的掺杂浓度小于第一次掺杂的掺杂浓度。由于第二次掺杂的掺杂浓度小于第一次掺杂的掺杂浓度，因此也可以将第二次掺杂称为轻掺杂(Lightly Doped Drain，简称LDD)，第一次掺杂称为重掺杂。After forming the first metal layer and before forming the second insulating layer, the above preparation method further includes: as shown in FIG. The doping concentration of the secondary doping is smaller than that of the first doping. Since the doping concentration of the second doping is smaller than that of the first doping, the second doping can also be called light doping (Lightly Doped Drain, LDD for short), and the first doping is called for heavy doping.
参考图7，栅极703的宽度方向即指由左向右的方向或由右向左的方向。图10为对有源层图案701进行第一次掺杂和第二次掺杂之后形成的薄膜晶体管的结构示意图。Referring to FIG. 7 , the width direction of the gate 703 refers to the direction from left to right or from right to left. FIG. 10 is a schematic structural diagram of a thin film transistor formed after the first doping and the second doping are performed on the active layer pattern 701 .
此外，由于对有源层图案701的源极接触区和漏极接触区进行第一次掺杂的步骤可以在形成第一绝缘层之前；也可以在形成第一绝缘层之后，第一金属层之前；当然还可以在第一金属层之后，第二绝缘层之前，因此可以在有源层图案701上形成光刻胶图案100；也可以在栅绝缘层702上形成光刻胶图案100；当然还可以在栅极703上形成光刻胶图案100。当在形成第一金属层之前，对有源层图案701的源极接触区和漏极接触区进行第一次掺杂时，对有源层图案701的源极接触区和漏极接触区的掺杂和对半导体图案501的掺杂可以同时进行。In addition, since the step of doping the source contact region and the drain contact region of the active layer pattern 701 for the first time may be before forming the first insulating layer; or after forming the first insulating layer, the first metal layer Before; Of course, after the first metal layer, before the second insulating layer, so the photoresist pattern 100 can be formed on the active layer pattern 701; The photoresist pattern 100 can also be formed on the gate insulating layer 702; Of course A photoresist pattern 100 may also be formed on the gate electrode 703 . When doping the source contact region and the drain contact region of the active layer pattern 701 for the first time before forming the first metal layer, the source contact region and the drain contact region of the active layer pattern 701 Doping and doping of the semiconductor pattern 501 may be performed simultaneously.
需要说明的是，由于有源层图案701上形成有光刻胶图案100，因而在对有源层图案701进行离子注入时，有源层图案701中被光刻胶图案100遮挡的区域不能被进行第一次掺杂。而由于有源层图案701的源极接触区和漏极接触区未被光刻胶图案100遮挡，因此至少有源层图案701的源极接触区和漏极接触区被进行第一次掺杂。当薄膜晶体管的栅极703为双栅结构时，如图7所示，有源层图案701中与两个栅极703之间的区域正对的部分也可以被进行第一次掺杂。It should be noted that since the photoresist pattern 100 is formed on the active layer pattern 701, when ion implantation is performed on the active layer pattern 701, the area of the active layer pattern 701 that is blocked by the photoresist pattern 100 cannot be covered. Do the first doping. Since the source contact region and the drain contact region of the active layer pattern 701 are not blocked by the photoresist pattern 100, at least the source contact region and the drain contact region of the active layer pattern 701 are doped for the first time. . When the gate 703 of the thin film transistor has a double-gate structure, as shown in FIG. 7 , the part of the active layer pattern 701 directly opposite to the region between the two gates 703 may also be doped for the first time.
此处，沿栅极703的宽度方向，栅极703在有源层图案701上正投影的边界位于光刻胶图案100在有源层图案701上正投影的边界以内，第二次掺杂区域是以栅极703为掩膜对有源层图案701进行掺杂，第一次掺杂区域是以光刻胶图案100为掩膜对有源层图案701进行掺杂，由于第一次掺杂的掺杂浓度大于第二次掺杂的掺杂浓度，因而第二次掺杂的掺杂区域指的是第一次掺杂的掺杂区域与沟道区域(有源层图案701中与栅极703正对的区域)之间的区域，因此LDD区域的长度与沿栅极703的宽度方向，光刻胶图案100的长度有关。第二次掺杂区域即LDD区域的长度指的是源极接触区(或漏极接触区域)与沟道区域之间的距离，参考图9，LDD区域的长度为图9中的a。在有源层图案701中设置LDD区域的目的是为了让其承受部分电压，来降低开关TFT关闭后的漏电流。LDD区域的长度越长，降低漏电流的效果越明显。Here, along the width direction of the gate 703, the boundary of the positive projection of the gate 703 on the active layer pattern 701 is located within the boundary of the positive projection of the photoresist pattern 100 on the active layer pattern 701, and the second doping region The active layer pattern 701 is doped with the gate 703 as a mask, and the active layer pattern 701 is doped with the photoresist pattern 100 as a mask for the first doping region. The doping concentration is greater than the doping concentration of the second doping, so the doping region of the second doping refers to the doping region and the channel region (in the active layer pattern 701 and the gate region) of the first doping Therefore, the length of the LDD region is related to the length of the photoresist pattern 100 along the width direction of the gate 703 . The length of the second doped region, that is, the LDD region refers to the distance between the source contact region (or drain contact region) and the channel region. Referring to FIG. 9 , the length of the LDD region is a in FIG. 9 . The purpose of setting the LDD region in the active layer pattern 701 is to allow it to bear part of the voltage, so as to reduce the leakage current after the switching TFT is turned off. The longer the length of the LDD region, the more obvious the effect of reducing the leakage current.
在此基础上，本发明实施例对有源层图案701进行第一次掺杂和第二次掺杂的掺杂类型相同，均为P型掺杂或均为N型掺杂。On this basis, in the embodiment of the present invention, the doping types of the first doping and the second doping of the active layer pattern 701 are the same, both being P-type doping or both being N-type doping.
现有技术制作LDD区域的过程为先以第一栅极为掩膜对有源层图案701进行第一次掺杂，再对第一栅极进行刻蚀，使第一栅极的宽度减小以形成第二栅极，之后，以第二栅极为掩膜对有源层图案701进行第二次掺杂，从而形成LDD区域，LDD区域为刻蚀掉的第一栅极正对的区域。考虑到现有工艺以及栅极的性能，第一栅极的宽度不能太大，且第二栅极的宽度不能太小，因而第一栅极刻蚀掉的部分较少，从而使得LDD区域的长度较小。但是本发明实施例，对有源层图案701进行第一次掺杂时是以光刻胶图案100为掩膜，而沿栅极703的宽度方向，光刻胶图案100的长度可以任意设置，这样在剥离光刻胶图案100后以栅极703为掩膜，对有源层图案701进行第二次掺杂时，LDD区域的长度相对于现有技术增加，因而本发明实施例相对于现有技术可以更好地降低漏电流。The process of manufacturing the LDD region in the prior art is to do the first doping of the active layer pattern 701 with the first gate as a mask, and then etch the first gate to reduce the width of the first gate to The second gate is formed, and then the active layer pattern 701 is doped for the second time by using the second gate as a mask to form an LDD region, which is the region opposite to the etched first gate. Considering the existing process and the performance of the gate, the width of the first gate cannot be too large, and the width of the second gate cannot be too small, so that the first gate is etched away less, so that the LDD region The length is smaller. However, in the embodiment of the present invention, the photoresist pattern 100 is used as a mask when the active layer pattern 701 is doped for the first time, and the length of the photoresist pattern 100 can be set arbitrarily along the width direction of the gate 703. In this way, when the active layer pattern 701 is doped for the second time by using the gate electrode 703 as a mask after stripping the photoresist pattern 100, the length of the LDD region is increased compared with the prior art. There are techniques to better reduce leakage current.
进一步优选的，对有源层图案701的源极接触区和漏极接触区进行第一次掺杂的步骤是在形成第一绝缘层之前完成的。Further preferably, the first doping step of the source contact region and the drain contact region of the active layer pattern 701 is completed before forming the first insulating layer.
本发明实施例，由于在形成半导体层之后，形成第一绝缘层之前就对有源层图案701的源极接触区和漏极接触区进行第一次掺杂，这样在对有源层图案701的源极接触区和漏极接触区进行离子注入时没有任何膜层阻挡，从而可以降低离子注入的功耗。此外，若离子注入需穿过第一绝缘层，则离子注入时的能量会增加，这样一来，由于在对有源层图案701的源极接触区和漏极接触区进行第一次掺杂时需要形成光刻胶图案100，光刻胶图案100用于抵挡离子注入，离子注入的能量增加会导致光刻胶图案100的碳化效应更加严重，从而会使得剥离光刻胶图案100更困难，因此本发明实施例优选对有源层图案701的源极接触区和漏极接触区的步骤是在形成第一绝缘层之前完成的。In the embodiment of the present invention, since the source contact region and the drain contact region of the active layer pattern 701 are doped for the first time after the formation of the semiconductor layer and before the formation of the first insulating layer, the active layer pattern 701 There is no film barrier when the source contact region and the drain contact region are implanted, so that the power consumption of ion implantation can be reduced. In addition, if the ion implantation needs to pass through the first insulating layer, the energy of the ion implantation will increase. In this way, since the source contact region and the drain contact region of the active layer pattern 701 are doped for the first time When it is necessary to form a photoresist pattern 100, the photoresist pattern 100 is used to resist ion implantation, and the increase in the energy of ion implantation will lead to a more serious carbonization effect of the photoresist pattern 100, which will make it more difficult to strip the photoresist pattern 100, Therefore, in the embodiment of the present invention, it is preferable that the steps for the source contact region and the drain contact region of the active layer pattern 701 are completed before forming the first insulating layer.
优选的，在形成半导体层之后，形成第一绝缘层之前，上述制备方法还包括：对有源层图案701进行第三次掺杂(即Vth掺杂或Vth Doping)，第三次掺杂的掺杂浓度小于第二次掺杂的掺杂浓度。Preferably, after forming the semiconductor layer and before forming the first insulating layer, the above preparation method further includes: performing a third doping (ie Vth doping or Vth Doping) on the active layer pattern 701, the third doping The doping concentration is smaller than that of the second doping.
此处，第三次掺杂的掺杂类型与第一次掺杂的掺杂类型相反，若第一次掺杂为P型掺杂，则第三次掺杂为N型掺杂，这样可以形成PNP结；若第一次掺杂为N型掺杂，则第三次掺杂为P型掺杂，这样可以形成NPN结。Here, the doping type of the third doping is opposite to that of the first doping, if the first doping is P-type doping, then the third doping is N-type doping, so that Form a PNP junction; if the first doping is N-type doping, the third doping is P-type doping, so that an NPN junction can be formed.
由于本发明实施例对有源层图案701进行第三次掺杂，因而增加了显示区域薄膜晶体管中有源层图案701的载流子迁移率，减小了显示区域薄膜晶体管的阈值电压(Vth)，即薄膜晶体管的开启电压。Since the active layer pattern 701 is doped for the third time in the embodiment of the present invention, the carrier mobility of the active layer pattern 701 in the thin film transistor in the display area is increased, and the threshold voltage (Vth) of the thin film transistor in the display area is reduced. ), that is, the turn-on voltage of the thin film transistor.
本发明实施例还提供一种薄膜晶体管的制备方法，如图10和图11所示，包括：The embodiment of the present invention also provides a method for preparing a thin film transistor, as shown in FIG. 10 and FIG. 11 , including:
S200、在衬底基板10上形成有源层图案701。S200 , forming an active layer pattern 701 on the base substrate 10 .
其中，对于有源层图案701的材料不进行限定，例如可以是单晶硅、多晶硅或非晶硅。由于多晶硅的电子迁移率快，稳定性较高，因而本发明实施例优选，有源层图案701的材料为多晶硅。Wherein, the material of the active layer pattern 701 is not limited, for example, it may be single crystal silicon, polycrystalline silicon or amorphous silicon. Since polysilicon has fast electron mobility and high stability, it is preferable in this embodiment of the present invention that the material of the active layer pattern 701 is polysilicon.
此处，在衬底基板10上形成有源层图案701之前，上述制备方法还包括：在衬底基板10上依次形成光阻挡图案80和缓冲层90；其中，光阻挡图案80和待形成的栅极703在有源层图案701上的正投影具有重叠区域。形成光阻挡图案80的目的是为了减少沟道区域受到的光照，以避免影响薄膜晶体管的开关性能，造成漏电流。形成缓冲层90的目的是为了平坦衬底基板10，屏蔽衬底基板10的缺陷，防止杂质离子渗透到衬底基板10中引起器件的各种不良。Here, before forming the active layer pattern 701 on the base substrate 10, the above preparation method further includes: sequentially forming a light blocking pattern 80 and a buffer layer 90 on the base substrate 10; wherein, the light blocking pattern 80 and the to-be-formed The orthographic projection of the gate 703 on the active layer pattern 701 has an overlapping area. The purpose of forming the light blocking pattern 80 is to reduce the light received by the channel region, so as to avoid affecting the switching performance of the thin film transistor and causing leakage current. The purpose of forming the buffer layer 90 is to flatten the base substrate 10 , shield the defects of the base substrate 10 , and prevent impurity ions from penetrating into the base substrate 10 to cause various defects of the device.
S201、在有源层图案701上形成栅绝缘层702和栅极703。S201 , forming a gate insulating layer 702 and a gate 703 on the active layer pattern 701 .
其中，栅绝缘层702的材料可以选自但不限于氧化硅、氮化硅或氮氧化硅中的至少一种。Wherein, the material of the gate insulating layer 702 may be selected from but not limited to at least one of silicon oxide, silicon nitride or silicon oxynitride.
栅极703的材料可以选自但不限于铝、钛、钼、银、铬或其合金中的一种或多种的组合。本发明实施例优选栅极的材料为依次层叠设置的Mo/Al/Mo。The material of the gate 703 may be selected from, but not limited to, one or a combination of aluminum, titanium, molybdenum, silver, chromium or alloys thereof. In the embodiment of the present invention, the material of the gate electrode is preferably Mo/Al/Mo stacked in sequence.
此处，本发明实施例的栅极703可以是单栅极，也可以是双栅极。Here, the gate 703 in the embodiment of the present invention may be a single gate or a double gate.
S202、以栅极703为掩膜，对有源层图案701进行第二次掺杂。S202 , using the gate 703 as a mask, doping the active layer pattern 701 for the second time.
其中，有源层图案701中被栅极703遮挡的区域，即栅极703正对的区域不能被掺杂，有源层图案701中其它区域在第二次掺杂时可以被掺杂。Wherein, the region of the active layer pattern 701 covered by the gate 703 , that is, the region facing the gate 703 cannot be doped, and other regions of the active layer pattern 701 can be doped during the second doping.
S203、在栅极703上依次形成层间介电层704和源漏极705，源漏极705穿过层间介电层704和栅绝缘层702上的过孔与有源层图案701电连接。S203, forming an interlayer dielectric layer 704 and a source-drain electrode 705 in sequence on the gate 703, and the source-drain electrode 705 is electrically connected to the active layer pattern 701 through the via hole on the interlayer dielectric layer 704 and the gate insulating layer 702 .
其中，层间介电层704的材料可以选自但不限于氧化硅、氮化硅或氮氧化硅中的至少一种。Wherein, the material of the interlayer dielectric layer 704 may be selected from but not limited to at least one of silicon oxide, silicon nitride or silicon oxynitride.
源漏极705的材料可以选自但不限于铝、钛、钼、银、铬或其合金中的一种或多种的组合。The material of the source and drain electrodes 705 may be selected from, but not limited to, one or more combinations of aluminum, titanium, molybdenum, silver, chromium or alloys thereof.
基于上述，在形成有源层图案701之后，形成层间介电层704之前，上述制备方法还包括：S204、在有源层图案701上形成光刻胶图案100；沿栅极703的宽度方向，栅极703在有源层图案701上正投影的边界位于光刻胶图案100在有源层图案701上正投影的边界以内，且光刻胶图案100在有源层图案701上的正投影与有源层图案701的源极接触区和漏极接触区无重叠区域；以光刻胶图案100为掩膜，对有源层图案701进行第一次掺杂，第一次掺杂的掺杂浓度大于第二次掺杂的掺杂浓度；剥离光刻胶图案100。Based on the above, after forming the active layer pattern 701 and before forming the interlayer dielectric layer 704, the above preparation method further includes: S204, forming a photoresist pattern 100 on the active layer pattern 701; , the boundary of the positive projection of the gate 703 on the active layer pattern 701 is located within the boundary of the positive projection of the photoresist pattern 100 on the active layer pattern 701, and the positive projection of the photoresist pattern 100 on the active layer pattern 701 There is no overlapping area with the source contact region and the drain contact region of the active layer pattern 701; using the photoresist pattern 100 as a mask, the active layer pattern 701 is doped for the first time, and the first doped doping The impurity concentration is greater than the doping concentration of the second doping; the photoresist pattern 100 is stripped.
此处，步骤S204可以在形成有源层图案701之后，形成栅绝缘层702之前；也可以在形成栅绝缘层702之后，形成栅极703之前；当然还可以在形成栅极703之后，形成层间介电层704之前。Here, step S204 can be formed after forming the active layer pattern 701 and before forming the gate insulating layer 702; it can also be after forming the gate insulating layer 702 and before forming the gate 703; of course, it can also be formed after forming the gate 703. Before the inter-dielectric layer 704.
其中，由于第一次掺杂的掺杂浓度大于第二次掺杂的掺杂浓度，因而可以将第一次掺杂称为重掺杂，将第二次掺杂称为轻掺杂。第一次掺杂的区域称为重掺杂区域，重掺杂区域和沟道区域之间的区域称为轻掺杂区域。Wherein, since the doping concentration of the first doping is greater than that of the second doping, the first doping can be called heavy doping, and the second doping can be called light doping. The area doped for the first time is called a heavily doped area, and the area between the heavily doped area and the channel area is called a lightly doped area.
需要说明的是，在重掺杂区域和沟道区域之间设置LDD区域的目的是为了让其承受部分电压，来降低开关TFT关闭后的漏电流。LDD区域的长度越长，降低漏电流的效果越明显。It should be noted that the purpose of setting the LDD region between the heavily doped region and the channel region is to allow it to bear part of the voltage, so as to reduce the leakage current after the switching TFT is turned off. The longer the length of the LDD region, the more obvious the effect of reducing the leakage current.
本发明实施例，由于对有源层图案701进行第一次掺杂时是以光刻胶图案100为掩膜，而沿栅极703的宽度方向，光刻胶图案100的长度可以任意设置，这样在剥离光刻胶图案100后以栅极703为掩膜，对有源层图案701进行第二次掺杂时，LDD区域的长度相对于现有技术增加，因而本发明实施例相对于现有技术可以更好地降低漏电流。In the embodiment of the present invention, since the photoresist pattern 100 is used as a mask when the active layer pattern 701 is doped for the first time, the length of the photoresist pattern 100 can be set arbitrarily along the width direction of the gate 703, In this way, when the active layer pattern 701 is doped for the second time by using the gate electrode 703 as a mask after stripping the photoresist pattern 100, the length of the LDD region is increased compared with the prior art. There are techniques to better reduce leakage current.
由于在形成栅绝缘层702或栅极703之后，以光刻胶图案100为掩膜对有源层图案701进行第一次掺杂，离子注入时需穿过栅绝缘层702，这就导致离子注入时的能量会增加，这样一来，光刻胶图案100用于抵挡离子注入，离子注入的能量增加会导致光刻胶图案100的碳化效应更加严重，从而会使得剥离光刻胶图案100更困难，因此本发明实施例优选步骤S204在形成有源层图案701之后，形成栅绝缘层702之前完成。Since the active layer pattern 701 is doped for the first time using the photoresist pattern 100 as a mask after forming the gate insulating layer 702 or the gate electrode 703, the ion implantation needs to pass through the gate insulating layer 702, which leads to ion implantation. The energy of the implantation will increase, so that the photoresist pattern 100 is used to resist the ion implantation, and the increase of the energy of the ion implantation will cause the carbonization effect of the photoresist pattern 100 to be more serious, so that the stripping of the photoresist pattern 100 will be easier. Therefore, in this embodiment of the present invention, step S204 is preferably completed after forming the active layer pattern 701 and before forming the gate insulating layer 702 .
优选的，上述制备方法还包括：在形成有源层图案701之后，形成栅绝缘层702之前，对有源层图案701进行第三次掺杂；第三次掺杂的掺杂浓度小于第二次掺杂的掺杂浓度。Preferably, the above preparation method further includes: after forming the active layer pattern 701 and before forming the gate insulating layer 702, doping the active layer pattern 701 for a third time; the doping concentration of the third doping is lower than that of the second doping The doping concentration of the secondary doping.
其中，当在形成有源层图案701之后，形成栅绝缘层702之前，对有源层图案701进行第一次掺杂时，可以先进行第三次掺杂，再进行第一次掺杂；也可以先进行第一次掺杂，再进行第三次掺杂。本发明实施例优选，先进行第三次掺杂，再进行第一次掺杂。Wherein, when the active layer pattern 701 is doped for the first time after the active layer pattern 701 is formed and before the gate insulating layer 702 is formed, the third doping can be performed first, and then the first doping can be performed; It is also possible to perform the first doping first, and then perform the third doping. In the embodiment of the present invention, preferably, the third doping is performed first, and then the first doping is performed.
本发明实施例，对有源层图案701进行第三次掺杂的目的是为了增加了显示区域薄膜晶体管中有源层图案701的载流子迁移率，减小了显示区域薄膜晶体管的阈值电压，即薄膜晶体管的开启电压。In the embodiment of the present invention, the purpose of performing the third doping on the active layer pattern 701 is to increase the carrier mobility of the active layer pattern 701 in the thin film transistor in the display area and reduce the threshold voltage of the thin film transistor in the display area. , that is, the turn-on voltage of the thin film transistor.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810003125.8ACN108257975B (en) | 2018-01-02 | 2018-01-02 | Array substrate and preparation method thereof, display device and preparation method of thin film transistor |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810003125.8ACN108257975B (en) | 2018-01-02 | 2018-01-02 | Array substrate and preparation method thereof, display device and preparation method of thin film transistor |
| Publication Number | Publication Date |
|---|---|
| CN108257975Atrue CN108257975A (en) | 2018-07-06 |
| CN108257975B CN108257975B (en) | 2022-10-04 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810003125.8AActiveCN108257975B (en) | 2018-01-02 | 2018-01-02 | Array substrate and preparation method thereof, display device and preparation method of thin film transistor |
| Country | Link |
|---|---|
| CN (1) | CN108257975B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109116647A (en)* | 2018-09-17 | 2019-01-01 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display device |
| CN115224050A (en)* | 2022-06-30 | 2022-10-21 | 昆山国显光电有限公司 | Array substrate, preparation method and display panel |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1700269A (en)* | 2004-05-21 | 2005-11-23 | 株式会社半导体能源研究所 | display device |
| CN1874001A (en)* | 2005-05-28 | 2006-12-06 | 三星Sdi株式会社 | Flat panel display |
| TW200703651A (en)* | 2005-07-08 | 2007-01-16 | Au Optronics Corp | A pixel circuit of the display panel |
| CN101539691A (en)* | 2008-03-19 | 2009-09-23 | 统宝光电股份有限公司 | Image display system and method of manufacturing the same |
| US20120161820A1 (en)* | 2010-12-27 | 2012-06-28 | Bon-Yong Koo | Gate drive circuit, display substrate having the same and method of manufacturing the display substrate |
| CN203480182U (en)* | 2013-08-30 | 2014-03-12 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN104064688A (en)* | 2014-07-11 | 2014-09-24 | 深圳市华星光电技术有限公司 | Manufacturing method of TFT substrate with storage capacitor and the TFT substrate |
| CN104282696A (en)* | 2014-10-22 | 2015-01-14 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN104536223A (en)* | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and array substrate thereof |
| KR20150076391A (en)* | 2013-12-26 | 2015-07-07 | 엘지디스플레이 주식회사 | Organic light emitting display device |
| CN105225633A (en)* | 2014-06-20 | 2016-01-06 | 乐金显示有限公司 | Organic LED display device |
| CN105355631A (en)* | 2015-10-10 | 2016-02-24 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, display apparatus and mask plate |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1700269A (en)* | 2004-05-21 | 2005-11-23 | 株式会社半导体能源研究所 | display device |
| CN101976547A (en)* | 2004-05-21 | 2011-02-16 | 株式会社半导体能源研究所 | Display device |
| CN1874001A (en)* | 2005-05-28 | 2006-12-06 | 三星Sdi株式会社 | Flat panel display |
| TW200703651A (en)* | 2005-07-08 | 2007-01-16 | Au Optronics Corp | A pixel circuit of the display panel |
| CN101539691A (en)* | 2008-03-19 | 2009-09-23 | 统宝光电股份有限公司 | Image display system and method of manufacturing the same |
| US20120161820A1 (en)* | 2010-12-27 | 2012-06-28 | Bon-Yong Koo | Gate drive circuit, display substrate having the same and method of manufacturing the display substrate |
| CN203480182U (en)* | 2013-08-30 | 2014-03-12 | 京东方科技集团股份有限公司 | Array substrate and display device |
| KR20150076391A (en)* | 2013-12-26 | 2015-07-07 | 엘지디스플레이 주식회사 | Organic light emitting display device |
| CN105225633A (en)* | 2014-06-20 | 2016-01-06 | 乐金显示有限公司 | Organic LED display device |
| CN104064688A (en)* | 2014-07-11 | 2014-09-24 | 深圳市华星光电技术有限公司 | Manufacturing method of TFT substrate with storage capacitor and the TFT substrate |
| CN104282696A (en)* | 2014-10-22 | 2015-01-14 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN104536223A (en)* | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and array substrate thereof |
| CN105355631A (en)* | 2015-10-10 | 2016-02-24 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, display apparatus and mask plate |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109116647A (en)* | 2018-09-17 | 2019-01-01 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display device |
| CN115224050A (en)* | 2022-06-30 | 2022-10-21 | 昆山国显光电有限公司 | Array substrate, preparation method and display panel |
| Publication number | Publication date |
|---|---|
| CN108257975B (en) | 2022-10-04 |
| Publication | Publication Date | Title |
|---|---|---|
| CN101110429B (en) | Electronic device, display device, image display system and manufacturing method thereof | |
| US7800177B2 (en) | Thin film transistor plate and method of fabricating the same | |
| US10325938B2 (en) | TFT array substrate, method for manufacturing the same, and display device | |
| US8829511B2 (en) | Hybrid thin film transistor, manufacturing method thereof and display panel having the same | |
| US11133366B2 (en) | Array substrate and method of manufacturing the same, and display device | |
| CN105185816A (en) | Array substrate, manufacturing method, and display device | |
| CN106024633A (en) | Preparation methods of thin film transistor and array substrate, array substrate and display device | |
| US20220320269A1 (en) | Display device, array substrate, thin film transistor and fabrication method thereof | |
| CN108447822A (en) | Manufacturing method of LTPS TFT substrate | |
| WO2019200824A1 (en) | Method for manufacturing ltps tft substrate and ltps tft substrate | |
| CN111755462A (en) | Array substrate and manufacturing method thereof | |
| JP5328015B2 (en) | Image display system and manufacturing method thereof | |
| CN108257975B (en) | Array substrate and preparation method thereof, display device and preparation method of thin film transistor | |
| US7786480B2 (en) | System for displaying images including thin film transistor device and method for fabricating the same | |
| CN101399273B (en) | Image display system and manufacturing method thereof | |
| US9496294B2 (en) | Array substrate, manufacturing method and display device | |
| US20250098415A1 (en) | Thin-film transistor and manufacturing method thereof, array substrate and display device | |
| CN105514126A (en) | Array base plate and manufacturing method and display device thereof | |
| US10672912B2 (en) | N-type thin film transistor, manufacturing method thereof and manufacturing method of an OLED display panel | |
| US12336386B2 (en) | Display substrate and manufacturing method thereof, and display device | |
| CN115440823A (en) | Thin film transistor, preparation method, array substrate and display device | |
| WO2022083430A1 (en) | Display panel, manufacturing method for display panel, and electronic device | |
| WO2017181698A1 (en) | Array substrate, and display device, and fabrication methods | |
| CN102222644A (en) | A method of manufacturing an active matrix organic light emitting diode device | |
| CN113113428A (en) | Array substrate and preparation method thereof |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |