CN108257855B - Preparation method of high-k gate dielectric layer and silicon carbide MOS power device - Google Patents

Abstract

The invention provides a preparation method of a high-k gate dielectric layer and a silicon carbide MOS power device, wherein the preparation method comprises the steps of carrying out high-temperature sacrificial oxidation on a silicon carbide epitaxial wafer with a first conduction type, and forming a sacrificial oxide layer on the upper surface of an epitaxial layer; corroding the sacrificial oxide layer until the sacrificial oxide layer on the epitaxial layer is completely removed; performing high-temperature surfacing treatment on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed to form a smooth passivated surface; sequential deposition of Al on smooth passivated surfaces₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Dielectric coating, and to Al₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃And annealing the laminated structure formed by the dielectric coating to form the high-k gate dielectric layer. Compared with the prior art, the preparation method of the high-k gate dielectric layer and the silicon carbide MOS power device provided by the invention can reduce SiC/SiO₂Interface defects caused by impurities and/or surface lattice defects at the interface improve the pressure resistance of the gate dielectric layer.

Description

Preparation method of high-k gate dielectric layer and silicon carbide MOS power device

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to a preparation method of a high-k gate dielectric layer and a silicon carbide MOS power device.

Background

The silicon carbide semiconductor material has wider forbidden band width (3.2eV), higher breakdown electric field intensity (2.2MV/cm) and higher high saturated electron migration rate (2.0 multiplied by 10)⁷cm/s), higher high thermal conductivity (5.0W/cm K), excellent physical and chemical stability, etc., and is suitable for manufacturing high-power, high-voltage, high-working-temperature, high-working-frequency power semiconductor devices, while silicon carbide is the only compound semiconductor material with the characteristic of generating dense SiO by oxidation₂The capability of the dielectric layer enables the silicon carbide process to have higher process compatibility and maturity with the conventional CMOS process, and also enables the silicon carbide MOS power device to be manufactured to have a more mature manufacturing process.

A mosfet is a widely used type of power device that provides a control signal to a gate electrode that separates the semiconductor surfaces by an intervening insulator, which may be silicon dioxide (SiO)₂). The current conduction is performed by the transport of majority carriers without the need for minority carrier injection when the bipolar transistor is in operation. Meanwhile, the silicon carbide MOS power device can provide a very large safe operating area, and a plurality of unit structures can be used in parallel. However, silicon carbide has the following drawbacks:

1. oxygen gasFormation of SiO by conversion of silicon carbide₂During oxidation, carbon residues in the form of dangling bonds and clusters may occur, resulting in SiC/SiO₂There is a higher density of interface states at the interface.

2. The crystal lattice of the silicon carbide has anisotropic characteristics, and the oxidation rate of the silicon carbide has strong anisotropy, so that the problem of uneven thickness of oxide layers of different crystal planes is caused;

3、SiO₂dielectric constant K of the dielectric material_OXThe value is only 3.9, so that SiC/SiO₂SiO in the distribution of interface electric field strength₂Higher electric field strengths occur on the sides, limiting the high breakdown electric field strength of silicon carbide.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a preparation method of a high-k gate dielectric layer and a silicon carbide MOS power device.

In a first aspect, the technical solution of the method for preparing a high-k gate dielectric layer in the present invention is:

the preparation method comprises the following steps:

performing high-temperature sacrificial oxidation on a silicon carbide epitaxial wafer with a first conduction type to form a sacrificial oxide layer on the upper surface of an epitaxial layer;

corroding the sacrificial oxide layer until the sacrificial oxide layer on the epitaxial layer is completely removed;

performing high-temperature surfacing treatment on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed to form a smooth passivated surface;

depositing Al on said smooth passivated surface in sequence₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Dielectric coating of said Al₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃And annealing the laminated structure formed by the dielectric coating to form the high-k gate dielectric layer.

In a second aspect, a technical solution of a silicon carbide MOS power device in the present invention is:

the silicon carbide MOS power device comprises:

the epitaxial silicon carbide wafer comprises a silicon carbide substrate and an epitaxial layer, wherein the silicon carbide substrate and the epitaxial layer are both provided with a first conduction type; wherein: the upper surface of the epitaxial layer is a smooth passivated surface formed after the high-temperature surfacing treatment is carried out on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed;

a high-k gate dielectric layer disposed on the smooth passivated surface, the high-k gate dielectric layer comprising stacked Al₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃And (4) coating the medium.

Compared with the closest prior art, the invention has the beneficial effects that:

1. according to the preparation method of the high-k gate dielectric layer, provided by the invention, after the silicon carbide epitaxial wafer is subjected to high-temperature sacrificial oxidation to form the sacrificial oxide layer, the sacrificial oxide layer is completely corroded and removed, the lattice damage and organic, metal and nonmetal contamination on the surface and near surface of the silicon carbide epitaxial wafer can be eliminated, the impurity content in the silicon carbide epitaxial wafer oxide layer and the SiC/SiO₂Interface defects (interface states) at the interface due to impurities and/or surface lattice defects; the high-temperature surface treatment of the silicon carbide epitaxial wafer is beneficial to reducing SiC/SiO₂Interface defects (interface states) caused by surface roughness at the interface improve the mobility of a carrier channel; depositing a high-k gate dielectric layer on the smooth passivated surface, and LaAlO₃The k value of (A) is in the range of 23-30, the forbidden band width is 5.5-6 eV, and Al₂O₃The k value range of the gate dielectric layer is 9-10, and the forbidden band width is 8.7-8.8 eV, so that the high-k gate dielectric layer has higher k value and forbidden band width, and the voltage endurance capability of the gate dielectric layer can be improved;

2. according to the silicon carbide MOS power device, the epitaxial layer of the silicon carbide epitaxial wafer is provided with the smooth passivated surface, the passivated surface is formed by performing high-temperature surfacing treatment on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed, the removal of the sacrificial oxide layer can eliminate lattice damage and organic, metal and nonmetal contamination on the surface and near the surface of the silicon carbide epitaxial wafer, and the reduction of organic, metal and nonmetal contamination is facilitatedImpurity content in oxide layer of epitaxial wafer of silicon carbide less, and SiC/SiO₂Interface defects (interface states) at the interface due to impurities and/or surface lattice defects, while the high temperature surfacing process helps to reduce SiC/SiO₂Interface defects (interface states) caused by surface roughness at the interface improve the mobility of a carrier channel; LaAlO₃The k value range of (1) is 17-25, the forbidden band width is 6-7 eV, and Al₂O₃The k value range of the gate dielectric layer is 9-10, and the forbidden band width is 8.7-8.8 eV, so that the high-k gate dielectric layer has higher k value and forbidden band width, and the voltage endurance capability of the gate dielectric layer can be improved.

Drawings

FIG. 1: the embodiment of the invention provides a preparation method of a high-k gate dielectric layer, which comprises the following steps of implementing a flow chart;

FIG. 2: the structure of the silicon carbide epitaxial wafer in the embodiment of the invention is shown schematically;

FIG. 3: in the embodiment of the invention, the well region, the source electrode contact region and the base electrode contact region of the silicon carbide epitaxial wafer are schematically illustrated;

FIG. 4: the schematic diagram of the sacrificial oxide layer of the silicon carbide epitaxial wafer in the embodiment of the invention;

FIG. 5: the passivation surface of a silicon carbide epitaxial wafer in the embodiment of the invention is schematically shown;

FIG. 6: the high-k gate dielectric layer of the silicon carbide epitaxial wafer in the embodiment of the invention is shown schematically;

FIG. 7: FIG. 6 is a schematic diagram of the structure of the high-k gate dielectric layer shown prior to annealing;

FIG. 8: FIG. 6 is a schematic diagram of the structure after annealing of the high-k gate dielectric layer;

FIG. 9: a schematic structural view of another silicon carbide epitaxial wafer according to an embodiment of the present invention;

FIG. 10: another schematic diagram of a base contact region and a trench region of a silicon carbide epitaxial wafer in an embodiment of the invention;

FIG. 11: the schematic diagram of the sacrificial oxide layer of another silicon carbide epitaxial wafer in the embodiment of the invention;

FIG. 12: a schematic view of a passivated surface of another silicon carbide epitaxial wafer in an embodiment of the invention;

FIG. 13: another high-k gate dielectric layer of a silicon carbide epitaxial wafer according to an embodiment of the present invention;

FIG. 14: FIG. 13 is a schematic diagram of the structure of the high-k gate dielectric layer shown prior to annealing;

FIG. 15: figure 13 is a schematic diagram of the structure after annealing of the high-k gate dielectric layer;

FIG. 16: the structure of another silicon carbide epitaxial wafer in the embodiment of the invention is shown schematically;

FIG. 17: in another embodiment of the present invention, a well region, a source contact region and a base contact region of a silicon carbide epitaxial wafer are schematically illustrated;

FIG. 18: in another embodiment of the present invention, a schematic diagram of a sacrificial oxide layer of a silicon carbide epitaxial wafer is provided;

FIG. 19: a schematic view of a passivated surface of another silicon carbide epitaxial wafer according to an embodiment of the present invention;

FIG. 20: the high-k gate dielectric layer of another silicon carbide epitaxial wafer in the embodiment of the invention is shown schematically;

FIG. 21: FIG. 20 is a schematic diagram of the structure of the high-k gate dielectric layer shown prior to annealing;

FIG. 22: FIG. 20 is a schematic diagram of the structure of the high-k gate dielectric layer shown prior to annealing;

wherein, 101: an n-type silicon carbide substrate; 102: an n-type silicon carbide epitaxial layer; 110: an n-type silicon carbide epitaxial wafer; 111: a p-type well region; 112: an n-type source contact region; 113: a p-type base contact region; 121: sacrificing the oxide layer; 131: passivating the surface; 140: a high-k gate dielectric layer before annealing; 141: al before annealing₂O₃A dielectric coating; 150: LaAlO before annealing₃A dielectric layer; 151: la₂O₃A nanolayer; 152: al (Al)₂O₃A nanolayer; 160: annealing the high-k dielectric layer; 161: al after annealing₂O₃A dielectric coating; 162: LaAlO after annealing₃A dielectric layer; high-k gate dielectric layer 201: an n-type silicon carbide substrate; 202: an n-type silicon carbide epitaxial layer; 203: a p-type silicon carbide epitaxial layer; 204: an n-type silicon carbide epitaxial layer; 210: an n-type silicon carbide epitaxial wafer; 211: a p-type base contact region; 212: a trench region; 221: sacrificing the oxide layer; 231: passivating the surface; 240: a high-k gate dielectric layer before annealing; 241: al before annealing₂O₃A dielectric coating; 250: LaAlO before annealing₃A dielectric layer; 251: la₂O₃A nanolayer; 252: al (Al)₂O₃A nanolayer; 260: annealing the high-k dielectric layer; 261: al after annealing₂O₃A dielectric coating; 262: LaAlO after annealing₃A dielectric layer; 301: a semi-insulating silicon carbide substrate; 302: an n-type silicon carbide epitaxial layer; 310: an n-type silicon carbide epitaxial wafer; 312: an n-type source contact region; 313: a p-type base contact region; 321: sacrificing the oxide layer; 331: passivating the surface; 340: a high-k gate dielectric layer before annealing; 341: al before annealing₂O₃A dielectric coating; 350: LaAlO before annealing₃A dielectric layer; 351: la₂O₃A nanolayer; 352: al (Al)₂O₃A nanolayer; 360: annealing the high-k dielectric layer; 361: al after annealing₂O₃A dielectric coating; 362: LaAlO after annealing₃A dielectric layer; and a high-k gate dielectric layer.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The following describes a method for manufacturing a high-k gate dielectric layer according to an embodiment of the present invention with reference to the accompanying drawings.

In this embodiment, the high-k gate dielectric layer may be prepared according to the following steps:

step S101: and carrying out high-temperature sacrificial oxidation on the silicon carbide epitaxial wafer with the first conductivity type to form a sacrificial oxide layer on the upper surface of the epitaxial layer.

Step S102: and etching the sacrificial oxide layer until the sacrificial oxide layer on the epitaxial layer is completely removed.

Step S103: and carrying out high-temperature surfacing treatment on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed to form a smooth passivated surface.

Step S104: sequential deposition of Al on smooth passivated surfaces₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Dielectric coating of said Al₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃And annealing the laminated structure formed by the dielectric coating to form the high-k gate dielectric layer.

In this embodiment, after the silicon carbide epitaxial wafer is subjected to high-temperature sacrificial oxidation to form the sacrificial oxide layer, the sacrificial oxide layer is completely corroded and removed, so that lattice damage and organic, metal and nonmetal contamination on the surface and near the surface of the silicon carbide epitaxial wafer can be eliminated, and the reduction of impurity content in the silicon carbide epitaxial wafer oxide layer and the reduction of SiC/SiO₂Interface defects (interface states) at the interface due to impurities and/or surface lattice defects; the high-temperature surface treatment of the silicon carbide epitaxial wafer is beneficial to reducing SiC/SiO₂Interface defects (interface states) caused by surface roughness at the interface improve the mobility of a carrier channel; depositing a high-k gate dielectric layer on the smooth passivated surface, and LaAlO₃The k value range of (1) is 17-25, the forbidden band width is 6-7 eV, and Al₂O₃The k value range of the gate dielectric layer is 9-10, and the forbidden band width is 8.7-8.8 eV, so that the high-k gate dielectric layer has higher k value and forbidden band width, and the voltage endurance capability of the gate dielectric layer can be improved.

Further, step S101 in this embodiment may further include the following steps, specifically:

1. an epitaxial layer having a first conductivity type is formed on a front surface of the silicon carbide epitaxial wafer.

2. And after the silicon carbide epitaxial wafer is cleaned, ions are implanted into the epitaxial layer to form a well region. Wherein: in this embodiment, the cleaning step is to sequentially perform Piranha process cleaning, RCA process cleaning, and DHF process cleaning on the silicon carbide epitaxial wafer.

3. And implanting ions into the well region to form a source contact region and a base contact region respectively, and annealing the silicon carbide epitaxial wafer under the protective mask and inert gas environment. Wherein: the annealing temperature is 1500-2100 ℃, and the annealing time is 10-30 min.

4. And cleaning the annealed silicon carbide epitaxial wafer. Wherein: in this embodiment, the cleaning step is to sequentially perform Piranha process cleaning, RCA process cleaning, and DHF process cleaning on the silicon carbide epitaxial wafer.

5. The high-temperature sacrificial oxidation is carried out on the silicon carbide epitaxial wafer, and the method specifically comprises the following steps: by using a box furnace or a tube furnace in oxygen O₂And (3) carrying out high-temperature sacrificial oxidation on the silicon carbide epitaxial wafer in the environment. Wherein: the oxidation temperature of the high-temperature sacrificial oxidation is 1200-1500 ℃, the oxidation time is 10-30 min, and oxygen O₂Has a purity of 6N, oxygen O₂The flow rate of (2) is 0.1 to 10 slm.

Further, step S101 in this embodiment may further include the following steps, specifically:

1. and sequentially forming a first epitaxial layer with a first conductivity type, a second epitaxial layer with a second conductivity type and a third epitaxial layer with the first conductivity type on the front surface of the silicon carbide epitaxial wafer from bottom to top.

2. And after the silicon carbide epitaxial wafer is cleaned, ions are injected into the third epitaxial layer to form a base contact region. Wherein: in this embodiment, the cleaning step is to sequentially perform Piranha process cleaning, RCA process cleaning, and DHF process cleaning on the silicon carbide epitaxial wafer.

3. And annealing the silicon carbide epitaxial wafer under the protective mask and inert gas environment. Wherein: the annealing temperature is 1500-2100 ℃, and the annealing time is 10-30 min.

4. And etching the first epitaxial layer, the second epitaxial layer and the third epitaxial layer to form a groove region. Wherein: the trench region penetrates through the first epitaxial layer and the second epitaxial layer, and the depth of the trench region is smaller than the sum of the junction depths of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer. In this embodiment, an ICP plasma etching method based on an F-based gas or a Cl-based gas may be employed, wherein the mask is a silicon oxide mask.

5. And cleaning the silicon carbide epitaxial wafer after the groove region is formed. Wherein: in this embodiment, the cleaning step is to sequentially perform Piranha process cleaning, RCA process cleaning, and DHF process cleaning on the silicon carbide epitaxial wafer.

6. The high-temperature sacrificial oxidation is carried out on the silicon carbide epitaxial wafer, and the method specifically comprises the following steps: by using a box furnace or a tube furnace in oxygen O₂And (3) carrying out high-temperature sacrificial oxidation on the silicon carbide epitaxial wafer in the environment. Wherein: the oxidation temperature of the high-temperature sacrificial oxidation is 1200-1500 ℃, the oxidation time is 10-30 min, and oxygen O₂Has a purity of 6N, oxygen O₂The flow rate of (2) is 0.1 to 10 slm.

Further, step S102 in this embodiment may further include the following steps, specifically: and corroding the sacrificial oxide layer by adopting wet corrosion at normal temperature. Wherein: the etching solution of the wet etching is BOE etching solution or DHF solution with the concentration of 1-50%, and the BOE etching solution can adopt conventional BOE etching solution.

Further, step S103 in this embodiment may further include the following steps, specifically: by using box-type or tube-type furnaces in hydrogen H₂And performing high-temperature surfacing treatment on the upper surface of the epitaxial layer under the environment. Wherein: the temperature of the high-temperature surface treatment is 1000-2000 ℃, the time is 0.1-4H, and the hydrogen H₂Has a purity of 6N, hydrogen H₂The flow rate of (2) is 0.1 to 10 slm.

Further, step S104 in this embodiment may further include the following steps, specifically:

1. deposition of Al on smooth passivated surfaces using ALD₂O₃A dielectric coating; wherein: the reaction precursor of the ALD method is trimethylaluminum TMA, and the oxidant precursor is ozone O₃The temperature range is 100-35 ℃.

2. In Al₂O₃Depositing LaAlO on the dielectric coating₃The dielectric layer specifically comprises: atomic Layer Deposition (ALD) on Al₂O₃Alternately depositing La on the dielectric coating₂O₃Nanolayer and Al₂O₃A nanolayer; wherein: depositing La₂O₃The reaction precursor of the nano layer is La (ⁱPrCp)₃The oxidant precursor is ozone O₃The temperature is 200-350 ℃; deposition of Al₂O₃The reaction precursor of the nano layer is trimethyl aluminum TMA, and the oxidant precursor is ozone O₃The temperature range is 200-400 ℃. In the embodiment, La can be adjusted₂O₃Nanolayer and Al₂O₃Relative distance between nanolayers such that LaAlO₃The chemical equivalent ratio of lanthanum element to aluminum element in the dielectric layer is 1: 1.

3. Applying ALD method on LaAlO₃Depositing Al on the dielectric layer₂O₃A dielectric coating; wherein: the reaction precursor of the ALD method is trimethylaluminum TMA, and the oxidant precursor is ozone O₃The temperature range is 100-35 ℃.

4. Adopting a rapid thermal annealing device and in nitrogen N₂Argon Ar or nitrous oxide N₂For Al in O environment₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Annealing the laminated structure formed by the dielectric coating; wherein: the annealing temperature is 800-1200 ℃, and the annealing time is 10-60 s.

Based on the above preparation method, the present invention further provides three embodiments of the preparation method of the high-k gate dielectric layer, and each embodiment is described below with reference to the accompanying drawings.

Example 1

Step S201: preparation of silicon carbide epitaxial wafer

Fig. 2 is a schematic structural diagram of a silicon carbide epitaxial wafer in an embodiment of the present invention, and as shown in the drawing, the siliconcarbide epitaxial wafer 110 in this embodiment includes an n-typesilicon carbide substrate 101 and an n-type siliconcarbide epitaxial layer 102.

Step S202: preparing well region, source contact region and base contact region

Fig. 3 is a schematic diagram of a well region, a source contact region and a base contact region of a silicon carbide epitaxial wafer according to an embodiment of the present invention, in which p-type ions are doped into an n-type siliconcarbide epitaxial layer 102 to form a p-type well region 111, and p-type ions and n-type ions are doped into the p-type well region 111 to form an n-typesource contact region 112 and a p-typebase contact region 113, respectively.

Step S203: preparation of sacrificial oxide layer

Fig. 4 is a schematic view of a sacrificial oxide layer of a silicon carbide epitaxial wafer according to an embodiment of the present invention, wherein in this embodiment, a high temperature sacrificial oxidation is performed on a siliconcarbide epitaxial wafer 110 to form asacrificial oxide layer 121 on an n-type siliconcarbide epitaxial layer 102.

Step S204: preparation of passivated surfaces

Fig. 5 is a schematic view of a passivated surface of a silicon carbide epitaxial wafer according to an embodiment of the invention, in which thesacrificial oxide layer 121 is etched until thesacrificial oxide layer 121 is completely removed. The upper surface ofepitaxial layer 102 after removal ofsacrificial oxide layer 121 is then subjected to a high temperature surfacing process to form a smooth passivatedsurface 131.

Step S205: preparation of high-k gate dielectric layer

FIG. 6 is a schematic view of a high-k gate dielectric layer of an epitaxial silicon carbide wafer according to an embodiment of the present invention, in which Al is deposited on thesmooth passivation surface 131 in sequence₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Dielectric coating, and to Al₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃And annealing the laminated structure formed by the dielectric coating to form the high-kgate dielectric layer 140.

FIG. 7 is a schematic structural diagram of the high-kgate dielectric layer 140 shown in FIG. 6 before annealing, in this embodiment, the high-k gate dielectric layer includes Al₂O₃Dielectric capping layer 141 and LaAlO₃Dielectric layer 150, LaAlO₃Dielectric layer 150 comprises La₂O₃Nanolayer 151 and Al₂O₃Ananolayer 152.

FIG. 8 is a schematic structural diagram of the high-k gate dielectric layer shown in FIG. 6 after annealing, wherein the high-kgate dielectric layer 160 in this embodiment comprises Al₂O₃Dielectric cap layer 161 and LaAlO₃A dielectric layer 162.

Example 2

Step S301: preparation of silicon carbide epitaxial wafer

Fig. 9 is a schematic structural diagram of another silicon carbide epitaxial wafer in this embodiment of the present invention, and as shown in the drawing, the siliconcarbide epitaxial wafer 210 in this embodiment includes an n-typesilicon carbide substrate 201, an n-type siliconcarbide epitaxial layer 202, a p-type siliconcarbide epitaxial layer 203, and an n-type siliconcarbide epitaxial layer 204.

Step S302: preparing base contact region and trench region

Fig. 10 is a schematic view of a base contact region and a trench region of another silicon carbide epitaxial wafer according to an embodiment of the present invention, where p-type ions are doped into the n-type siliconcarbide epitaxial layer 204 to form abase contact region 211, and the n-type siliconcarbide epitaxial layer 202, the p-type siliconcarbide epitaxial layer 203, and the n-type siliconcarbide epitaxial layer 204 are etched to form atrench region 212 in this embodiment.

Step S303: preparation of sacrificial oxide layer

Fig. 11 is a schematic view of a sacrificial oxide layer of another silicon carbide epitaxial wafer according to an embodiment of the present invention, in which a high-temperature sacrificial oxidation is performed on a siliconcarbide epitaxial wafer 210 to form asacrificial oxide layer 221 on the siliconcarbide epitaxial wafer 210.

Step S304: preparation of passivated surfaces

Fig. 12 is a schematic view of a passivated surface of another sic epitaxial wafer according to an embodiment of the invention, in which thesacrificial oxide layer 221 is etched until thesacrificial oxide layer 221 is completely removed. The upper surface of the siliconcarbide epitaxial wafer 210 after removal of thesacrificial oxide layer 221 is then subjected to a high temperature surfacing process to form a smooth passivatedsurface 231.

Step S305: preparation of high-k gate dielectric layer

FIG. 13 is a schematic view of a high-k gate dielectric layer of an epitaxial wafer of silicon carbide according to an embodiment of the present invention, in which Al is deposited sequentially on the smooth passivatedsurface 231 according to this embodiment₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Dielectric coating, and to Al₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃And annealing the laminated structure formed by the dielectric coating to form the high-kgate dielectric layer 240.

FIG. 14 is the drawing of FIG. 13The structure of the high-k gate dielectric layer before annealing is schematically shown, and as shown in the figure, the high-kgate dielectric layer 240 in this embodiment comprises Al₂O₃Dielectric capping layer 241 and LaAlO₃Dielectric layer 250, LaAlO₃Dielectric layer 250 comprises La₂O₃Nanolayer 251 and HfO₂Thenanolayer 252.

FIG. 15 is a schematic structural diagram of the high-k gate dielectric layer shown in FIG. 13 after annealing, wherein the high-kgate dielectric layer 260 in this embodiment comprises Al₂O₃Dielectric overcoat 261 and LaAlO₃Adielectric layer 262.

Example 3

Step S401: preparation of silicon carbide epitaxial wafer

Fig. 16 is a schematic structural diagram of another silicon carbide epitaxial wafer in this embodiment of the present invention, and as shown in the drawing, the siliconcarbide epitaxial wafer 310 in this embodiment includes a semi-insulatingsilicon carbide substrate 301 and an n-type siliconcarbide epitaxial layer 302.

Step S402: preparing well region, source contact region and base contact region

Fig. 17 is a schematic diagram of a well region, a source contact region and a base contact region of another sic epitaxial wafer according to an embodiment of the present invention, in which p-type ions are doped into an n-typesic epitaxial layer 302 to form a p-type well region 311, and p-type ions and n-type ions are doped into the p-type well region 311 to form an n-typesource contact region 312 and a p-typebase contact region 313, respectively.

Step S403: preparation of sacrificial oxide layer

Fig. 18 is a schematic view of a sacrificial oxide layer of another silicon carbide epitaxial wafer according to an embodiment of the present invention, wherein in this embodiment, a high temperature sacrificial oxidation is performed on the siliconcarbide epitaxial wafer 210 to form asacrificial oxide layer 321 on the n-type siliconcarbide epitaxial layer 302.

Step S404: preparation of passivated surfaces

FIG. 19 is a schematic illustration of a passivated surface of another SiC epitaxial wafer in accordance with an embodiment of the invention, wherein thesacrificial oxide 321 is etched until thesacrificial oxide 321 is completely removed. The upper surface ofepitaxial layer 302 aftersacrificial oxide layer 321 is removed is then subjected to a high temperature surfacing process to form a smooth passivatedsurface 331.

Step S405: preparation of high-k gate dielectric layer

FIG. 20 is a schematic view of a high-k gate dielectric layer of an epitaxial wafer of silicon carbide according to an embodiment of the present invention, in which Al is deposited sequentially on a smooth passivatedsurface 331 as shown₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Dielectric coating, and to Al₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃And annealing the laminated structure formed by the dielectric coating to form the high-kgate dielectric layer 340.

FIG. 21 is a schematic structural diagram of the high-kgate dielectric layer 340 shown in FIG. 20 before annealing, in this embodiment, the high-k gate dielectric layer includes Al₂O₃Dielectric capping layer 341 and LaAlO₃Dielectric layer 350, LaAlO₃Dielectric layer 350 comprises La₂O₃Nanolayer 351 and HfO₂Ananolayer 352.

FIG. 22 is a schematic structural diagram of the high-k gate dielectric layer of FIG. 20 after annealing, wherein the high-kgate dielectric layer 360 in this embodiment comprises Al₂O₃Dielectric coating 361 and LaAlO₃Adielectric layer 362.

The invention also provides a silicon carbide MOS power device and provides a specific embodiment.

The silicon carbide MOS power device in the embodiment comprises a silicon carbide epitaxial wafer and a high-k gate dielectric layer.

Wherein: the silicon carbide epitaxial wafer comprises a silicon carbide substrate and an epitaxial layer which have the same conductivity type at the same time, and the epitaxial layer is arranged on the front surface of the silicon carbide substrate. In this embodiment, the upper surface of the epitaxial layer is a smooth passivated surface formed after the high-temperature surfacing treatment is performed on the upper surface of the epitaxial layer from which the sacrificial oxide layer is removed.

A high-k gate dielectric layer is disposed on the smooth passivated surface of the epitaxial layer. In this embodiment, the high-k gate dielectric layer comprises stacked Al layers₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃And (4) coating the medium.

Carbon in this exampleThe epitaxial layer of the silicon carbide epitaxial wafer has a smooth passivated surface formed by high-temperature surfacing of the upper surface of the epitaxial layer after removal of the sacrificial oxide layer, which can eliminate lattice damage and organic, metallic and non-metallic contamination on and near the surface of the silicon carbide epitaxial wafer, help to reduce the impurity content in the silicon carbide epitaxial wafer oxide layer, and SiC/SiO₂Interface defects (interface states) at the interface due to impurities and/or surface lattice defects, while the high temperature surfacing process helps to reduce SiC/SiO₂Interface defects (interface states) caused by surface roughness at the interface improve the mobility of a carrier channel; LaAlO₃The k value range of (1) is 17-25, the forbidden band width is 6-7 eV, and Al₂O₃The k value range of the gate dielectric layer is 9-10, and the forbidden band width is 8.7-8.8 eV, so that the high-k gate dielectric layer has higher k value and forbidden band width, and the voltage endurance capability of the gate dielectric layer can be improved.

Further, in this embodiment, the silicon carbide substrate may be a silicon carbide substrate, specifically:

in the embodiment, the silicon carbide substrate is 4H-SiC or 6H-SiC, and the thickness of the silicon carbide substrate is 300-1000 μm or 10-400 μm. Meanwhile, the silicon carbide substrate can be a silicon carbide substrate heavily doped with nitrogen ions N or phosphorus ions P, and the resistivity is 0.001-0.1 omega cm. Alternatively, the silicon carbide substrate may be a silicon carbide substrate doped with vanadium ions V or not doped with any ions, and the resistivity is greater than 105 Ω · cm.

Further, in this embodiment, the epitaxial layer may be the following epitaxial layer, specifically:

the epitaxial layer in this embodiment may comprise a silicon carbide epitaxial layer. Wherein: the silicon carbide epitaxial layer is 4H-SiC or 6H-SiC, and the thickness of the silicon carbide epitaxial layer is 2-300 mu m. Meanwhile, the silicon carbide epitaxial layer may be a silicon carbide epitaxial layer doped with nitrogen ions N or phosphorus ions P, and the doping concentration of the silicon carbide epitaxial layer is 1 × 10¹³～1×10¹⁶cm^-3。

In this embodiment, the epitaxial layers may also include a first silicon carbide epitaxial layer, a second silicon carbide epitaxial layer, and a third silicon carbide epitaxial layer, which are sequentially disposed on the silicon carbide substrate from bottom to top. Wherein: the first silicon carbide epitaxial layer, the second silicon carbide epitaxial layer and the third silicon carbide epitaxial layer are all 4H-SiC or 6H-SiC. At the same time, the user can select the desired position,

the first silicon carbide epitaxial layer is doped with nitrogen ions N or phosphorus ions P and has a doping concentration of 1 × 10¹³～1×10¹⁶cm^-3The thickness is 2 to 300 μm.

The second silicon carbide epitaxial layer is a silicon carbide epitaxial layer doped with aluminum ions Al or boron ions B, and the doping concentration of the second silicon carbide epitaxial layer is 1 multiplied by 10¹⁵～1×10¹⁷cm^-3The thickness is 0.2 to 10 μm.

The third silicon carbide epitaxial layer is doped with nitrogen ions N or phosphorus ions P and has a doping concentration of 1 × 10¹⁸～1×10²¹cm^-3The thickness is 0.1 to 0.5 μm.

Further, Al in the present embodiment₂O₃The thickness of the dielectric coating is 1-10 nm, and LaAlO₃The thickness of the dielectric layer is 1-100 nm, and the chemical equivalent ratio of the lanthanum element to the aluminum element is 1: 1.

Further, the silicon carbide MOS power device in this embodiment may further include the following structure, specifically:

the silicon carbide MOS power device in the embodiment comprises a well region, a source electrode contact region and a base electrode contact region:

wherein: the well region is a well region of a second conductivity type disposed within the epitaxial layer of silicon carbide epitaxy comprising an epitaxial layer of silicon carbide. In this embodiment, the junction depth of the well region is 0.2-1.0 μm, the impurity ions are aluminum ions Al or boron ions B, and the concentration of the impurity ions is 1 × 10¹⁵～1×10¹⁷cm^-3。

The source contact region is a contact region having the first conductivity type and disposed in the well region. In this embodiment, the junction depth of the source contact region is 0.1-0.5 μm, the impurity ions are Al ions or B ions, and the concentration of the impurity ions is 1 × 10¹⁹～1×10²¹cm^-3。

The base contact region is a contact region having the second conductivity type disposed within the well region. In this embodiment, the junction depth of the base contact region is 0.1-0.5 μm, the impurity ions are nitrogen ions N or phosphorus ions P, and the concentration of the impurity ions is 1 × 10¹⁸～1×10²¹cm^-3。

Further, the silicon carbide MOS power device in this embodiment may further include the following structure, specifically:

the silicon carbide MOS power device in the embodiment comprises a base contact region and a groove region:

wherein: the base contact region is a contact region of the second conductivity type which is disposed within the third silicon carbide epitaxial layer of the silicon carbide epitaxy comprising the three silicon carbide epitaxial layers described above. In this embodiment, the junction depth of the base contact region is 0.1-0.5 μm, the impurity ions are nitrogen ions N or phosphorus ions P, and the concentration of the impurity ions is 1 × 10¹⁸～1×10²¹cm^-3。

The trench region penetrates through the first epitaxial layer and the second epitaxial layer, and the depth of the trench region is smaller than the sum of the junction depths of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer. In this embodiment, the depth of the trench penetrating into the third epitaxial layer is 0.1-1 μm.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (17)

1. A preparation method of a high-k gate dielectric layer is characterized by comprising the following steps:

performing high-temperature sacrificial oxidation on a silicon carbide epitaxial wafer with a first conduction type to form a sacrificial oxide layer on the upper surface of an epitaxial layer;

corroding the sacrificial oxide layer until the sacrificial oxide layer on the epitaxial layer is completely removed;

in hydrogen H₂Performing high-temperature surface treatment on the upper surface of the epitaxial layer under the environmentThe temperature of the high-temperature surface treatment is 1000-2000 ℃, and a smooth passivated surface is formed;

depositing Al on said smooth passivated surface in sequence₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Dielectric coating of said Al₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Annealing the laminated structure formed by the dielectric coating to form a high-k gate dielectric layer;

the deposited Al₂O₃The dielectric coating includes: applying ALD to the smooth passivated surface and the LaAlO₃Depositing Al on the dielectric layer₂O₃A dielectric coating; wherein: the reaction precursor of the ALD method is trimethylaluminum TMA, and the oxidant precursor is ozone O₃The temperature is 100-350 ℃;

said deposited LaAlO₃The dielectric layer includes: applying ALD to the Al₂O₃Alternately depositing La on the dielectric coating₂O₃Nanolayer and Al₂O₃A nanolayer; wherein: the deposited La₂O₃The reaction precursor of the nano layer is La (ⁱPrCp)₃The oxidant precursor is ozone O₃The temperature is 200-400 ℃; the deposited Al₂O₃The reaction precursor of the nano layer is trimethyl aluminum TMA, and the oxidant precursor is ozone O₃The temperature range is 200-350 ℃.

2. The method of claim 1, wherein the step of performing high temperature sacrificial oxidation on the silicon carbide epitaxial wafer comprises:

forming an epitaxial layer with a first conductivity type on the front surface of the silicon carbide epitaxial wafer;

after the silicon carbide epitaxial wafer is cleaned, injecting ions into the epitaxial layer to form a well region;

implanting ions into the well region to form a source contact region and a base contact region respectively;

and sequentially annealing and cleaning the silicon carbide epitaxial wafer after ion implantation.

3. The method of claim 1, wherein the step of performing high temperature sacrificial oxidation on the silicon carbide epitaxial wafer comprises:

sequentially forming a first epitaxial layer with a first conductivity type, a second epitaxial layer with a second conductivity type and a third epitaxial layer with the first conductivity type on the front surface of the silicon carbide epitaxial wafer from bottom to top;

after the silicon carbide epitaxial wafer is cleaned, injecting ions into the third epitaxial layer to form a base contact region;

sequentially annealing, etching and cleaning the silicon carbide epitaxial wafer after ion implantation;

wherein: the groove etching comprises etching the first epitaxial layer, the second epitaxial layer and the third epitaxial layer to form a groove region; the groove region penetrates through the third epitaxial layer and the second epitaxial layer, and the depth of the groove region is smaller than the sum of the junction depths of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer.

4. The method of claim 2 or 3, wherein the cleaning the silicon carbide epitaxial wafer comprises: and sequentially carrying out Piranha process cleaning, RCA process cleaning and DHF process cleaning on the silicon carbide epitaxial wafer.

5. The method of claim 1, wherein the high-k gate dielectric layer is formed on the substrate,

the high-temperature sacrificial oxidation of the silicon carbide epitaxial wafer comprises the following steps: by using a box furnace or a tube furnace in oxygen O₂Carrying out high-temperature sacrificial oxidation on the silicon carbide epitaxial wafer in the environment;

wherein: the oxidation temperature of the high-temperature sacrificial oxidation is 1200-1500 ℃, the oxidation time is 10-30 min, and oxygen O₂Has a purity of 6N, oxygen O₂The flow rate of (2) is 0.1 to 10 slm.

6. The method of claim 1, wherein the high-k gate dielectric layer is formed on the substrate,

the etching the sacrificial oxide layer comprises: corroding the sacrificial oxide layer by adopting wet corrosion at normal temperature;

wherein: the etching solution of the wet etching is BOE etching solution or DHF solution with the concentration of 1-50%.

7. The method of claim 1, wherein the high-k gate dielectric layer is formed on the substrate,

the high-temperature surfacing treatment of the upper surface of the epitaxial layer comprises the following steps: by using box-type or tube-type furnaces in hydrogen H₂Performing high-temperature surfacing treatment on the upper surface of the epitaxial layer in the environment;

wherein: the temperature of the high-temperature surface treatment is 1000-2000 ℃, the time is 0.1-4H, and the hydrogen H₂Has a purity of 6N, hydrogen H₂The flow rate of (2) is 0.1 to 10 slm.

8. The method of claim 1, wherein the Al is doped₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Annealing the laminated structure of the dielectric coating comprises: adopting a rapid thermal annealing device and in nitrogen N₂Argon Ar or nitrous oxide N₂Annealing the laminated structure in an O environment; wherein: the annealing temperature is 800-1200 ℃, and the annealing time is 10-60 s.

9. A silicon carbide MOS power device, the silicon carbide MOS power device comprising:

the epitaxial silicon carbide wafer comprises a silicon carbide substrate and an epitaxial layer, wherein the silicon carbide substrate and the epitaxial layer are both provided with a first conduction type; wherein: in hydrogen H₂Carrying out high-temperature surfacing treatment on the upper surface of the epitaxial layer under the environment, wherein the temperature of the high-temperature surfacing treatment is 1000-2000 ℃, and forming lightA smooth, passivated surface;

a high-k gate dielectric layer disposed on the smooth passivated surface,

depositing Al on said smooth passivated surface in sequence₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Dielectric coating of said Al₂O₃Dielectric coating, LaAlO₃Dielectric layer and Al₂O₃Annealing the laminated structure formed by the dielectric coating to form a high-k gate dielectric layer; the deposited Al₂O₃The dielectric coating includes: applying ALD to the smooth passivated surface and the LaAlO₃Depositing Al on the dielectric layer₂O₃A dielectric coating; wherein: the reaction precursor of the ALD method is trimethylaluminum TMA, and the oxidant precursor is ozone O₃The temperature is 100-350 ℃; said deposited LaAlO₃The dielectric layer includes: applying ALD to the Al₂O₃Alternately depositing La on the dielectric coating₂O₃Nanolayer and Al₂O₃A nanolayer; wherein: the deposited La₂O₃The reaction precursor of the nano layer is La (ⁱPrCp)₃The oxidant precursor is ozone O₃The temperature is 200-400 ℃; the deposited Al₂O₃The reaction precursor of the nano layer is trimethyl aluminum TMA, and the oxidant precursor is ozone O₃The temperature is 200-350 ℃;

the silicon carbide substrate is 4H-SiC or 6H-SiC, and the thickness of the silicon carbide substrate is 300-1000 μm or 10-400 μm;

the silicon carbide substrate is a silicon carbide substrate heavily doped with nitrogen ions N or phosphorus ions P, and the resistivity is 0.001-0.1 omega cm; or the silicon carbide substrate is doped with vanadium ions V or not doped with any ions, and the resistivity is more than 10⁵Ω·cm。

10. The silicon carbide MOS power device of claim 9,

the epitaxial layer comprises a silicon carbide epitaxial layer having a first conductivity type; or,

the epitaxial layer comprises a first silicon carbide epitaxial layer with a first conductivity type, a second silicon carbide epitaxial layer with a second conductivity type and a third silicon carbide epitaxial layer with the first conductivity type, which are sequentially arranged on the front surface of the silicon carbide substrate from bottom to top.

11. The silicon carbide MOS power device of claim 10,

the silicon carbide epitaxial layer is 4H-SiC or 6H-SiC, and the thickness of the silicon carbide epitaxial layer is 2-300 mu m;

the silicon carbide epitaxial layer is doped with nitrogen ions N or phosphorus ions P, and the doping concentration is 1 multiplied by 10¹³～1×10¹⁶cm^-3。

12. The silicon carbide MOS power device of claim 10,

the first silicon carbide epitaxial layer, the second silicon carbide epitaxial layer and the third silicon carbide epitaxial layer are all 4H-SiC or 6H-SiC;

the first silicon carbide epitaxial layer is a silicon carbide epitaxial layer doped with nitrogen ions N or phosphorus ions P, and the doping concentration of the first silicon carbide epitaxial layer is 1 multiplied by 10¹³～1×10¹⁶cm^-3The thickness is 2 to 300 μm;

the second silicon carbide epitaxial layer is a silicon carbide epitaxial layer doped with aluminum ions Al or boron ions B, and the doping concentration of the second silicon carbide epitaxial layer is 1 multiplied by 10¹⁵～1×10¹⁷cm^-3The thickness is 0.2 to 10 μm;

the third silicon carbide epitaxial layer is a silicon carbide epitaxial layer doped with nitrogen ions N or phosphorus ions P, and the doping concentration of the third silicon carbide epitaxial layer is 1 multiplied by 10¹⁸～1×10²⁰cm^-3The thickness is 0.1 to 0.5 μm.

13. The silicon carbide MOS power device of claim 9,

the Al is₂O₃The thickness of the dielectric coating is 1-10 nm;

the LaAlO₃The thickness of the dielectric layer is 1-100 nm, and the chemical equivalent ratio of the lanthanum element to the aluminum element is 1: 1.

14. The silicon carbide MOS power device of claim 10, further comprising a well region, a source contact region, and a base contact region;

the well region is a well region with a second conduction type and is arranged in the silicon carbide epitaxial layer;

the source electrode contact region is a contact region with a first conduction type and is arranged in the well region;

the base contact region is a contact region having a second conductivity type disposed within the well region.

15. The silicon carbide MOS power device of claim 14,

the junction depth of the well region is 0.2-1.0 μm, the impurity ions are aluminum ions Al or boron ions B, and the concentration of the impurity ions is 1 x 10¹⁵～1×10¹⁷cm^-3；

The junction depth of the source electrode contact region is 0.1-0.5 mu m, and the impurity ions are n-type ions; the concentration of the impurity ions is 1 × 10¹⁹～1×10²¹cm^-3；

The junction depth of the base electrode contact region is 0.1-0.8 mu m, and the impurity ions are p-type ions; the concentration of the impurity ions is 1 × 10¹⁸～1×10²¹cm^-3。

16. The silicon carbide MOS power device of claim 10, wherein the silicon carbide MOS power device further comprises a base contact region and a trench region;

the base contact region is a contact region having a second conductivity type disposed within the third silicon carbide epitaxial layer;

the groove region penetrates through the third silicon carbide epitaxial layer and the second silicon carbide epitaxial layer, and the depth of the groove region is smaller than the sum of the junction depths of the first silicon carbide epitaxial layer, the second silicon carbide epitaxial layer and the third silicon carbide epitaxial layer.

17. The silicon carbide MOS power device of claim 16,

the junction depth of the base electrode contact region is 0.1-0.5 mu m, and the impurity ions are p-type ions; the concentration of the impurity ions is 1 × 10¹⁸～1×10²¹cm^-3；

The depth of the groove region penetrating into the first epitaxial layer is 0.1-1 mu m.

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