CN108234064A - Quasi-cyclic LDPC code data processing equipment and processing method - Google Patents

Abstract

The invention discloses a kind of quasi-cyclic LDPC code data processing equipment and processing method, described device includes memory module, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；Coding module, for obtaining the basis matrix and a spreading factor value from the memory module, the basis matrix and spreading factor value based on acquisition treat coded information sequences and carry out quasi-cyclic LDPC coding, obtain LDPC encoded output sequences；Rate Matching block, for from the LDPC encoded output sequences, selecting rate-matched output sequence.Present invention efficiently solves the problem of LDPC coding and decodings process lacks flexibility in the prior art.

Description

Quasi-cyclic LDPC code data processing equipment and processing method

Technical field

The present invention relates to the communications field, more particularly to a kind of quasi-cyclic LDPC code data processing equipment and processing method.

Background technology

At present, common forward error correction (Forward Error Correction, referred to as FEC) coding includes：ConvolutionCode, Turbo code and low-density checksum (Low Density Parity Check, referred to as LDPC) code.

In FEC cataloged procedures, the FEC coding codes that FEC codings obtain n-bit are carried out to the information sequence that bit number is kWord (redundant bit n-k), FEC encoder bit rates (abbreviation code check) are k/n.LDPC code is a kind of can to use very sparse odd evenThe linear block codes that check matrix or bipartite graph define exactly using the openness of its check matrix, could be realized low multipleThe coding and decoding of miscellaneous degree, so that LDPC moves towards practical.By various practices and theoretical proof, LDPC code is in additive GaussianPerformance channel coding the most excellent under white noise (Additive White Gaussian Noise, referred to as AWGN) channel,Performance is very close to shannon limit.

Quasi- cycle quasi-cyclic LDPC code has been widely applied in multiple standards, although can by change extend becauseThe shortening coding of son can obtain flexible code check code length design, improve LDPC code flexibility.Although improving flexibility, propertyException can be will appear, i.e., the penalty under certain code length code checks shows as burr phenomena on performance curve.

Invention content

The defects of in order to overcome the above-mentioned prior art, the technical problem to be solved in the present invention is to provide a kind of quasi-cyclic LDPCsCode data processing equipment and processing method, lack asking for flexibility at least to solve LDPC coding and decodings process in the prior artTopic.

In order to solve the above technical problems, a kind of quasi-cyclic LDPC code data processing equipment in the present invention, including：

Memory module, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；InstituteThe matrix that basis matrix is a mb rows nb row is stated, the element for being used to indicate complete zero square formation is included in the basis matrix and is used forIndicate the element of the shift size of unit matrix cyclic shift, the spreading factor value is used to indicate complete zero square formation or the listThe line number of position battle array, the spreading factor value are greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the whole of mbNumber；

Coding module, for obtaining the basis matrix and a spreading factor value from the memory module, based on obtainingThe basis matrix and spreading factor value taken treats coded information sequences and carries out quasi-cyclic LDPC coding, obtains LDPC codingsOutput sequence；

Rate Matching block, for from the LDPC encoded output sequences, selecting rate-matched output sequence.

In order to solve the above technical problems, a kind of quasi-cyclic LDPC code data processing equipment in the present invention, including processorAnd storage device, the storage device memory contain a quasi-cyclic LDPC coding basis matrix used and one group of spreading factorIt is worth and is stored with multiple instruction to realize LDPC code data processing method, the processor performs the multiple instruction with realityIt is existing：

The basis matrix and a spreading factor value are obtained from the memory module, the basic square based on acquisitionBattle array and spreading factor value treat coded information sequences and carry out quasi-cyclic LDPC coding, obtain LDPC encoded output sequences；The basePlinth matrix is the matrix of a mb rows nb row, and the element for being used to indicate complete zero square formation is included in the basis matrix and is used to indicateThe element of the shift size of unit matrix cyclic shift, the spreading factor value are used to indicate complete zero square formation or the unit matrixLine number, the spreading factor value is greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the integer of mb；

From the LDPC encoded output sequences, rate-matched output sequence is selected.

In order to solve the above technical problems, a kind of quasi-cyclic LDPC code data processing method in the present invention, including：

In a basis matrix and one group of spreading factor value used from pre-stored quasi-cyclic LDPC coding, institute is obtainedState basis matrix and a spreading factor value；The basis matrix is the matrix of a mb rows nb row, is wrapped in the basis matrixContaining the element for being used to indicate complete zero square formation and the element of shift size for being used to indicate unit matrix cyclic shift, the spreading factorValue is used to indicate complete zero square formation or the line number of the unit matrix, and the spreading factor value is greater than 0 integer, and the mb isInteger more than 0, the nb are greater than the integer of mb；

The basis matrix parameter and spreading factor value based on acquisition treat coded information sequences and carry out quasi-cyclic LDPCCoding, obtains mother's LDPC codeword sequence；

From mother's LDPC codeword sequence, rate-matched output sequence is selected.

The present invention has the beneficial effect that：

Device and method the problem of effectively LDPC coding and decodings process lacks flexibility in the prior art in the present invention, support spiritCode length living and code check, and retention property is good.

Description of the drawings

Fig. 1 is a kind of structure diagram of quasi-cyclic LDPC code data processing equipment in the embodiment of the present invention；

Fig. 2 is the structure diagram of existing digital communication system in the embodiment of the present invention；

Fig. 3 is that girth is 4 schematic diagram in parity matrix corresponding to basis matrix in the embodiment of the present invention；

Fig. 4 is the schematic diagram of basis matrix in the embodiment of the present invention；

Fig. 5 is a kind of flow chart of LDPC code data processing method in the embodiment of the present invention；

Fig. 6 is a kind of performance comparison figure of LDPC code data processing method in the embodiment of the present invention.

Specific embodiment

In order to solve problem of the prior art, the present invention provides a kind of quasi-cyclic LDPC code data processing equipment and processingMethod, below in conjunction with attached drawing and embodiment, the present invention will be described in further detail.It should be appreciated that described hereinSpecific embodiment does not limit the present invention only to explain the present invention；In the absence of conflict, in embodiment and embodimentFeature can be combined with each other；Term " first ", " second " in specification and claims and above-mentioned attached drawing etc. are for areaNot similar object describes specific sequence or precedence without being used for.

Quasi-cyclic LDPC code data processing equipment and processing method in the present invention, can be used for LTE mobile communication system orPerson's future the 5th Generation Mobile Communication System or other Wireless-wire communication systems, data transfer direction are base station to mobile subscriberTransmission data (downlink transfer business datum) or data transfer direction are mobile subscriber to base station transmission data (uplinkBusiness datum).Mobile subscriber includes：Mobile equipment, for access terminal, user terminal, subscriber station, subscriber unit, movement station, remoteJourney station, remote terminal, user agent, user apparatus, user equipment or some other terms.Base station includes access point (AccessPoint, AP) or be properly termed as node B (node B), radio network controller (Radio Network Controller,RNC), evolved Node B (Evolved Node B, eNB), base station controller (Base Station Controller,BSC), base transceiver station (Base Transceiver Station, BTS), base station (Base Station, BS), transceiver work(It can body (TF), Radio Router, wireless set, basic service unit (Basic Service Set, BSS), extension clothesIt is engaged in unit (extended service set, ESS), radio base station (radio base station, RBS) or some itsIts term.

Quasi-cyclic LDPC code data processing equipment and processing method in the embodiment of the present invention can also be applied to newly wirelessly connectEnter the enhancing mobile broadband (enhanced in technology (New Radio Access Technology, referred to as new RAT)Mobile Broadband, referred to as eMBB) scene, super reliable low time delay communication (Ultra-Reliable and LowLatency Communications, referred to as URLLC) scene or extensive Internet of Things (massive Machine TypeCommunications, referred to as mMTC) in scene.Wherein downlink maximum throughput can reach 20Gbps in eMBB scenes,Upstream data maximum throughput can reach 10Gbps；And in URLLC, it can support reliability is minimum to reach 10e-5'sBLER (Block Error Rate) and uplink and downlink reach most short time-delay and reach 0.5 millisecond；And mMTC can make device batteryIt can use and not power off for many years.

Include as shown in Figure 1, the embodiment of the present invention provides a kind of quasi-cyclic LDPC code data processing equipment：

Memory module 110, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；The basis matrix is the matrix of a mb rows nb row, and the element and use for being used to indicate complete zero square formation are included in the basis matrixIn the element of the shift size of instruction unit matrix cyclic shift, the spreading factor value is used to indicate complete zero square formation or describedThe line number of unit matrix, the spreading factor value are greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than mb'sInteger；

Quasi-cyclic LDPC coding module (abbreviation coding module) 120, for obtaining the basis from the memory moduleMatrix and a spreading factor value, the basis matrix and spreading factor value based on acquisition treat coded information sequences progressQuasi-cyclic LDPC encodes, and obtains LDPC encoded output sequences；

Rate Matching block 130, for from the LDPC encoded output sequences, selecting rate-matched output sequence.

For example, spreading factor parameter is { 468 10 12 14 16 20 24 28 32 40 48 56 64 80 96112 128 160 192 224 256 320 384 448 512 640 768 896 1024}。

Device supports flexible code length and code check in the embodiment of the present invention, and retention property is good.

Embodiment in order to better understand the present invention, digital communication system described briefly below.

As shown in Fig. 2, digital communication system generally comprises three parts：Transmitting terminal, channel and receiving terminal.Transmitting terminal can be rightInformation sequence carries out channel coding so as to obtain coding codeword, coding codeword is interleaved, and by the bit map after intertextureInto modulation symbol, then modulation symbol can be handled and sent according to communication channel information.In the channel, due to multipath, shiftingThe factors such as dynamic lead to specific channel response, these can all be distorted data transmission, simultaneously because noise and interference also can be into oneStep deteriorates data transmission.Receiving terminal is received through the modulation symbol data after channel, and modulation symbol data at this time has been distorted,Need progress particular procedure that could restore original information sequence.

According to coding method of the transmitting terminal to information sequence, receiving terminal can to receive data carry out respective handling so as toRestore original information sequence by ground.The coding method must be that transmitting-receiving two-end is all visible.Usually, at the codingReason method is encoded based on forward error correction (Forward Error Correction, referred to as FEC), wherein, forward error correction is compiledCode adds some redundancies in information sequence.Receiving terminal can reliably restore raw information sequence using the redundancyRow.

In transmitting terminal, need to obtain more parts of small transmission blocks to transmission block to be transmitted progress code block segmentation, then to more partsSmall transmission block carries out FEC codings respectively, and the length of the transmission block to be transmitted is TBS (Transport Block Size),FEC encoder bit rates are commonly defined as ratio of the bit number than upper actual transmissions bit for entering encoder.In LTE (LongTerm Evolution, the long term evolution of universal mobile communications technology) in system, very flexible transport block size can be supportedThe various packet size requirements of LTE system and use Modulation and Coding Scheme (Modulation and Coding Scheme, letterReferred to as MCS) index indicates different modulating exponent number and encoder bit rate R and determining TBS indexes and according to resource block(Resource Block) number N RB and transport block size (TBS) index to determine in different transport block sizes, the resourceBlock size is that continuous size is resource of 12 subcarriers on 1 time slot, wherein removal number control signal and reference signal instituteRemaining resource.It can include data channel and control channel in channel type, that data channel generally carries is user (UserEquipment) data, control channel carrying control information, category information is controlled including MCS call numbers, channel information etc..With roomyThe small system that generally refers to distributes to the occupied amount of bandwidth of data transmission, is divided into 20M, 10M, 5M equiband in LTE system.NumberInclude upstream data and downlink data according to transmission direction, the upstream data generally refers to user and transmits data, downlink to base stationData refer to that data are transmitted in base station to user.

In IEEE802.11ac, IEEE802.11ad, IEEE802.11aj, IEEE802.16e, IEEE802.11n, microwaveIn communication and fiber optic communication etc., LDPC code is all widely applied.All it is one per a line in the parity matrix of LDPC codeA parity check code often illustrates that the bit participates in the even-odd check in a line if a certain index position element value is equal to 1Code, if equal to 0, then illustrate that the position bit is not involved in the parity check code.And the parity check matrix H of quasi-cyclic LDPC codeFor the matrix that M × Z rows and N × Z are arranged, it is made of M × N number of submatrix, and each submatrix is that size is the basic of Z × ZThe different powers of permutation matrix, if it is also assumed that being the sub- square that size is obtained by the cyclic shift dry values of Z × Z unit matrixBattle array.The quasi-cyclic LDPC code can also be called structured LDPC code.At this point, only it is to be understood that cyclic shift value and submatrix are bigSmall to be assured that a quasi-cyclic LDPC code, all shift values form a M × N matrix, are properly termed as basic schoolTesting matrix, either basis matrix or protograph (base protograph), the submatrix size can become spreading factorOr lifting values (lift size), spreading factor is described mainly as in this patent content, the meaning is all consistent.Quasi- cycleThe parity matrix of LDPC code has following form：

If hb_ij==- 1, then haveIt is the full null matrix that size is Z × Z；It is single in order to mathematically be easier to describeThe cyclic shift of position battle array in the check matrix of above-described quasi-cyclic LDPC code basis, defines size Z × Z's hereinBasic permutation matrix P carries out power of corresponding size, the base to the cyclic shift of unit matrix to basic permutation matrix PThis permutation matrix P is as follows：

Power hb in this way_ijCan unique mark each matrix in block form, if a certain matrix in block form is full 0 squareBattle array, matrix are generally represented or null value represents with -1；And if the cyclic shift s of unit matrix is obtained, then equal to s, soAll hb_ijA basic check matrix H b is may be constructed, and then basis matrix (or basic check matrix) Hb of LDPC code canTo represent as follows：

So quasi-cyclic LDPC code can be uniquely determined completely by basis matrix Hb and spreading factor Z.Basic check matrixIncluding multiple parameters：MB, NB and KB, wherein, MB is basis matrix line number (the verification columns that can be described as basis matrix), NB basesThe total columns of plinth matrix, and KB=NB-MB is the system columns of basis matrix.

For example, basis check matrix H b (2 rows 4 arrange) is following and spreading factor z is equal to 4：

Then parity matrix is：

Element in the parity matrix only has 0 and 1 two kind of element value, it is possible to describe it as binary systemMatrix；And it is transformed into parity matrix (binary matrix) from basis matrix and can be described as：Basis matrix change is extended toParity matrix or basis matrix, which become, to be promoted into parity matrix.Come from above-described LDPC code parity matrixIt sees, it is recognised that element index of the 1st row of parity matrix equal to 1 is [1 6 9], illustrates in the quasi-cyclic LDPC codeIn, the 1st bit, the 6th bit and the 9th bit form a parity check code；Similarly, the index in the 2nd row equal to 1 is [2 710], then the 2nd bit, the 7th bit and the 10th bit form a parity check code；The rest may be inferred, it is known that LDPC code is in factIt is exactly the code word that many parity check code heaps come.And quasi-cyclic LDPC code, as long as being advantageous in that storage basis verification squareBattle array Hb and spreading factor Z, its block characteristic, Ke Yijian can be utilized by storing in very simple and coding/decoding algorithmChange algorithm, such as use hierarchical decoder, and often row Nepit node location does not conflict, and pile line operation may be used, and can subtractFew decoding delay and decoding complexity, are realized very simple.

There are many LDPC interpretation methods, such as probability domain BP decoding algorithms, log-domain BP decoding algorithms and layering it is minimum andDecoding algorithm etc..Probability domain BP decoding algorithm performances are best, but have the disadvantage that since it is related to a large amount of multiplyings, operationAmount is very big, so as to which required hardware cost is very high, and the big stability of dynamic range of numerical value is bad, so generally in realityIt will not be used in the application of border.Relative to probability domain BP decoding algorithms, log-domain BP decoding algorithms reduce many computing units, butStill many multiplyings are needed, required hardware cost is quite a few.It is layered Min-Sum decoding algorithm and log-domain BP is decoded into calculationCrucial calculating (log operations and multiplying) unit of method, which is converted to, minimizes with time minimum value, and the hardware resource needed is bigAmount is reduced, and performance has dot loss, but can be much less hardware resource.So practical application it is more be pointLayer Min-Sum decoding algorithm.All it is to need to be iterated decoding, decoding module is broadly divided into two regardless of interpretation methodPart：Check-node update module and variable node update module.

In LDPC is encoded and is decoded, in order to ensure to be had excellent performance, handling capacity is high, flexibility is high low with complexity etc.Characteristic, the LDPC code parity matrix with design is closely bound up., whereas if design LDPC parity matrixs are notIt is good, it will cause its hydraulic performance decline, while complexity and flexibility may also can be caused to be affected.Therefore, it is designed in LDPC codeThe concept of short circle girth is introduced in the process.In order to be best understood from the concept of girth, LDPC code basis matrix is introduced hereinThere is short 4 ring and short 6 ring forms the situation of girth.In general need by basis matrix be extended to parity matrix orBinary matrix.In parity matrix, in arbitrary 2 different line index on i and l and arbitrary 2 different rowIndex as on j and k, if be i by line index and l in column index is j and k is indicated collectively 4 elements, this described 4 membersElement is equal to 1, then it is considered that there are the short circles that a length is 4 in the parity matrix；Similarly, in even-odd check squareIn battle array, in arbitrary 3 different line index be on i, l and a and arbitrary 3 different column indexes are on j, k and b, if byLine index is i, l and a and column index is in 6 elements that j, k and b are indicated collectively, if this 6 elements are equal to 1, weThink that there are the short circles that a length is 6 in the parity matrix；Similarly, in parity matrix, at arbitrary 3 notWith line index be on i, l, a and c and arbitrary 4 different column indexes are on i, l, a and c, if by line index be i, l,In 8 elements that a and c is indicated collectively with column index for i, l, a and c, if this 8 elements are equal to 1, it is considered that describedThere are the short circles that a length is 8 in parity matrix.As described above citing in there is also a girth be 4 short circle, such asShown in Fig. 3 601 and 602.In basis matrix, it is believed that in the parity matrix corresponding to it, short 4 ring occursThe sufficient and necessary condition of girth=4 is：In basis matrix, 4 element [h of 4 rings can be arbitrarily formed_ai,h_bi,h_bj,h_aj] fullFoot

(h_ai-h_bi+h_bj-h_aj) %zf==0

Zf is spreading factor, then can lead to the appearance of girth=4 between the element of 4 positions.In this way due to information onlyThe transfer between this 4 node (+2 check-nodes of 2 variable nodes), due to constantly handing over after successive ignition is carried outThe information changed is largely from itself feedack, and external information is less, then final code word performance will be deteriorated.

In parity matrix corresponding to it, the sufficient and necessary condition that girth=6 occurs in short 6 ring is：In basis matrixIn, it can arbitrarily form 6 element [h of 6 rings_ai,h_bi,h_bj,h_cj,h_ck,h_ak] meet

(h_ab-h_cd+h_ef-h_gj+h_nm-h_qw) %zf=0

Zf is spreading factor, then can lead to the appearance of girth=6 between the element of 6 positions.In this way since information is bigPart transfer between this 6 node (+3 check-nodes of 3 variable nodes), is handed over due to similary with girth=4The external information changed is less, and final code word performance may also can be slightly worse.Although quasi-cyclic LDPC code is in a variety of communication marksIt is applied in standard, but by analysis it can be found that the code check of various standards and code length are all than relatively limited, i.e. flexibilityIt is poor.For example, in IEEE802.11ad standards, only a kind of code length (672) and 4 kinds of code checks (1/2,5/8,3/4,13/16)；In IEEE802.11n standards, only 3 kinds of code lengths (648,1296,1944) and 4 kinds of code checks (1/2,2/3,3/4,5/6).It can be found that since quasi-cyclic LDPC is defined by part basis matrix, so, the quasi-cyclic LDPC code in these usesThe shortcomings that be all flexibility deficiency, the flexibility refer to encoder bit rate and coding code length flexibly change, then if requirementLDPC code realizes flexible code check code length, and just not occurring exception than the performance under each code length code check relatively difficult to achieve (hair occursThorn), it is extremely difficult that retention property and flexibility is wanted all to meet this for LDPC code.Also, in new RAT (newRadio Access Technology) in system, channel coding schemes is needed to support flexible code check code length, the i.e. variation of code lengthInterval is at least 8 bits, and code check can flexibly change.Device can effectively solve the above problems in the embodiment of the present invention.

On the basis of above-described embodiment, it is further proposed that the variant embodiment of above-described embodiment, needs what is illustrated hereinIt is, in order to make description brief, the only description and the difference of above-described embodiment in each variant embodiment.

In one embodiment of the invention, the row of the basis matrix includes at least 3/4 element of following set again：{ 8,9,9,8,5,6,5,6,6,6,5,6,4,5,5,5,5 }；And/or

The row of the basis matrix include at least 3/4 element of following set again：17,5,16,4,4,4,15,4,4,10,4,3,1,1,1,1,1,1,1,1,1,1,1,1,1 }；

Wherein, the row refers to line index in the basis matrix and fixes and useful when column index is 0~(nb-1) againIn the number of the element of instruction unit matrix cyclic shift；

The row refer to column index in the basis matrix again to be fixed and all being used to indicate when line index is 0~(mb-1)The number of the element of unit matrix cyclic shift.

Wherein, in the basis matrix, the element for being used to indicate complete zero square formation is represented using ' -1 ', is used to indicate unit matrixThe element of cyclic shift is used more than or equal to 0 and less than basis matrix described in the integer representation of the spreading factor value at least80% element is identical with below with reference to basis matrix Hb：

Furtherly, the position at least 80% of the element of unit matrix cyclic shift is used to indicate in the basis matrixElement position is identical with the position below with reference in basis matrix Hb ' ' 1 '：

Specifically, it is used to indicate in the new basis matrix that the basis matrix obtains after line replacement and/or column permutationThe element position of the position of the element of unit matrix cyclic shift at least 80% and the position phase with reference in basis matrix Hb ' ' 1 'Together.

For example, code data processing equipment in the embodiment of the present invention, including：

Memory module is configured to：For storing one group of basis matrix parameter and one group of spreading factor parameter；Described one groupBasis matrix includes 1 basis matrix, as follows：

Wherein, the basis matrix corresponds to the basis matrix of largest extension factor Z max=1024, and " -1 " representsBe used to indicate the element of complete zero square formation, other are indicated for the element of unit matrix cyclic shift, concrete numerical value be greater than orIt is less than the integer of Z=1024 equal to 0.One group of spreading factor parameter is { 468 10 12 14 16 20 24 28 3240 48 56 64 80 96 112 128 160 192 224 256 320 384 448 512 640 768 896 1024}。

Coding module is connected with the memory module, is configured to：Quasi-cyclic LDPC coding is obtained from the memory moduleThe basis matrix and spreading factor parameter Z=56, a kb=nb-mb=8 of mb=18 rows nb=26 row used, are based onThe basis matrix of one mb=18 rows nb=26 row and a spreading factor parameter are kb × Z=8 × 56=448 to lengthThe information sequence X to be encoded of bit carries out quasi-cyclic LDPC coding, and acquisition length is nb × Z=26 × 56=1456 bitsLDPC code sequence Y；The basis matrix of the mb=16 rows nb=26 row, it is as follows

The basis matrix that the 18=4 rows nb=26 that above-described corresponding spreading factor value is 56 is arranged is corresponding described aboveThe basis matrix of largest extension factor values Zmax=1024, is obtained using the following formula：

Include the B0=371 elements for being used to indicate complete zero square formation (being represented in the present embodiment using " -1 ") and B1=97A element for being used to indicate unit matrix cyclic shift, the concrete numerical value of the element for being used to indicate complete zero square formation are greater than or waitIn 0 and less than Z=56 integer；

Rate Matching block is connected with the quasi-cyclic LDPC coding module, is configured to：It is nb × Z=from the lengthLength is selected in mother's LDPC code sequence Y of 26 × 56=1456 bits as LDPC code sequence after the rate-matched of N=1344 bitsRow.Performance is as shown in Figure 6, it can be seen that the performance of new departure is compared with the performance better than old scheme, therefore, it can be seen that this programme canTo improve performance.

Wherein, the row weight in the basis matrix there are 1 row is most heavy.

In another embodiment of the present invention, the rate-matched output sequence does not include the information sequence to be encodedMiddle A0 successive bits block, the A0 successive bits block corresponds respectively to A0 column index number of the basis matrix, describedIt is arbitrary integer in 0 to 3 that A0 column index number, which forms set T0, the A0,；Wherein, the element value of the set T0 and first prime numberMesh is determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

The concrete numerical value of the A0 is determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, the group of code check R, transport block size TBS and code check RConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

Wherein, the transport block size TBS is greater than 0 integer；The application scenarios include：Mobile broadband enhancesThe reliable low time delay communication URLLC and extensive Internet of Things mMTC of eMBB, superelevation；The frequency range includes：The frequency model of system configurationIt encloses；The code check R is greater than 0 and the real number less than 1；The channel type includes：Control channel and data channel；The dataTransmission direction includes：Upstream data and downlink data；The TBS call numbers are used to combine the corresponding biography of resource unit number instructionDefeated block size TBS, the TBS call numbers are greater than or equal to 0 integer；The MCS call numbers are used to indicate a MCS sideThe combination of case or an order of modulation and TBS indexes, the MCS call numbers are greater than or equal to 0 integer；The resourceUnit number NRB is the resource block number of system configuration；The amount of bandwidth is greater than 0 real number.User's UE types are LTE systemsDefined in user type.

Optionally, if it is set G1 that the transport block size TBS, which is less than positive integer TBS0, A0 value,；

If it is set G2 that the transport block size TBS, which is greater than or equal to positive integer TBS0, A0 value,；Wherein, G1 is neutralizedElement value in G2 is 0 to 3 integer, and the intersection of G1 and G2 are empty set.

According to different transport block size TBS using different A0 values, advantageous effect is：It can cause quasi-cyclic LDPCThe decoding performance of coding is more balanced, and in low code length, performance is more excellent, such as message length (or transport block size TBS) is less thanDuring TBS0=1024 bits, A0 is equal to 0, i.e., in Rate Matching block, performances of the A0 equal to 0 is more than 0 performance better than A0, butIt is in long code length, during such as message length (or transport block size TBS) more than or equal to TBS0=1024 bits, A0 is greater than 0Integer, performance is more excellent.Therefore, it can cause LDPC code that can keep preferable decoding performance under flexible code length code check.WithThe upper TBS0=1024 is an example, is designed according to different basis matrixes, and TBS0 is not limited to above-described numberValue.Further, for example, in the Rate Matching block, it is whole less than one of 4096 that the positive integer TBS0 is greater than 256Number.

Optionally, if concrete numerical values of the code check R more than arithmetic number R ', A0 is set G3；

If concrete numerical values of the code check R less than or equal to arithmetic number R ', A0 is set G4；Arithmetic number R ' is greater than 0And the real number less than 1, the code check R are the code checks of LDPC code sequence after the rate-matched, R is greater than 0 real number for being less than 1,Wherein, the element value in G3 and in G4 is 0 to 3 integer, and the intersection of G3 and G4 are empty set.

The concrete numerical value of the A0 is set according to different code checks, advantageous effect is：So that quasi-cyclic LDPC code can be withUnder different code checks, impartial preferably decoding performance can be obtained, i.e., under identical code length, different code checks (such as 0.2~0.93) its performance under can be smoother, is not in that some code check performance is poor, and part code check better performances.

Optionally, if concrete numerical value of the frequency range more than arithmetic number FB0, A0 is set G5；

If concrete numerical value of the frequency range less than or equal to arithmetic number FB0, A0 is set G6；Wherein, in G5 and in G6Element value be 0 to 3 integer, the intersection of G5 and G6 is empty set.

The concrete numerical value of the A0 is determined according to different frequency range, and advantageous effect is：If frequency range is in low frequency part,Available bandwidth is smaller, so general data amount is small, transport block size TBS is also smaller, low frequency channel multipath etc. influence compared withGreatly, so more low bit- rate is needed to be transmitted, so the concrete numerical value of adjustment A0 is also required to, so that the quasi-cyclic LDPC codeOptimal decoded state is may be at, and then the robustness of system can be improved；When frequency range is higher, due to available bandwidth compared withGreatly, the multipath of signal is reduced, and can transmit the transport block size TBS of bigger and code check higher, adjust the concrete numerical value of A0 according toIt can so ensure that the performance of quasi-cyclic LDPC code is still good under different frequency range；The frequency range refers to the communication used in systemThe center frequency points of bandwidth, such as communication bandwidth are 20MHz, and position is known that it at this time between 1.5GHz~1.52GHzCommunications band is in 1.51GHz.

Optionally, if the channel type is control channel, the concrete numerical value of A0 is set G7；

If the channel type is data channel, the concrete numerical value of A0 is set G8；Wherein, the element in G7 and in G8Value is 0 to 3 integer, and the intersection of G7 and G8 are empty set.

The concrete numerical value of the A0 is determined according to different channels type, and advantageous effect is：The number of general control channelAccording to being all fewer and code check is relatively low, and the data volume of data channel is larger and code check is relatively higher, so at this point,The concrete numerical value of A0 can be determined according to whether data are control channel and data channel, can cause in different data classProperty retention under type is good.For example, quasi-cyclic LDPC coding is equal to 0 using A0 in the data encoding of control channel, and in numberIt is believed that the data encoding quasi-cyclic LDPC coding under road is equal to 1 or 2 (or selecting 1 from { 1,2 }) using A0.The tool of the A0Body numerical value is not limited to the process described above.

Optionally, if the data transfer direction is transmitting uplink data, the concrete numerical value of A0 is set G9；

If the data transfer direction is downlink data transmission, the concrete numerical value of A0 is set G10；Wherein, G9 is neutralizedElement value in G10 is 0 to 3 integer, and the intersection of G9 and G10 are empty set.

The concrete numerical value of the A0 is determined according to different data transmission direction, and advantageous effect is：In general, uplinkThe data flow of data is less, and the data flow of downlink data is larger, it is possible to always be determined according to different transmission side datasThe concrete numerical value of A0 can so that the property retention of the data encoding of different transmission directions is preferable.The upstream data refers to useFamily terminal (mobile equipment UE) transmits data to base station, and downlink data refers to base station to user terminal (mobile equipment UE) transmission numberAccording to.

Optionally, if the concrete numerical value that the band is wider than arithmetic number BW0, A0 is set G11；

If concrete numerical value of the frequency range less than or equal to arithmetic number BW0, A0 is set G12；Wherein, in G11 and G12In element value be 0 to 3 integer, the intersection of G11 and G12 is empty set.

The concrete numerical value of the A0 is determined according to different bandwidth, and advantageous effect is：When bandwidth is larger, data volume is allBigger, i.e. transport block size TBS also can be accordingly bigger, however when bandwidth is smaller, the data volume of transmission, can with regard to smallerSo that quasi-cyclic LDPC code is preferable in the property retention of different bandwidth condition.For example, (bandwidth is less than BW0 when bandwidth is smaller=10MHz) A0 can be caused to be equal to 0, i.e. G11={ 0 }, and at bandwidth larger (bandwidth is greater than or equal to BW0=10MHz),A0 can be equal to 1 or 2, i.e. G12={ 1,2 }.The concrete numerical value of the BW0 is not limited to above-mentioned numerical value.

Specifically, when the value of the parameter differs, the set T0 is different.

In yet another embodiment of the present invention, the rate-matched output sequence does not include LDPC coding output sequencesA2 successive bits block in the check bit of row, the A2 successive bits block correspond respectively to A2 of the basis matrixColumn index number, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；Wherein, the set T1Element value and element number are determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

Specifically, when the value of the parameter differs, the set T1 is different.

In another embodiment of the present invention, the Rate Matching block, it is defeated specifically for first being encoded to the LDPCGo out sequence to be interleaved by intertexture pattern InP, then sequential selection goes out the rate-matched output sequence；The intertexture patternInP is not mutually equal comprising nb whole as unit of the successive bits block of Z bit, in the intertexture pattern InP from 0 to (nb-1)Number；Wherein, the specific element value of the intertexture pattern InP and specific element number are determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

Wherein, when the value of the parameter differs, the intertexture pattern InP is different.

In yet another embodiment of the present invention, the rate-matched output sequence does not include the information sequence to be encodedMiddle A0 successive bits block, the A0 successive bits block corresponds respectively to A0 column index number of the basis matrix, describedIt is arbitrary integer in 0 to 3 that A0 column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) asThe matrix Matrix0, the mb ' that all elements indicated by line index number form mb ' rows A0 row are greater than 0 less than or equal to mbInteger, the matrix Matrix0 has following at least one condition：

The difference of the row weight of arbitrary 2 row is not more than 1 in the matrix Matrix0；

In the matrix Matrix0 1 element for being used to indicate complete zero square formation is included at least in the element of arbitrary 1 row；

A3 non-full rows are included at least in the matrix Matrix0, the non-full row is that 1 is included at least in row for referring toShow complete zero square formation element；The A3 values are equal to 2 or 3；

The row that 1 row is equal to 1 again is included at least in the matrix Matrix0；

The row that 1 row is equal to A0 again is included at least in the matrix Matrix0.

In yet another embodiment of the present invention, the rate-matched output sequence does not include LDPC coding output sequencesA2 successive bits block in the check bit of row, the A2 successive bits block correspond respectively to A2 of the basis matrixColumn index number, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) asThe matrix Matrix1, the mb ' that all elements indicated by line index number form mb ' rows A2 row are greater than 0 less than or equal to mbInteger, the matrix Matrix1 has following at least one condition：

At most there is 1 finger in 2 elements indicated by identical line index number in arbitrary 2 row in the matrix Matrix1Show the element of the shift size of unit matrix cyclic shift；

Arbitrary 1 row includes up to the member of the shift size of 2 instruction unit matrix cyclic shifts in the matrix Matrix1Element.

In yet another embodiment of the present invention, the rate-matched output sequence does not include the information sequence to be encodedMiddle A0 successive bits block, the A0 successive bits block corresponds respectively to A0 column index number of the basis matrix, describedIt is arbitrary integer in 0 to 3 that A0 column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) asAll elements indicated by line index number form the matrix Matrix0 of mb ' rows A0 row, and it is whole less than mb that the mb ' is greater than 0Number；

The A2 that the rate-matched output sequence is not included in the check bit of the LDPC encoded output sequences is a continuousBit block, the A2 successive bits block correspond respectively to A2 column index number of the basis matrix, the A2 column indexNumber set T1 is formed, the A2 is arbitrary integer in 0 to mb；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) asThe matrix Matrix1, the mb ' that all elements indicated by line index number form mb ' rows A2 row are greater than 0 less than or equal to mbInteger；

The matrix Matrix0 and matrix Matrix1 forms the matrix Matrix2=of mb ' rows (A0+A2) row[Matrix0Matrix1], wherein, matrix Matrix2 has following at least one condition：

Row is equal to the column index of the element of 1 instruction unit matrix cyclic shift in 1 row again in the matrix Matrix2Number it is 0 integer for arriving (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, the column index number of the element of at least 1 instruction unit matrix cyclic shift in arbitrary rowIt is 0 integer for arriving (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, at least the row of 1 row is equal to 2 again, wherein 2 instructions are single in the row that the row weight is 2The column index number of the element of the shift size of position battle array cyclic shift is 0 integer for arriving (A0-1), and A0 is greater than 1 integer；

In the matrix Matrix2, at least the row of 1 row is greater than or equal to A0 again, wherein all instructions are single in the rowThe preceding A0 of the column index number of the element of the shift size of position battle array cyclic shift is 0 integer for arriving (A0-1), A0 be greater than 0 it is wholeNumber.

In rate matching procedure, example as shown in Figure 4, basis matrix is the matrix of a mb=6 rows nb=16 row,Kb=nb-mb=16-6=10, information sequence to be encoded obtain mother's LDPC code sequence 502 after carrying out quasi-cyclic LDPC coding for X,Y=[X, P], wherein P are the redundancy check bits (or can be described as LDPC code check bit) that quasi-cyclic LDPC coding obtains,Black box 503 refers to be used to indicate the element of unit matrix cyclic shift in basis matrix, and black box 504 refers to refer toShow the element of complete zero square formation, it can be seen that the exemplary basis matrix includes being used to indicate complete zero square formation comprising B0=40Element and B1=56 be used to indicate the elements of unit matrix cyclic shift, the dimension of the unit matrix or complete zero square formation is allEach continuous Z bit is to correspond with basis matrix in Z × Z, LDPC mother's code code word 502, as rate matching procedure is exactlyCorresponding N-bit is selected from mother's LDPC code code word Y, so as to obtain the LDPC code word sequence after rate-matched, exampleThe A1 bits in A0 × Z bit and verification sequence in information sequence to be encoded are such as removed, after rate-matched being obtainedLDPC code word sequence.

In Fig. 4 examples, then with the Matrix0 in the one-to-one basis matrix of A0 × Z bit be it is preceding 2 row formMatrix.The characteristics of above-described Matrix0, that brings has the beneficial effect that：Quasi-cyclic LDPC code can be caused in rate-matchedMore excellent performance is obtained in the process.

The characteristics of above-described Matrix1, that brings has the beneficial effect that：Quasi-cyclic LDPC code can be caused in rateWith obtaining more excellent performance in the process.

The characteristics of above-described Matrix2, constrains the relationship of Matrix0 and Matrix1, and that brings has the beneficial effect that：Quasi-cyclic LDPC code can be caused to obtain more excellent performance in rate matching procedure.

In yet another embodiment of the present invention, the system columns kb of the basis matrix of used mb rows nb row；InstituteThe code check for stating LDPC code sequence after rate-matched is R, wherein, there are threshold value R0, R1, kb0, kb1, kb2, kb3, kb4.

If R is less than or equal to R0, kb value ranges are [kb0kb1]；R is more than R0 and is less than or equal to R1, then kb valuesRanging from [kb2kb3]；R is more than R1, then kb value ranges are [kb1kb4]；

Wherein, mb and nb meets relational expression kb=nb-mb, R0 is greater than 0 real number for being less than 1, and R1 is greater than R0 less than 1Real number, kb0 are greater than 0 integer for being less than kb, and kb1 is greater than the integer that kb0 is less than kb, and it is whole less than kb1 that kb2 is greater than kb0Number, kb3 are greater than kb1 less than kb4, and kb4 is greater than the integer of kb3, and R is greater than 0 real number for being less than 1.

In the system columns kb for the basis matrix for determining quasi-cyclic LDPC code, since system columns kb is and information sequenceLength be closely bound up, the length of information sequence is generally equivalent to the product of system columns kb and spreading factor, so systemColumns kb can change in very large range, the code length and its length under different code checks that can flexibly support different lengthDifference, primarily to ensureing that quasi-cyclic LDPC code in corresponding range of code rates and under corresponding code length, obtains more excellentDecoding performance.

Further, the threshold parameter is：R0=2/5, R1=2/3, kb0=8, kb1=12, kb2=10,Kb3=14, kb4=16.The threshold parameter of this example is not limited to the above numerical value.

Further, the code check of LDPC code sequence is greater than or equal to 8/9 and the reality less than 1 for R after the rate-matchedNumber.

In yet another embodiment of the present invention, if the code check of LDPC code sequence is R after the rate-matched, more than R2Under conditions of, it needs first to be interleaved LDPC code sequence Y of the length for nb × Z bit, then selects length as N ratiosLDPC code sequence after special rate-matched；Wherein, shown R2 is greater than 5/6 real number for being less than 1, and R is greater than 0 real number for being less than 1.

Furtherly, described device further includes：

Module is filled, information sequence to be encoded, the filling are obtained for being filled dummy argument bit to source information sequenceThe position of dummy argument bit is in the forepart of the source information sequence.

Furtherly, it further includes：The position of the A0 × Z bit is located at the tail portion of information sequence to be encoded.

Furtherly, the Rate Matching block, specifically for the LDPC encoded output sequences by reset serial number intoRow interweaves, and then selects N-bit rate-matched output sequence；

Wherein, the determining mode for resetting serial number includes：It is unit into rearrangement by Z successive bits block, the ZThe serial number of successive bits block is corresponded in the column index number of the basis matrix, corresponding with the A0 successive bits blockThe column index number of the basis matrix is located at the tail portion in the rearrangement serial number.

Device obtains rate-matched output sequence after quasi-cyclic LDPC coding in the present invention in rate matching procedure,Medium-rate matches output sequence by not selecting A0 successive bits block in information sequence to be encoded and/or not including LDPC volumesA2 successive bits block in the check bit of code output sequence, it is described to be encoded so as to which rate-matched output sequence be made not includeIn information sequence A0 successive bits block and/or, the rate-matched output sequence not include the LDPC encoded output sequencesCheck bit in A2 successive bits block and according to being defined under the conditions of different parameters to A0 and A2, Yi JiyuePosition and A2 successive bits block of the A0 successive bits block of beam in information sequence to be encoded are in LDPC encoded output sequencesPosition, performance of the quasi-cyclic LDPC code in varying environment or scene is improved, to adapt to the performance of various code lengths and code checkIt is required that so as to support flexible code length and code check and retention property good.

Illustrate the present invention device in embodiment.

Specific example 1

A kind of quasi-cyclic LDPC code data processing equipment is provided, including：

Memory module, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；InstituteThe matrix that basis matrix is a mb rows nb row is stated, the element for being used to indicate complete zero square formation is included in the basis matrix and is used forIndicate the element of the shift size of unit matrix cyclic shift, the spreading factor value is used to indicate complete zero square formation or the listThe line number of position battle array, the spreading factor value are greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the whole of mbNumber；The basis matrix can describe basic check matrix or other exponential index matrixes, and (index is displacement battle arrayExponent number) etc., spreading factor value is also lifting values (lift size) or shift value (shift size) or submatrix size (sub-Block size) etc. terms, be not limited to other terms in the patent, the meaning is just as.

Coding module, for obtaining the basis matrix and a spreading factor value from the memory module, based on obtainingThe basis matrix and spreading factor value taken treats coded information sequences and carries out quasi-cyclic LDPC coding, obtains LDPC codingsOutput sequence；

Rate Matching block, for from the LDPC encoded output sequences, selecting rate-matched output sequence.

In the memory module, the row of the basis matrix includes at least 3/4 element of following set again：8,9,9,8,5,6,5,6,6,6,5,6,4,5,5,5,5 }；And/or

The row of the basis matrix include at least 3/4 element of following set again：4,15,4,4,4,16,5,17,4,10,4,3,1,1,1,1,1,1 }；

Wherein, the row refer to again line index in the basis matrix fix and column index be 0~(nb-1) when, be used to indicateThe number of the element of the shift size of unit matrix cyclic shift；

It is described row refer to again column index in the basis matrix fix and line index be 0~(mb-1) when, be used to indicate unitThe number of the element of the shift size of battle array cyclic shift.

And in the basis matrix, the element for being used to indicate complete zero square formation is represented using ' -1 ', is used to indicate unit matrixThe element of cyclic shift uses more than or equal to 0 and is less than the integer representation of the spreading factor value, at this time spreading factor value etc.In 1024, including：The basis matrix is following basis matrix Hb：

An alternatively, basis matrix of the storage, which is characterized in that be used to indicate unit matrix in the basis matrix and followThe element position of the position at least 80% of the element of ring displacement is identical with the position below with reference in basis matrix Hb ' ' 1 '：

And it is used to indicate list in the new basis matrix that is obtained after line replacement and/or column permutation of the basis matrixThe element position of the position at least 80% of the element of position battle array cyclic shift and the position below with reference in basis matrix Hb ' ' 1 'It is identical.The line replacement refers to：Arbitrary 2 row in basis matrix swaps and can carry out multi-pass operation；DescribedColumn permutation refers to：Arbitrary 2 row in basis matrix swap and can carry out multi-pass operation.

Specific example 2

A kind of quasi-cyclic LDPC code data processing equipment is provided, including：

Memory module, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；InstituteThe matrix that basis matrix is a mb rows nb row is stated, the element for being used to indicate complete zero square formation is included in the basis matrix and is used forIndicate the element of the shift size of unit matrix cyclic shift, the spreading factor value is used to indicate complete zero square formation or the listThe line number of position battle array, the spreading factor value are greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the whole of mbNumber；

Coding module, for obtaining the basis matrix and a spreading factor value from the memory module, based on obtainingThe basis matrix and spreading factor value taken treats coded information sequences and carries out quasi-cyclic LDPC coding, obtains LDPC codingsOutput sequence；

Rate Matching block, for from the LDPC encoded output sequences, selecting rate-matched output sequence.

In the Rate Matching block, including：The rate-matched output sequence does not include the information sequence to be encodedMiddle A0 successive bits block, the column index number that the A0 successive bits block corresponds respectively to the basis matrix form setT0, the A0 are arbitrary integer in 0 to 3；Wherein, the element value of the set T0 and element number are by following at least one parameterIt determines：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

In example described below, used basis matrix size example is the basis matrix of mb=8 rows nb=16 row,So the value of T1 is 8 to 15 integer value, i.e., the check bit part of described LDPC encoded output sequences is as unit of Z bitThe call number of number sorting.

The element value and element number of T0 is determined according to the transport block size TBS parameters, wherein, when the transmission block is bigSmall TBS is less than positive integer TBS0, then the value of T0 is set G1；The transport block size TBS is greater than or equal to positive integer TBS0,Then T0 values are set G2；Wherein, the intersection of G1 and G2 is empty set.For example, TBS0 is empty set equal to 1024, G1, G1 is set{0}；Illustrate that the transport block size TBS is less than TBS0=1024, A0 is equal to 0, LDPC encoded output sequences and passes through rateWithout punching (deletion) systematic bits (information bit) after matching；Illustrate that the transport block size TBS is greater than or equal to TBS0=1024, A0, which are equal to 1, LDPC encoded output sequences, needs to punch the systematic bits of (deletion) A0 × Z bit after rate-matched(information bit).

The element value and element number of T0 is determined according to the application scenarios, wherein, the application scenarios include：It is mobile wideThe reliable low time delay communication URLLC and extensive Internet of Things mMTC of band enhancing eMBB, superelevation.When the application scenarios are reliable for superelevationLow time delay communication URLLC and/or extensive Internet of Things mMTC, then the value of T0 is set G1；The application scenarios are mobile wideBand enhancing eMBB, then T0 values are set G2；Wherein, the intersection of G1 and G2 is empty set.For example, application scenarios are reliably low for superelevationTime delay communication URLLC and/or extensive Internet of Things mMTC, G1 are empty set, and G1 is set { 2 }, i.e. it is defeated that A0 is equal to 0, LDPC codingsGo out sequence after rate-matched without punching (deletion) systematic bits (information bit)；Application scenarios enhance for mobile broadbandEMBB illustrates that the transport block size TBS is greater than or equal to TBS0=1024, A0 passes through equal to 2, LDPC encoded output sequencesThe systematic bits (information bit) of punching (deletion) A0 × Z bit are needed after rate-matched.

The element value and element number of T0 is determined according to the user UE types, wherein, the user UE types include LTEVarious mobile subscriber's types of definition.The element value and element number of T0 is determined according to different user types.

The element value and element number of T0 is determined according to the frequency range, wherein, the frequency range is more than arithmetic number FB0, then T0For set G5；The frequency range is less than or equal to arithmetic number FB0, then T0 is set G6；Wherein, the intersection of G5 and G6 is empty set.According toThe T0 is determined according to different frequency range, advantageous effect is：If frequency range is in low frequency part, available bandwidth is smaller, instituteSmall with general data amount, transport block size TBS is also smaller, and low frequency channel multipath etc. is affected, so needing more low bit- rateIt is transmitted, so the concrete numerical value (or T0) of adjustment A0 is also required to, so that the quasi-cyclic LDPC code may be at mostExcellent decoded state, and then the robustness of system can be improved；When frequency range is higher, since available bandwidth is larger, signal it is moreDiameter is reduced, and can transmit the transport block size TBS of bigger and code check higher, adjusting the concrete numerical value of A0 can still ensureThe performance of quasi-cyclic LDPC code is still good under different frequency range；The frequency range refers to the center of the communication bandwidth used in systemFrequency point, such as communication bandwidth are 20MHz, and position is between 1.5GHz~1.52GHz, at this time it is known that its communications band exists1.51GHz。

T0 is determined according to the amount of bandwidth, wherein, the amount of bandwidth is more than arithmetic number BW0, then T0 is set G11；The amount of bandwidth is less than or equal to arithmetic number BW0, then T0 is set G12；Wherein, the intersection of G11 and G12 is empty set.FoundationDifferent bandwidth come determine the concrete numerical value of the A0 (or to include different numerical value and numerical value number different by T0, T0, then it is assumed thatAll it is different), advantageous effect is：When bandwidth is larger, data volume is all bigger, i.e., transport block size TBS also can phaseShould be bigger, however when bandwidth is smaller, the data volume of transmission can cause quasi-cyclic LDPC code in different bandwidth item with regard to smallerThe property retention of part is preferable.For example, (bandwidth is less than BW0=10MHz) can cause A0 to be equal to 0 when bandwidth is smaller, i.e. G11={ 0 }, and at bandwidth larger (bandwidth is greater than or equal to BW0=10MHz), A0 can be equal to 1 or 2, i.e. G12={ 1,2 }.I.e.G11 is empty set, and G12 is { 1,2 }.The concrete numerical value of the BW0 is not limited to above-mentioned numerical value.

The occurrence of A0 is determined according to the code check R, wherein, the code check R is more than arithmetic number R ', then T0 is set G3；The code check R is less than or equal to arithmetic number R ', then T0 is set G4；Arithmetic number R ' is greater than 0 and the real number less than 1, the codeRate R is the code check of the rate-matched output sequence, and R is greater than 0 real number for being less than 1, wherein, the intersection of G3 and G4 are empty set.The T0 is set according to different code checks, advantageous effect is：Quasi-cyclic LDPC code can be obtained under different code checksImpartial preferably decoding performance is obtained, i.e., under identical code length, its performance under different code checks (such as 0.2~0.93) can be relatively more flatIt is sliding, be not in that some code check performance is poor, and part code check better performances.

It is of course also possible to use the combination of transport block size TBS and code check R are determined T0, to increase system communicationRobustness.

T0 is determined according to the channel type, wherein, the channel type is control channel, then T0 is set G7；It is describedChannel type is data channel, then T0 is set G8；Wherein, the intersection of G7 and G8 is empty set.Come according to different channels type trueThe fixed T0, advantageous effect are：The data of general control channel are all that fewer and code check is relatively low, and data channelData volume it is larger and code check is relatively higher, so at this point it is possible to according to data whether be control channel and data channel comeIt determines T0, can cause good in the property retention under different types of data.For example, standard is followed in the data encoding of control channelRing LDPC codings are equal to 0 using A0, i.e. T0 is empty set；And the data encoding quasi-cyclic LDPC coding under data channel is using A0Equal to 1 or 2 (or selecting 1 from { 1,2 }).The T0 is not limited to above-described value.

T0 is determined according to the data transfer direction, wherein, the data transfer direction is transmitting uplink data, then T0 isSet G9；The data transfer direction is downlink data transmission, then T0 is set G10；Wherein, the intersection of G9 and G10 is empty set.The concrete numerical value of the A0 is determined according to different data transmission direction, and advantageous effect is：In general, the number of upstream dataIt is less according to flowing, and the data flow of downlink data is larger, it is possible to always determine that T0 can make according to different transmission side datasThe property retention for obtaining the data encoding of different transmission directions is preferable.The upstream data refers to user terminal (mobile equipment UE)Data are transmitted to base station, downlink data refers to base station to user terminal (mobile equipment UE) transmission data.

It is of course possible to determine T0 according to the combination of TBS call numbers and resource unit number NRB, the TBS call numbers refer toFor the transport block size index number under different MCS (coded modulation scheme) (such as in LTE) in related system, with source unit numberNRB is combined to can be used for indexing and is indicated to obtain transport block size TBS, can determine T0's according to similar the process described aboveValue.

T0, MCS indexes are determined it is of course possible to the combination according to Modulation and Coding Scheme MCS call numbers and resource unit number NRBNumber it can indicate TBS call numbers, and then the combination that above-mentioned foundation TBS call numbers and resource unit number NRB may be used comesDetermine T0.The MCS indexes are usually have a default or signaling to indicate.

It is of course possible to determine T0 according to the combination of code check R and resource unit number NRB, the number of resource unit number NRB is knownMesh may know that number of modulation symbols, according to exponent number, it is known that the size of rate-matched output sequence, so with code check R phasesTransport block size TBS can be obtained by multiplying, and then determining T0 similar to the above.

Can also band and out-of-band instruction determine T0, if data are sent in the bandwidth of system distribution, T0 is collectionIntersection closes G20；If data are sent in outside the bandwidth of system distribution, T0 is set set G21；Wherein, the friendship of G20 and G21Integrate as empty set.

Above-described T0 values are not limited to the above method.

Specific example 3

A kind of quasi-cyclic LDPC code data processing equipment is provided, including：

Memory module, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；InstituteThe matrix that basis matrix is a mb rows nb row is stated, the element for being used to indicate complete zero square formation is included in the basis matrix and is used forIndicate the element of the shift size of unit matrix cyclic shift, the spreading factor value is used to indicate complete zero square formation or the listThe line number of position battle array, the spreading factor value are greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the whole of mbNumber；

Coding module, for obtaining the basis matrix and a spreading factor value from the memory module, based on obtainingThe basis matrix and spreading factor value taken treats coded information sequences and carries out quasi-cyclic LDPC coding, obtains LDPC codingsOutput sequence；

Rate Matching block, for from the LDPC encoded output sequences, selecting rate-matched output sequence.

In the Rate Matching block, including：The rate-matched output sequence does not include LDPC coding output sequencesA2 successive bits block in the check bit of row, the A2 successive bits block correspond respectively to the row rope of the basis matrixIt is arbitrary integer in 0 to mb that quotation marks, which form set T1, the A2,；Wherein, the element value of the set T1 and element number by withLower at least one parameter determines：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

In example described below, used basis matrix size example is the basis matrix of mb=8 rows nb=16 row,So the value of T1 is 8 to 15 integer value, i.e., the check bit part of described LDPC encoded output sequences is as unit of Z bitThe call number of number sorting.

The element value and element number of T1 is determined according to the transport block size TBS parameters, wherein, when the transmission block is bigSmall TBS is less than positive integer TBS0, then the value of T1 is set G1；The transport block size TBS is greater than or equal to positive integer TBS0,Then T1 values are set G2；Wherein, the TBS0 is the integer less than 4096 more than 600.For example, TBS0 is equal to 892, G1 for collectionIt closes { 8,10,12,13,14,15 }, G2 is set { 9,11,12,13,14,15 }.

The element value and element number of T1 is determined according to the application scenarios, wherein, the application scenarios include：It is mobile wideThe reliable low time delay communication URLLC and extensive Internet of Things mMTC of band enhancing eMBB, superelevation.When the application scenarios are reliable for superelevationLow time delay communicate URLLC and/or extensive Internet of Things mMTC, then the value of T1 be set G3 be gather 8,10,12,13,14,15}；The application scenarios enhance eMBB for mobile broadband, then T1 values are set G4, G4 for gather 9,11,12,13,14,15}。

The element value and element number of T1 is determined according to the user UE types, wherein, the user UE types include LTEVarious mobile subscriber's types of definition.The element value and element number of T1 is determined according to different user types.

The element value and element number of T1 is determined according to the frequency range, wherein, the frequency range is more than arithmetic number FB0, then T1For set G5；The frequency range is less than or equal to arithmetic number FB0, then T1 is set G6.G5 is set { 8,10,11,13,14,15 },G6 is set { 9,10,12,13,14,15 }.The T1 is determined according to different frequency range, and advantageous effect is：If frequency range is inLow frequency part, available bandwidth is smaller, so general data amount is small, transport block size TBS is also smaller, low frequency channel multipathEtc. being affected, so more low bit- rate is needed to be transmitted, so the concrete numerical value (or T1) of adjustment A2 is also required to, so thatThe quasi-cyclic LDPC code may be at optimal decoded state, and then can improve the robustness of system；When frequency range is higher, byLarger in available bandwidth, the multipath of signal is reduced, and can transmit the transport block size TBS of bigger and code check higher, is adjustedThe concrete numerical value of A2 can still ensure that the performance of quasi-cyclic LDPC code is still good under different frequency range；The frequency range refers toThe center frequency points of communication bandwidth used in system, for example, communication bandwidth be 20MHz, position between 1.5GHz~1.52GHz,At this time it is known that its communications band is in 1.51GHz.

T1 is determined according to the amount of bandwidth, wherein, the amount of bandwidth is more than arithmetic number BW0, then T1 is set G11；The amount of bandwidth is less than or equal to arithmetic number BW0, then T1 is set G12.Determine that the A2's is specific according to different bandwidthNumerical value (or T1, T1 include different numerical value and numerical value number is different, then it is assumed that and all it is different), advantageous effect is：When bandwidth is larger, data volume is all bigger, i.e. transport block size TBS also can be accordingly bigger, however when bandwidth is smaller, it passesDefeated data volume can so that quasi-cyclic LDPC code is preferable in the property retention of different bandwidth condition with regard to smaller.For example, G11To gather { 8,10,12,13,14,15 }, G12 is set { 9,11,12,13,14,15 }

The occurrence of A2 is determined according to the code check R, wherein, the code check R is more than arithmetic number R ', then T1 is set G3；The code check R is less than or equal to arithmetic number R ', then T1 is set G4；Arithmetic number R ' is greater than 0 and the real number less than 1, the codeRate R is the code check of the rate-matched output sequence, and R is greater than 0 real number for being less than 1, wherein, the intersection of G3 and G4 are empty set.The T1 is set according to different code checks, advantageous effect is：Quasi-cyclic LDPC code can be obtained under different code checksImpartial preferably decoding performance is obtained, i.e., under identical code length, its performance under different code checks (such as 0.2~0.93) can be relatively more flatIt is sliding, be not in that some code check performance is poor, and part code check better performances.For example, G3 for set 8,10,12,13,14,15 }, G4 is set { 9,11,12,13,14,15 }

It is of course also possible to use the combination of transport block size TBS and code check R are determined T1, to increase system communicationRobustness.

T1 is determined according to the channel type, wherein, the channel type is control channel, then T1 is set G7；It is describedChannel type is data channel, then T1 is set G8；Wherein, the intersection of G7 and G8 is empty set.Come according to different channels type trueThe fixed T1, advantageous effect are：The data of general control channel are all that fewer and code check is relatively low, and data channelData volume it is larger and code check is relatively higher, so at this point it is possible to according to data whether be control channel and data channel comeIt determines T1, can cause good in the property retention under different types of data.For example, for example, G7 for set 8,10,12,13,14,15 }, G8 is set { 9,11,12,13,14,15 }.The T1 is not limited to above-described value.

T1 is determined according to the data transfer direction, wherein, the data transfer direction is transmitting uplink data, then T1 isSet G9；The data transfer direction is downlink data transmission, then T1 is set G10；Wherein, the intersection of G9 and G10 is empty set.The concrete numerical value of the A2 is determined according to different data transmission direction, and advantageous effect is：In general, the number of upstream dataIt is less according to flowing, and the data flow of downlink data is larger, it is possible to always determine that T1 can make according to different transmission side datasThe property retention for obtaining the data encoding of different transmission directions is preferable.The upstream data refers to user terminal (mobile equipment UE)Data are transmitted to base station, downlink data refers to base station to user terminal (mobile equipment UE) transmission data.For example, G9 is set{ 8,10,12,13,14,15 }, G10 are set { 9,11,12,13,14,15 }

It is of course possible to determine T1 according to the combination of TBS call numbers and resource unit number NRB, the TBS call numbers refer toFor the transport block size index number under different MCS (coded modulation scheme) (such as in LTE) in related system, with source unit numberNRB is combined to can be used for indexing and is indicated to obtain transport block size TBS, can determine T1's according to similar the process described aboveValue.

T1, MCS indexes are determined it is of course possible to the combination according to Modulation and Coding Scheme MCS call numbers and resource unit number NRBNumber it can indicate TBS call numbers, and then the combination that above-mentioned foundation TBS call numbers and resource unit number NRB may be used comesDetermine T1.The MCS indexes are usually have a default or signaling to indicate.

It is of course possible to determine T1 according to the combination of code check R and resource unit number NRB, the number of resource unit number NRB is knownMesh may know that number of modulation symbols, according to exponent number, it is known that the size of rate-matched output sequence, so with code check R phasesTransport block size TBS can be obtained by multiplying, and then determining T1 similar to the above.

Can also band and out-of-band instruction determine T1, if data are sent in the bandwidth of system distribution, T1 is collectionIntersection closes G20；If data are sent in outside the bandwidth of system distribution, T1 is set set G21；Wherein, the friendship of G20 and G21Integrate as empty set.For example, G20 is set { 8,10,12,13,14 }, G21 is set { 9,11,12,13,14,15 }.

Above-described T0 values are not limited to the above method.

Specific example 4

A kind of quasi-cyclic LDPC code data processing equipment is provided, including：

Memory module, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；InstituteThe matrix that basis matrix is a mb rows nb row is stated, the element for being used to indicate complete zero square formation is included in the basis matrix and is used forIndicate the element of the shift size of unit matrix cyclic shift, the spreading factor value is used to indicate complete zero square formation or the listThe line number of position battle array, the spreading factor value are greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the whole of mbNumber；

Coding module, for obtaining the basis matrix and a spreading factor value from the memory module, based on obtainingThe basis matrix and spreading factor value taken treats coded information sequences and carries out quasi-cyclic LDPC coding, obtains LDPC codingsOutput sequence；

Rate Matching block, for from the LDPC encoded output sequences, selecting rate-matched output sequence.

In the Rate Matching block, including：First the LDPC encoded output sequences are interleaved by intertexture pattern InPThen sequential selection goes out the rate-matched output sequence, and the intertexture pattern InP is using the successive bits block of Z bit as list, the integers being not mutually equal in the intertexture pattern InP comprising nb from 0 to (nb-1)；Wherein, the intertexture pattern InPSpecific element value and specific element number are determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

According to above-described different condition, intertexture pattern InP can be from following

Specific example 5

A kind of quasi-cyclic LDPC code data processing equipment is also provided, including：

Memory module, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；InstituteThe matrix that basis matrix is a mb rows nb row is stated, the element for being used to indicate complete zero square formation is included in the basis matrix and is used forIndicate the element of the shift size of unit matrix cyclic shift, the spreading factor value is used to indicate complete zero square formation or the listThe line number of position battle array, the spreading factor value are greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the whole of mbNumber；

Coding module, for obtaining the basis matrix and a spreading factor value from the memory module, based on obtainingThe basis matrix and spreading factor value taken treats coded information sequences and carries out quasi-cyclic LDPC coding, obtains LDPC codingsOutput sequence；

Rate Matching block, for from the LDPC encoded output sequences, selecting rate-matched output sequence.

In the Rate Matching block, including：The rate-matched output sequence does not include the information sequence to be encodedMiddle A0 successive bits block, the column index number that the A0 successive bits block corresponds respectively to the basis matrix form setT0, the A0 are arbitrary integer in 0 to 3；In the basis matrix, in the set T0 all elements value as column index number andThe matrix Matrix0, the mb ' that line index number forms mb ' rows A0 row for all elements indicated by 0 to (mb ' -1) are greater than 0Integer less than mb, the matrix Matrix0 have following at least one condition：

The difference of the row weight of arbitrary 2 row is not more than 1 in the matrix Matrix0；

In the matrix Matrix0 1 element for being used to indicate complete zero square formation is included at least in the element of arbitrary 1 row；

A3 non-full rows are included at least in the matrix Matrix0, the non-full row is that 1 is included at least in row for referring toShow complete zero square formation element；The A3 values are equal to 2 or 3；

The row that 1 row is equal to 1 again is included at least in the matrix Matrix0；

The row that 1 row is equal to A0 again is included at least in the matrix Matrix0.

The advantageous effect of the operation is：So that the LDPC decoding performances are preferable, and support flexible code length and code checkDesign.

Specific example 6

A kind of quasi-cyclic LDPC code data processing equipment is provided, including：

Memory module, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；InstituteThe matrix that basis matrix is a mb rows nb row is stated, the element for being used to indicate complete zero square formation is included in the basis matrix and is used forIndicate the element of the shift size of unit matrix cyclic shift, the spreading factor value is used to indicate complete zero square formation or the listThe line number of position battle array, the spreading factor value are greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the whole of mbNumber；

Coding module, for obtaining the basis matrix and a spreading factor value from the memory module, based on obtainingThe basis matrix and spreading factor value taken treats coded information sequences and carries out quasi-cyclic LDPC coding, obtains LDPC codingsOutput sequence；

Rate Matching block, for from the LDPC encoded output sequences, selecting rate-matched output sequence.

In the Rate Matching block, including：The rate-matched output sequence does not include LDPC coding output sequencesA2 successive bits block in the check bit of row, the A2 successive bits block correspond respectively to the row rope of the basis matrixIt is arbitrary integer in 0 to mb that quotation marks, which form set T1, the A2,；In the basis matrix, all elements value in the set T0The matrix Matrix1 of mb ' rows A2 row is formed for all elements indicated by 0 to (mb ' -1) as column index number and line index number,The mb ' is greater than 0 integer for being less than mb, and the matrix Matrix1 has following at least one condition：

At most there is 1 finger in 2 elements indicated by identical line index number in arbitrary 2 row in the matrix Matrix1Show the element of the shift size of unit matrix cyclic shift；

Arbitrary 1 row includes up to the member of the shift size of 2 instruction unit matrix cyclic shifts in the matrix Matrix1Element.

The advantageous effect of the operation is：So that the LDPC decoding performances are preferable, and support flexible code length and code checkDesign.

Specific example 7

A kind of quasi-cyclic LDPC code data processing equipment is also provided, including：

Memory module, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；InstituteThe matrix that basis matrix is a mb rows nb row is stated, the element for being used to indicate complete zero square formation is included in the basis matrix and is used forIndicate the element of the shift size of unit matrix cyclic shift, the spreading factor value is used to indicate complete zero square formation or the listThe line number of position battle array, the spreading factor value are greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the whole of mbNumber；

Coding module, for obtaining the basis matrix and a spreading factor value from the memory module, based on obtainingThe basis matrix and spreading factor value taken treats coded information sequences and carries out quasi-cyclic LDPC coding, obtains LDPC codingsOutput sequence；

Rate Matching block, for from the LDPC encoded output sequences, selecting rate-matched output sequence.

In the Rate Matching block, including：The rate-matched output sequence does not include the information sequence to be encodedMiddle A0 successive bits block, the column index number that the A0 successive bits block corresponds respectively to the basis matrix form setT0, the A0 are arbitrary integer in 0 to 3；In the basis matrix, in the set T0 all elements value as column index number andThe matrix Matrix0, the mb ' that line index number forms mb ' rows A0 row for all elements indicated by 0 to (mb ' -1) are greater than 0Integer less than mb；

The A2 that the rate-matched output sequence is not included in the check bit of the LDPC encoded output sequences is a continuousBit block, column index number composition the set T1, the A2 that the A2 successive bits block corresponds respectively to the basis matrix are 0The arbitrary integer into mb；In the basis matrix, all elements value is 0 as column index number and line index number in the set T0The matrix Matrix1 of mb ' rows A2 row is formed to all elements indicated by (mb ' -1), it is whole less than mb that the mb ' is greater than 0Number；

The matrix Matrix0 and matrix Matrix1 forms the matrix Matrix2=of mb ' rows (A0+A2) row[Matrix0Matrix1], wherein, matrix Matrix2 has following at least one condition：

Row is equal to the column index of the element of 1 instruction unit matrix cyclic shift in 1 row again in the matrix Matrix2Number it is 0 integer for arriving (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, the column index number of the element of at least 1 instruction unit matrix cyclic shift in arbitrary rowIt is 0 integer for arriving (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, at least the row of 1 row is equal to 2 again, wherein 2 instructions are single in the row that the row weight is 2The column index number of the element of the shift size of position battle array cyclic shift is 0 integer for arriving (A0-1), and A0 is greater than 1 integer；

In the matrix Matrix2, at least the row of 1 row is greater than or equal to A0 again, wherein all instructions are single in the rowThe preceding A0 of the column index number of the element of the shift size of position battle array cyclic shift is 0 integer for arriving (A0-1), A0 be greater than 0 it is wholeNumber.

The advantageous effect of the operation is：So that the LDPC decoding performances are preferable, and support flexible code length and code checkDesign.

Based on the various embodiments described above, present invention further propose that a kind of quasi-cyclic LDPC code data processing method.

As shown in figure 5, a kind of quasi-cyclic LDPC code data processing method in the embodiment of the present invention, including：

S501, from the basis matrix and one group of spreading factor value used in pre-stored quasi-cyclic LDPC coding,Obtain the basis matrix and a spreading factor value；The basis matrix is the matrix of a mb rows nb row, the basis squareThe element for being used to indicate complete zero square formation and the element for the shift size for being used to indicate unit matrix cyclic shift, the expansion are included in battle arrayExhibition factor values are used to indicate complete zero square formation or the line number of the unit matrix, and the spreading factor value is greater than 0 integer, instituteThe integer that mb is greater than 0 is stated, the nb is greater than the integer of mb；

S502, the basis matrix parameter and spreading factor value based on acquisition are treated coded information sequences progress standard and are followedRing LDPC is encoded, and obtains mother's LDPC codeword sequence；

S503 from mother's LDPC codeword sequence, selects rate-matched output sequence.

In one embodiment of the invention, the row of the basis matrix includes at least 3/4 element of following set again：{ 8,9,9,8,5,6,5,6,6,6,5,6,4,5,5,5,5 }；And/or

The row of the basis matrix include at least 3/4 element of following set again：17,5,16,4,4,4,15,4,4,10,4,3,1,1,1,1,1,1,1,1,1,1,1,1,1 }；

Wherein, the row refer to again line index in the basis matrix fix and column index be 0~(nb-1) when, be used to indicateThe number of the element of unit matrix cyclic shift；

It is described row refer to again column index in the basis matrix fix and line index be 0~(mb-1) when, be used to indicate unitThe number of the element of battle array cyclic shift.

In one embodiment of the invention, in the basis matrix, the element for being used to indicate complete zero square formation uses ' -1 'It represents, the element for being used to indicate unit matrix cyclic shift is used more than or equal to 0 and less than the integer table of the spreading factor valueShow；The element of the basis matrix at least 80% is identical with below with reference to basis matrix Hb：

In one embodiment of the invention in being used to indicate the element of unit matrix cyclic shift in the basis matrixThe element position of position at least 80% is identical with the position below with reference in basis matrix Hb ' ' 1 '：

Specifically, it is used to indicate in the new basis matrix that the basis matrix obtains after line replacement and/or column permutationThe element position of the position of the element of unit matrix cyclic shift at least 80% and the position phase with reference in basis matrix Hb ' ' 1 'Together.

In one embodiment of the invention, the rate-matched output sequence does not include in the information sequence to be encodedA0 successive bits block, the A0 successive bits block correspond respectively to A0 column index number of the basis matrix, the A0It is arbitrary integer in 0 to 3 that a column index number, which forms set T0, the A0,；Wherein, the element value and element number of the set T0It is determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

Specifically, if the transport block size TBS is less than setting positive integer, TBS0, the A0 are any member in set G1Element value；

If the transport block size TBS is greater than or equal to setting positive integer, TBS0, the A0 are any member in set G2Element value；

Wherein, the element value that the set G1 neutralizes in the set G2 is 0 to 3 integer respectively, and the set G1Intersection with the set G2 is empty set；The numberical range of the positive integer TBS0 is to be less than 4096 more than 256.

Specifically, if the code check R is more than setting arithmetic number, R ', the A0 are either element value in set G3；

If the code check R is less than or equal to setting arithmetic number, R ', the A0 are either element value in set G4；

Wherein, the arithmetic number R ' is greater than 0 and the real number less than 1, and the code check R is greater than 0 real number for being less than 1, instituteState the integer that the element value that set G3 is neutralized in the set G4 is 0 to 3 respectively, and the friendship of the set G3 and the set G4Integrate as empty set.

Specifically, if the frequency range is more than setting arithmetic number, FB0, the A0 are either element value in set G5；

If the frequency range is less than or equal to setting arithmetic number, FB0, the A0 are either element value in set G6；

Wherein, the element value that the set G5 neutralizes in the set G6 is 0 to 3 integer respectively, and the set G5Intersection with the set G6 is empty set.

Specifically, if the channel type is control channel, the A0 is either element value in set G7；

If the channel type is data channel, the A0 is either element value in set G8；

Wherein, the element value that the set G7 neutralizes in the set G8 is 0 to 3 integer, and the set G7 and instituteThe intersection for stating set G8 is empty set.

Specifically, if the data transfer direction is transmitting uplink data, the A0 is either element value in set G9；

If the data transfer direction is downlink data transmission, the A0 is either element value in set G10；

Wherein, the element value that the set G9 neutralizes in the set G10 is 0 to 3 integer, and the set G9 and instituteThe intersection for stating set G10 is empty set.

Specifically, if the band is wider than arithmetic number, BW0, the A0 are either element value in set G11；

If the frequency range is less than or equal to arithmetic number, BW0, the A0 are either element value in set G12；

Wherein, the element value that the set G11 neutralizes in the set G12 is 0 to 3 integer, and the set G11 withThe intersection of the set G12 is empty set.

Furtherly, when the value of the parameter differs, the set T0 is different.

In one embodiment of the invention, the rate-matched output sequence does not include the LDPC encoded output sequencesCheck bit in A2 successive bits block, the A2 successive bits block corresponds respectively to A2 of basis matrix rowCall number, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；Wherein, the member of the set T1Plain value and element number are determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

Specifically, when the value of the parameter differs, the set T1 is different.

In one embodiment of the invention, it is described from mother's LDPC codeword sequence, select rate-matched outputSequence, including：

First the LDPC encoded output sequences are interleaved by intertexture pattern InP, then sequential selection goes out the rateMatch output sequence；The intertexture pattern InP is included as unit of the successive bits block of Z bit in the intertexture pattern InPThe nb integers being not mutually equal from 0 to (nb-1)；Wherein, the specific element value and specific element number of the intertexture pattern InPIt is determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

In one embodiment of the invention, when the value of the parameter differs, the intertexture pattern InP is different.

In one embodiment of the invention, the rate-matched output sequence does not include in the information sequence to be encodedA0 successive bits block, the A0 successive bits block correspond respectively to A0 column index number of the basis matrix, the A0It is arbitrary integer in 0 to 3 that a column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) asThe matrix Matrix0, the mb ' that all elements indicated by line index number form mb ' rows A0 row are greater than 0 less than or equal to mbInteger, the matrix Matrix0 has following at least one condition：

The difference of the row weight of arbitrary 2 row is not more than 1 in the matrix Matrix0；

In the matrix Matrix0 1 element for being used to indicate complete zero square formation is included at least in the element of arbitrary 1 row；

A3 non-full rows are included at least in the matrix Matrix0, the non-full row is that 1 is included at least in row for referring toShow complete zero square formation element；The A3 values are equal to 2 or 3；

The row that 1 row is equal to 1 again is included at least in the matrix Matrix0；

The row that 1 row is equal to A0 again is included at least in the matrix Matrix0.

In one embodiment of the invention, the rate-matched output sequence does not include the LDPC encoded output sequencesCheck bit in A2 successive bits block, the A2 successive bits block corresponds respectively to A2 of basis matrix rowCall number, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) asThe matrix Matrix1, the mb ' that all elements indicated by line index number form mb ' rows A2 row are greater than 0 less than or equal to mbInteger, the matrix Matrix1 has following at least one condition：

At most there is 1 finger in 2 elements indicated by identical line index number in arbitrary 2 row in the matrix Matrix1Show the element of the shift size of unit matrix cyclic shift；

Arbitrary 1 row includes up to the member of the shift size of 2 instruction unit matrix cyclic shifts in the matrix Matrix1Element.

In one embodiment of the invention, the rate-matched output sequence does not include in the information sequence to be encodedA0 successive bits block, the A0 successive bits block correspond respectively to A0 column index number of the basis matrix, the A0It is arbitrary integer in 0 to 3 that a column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) asAll elements indicated by line index number form the matrix Matrix0 of mb ' rows A0 row, and it is whole less than mb that the mb ' is greater than 0Number；

The A2 that the rate-matched output sequence is not included in the check bit of the LDPC encoded output sequences is a continuousBit block, the A2 successive bits block correspond respectively to A2 column index number of the basis matrix, the A2 column indexNumber set T1 is formed, the A2 is arbitrary integer in 0 to mb；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) asThe matrix Matrix1, the mb ' that all elements indicated by line index number form mb ' rows A2 row are greater than 0 less than or equal to mbInteger；

The matrix Matrix0 and matrix Matrix1 forms the matrix Matrix2=of mb ' rows (A0+A2) row[Matrix0Matrix1], wherein, matrix Matrix2 has following at least one condition：

Row is equal to the column index of the element of 1 instruction unit matrix cyclic shift in 1 row again in the matrix Matrix2Number it is 0 integer for arriving (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, the column index number of the element of at least 1 instruction unit matrix cyclic shift in arbitrary rowIt is 0 integer for arriving (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, at least the row of 1 row is equal to 2 again, wherein 2 instructions are single in the row that the row weight is 2The column index number of the element of the shift size of position battle array cyclic shift is 0 integer for arriving (A0-1), and A0 is greater than 1 integer；

In the matrix Matrix2, at least the row of 1 row is greater than or equal to A0 again, wherein all instructions are single in the rowThe preceding A0 of the column index number of the element of the shift size of position battle array cyclic shift is 0 integer for arriving (A0-1), A0 be greater than 0 it is wholeNumber.

In yet another embodiment of the present invention, if the code check R of the LDPC code sequence of the rate-matched is less than or equal toThresholding R0 is set, then the system columns kb value ranges of the basis matrix are [setting thresholding kb0 sets thresholding kb1]；

If the code check R of the LDPC code sequence of the rate-matched is more than setting thresholding R0 and less than or equal to setting thresholdingR1, then the system columns kb value ranges of the basis matrix are [setting thresholding kb2 sets thresholding kb3]；

If the code check R of the LDPC code sequence of the rate-matched is more than R1, the system columns kb of the basis matrix takesValue ranging from [setting thresholding kb1 setting thresholdings kb4]；

Wherein, the setting thresholding R0 is greater than 0 real number for being less than 1, and the setting thresholding R1 is greater than the setting doorThe real number that R0 is less than 1 is limited, the setting thresholding kb0 is greater than 0 and the integer less than kb, the setting thresholding kb1 are greater than instituteSetting thresholding kb0 and the integer less than kb are stated, the setting thresholding kb2 is greater than the setting thresholding kb0 and is set less than describedDetermine the integer of thresholding kb1, the setting thresholding kb3 is greater than the setting thresholding kb1 and less than the setting thresholding kb4, instituteState the integer that setting thresholding kb4 is greater than the setting thresholding kb3.

In yet another embodiment of the present invention, the setting thresholding R0=2/5, the setting thresholding R1=2/3 are describedSet thresholding kb0=8, the setting thresholding kb1=12, the setting thresholding kb2=10, the setting thresholding kb3=14, instituteState setting thresholding kb4=16.

Specifically, the code check R of the LDPC code sequence of the rate-matched is greater than or equal to 8/9 and the real number less than 1.

In yet another embodiment of the present invention, if the code check R of the LDPC code sequence of the rate-matched is more than R2, to instituteIt states LDPC encoded output sequences to be interleaved, then selects the rate-matched output sequence of N-bit rate-matched；Wherein, instituteIt states R2 and is greater than 5/6 real number for being less than 1, the code check R of the LDPC code sequence of the rate-matched is greater than 0 real number for being less than 1.

Furtherly, the method further includes：

Dummy argument bit is filled to source information sequence and obtains information sequence to be encoded, the position of the filling dummy argument bitIn the forepart of the source information sequence.

Furtherly, the position of the A0 × Z bit is located at the tail portion of information sequence to be encoded.

Furtherly, the method further includes：

The LDPC encoded output sequences by serial number is reset are interleaved, then select the output of N-bit rate-matchedSequence；

Wherein, the determining mode for resetting serial number includes：It is unit into rearrangement by Z successive bits block, the ZThe serial number of successive bits block is corresponded in the column index number of the basis matrix, corresponding with the A0 successive bits blockThe column index number of the basis matrix is located at the tail portion in the rearrangement serial number.

Method obtains rate-matched output sequence after quasi-cyclic LDPC coding in the present invention in rate matching procedure,Medium-rate matches output sequence by not selecting A0 successive bits block in information sequence to be encoded and/or not including LDPC volumesA2 successive bits block in the check bit of code output sequence, it is described to be encoded so as to which rate-matched output sequence be made not includeIn information sequence A0 successive bits block and/or, the rate-matched output sequence not include the LDPC encoded output sequencesCheck bit in A2 successive bits block and according to being defined under the conditions of different parameters to A0 and A2, Yi JiyuePosition and A2 successive bits block of the A0 successive bits block of beam in information sequence to be encoded are in LDPC encoded output sequencesPosition, performance of the quasi-cyclic LDPC code in varying environment or scene is improved, to adapt to the performance of various code lengths and code checkIt is required that so as to support flexible code length and code check and retention property good.

Based on method in the various embodiments described above, present invention further propose that a kind of quasi-cyclic LDPC code data processing equipment.

A kind of quasi-cyclic LDPC code data processing equipment, described including processor and storage device in the embodiment of the present inventionStorage device memory contains a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value and is stored with moreTo realize LDPC code data processing method, the processor performs the multiple instruction to realize for a instruction：

The basis matrix and a spreading factor value are obtained from the memory module, the basic square based on acquisitionBattle array and spreading factor value treat coded information sequences and carry out quasi-cyclic LDPC coding, obtain LDPC encoded output sequences；The basePlinth matrix is the matrix of a mb rows nb row, and the element for being used to indicate complete zero square formation is included in the basis matrix and is used to indicateThe element of the shift size of unit matrix cyclic shift, the spreading factor value are used to indicate complete zero square formation or the unit matrixLine number, the spreading factor value is greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the integer of mb；

From the LDPC encoded output sequences, rate-matched output sequence is selected.

In one embodiment of the invention, the row of the basis matrix includes at least 3/4 element of following set again：{ 8,9,9,8,5,6,5,6,6,6,5,6,4,5,5,5,5 }；And/or

The row of the basis matrix include at least 3/4 element of following set again：17,5,16,4,4,4,15,4,4,10,4,3,1,1,1,1,1,1,1,1,1,1,1,1,1 }；

Wherein, the row refer to again line index in the basis matrix fix and column index be 0~(nb-1) when, be used to indicateThe number of the element of unit matrix cyclic shift；

It is described row refer to again column index in the basis matrix fix and line index be 0~(mb-1) when, be used to indicate unitThe number of the element of battle array cyclic shift.

In one embodiment of the invention, in the basis matrix, the element for being used to indicate complete zero square formation uses ' -1 'It represents, the element for being used to indicate unit matrix cyclic shift is used more than or equal to 0 and less than the integer table of the spreading factor valueShow；The element of the basis matrix at least 80% is identical with below with reference to basis matrix Hb：

In one embodiment of the invention, the position of the element of unit matrix cyclic shift is used to indicate in the basis matrixPut at least 80% element position it is identical with the position below with reference in basis matrix Hb ' ' 1 '：

Specifically, it is used to indicate in the new basis matrix that the basis matrix obtains after line replacement and/or column permutationThe element position of the position of the element of unit matrix cyclic shift at least 80% and the position phase with reference in basis matrix Hb ' ' 1 'Together.

In one embodiment of the invention, the rate-matched output sequence does not include in the information sequence to be encodedA0 successive bits block, the A0 successive bits block correspond respectively to A0 column index number of the basis matrix, the A0It is arbitrary integer in 0 to 3 that a column index number, which forms set T0, the A0,；Wherein, the element value and element number of the set T0It is determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

Specifically, when the value of the parameter differs, the set T0 is different.

In one embodiment of the invention, the rate-matched output sequence does not include the LDPC encoded output sequencesCheck bit in A2 successive bits block, the A2 successive bits block corresponds respectively to A2 of basis matrix rowCall number, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；Wherein, the member of the set T1Plain value and element number are determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

Specifically, when the value of the parameter differs, the set T1 is different.

In one embodiment of the invention, the Rate Matching block is exported specifically for first being encoded to the LDPCSequence is interleaved by intertexture pattern InP, and then sequential selection goes out the rate-matched output sequence；The intertexture patternInP is not mutually equal comprising nb whole as unit of the successive bits block of Z bit, in the intertexture pattern InP from 0 to (nb-1)Number；Wherein, the specific element value of the intertexture pattern InP and specific element number are determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R groupConjunction, channel type, data transfer direction, TBS call numbers and resource unit number NRB combination, Modulation and Coding Scheme MCS call numbersCombination, amount of bandwidth, the band and out-of-band instruction of combination, code check R and resource unit number NRB with resource unit number NRB.

Specifically, when the value of the parameter differs, the intertexture pattern InP is different.

In one embodiment of the invention, the rate-matched output sequence does not include in the information sequence to be encodedA0 successive bits block, the A0 successive bits block correspond respectively to A0 column index number of the basis matrix, the A0It is arbitrary integer in 0 to 3 that a column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) asThe matrix Matrix0, the mb ' that all elements indicated by line index number form mb ' rows A0 row are greater than 0 less than or equal to mbInteger, the matrix Matrix0 has following at least one condition：

The difference of the row weight of arbitrary 2 row is not more than 1 in the matrix Matrix0；

In the matrix Matrix0 1 element for being used to indicate complete zero square formation is included at least in the element of arbitrary 1 row；

A3 non-full rows are included at least in the matrix Matrix0, the non-full row is that 1 is included at least in row for referring toShow complete zero square formation element；The A3 values are equal to 2 or 3；

The row that 1 row is equal to 1 again is included at least in the matrix Matrix0；

The row that 1 row is equal to A0 again is included at least in the matrix Matrix0.

In one embodiment of the invention, the rate-matched output sequence does not include the LDPC encoded output sequencesCheck bit in A2 successive bits block, the A2 successive bits block corresponds respectively to A2 of basis matrix rowCall number, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) asThe matrix Matrix1, the mb ' that all elements indicated by line index number form mb ' rows A2 row are greater than 0 less than or equal to mbInteger, the matrix Matrix1 has following at least one condition：

At most there is 1 finger in 2 elements indicated by identical line index number in arbitrary 2 row in the matrix Matrix1Show the element of the shift size of unit matrix cyclic shift；

Arbitrary 1 row includes up to the member of the shift size of 2 instruction unit matrix cyclic shifts in the matrix Matrix1Element.

In one embodiment of the invention, the rate-matched output sequence does not include in the information sequence to be encodedA0 successive bits block, the A0 successive bits block correspond respectively to A0 column index number of the basis matrix, the A0It is arbitrary integer in 0 to 3 that a column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) asAll elements indicated by line index number form the matrix Matrix0 of mb ' rows A0 row, and it is whole less than mb that the mb ' is greater than 0Number；

The A2 that the rate-matched output sequence is not included in the check bit of the LDPC encoded output sequences is a continuousBit block, the A2 successive bits block correspond respectively to A2 column index number of the basis matrix, the A2 column indexNumber set T1 is formed, the A2 is arbitrary integer in 0 to mb；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) asThe matrix Matrix1, the mb ' that all elements indicated by line index number form mb ' rows A2 row are greater than 0 less than or equal to mbInteger；

The matrix Matrix0 and matrix Matrix1 forms the matrix Matrix2=of mb ' rows (A0+A2) row[Matrix0Matrix1], wherein, matrix Matrix2 has following at least one condition：

Row is equal to the column index of the element of 1 instruction unit matrix cyclic shift in 1 row again in the matrix Matrix2Number it is 0 integer for arriving (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, the column index number of the element of at least 1 instruction unit matrix cyclic shift in arbitrary rowIt is 0 integer for arriving (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, at least the row of 1 row is equal to 2 again, wherein 2 instructions are single in the row that the row weight is 2The column index number of the element of the shift size of position battle array cyclic shift is 0 integer for arriving (A0-1), and A0 is greater than 1 integer；

In the matrix Matrix2, at least the row of 1 row is greater than or equal to A0 again, wherein all instructions are single in the rowThe preceding A0 of the column index number of the element of the shift size of position battle array cyclic shift is 0 integer for arriving (A0-1), A0 be greater than 0 it is wholeNumber.

Device obtains rate-matched output sequence after quasi-cyclic LDPC coding in the present invention in rate matching procedure,Medium-rate matches output sequence by not selecting A0 successive bits block in information sequence to be encoded and/or not including LDPC volumesA2 successive bits block in the check bit of code output sequence, it is described to be encoded so as to which rate-matched output sequence be made not includeIn information sequence A0 successive bits block and/or, the rate-matched output sequence not include the LDPC encoded output sequencesCheck bit in A2 successive bits block and according to being defined under the conditions of different parameters to A0 and A2, Yi JiyuePosition and A2 successive bits block of the A0 successive bits block of beam in information sequence to be encoded are in LDPC encoded output sequencesPosition, performance of the quasi-cyclic LDPC code in varying environment or scene is improved, to adapt to the performance of various code lengths and code checkIt is required that so as to support flexible code length and code check and retention property good.

Although This application describes the particular example of the present invention, those skilled in the art can not depart from the present invention generallyVariant of the invention is designed on the basis of thought.

Under the inspiration that those skilled in the art conceive in the technology of the present invention, on the basis of the content of present invention is not departed from, alsoVarious improvement can be made to the present invention, this still falls within the scope and spirit of the invention.

Claims (42)

1. a kind of quasi-cyclic LDPC code data processing equipment, which is characterized in that described device includes：

Memory module, for storing a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value；The basePlinth matrix is the matrix of a mb rows nb row, and the element for being used to indicate complete zero square formation is included in the basis matrix and is used to indicateThe element of the shift size of unit matrix cyclic shift, the spreading factor value are used to indicate complete zero square formation or the unit matrixLine number, the spreading factor value is greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the integer of mb；

Coding module, for obtaining the basis matrix and a spreading factor value from the memory module, based on acquisitionThe basis matrix and spreading factor value treat coded information sequences and carry out quasi-cyclic LDPC coding, obtain LDPC coding outputsSequence；

Rate Matching block, for from the LDPC encoded output sequences, selecting rate-matched output sequence.

2. device as described in claim 1, which is characterized in that the row of the basis matrix includes at least the 3/ of following set again4 elements：{ 8,9,9,8,5,6,5,6,6,6,5,6,4,5,5,5,5 }；And/or

The row of the basis matrix include at least 3/4 element of following set again：4,15,4,4,4,16,5,17,4,10,4,3,1,1,1,1,1,1 }；

Wherein, the row refer to again line index in the basis matrix fix and column index be 0~(nb-1) when, be used to indicate unitThe number of the element of the shift size of battle array cyclic shift；

It is described row refer to again column index in the basis matrix fix and line index be 0~(mb-1) when, be used to indicate unit matrix and followThe number of the element of the shift size of ring displacement.

3. device as described in claim 1, which is characterized in that in the basis matrix, be used to indicate the element of complete zero square formationIt is represented using ' -1 ', the element for being used to indicate unit matrix cyclic shift is used more than or equal to 0 and less than the spreading factor valueInteger representation；The element of the basis matrix at least 80% is identical with below with reference to basis matrix Hb：

4. device as described in claim 1, which is characterized in that unit matrix cyclic shift is used to indicate in the basis matrixThe element position of the position of element at least 80% is identical with the position below with reference in basis matrix Hb ' ' 1 '：

5. device as claimed in claim 4, the new basic square that the basis matrix obtains after line replacement and/or column permutationThe element position of the position at least 80% of the element of unit matrix cyclic shift is used to indicate in battle array and with reference in basis matrix Hb '' 1 ' position is identical.

6. device as described in claim 1, which is characterized in that the rate-matched output sequence does not include the letter to be encodedA0 successive bits block in sequence is ceased, the A0 successive bits block corresponds respectively to A0 column index of the basis matrixNumber, it is arbitrary integer in 0 to 3 that the A0 column index number, which forms set T0, the A0,；Wherein, the element value of the set T0It is determined with element number by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R combination,Channel type, data transfer direction, the combination of TBS call numbers and resource unit number NRB, Modulation and Coding Scheme MCS call numbers andThe combination of resource unit number NRB, the combination of code check R and resource unit number NRB, amount of bandwidth, band and out-of-band instruction.

7. device as claimed in claim 6, which is characterized in that when the value of the parameter differs, the set T0 is notTogether.

8. device as described in claim 1, which is characterized in that the rate-matched output sequence does not include the LDPC and encodesA2 successive bits block in the check bit of output sequence, the A2 successive bits block correspond respectively to the basis matrixA2 column index number, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；Wherein, the collectionThe element value and element number for closing T1 are determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R combination,Channel type, data transfer direction, the combination of TBS call numbers and resource unit number NRB, Modulation and Coding Scheme MCS call numbers andThe combination of resource unit number NRB, the combination of code check R and resource unit number NRB, amount of bandwidth, band and out-of-band instruction.

9. device as claimed in claim 8, which is characterized in that when the value of the parameter differs, the set T1 is notTogether.

10. device as described in claim 1, which is characterized in that the Rate Matching block, specifically for first to the LDPCEncoded output sequence is interleaved by intertexture pattern InP, and then sequential selection goes out the rate-matched output sequence；The friendshipPattern InP is knitted as unit of the successive bits block of Z bit, comprising nb from 0 to (nb-1) mutual not phase in the intertexture pattern InPDeng integer；Wherein, the specific element value of the intertexture pattern InP and specific element number are true by following at least one parameterIt is fixed：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R combination,Channel type, data transfer direction, the combination of TBS call numbers and resource unit number NRB, Modulation and Coding Scheme MCS call numbers andThe combination of resource unit number NRB, the combination of code check R and resource unit number NRB, amount of bandwidth, band and out-of-band instruction.

11. device as claimed in claim 10, which is characterized in that when the value of the parameter differs, the intersection chartSample InP is different.

12. device as described in claim 1, which is characterized in that the rate-matched output sequence does not include described to be encodedA0 successive bits block in information sequence, the A0 successive bits block correspond respectively to A0 column index of the basis matrixNumber, it is arbitrary integer in 0 to 3 that the A0 column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) as row ropeAll elements indicated by quotation marks form the matrix Matrix0 of mb ' rows A0 row, and it is whole less than or equal to mb that the mb ' is greater than 0Number, the matrix Matrix0 have following at least one condition：

The difference of the row weight of arbitrary 2 row is not more than 1 in the matrix Matrix0；

In the matrix Matrix0 1 element for being used to indicate complete zero square formation is included at least in the element of arbitrary 1 row；

A3 non-full rows are included at least in the matrix Matrix0, the non-full row is used to indicate entirely including at least 1 in rowZero square formation element；The A3 values are equal to 2 or 3；

The row that 1 row is equal to 1 again is included at least in the matrix Matrix0；

The row that 1 row is equal to A0 again is included at least in the matrix Matrix0.

13. device as described in claim 1, which is characterized in that the rate-matched output sequence does not include the LDPC and compilesA2 successive bits block in the check bit of code output sequence, the A2 successive bits block correspond respectively to the basic squareA2 column index number of battle array, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) as row ropeAll elements indicated by quotation marks form the matrix Matrix1 of mb ' rows A2 row, and it is whole less than or equal to mb that the mb ' is greater than 0Number, the matrix Matrix1 have following at least one condition：

At most there is 1 instruction list in the matrix Matrix1 in arbitrary 2 row in 2 elements indicated by identical line index numberThe element of the shift size of position battle array cyclic shift；

Arbitrary 1 row includes up to the element of the shift size of 2 instruction unit matrix cyclic shifts in the matrix Matrix1.

14. device as described in claim 1, which is characterized in that the rate-matched output sequence does not include described to be encodedA0 successive bits block in information sequence, the A0 successive bits block correspond respectively to A0 column index of the basis matrixNumber, it is arbitrary integer in 0 to 3 that the A0 column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) as row ropeThe matrix Matrix0, the mb ' that all elements indicated by quotation marks form mb ' rows A0 row are greater than 0 integer for being less than mb；

The rate-matched output sequence does not include A2 successive bits in the check bit of the LDPC encoded output sequencesBlock, the A2 successive bits block correspond respectively to A2 column index number of the basis matrix, the A2 column index structureInto set T1, the A2 is arbitrary integer in 0 to mb；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) as row ropeAll elements indicated by quotation marks form the matrix Matrix1 of mb ' rows A2 row, and it is whole less than or equal to mb that the mb ' is greater than 0Number；

The matrix Matrix0 and matrix Matrix1 forms the matrix Matrix2=of mb ' rows (A0+A2) row[Matrix0Matrix1], wherein, matrix Matrix2 has following at least one condition：

The column index number of element of row 1 instruction unit matrix cyclic shift in the row equal to 1 again is in the matrix Matrix20 arrives the integer of (A0-1), and A0 is greater than 0 integer；

In the matrix Matrix2, the column index number of the element of at least 1 instruction unit matrix cyclic shift is 0 in arbitrary rowTo the integer of (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, at least the row of 1 row is equal to 2 again, wherein 2 instruction unit matrix in the row that the row weight is 2The column index number of the element of the shift size of cyclic shift is 0 integer for arriving (A0-1), and A0 is greater than 1 integer；

In the matrix Matrix2, at least the row of 1 row is greater than or equal to A0 again, wherein all instruction unit matrix in the rowPreceding A0 of the column index number of the element of the shift size of cyclic shift are 0 integers for arriving (A0-1), and A0 is greater than 0 integer.

15. a kind of quasi-cyclic LDPC code data processing equipment, which is characterized in that described device includes processor and storage device,The storage device memory contains a quasi-cyclic LDPC coding basis matrix used and one group of spreading factor value and storageThere is multiple instruction to realize LDPC code data processing method, the processor performs the multiple instruction to realize：

The basis matrix and a spreading factor value are obtained from the memory module, the basis matrix based on acquisition andSpreading factor value treats coded information sequences and carries out quasi-cyclic LDPC coding, obtains LDPC encoded output sequences；The basis squareBattle array is the matrix of a mb rows nb row, and the element for being used to indicate complete zero square formation is included in the basis matrix and is used to indicate unitThe element of the shift size of battle array cyclic shift, the spreading factor value are used to indicate the row of complete zero square formation or the unit matrixNumber, the spreading factor value are greater than 0 integer, and the mb is greater than 0 integer, and the nb is greater than the integer of mb；

From the LDPC encoded output sequences, rate-matched output sequence is selected.

16. device as claimed in claim 15, which is characterized in that the row of the basis matrix is again including at least following set3/4 element：{ 8,9,9,8,5,6,5,6,6,6,5,6,4,5,5,5,5 }；And/or

The row of the basis matrix include at least 3/4 element of following set again：17,5,16,4,4,4,15,4,4,10,4,3,1,1,1,1,1,1,1,1,1,1,1,1,1 }；

Wherein, the row refer to again line index in the basis matrix fix and column index be 0~(nb-1) when, be used to indicate unitThe number of the element of battle array cyclic shift；

It is described row refer to again column index in the basis matrix fix and line index be 0~(mb-1) when, be used to indicate unit matrix and followThe number of the element of ring displacement.

17. device as claimed in claim 15, which is characterized in that in the basis matrix, be used to indicate the member of complete zero square formationElement represents that the element for being used to indicate unit matrix cyclic shift is used more than or equal to 0 and less than the spreading factor using ' -1 'The integer representation of value；The element of the basis matrix at least 80% is identical with below with reference to basis matrix Hb：

18. device as claimed in claim 15, which is characterized in that unit matrix cyclic shift is used to indicate in the basis matrixElement position at least 80% element position it is identical with the position below with reference in basis matrix Hb ' ' 1 '：

19. device as claimed in claim 18, the new basis that the basis matrix obtains after line replacement and/or column permutationThe element position of the position at least 80% of the element of unit matrix cyclic shift and reference basis matrix Hb ' are used to indicate in matrixIn ' 1 ' position it is identical.

20. device as claimed in claim 15, which is characterized in that the rate-matched output sequence does not include described to be encodedA0 successive bits block in information sequence, the A0 successive bits block correspond respectively to A0 column index of the basis matrixNumber, it is arbitrary integer in 0 to 3 that the A0 column index number, which forms set T0, the A0,；Wherein, the element value of the set T0It is determined with element number by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R combination,Channel type, data transfer direction, the combination of TBS call numbers and resource unit number NRB, Modulation and Coding Scheme MCS call numbers andThe combination of resource unit number NRB, the combination of code check R and resource unit number NRB, amount of bandwidth, band and out-of-band instruction.

21. device as claimed in claim 20, which is characterized in that when the value of the parameter differs, the set T0It is different.

22. device as claimed in claim 15, which is characterized in that the rate-matched output sequence does not include the LDPC and compilesA2 successive bits block in the check bit of code output sequence, the A2 successive bits block correspond respectively to the basic squareA2 column index number of battle array, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；Wherein, it is describedThe element value and element number of set T1 is determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R combination,Channel type, data transfer direction, the combination of TBS call numbers and resource unit number NRB, Modulation and Coding Scheme MCS call numbers andThe combination of resource unit number NRB, the combination of code check R and resource unit number NRB, amount of bandwidth, band and out-of-band instruction.

23. device as claimed in claim 22, which is characterized in that when the value of the parameter differs, the set T1It is different.

24. device as claimed in claim 15, which is characterized in that the Rate Matching block, specifically for first to describedLDPC encoded output sequences are interleaved by intertexture pattern InP, and then sequential selection goes out the rate-matched output sequence；It is describedIntertexture pattern InP as unit of the successive bits block of Z bit, it is mutual from 0 to (nb-1) comprising nb in the intertexture pattern InPUnequal integer；Wherein, the specific element value of the intertexture pattern InP and specific element number are by following at least one parameterIt determines：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R combination,Channel type, data transfer direction, the combination of TBS call numbers and resource unit number NRB, Modulation and Coding Scheme MCS call numbers andThe combination of resource unit number NRB, the combination of code check R and resource unit number NRB, amount of bandwidth, band and out-of-band instruction.

25. device as claimed in claim 24, which is characterized in that when the value of the parameter differs, the intersection chartSample InP is different.

26. device as claimed in claim 15, which is characterized in that the rate-matched output sequence does not include described to be encodedA0 successive bits block in information sequence, the A0 successive bits block correspond respectively to A0 column index of the basis matrixNumber, it is arbitrary integer in 0 to 3 that the A0 column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) as row ropeAll elements indicated by quotation marks form the matrix Matrix0 of mb ' rows A0 row, and it is whole less than or equal to mb that the mb ' is greater than 0Number, the matrix Matrix0 have following at least one condition：

The difference of the row weight of arbitrary 2 row is not more than 1 in the matrix Matrix0；

In the matrix Matrix0 1 element for being used to indicate complete zero square formation is included at least in the element of arbitrary 1 row；

A3 non-full rows are included at least in the matrix Matrix0, the non-full row is used to indicate entirely including at least 1 in rowZero square formation element；The A3 values are equal to 2 or 3；

The row that 1 row is equal to 1 again is included at least in the matrix Matrix0；

The row that 1 row is equal to A0 again is included at least in the matrix Matrix0.

27. device as claimed in claim 15, which is characterized in that the rate-matched output sequence does not include the LDPC and compilesA2 successive bits block in the check bit of code output sequence, the A2 successive bits block correspond respectively to the basic squareA2 column index number of battle array, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) as row ropeAll elements indicated by quotation marks form the matrix Matrix1 of mb ' rows A2 row, and it is whole less than or equal to mb that the mb ' is greater than 0Number, the matrix Matrix1 have following at least one condition：

At most there is 1 instruction list in the matrix Matrix1 in arbitrary 2 row in 2 elements indicated by identical line index numberThe element of the shift size of position battle array cyclic shift；

Arbitrary 1 row includes up to the element of the shift size of 2 instruction unit matrix cyclic shifts in the matrix Matrix1.

28. device as claimed in claim 15, which is characterized in that the rate-matched output sequence does not include described to be encodedA0 successive bits block in information sequence, the A0 successive bits block correspond respectively to A0 column index of the basis matrixNumber, it is arbitrary integer in 0 to 3 that the A0 column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) as row ropeThe matrix Matrix0, the mb ' that all elements indicated by quotation marks form mb ' rows A0 row are greater than 0 integer for being less than mb；

The rate-matched output sequence does not include A2 successive bits in the check bit of the LDPC encoded output sequencesBlock, the A2 successive bits block correspond respectively to A2 column index number of the basis matrix, the A2 column index structureInto set T1, the A2 is arbitrary integer in 0 to mb；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) as row ropeAll elements indicated by quotation marks form the matrix Matrix1 of mb ' rows A2 row, and it is whole less than or equal to mb that the mb ' is greater than 0Number；

The matrix Matrix0 and matrix Matrix1 forms the matrix Matrix2=of mb ' rows (A0+A2) row[Matrix0Matrix1], wherein, matrix Matrix2 has following at least one condition：

The column index number of element of row 1 instruction unit matrix cyclic shift in the row equal to 1 again is in the matrix Matrix20 arrives the integer of (A0-1), and A0 is greater than 0 integer；

In the matrix Matrix2, the column index number of the element of at least 1 instruction unit matrix cyclic shift is 0 in arbitrary rowTo the integer of (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, at least the row of 1 row is equal to 2 again, wherein 2 instruction unit matrix in the row that the row weight is 2The column index number of the element of the shift size of cyclic shift is 0 integer for arriving (A0-1), and A0 is greater than 1 integer；

In the matrix Matrix2, at least the row of 1 row is greater than or equal to A0 again, wherein all instruction unit matrix in the rowPreceding A0 of the column index number of the element of the shift size of cyclic shift are 0 integers for arriving (A0-1), and A0 is greater than 0 integer.

29. a kind of quasi-cyclic LDPC code data processing method, which is characterized in that the method includes：

In a basis matrix and one group of spreading factor value used from pre-stored quasi-cyclic LDPC coding, the base is obtainedPlinth matrix and a spreading factor value；The basis matrix is the matrix of a mb rows nb row, and use is included in the basis matrixIn the element and the element for the shift size for being used to indicate unit matrix cyclic shift that indicate complete zero square formation, the spreading factor value is usedIn the line number for indicating complete zero square formation or the unit matrix, the spreading factor value is greater than 0 integer, and the mb is greater than0 integer, the nb are greater than the integer of mb；

The basis matrix parameter and spreading factor value based on acquisition treat coded information sequences and carry out quasi-cyclic LDPC volumeCode, obtains mother's LDPC codeword sequence；

From mother's LDPC codeword sequence, rate-matched output sequence is selected.

30. method as claimed in claim 29, which is characterized in that the row of the basis matrix is again including at least following set3/4 element：{ 8,9,9,8,5,6,5,6,6,6,5,6,4,5,5,5,5 }；And/or

The row of the basis matrix include at least 3/4 element of following set again：17,5,16,4,4,4,15,4,4,10,4,3,1,1,1,1,1,1,1,1,1,1,1,1,1 }；

Wherein, the row refer to again line index in the basis matrix fix and column index be 0~(nb-1) when, be used to indicate unitThe number of the element of battle array cyclic shift；

It is described row refer to again column index in the basis matrix fix and line index be 0~(mb-1) when, be used to indicate unit matrix and followThe number of the element of ring displacement.

31. method as claimed in claim 29, which is characterized in that in the basis matrix, be used to indicate the member of complete zero square formationElement represents that the element for being used to indicate unit matrix cyclic shift is used more than or equal to 0 and less than the spreading factor using ' -1 'The integer representation of value；The element of the basis matrix at least 80% is identical with below with reference to basis matrix Hb：

32. method as claimed in claim 29, which is characterized in that unit matrix cyclic shift is used to indicate in the basis matrixElement position at least 80% element position it is identical with the position below with reference in basis matrix Hb ' ' 1 '：

33. method as claimed in claim 32, which is characterized in that the basis matrix is after line replacement and/or column permutationThe element position and ginseng of the position at least 80% of the element of unit matrix cyclic shift are used to indicate in the new basis matrix obtainedExamine in basis matrix Hb ' ' 1 ' position it is identical.

34. method as claimed in claim 29, which is characterized in that the rate-matched output sequence does not include described to be encodedA0 successive bits block in information sequence, the A0 successive bits block correspond respectively to A0 column index of the basis matrixNumber, it is arbitrary integer in 0 to 3 that the A0 column index number, which forms set T0, the A0,；Wherein, the element value of the set T0It is determined with element number by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R combination,Channel type, data transfer direction, the combination of TBS call numbers and resource unit number NRB, Modulation and Coding Scheme MCS call numbers andThe combination of resource unit number NRB, the combination of code check R and resource unit number NRB, amount of bandwidth, band and out-of-band instruction.

35. method as claimed in claim 34, which is characterized in that when the value of the parameter differs, the set T0It is different.

36. method as claimed in claim 29, which is characterized in that the rate-matched output sequence does not include the LDPC and compilesA2 successive bits block in the check bit of code output sequence, the A2 successive bits block correspond respectively to the basic squareA2 column index number of battle array, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；Wherein, it is describedThe element value and element number of set T1 is determined by following at least one parameter：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R combination,Channel type, data transfer direction, the combination of TBS call numbers and resource unit number NRB, Modulation and Coding Scheme MCS call numbers andThe combination of resource unit number NRB, the combination of code check R and resource unit number NRB, amount of bandwidth, band and out-of-band instruction.

37. method as claimed in claim 36, which is characterized in that when the value of the parameter differs, the set T1It is different.

38. method as claimed in claim 29, which is characterized in that it is described from mother's LDPC codeword sequence, select speedRate matches output sequence, including：

First the LDPC encoded output sequences are interleaved by intertexture pattern InP, then sequential selection goes out the rate-matchedOutput sequence；The intertexture pattern InP includes nb as unit of the successive bits block of Z bit in the intertexture pattern InPThe integer being not mutually equal from 0 to (nb-1)；Wherein, the specific element value of the intertexture pattern InP and specific element number by withLower at least one parameter determines：

Transport block size TBS, application scenarios, user UE types, frequency range, code check R, transport block size TBS and code check R combination,Channel type, data transfer direction, the combination of TBS call numbers and resource unit number NRB, Modulation and Coding Scheme MCS call numbers andThe combination of resource unit number NRB, the combination of code check R and resource unit number NRB, amount of bandwidth, band and out-of-band instruction.

39. method as claimed in claim 38, which is characterized in that when the value of the parameter differs, the intersection chartSample InP is different.

40. method as claimed in claim 29, which is characterized in that the rate-matched output sequence does not include described to be encodedA0 successive bits block in information sequence, the A0 successive bits block correspond respectively to A0 column index of the basis matrixNumber, it is arbitrary integer in 0 to 3 that the A0 column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) as row ropeAll elements indicated by quotation marks form the matrix Matrix0 of mb ' rows A0 row, and it is whole less than or equal to mb that the mb ' is greater than 0Number, the matrix Matrix0 have following at least one condition：

The difference of the row weight of arbitrary 2 row is not more than 1 in the matrix Matrix0；

In the matrix Matrix0 1 element for being used to indicate complete zero square formation is included at least in the element of arbitrary 1 row；

A3 non-full rows are included at least in the matrix Matrix0, the non-full row is used to indicate entirely including at least 1 in rowZero square formation element；The A3 values are equal to 2 or 3；

The row that 1 row is equal to 1 again is included at least in the matrix Matrix0；

The row that 1 row is equal to A0 again is included at least in the matrix Matrix0.

41. method as claimed in claim 29, which is characterized in that the rate-matched output sequence does not include the LDPC and compilesA2 successive bits block in the check bit of code output sequence, the A2 successive bits block correspond respectively to the basic squareA2 column index number of battle array, it is arbitrary integer in 0 to mb that the A2 column index number, which forms set T1, the A2,；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) as row ropeAll elements indicated by quotation marks form the matrix Matrix1 of mb ' rows A2 row, and it is whole less than or equal to mb that the mb ' is greater than 0Number, the matrix Matrix1 have following at least one condition：

At most there is 1 instruction list in the matrix Matrix1 in arbitrary 2 row in 2 elements indicated by identical line index numberThe element of the shift size of position battle array cyclic shift；

Arbitrary 1 row includes up to the element of the shift size of 2 instruction unit matrix cyclic shifts in the matrix Matrix1.

42. method as claimed in claim 29, which is characterized in that the rate-matched output sequence does not include described to be encodedA0 successive bits block in information sequence, the A0 successive bits block correspond respectively to A0 column index of the basis matrixNumber, it is arbitrary integer in 0 to 3 that the A0 column index number, which forms set T0, the A0,；

In the basis matrix, using all elements value in the set T0 as column index number and using 0 to (mb ' -1) as row ropeThe matrix Matrix0, the mb ' that all elements indicated by quotation marks form mb ' rows A0 row are greater than 0 integer for being less than mb；

The rate-matched output sequence does not include A2 successive bits in the check bit of the LDPC encoded output sequencesBlock, the A2 successive bits block correspond respectively to A2 column index number of the basis matrix, the A2 column index structureInto set T1, the A2 is arbitrary integer in 0 to mb；

In the basis matrix, using all elements value in the set T1 as column index number and using 0 to (mb ' -1) as row ropeAll elements indicated by quotation marks form the matrix Matrix1 of mb ' rows A2 row, and it is whole less than or equal to mb that the mb ' is greater than 0Number；

The matrix Matrix0 and matrix Matrix1 forms the matrix Matrix2=of mb ' rows (A0+A2) row[Matrix0Matrix1], wherein, matrix Matrix2 has following at least one condition：

The column index number of element of row 1 instruction unit matrix cyclic shift in the row equal to 1 again is in the matrix Matrix20 arrives the integer of (A0-1), and A0 is greater than 0 integer；

In the matrix Matrix2, the column index number of the element of at least 1 instruction unit matrix cyclic shift is 0 in arbitrary rowTo the integer of (A0-1), A0 is greater than 0 integer；

In the matrix Matrix2, at least the row of 1 row is equal to 2 again, wherein 2 instruction unit matrix in the row that the row weight is 2The column index number of the element of the shift size of cyclic shift is 0 integer for arriving (A0-1), and A0 is greater than 1 integer；

In the matrix Matrix2, at least the row of 1 row is greater than or equal to A0 again, wherein all instruction unit matrix in the rowPreceding A0 of the column index number of the element of the shift size of cyclic shift are 0 integers for arriving (A0-1), and A0 is greater than 0 integer.