技术领域technical field
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管和阵列基板的制备方法、阵列基板、以及显示装置。The present disclosure relates to the field of display technology, and in particular to a method for preparing a thin film transistor and an array substrate, the array substrate, and a display device.
背景技术Background technique
近些年来显示装置呈现出了高集成度以及低成本的发展趋势。以阵列基板行驱动(Gate Driver on Array，GOA)技术为代表，利用GOA技术将栅极驱动电路集成于阵列基板的周边区域，可在实现窄边框设计的同时，有效的提升模组工艺产量、提升产品良率、以及节约成本。In recent years, display devices have shown a development trend of high integration and low cost. Represented by Gate Driver on Array (GOA) technology, GOA technology is used to integrate the gate driver circuit in the peripheral area of the array substrate, which can effectively improve the module process output while realizing the narrow frame design. Improve product yield and save costs.
低温多晶氧化物(Low Temperature Poly-Oxide，LTPO)技术是近年来新兴的薄膜晶体管技术。为了保证液晶显示器(Liquid Crystal Display，LCD)或者有机发光二极管显示器(Orginic Light Emitting Diode，OLED)能够同时实现窄边框和低功耗功能，在GOA区域通常会采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)技术制备薄膜晶体管，由于LTPS薄膜晶体管的迁移率高、尺寸较小，因此能够有效的减小边框尺寸，而在有效显示区通常会采用金属氧化物薄膜晶体管，由于金属氧化物薄膜晶体管可以低频驱动，最低可至1Hz，因此能够有效的降低功耗。但是，目前采用LTPO技术的构图工艺次数较多，例如从多晶硅层到保护层至少需要7～8道光刻工艺，因此工艺成本较高。The low temperature polycrystalline oxide (Low Temperature Poly-Oxide, LTPO) technology is an emerging thin film transistor technology in recent years. In order to ensure that Liquid Crystal Display (LCD) or Organic Light Emitting Diode (OLED) can achieve both narrow frame and low power consumption, low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) technology to prepare thin film transistors, due to the high mobility and small size of LTPS thin film transistors, it can effectively reduce the frame size, and metal oxide thin film transistors are usually used in the effective display area, because metal oxide thin film transistors can Low-frequency drive, the lowest can reach 1Hz, so it can effectively reduce power consumption. However, at present, the number of patterning processes using LTPO technology is relatively large, for example, at least 7 to 8 photolithography processes are required from the polysilicon layer to the protective layer, so the process cost is relatively high.
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。It should be noted that the information disclosed in the above background section is only for enhancing the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art.
发明内容Contents of the invention
本公开的目的在于提供一种薄膜晶体管和阵列基板的制备方法、阵列基板、以及显示装置，以用于解决阵列基板的构图工艺次数过多而引起的产能过低和成本过高的问题。The purpose of the present disclosure is to provide a method for preparing a thin film transistor, an array substrate, an array substrate, and a display device, so as to solve the problems of low production capacity and high cost caused by too many patterning processes of the array substrate.
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。Other features and advantages of the present disclosure will become apparent from the following detailed description, or in part, be learned by practice of the present disclosure.
根据本公开的一个方面，提供一种薄膜晶体管的制备方法，包括：According to one aspect of the present disclosure, a method for manufacturing a thin film transistor is provided, including:
在基板的上方通过一次构图工艺形成位于周边电路区的第一半导体有源层；forming a first semiconductor active layer located in the peripheral circuit region above the substrate through a patterning process;
在所述第一半导体有源层的上方形成第一绝缘层，并在所述第一绝缘层的上方通过一次构图工艺形成位于有效显示区的遮光层以及正对所述第一半导体有源层的第一栅极；Forming a first insulating layer above the first semiconductor active layer, and forming a light-shielding layer located in the effective display area and facing the first semiconductor active layer through a patterning process above the first insulating layer the first grid;
在所述遮光层和所述第一栅极的上方形成第二绝缘层，并通过一次构图工艺形成贯穿于所述第一绝缘层和所述第二绝缘层的第一过孔和第二过孔，所述第一过孔和所述第二过孔分别露出所述第一半导体有源层的两侧；Form a second insulating layer above the light shielding layer and the first gate, and form a first via hole and a second via through the first insulating layer and the second insulating layer through a patterning process. holes, the first via hole and the second via hole respectively expose both sides of the first semiconductor active layer;
在所述第二绝缘层的上方通过一次构图工艺形成通过所述第一过孔和所述第二过孔分别与所述第一半导体有源层的两侧相接触的断开的第二半导体保留图案、分别位于所述第二半导体保留图案上的第一源极和第一漏极、正对所述遮光层的第二半导体有源层、以及分别与所述第二半导体有源层的两侧相接触的第二源极和第二漏极；On the second insulating layer, a disconnected second semiconductor contacting both sides of the first semiconductor active layer through the first via hole and the second via hole is formed through a patterning process. The reserved pattern, the first source electrode and the first drain electrode respectively located on the second semiconductor reserved pattern, the second semiconductor active layer facing the light shielding layer, and the second semiconductor active layer respectively connected with the second semiconductor active layer a second source electrode and a second drain electrode with two sides in contact;
在所述第一源极、所述第一漏极、所述第二源极和所述第二漏极的上方通过一次构图工艺形成保护层以及正对所述第二半导体有源层的第二栅极。On the first source, the first drain, the second source, and the second drain, a protective layer and a first layer facing the second semiconductor active layer are formed through a patterning process. Two gates.
本公开的一种示例性实施例中，在基板的上方通过一次构图工艺形成位于周边电路区的第一半导体有源层包括：In an exemplary embodiment of the present disclosure, forming the first semiconductor active layer located in the peripheral circuit region through a patterning process above the substrate includes:
采用低温多晶硅工艺在形成有缓冲层的基板上形成多晶硅薄膜，并通过一次构图工艺使所述多晶硅薄膜形成位于所述周边电路区的多晶硅有源层。A low-temperature polysilicon process is used to form a polysilicon film on the substrate on which the buffer layer is formed, and the polysilicon film is formed into a polysilicon active layer located in the peripheral circuit area through a patterning process.
本公开的一种示例性实施例中，在所述第一绝缘层的上方通过一次构图工艺形成位于有效显示区的遮光层以及正对所述第一半导体有源层的第一栅极包括：In an exemplary embodiment of the present disclosure, forming a light-shielding layer located in the effective display area and a first gate facing the first semiconductor active layer on the first insulating layer through a patterning process includes:
在所述第一绝缘层的上方形成第一金属层薄膜，通过一次构图工艺使所述第一金属层薄膜形成位于所述有效显示区的遮光层以及正对所述第一半导体有源层的第一栅极。A first metal layer thin film is formed on the first insulating layer, and the first metal layer thin film forms a light-shielding layer located in the effective display area and a light-shielding layer facing the first semiconductor active layer through a patterning process. first grid.
本公开的一种示例性实施例中，在所述第二绝缘层的上方通过一次构图工艺形成通过所述第一过孔和所述第二过孔分别与所述第一半导体有源层的两侧相接触的断开的第二半导体保留图案、分别位于所述第二半导体保留图案上的第一源极和第一漏极、正对所述遮光层的第二半导体有源层、以及分别与所述第二半导体有源层的两侧相接触的第二源极和第二漏极包括：In an exemplary embodiment of the present disclosure, the first via hole and the second via hole respectively connected to the first semiconductor active layer are formed on the second insulating layer through a patterning process. A disconnected second semiconductor retention pattern with two sides in contact, a first source electrode and a first drain electrode respectively located on the second semiconductor retention pattern, a second semiconductor active layer facing the light-shielding layer, and The second source and the second drain respectively contacting both sides of the second semiconductor active layer include:
在所述第二绝缘层的上方依次形成金属氧化物半导体薄膜和第二金属层薄膜；sequentially forming a metal oxide semiconductor film and a second metal layer film on the second insulating layer;
采用半灰阶掩膜工艺使所述金属氧化物半导体薄膜形成通过所述第一过孔和所述第二过孔分别与所述第一半导体有源层的两侧相接触的断开的金属氧化物半导体保留图案、以及正对所述遮光层的金属氧化物半导体有源层，并使所述第二金属层薄膜形成分别位于所述金属氧化物半导体保留图案上的第一源极和第一漏极、以及分别与所述金属氧化物半导体有源层的两侧相接触的第二源极和第二漏极。Using a half-gray scale masking process, the metal oxide semiconductor thin film is formed with disconnected metal that is respectively in contact with both sides of the first semiconductor active layer through the first via hole and the second via hole. The oxide semiconductor reserved pattern, and the metal oxide semiconductor active layer facing the light-shielding layer, and the second metal layer thin film forms the first source electrode and the second electrode respectively located on the metal oxide semiconductor reserved pattern. A drain, and a second source and a second drain respectively contacting the two sides of the metal oxide semiconductor active layer.
本公开的一种示例性实施例中，在所述第一源极、所述第一漏极、所述第二源极和所述第二漏极的上方通过一次构图工艺形成保护层以及正对所述第二半导体有源层的第二栅极包括：In an exemplary embodiment of the present disclosure, a protective layer and a positive The second gate of the second semiconductor active layer includes:
在所述第一源极、所述第一漏极、所述第二源极和所述第二漏极的上方依次形成保护层薄膜和第三金属层薄膜；sequentially forming a protective layer film and a third metal layer film above the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode;
采用半灰阶掩膜工艺在所述保护层薄膜中形成使所述有效显示区和所述周边电路区断开的区域以形成所述保护层，并使所述第三金属层薄膜形成正对所述第二半导体有源层的第二栅极。A half-gray-scale masking process is used to form a region in the protective layer film that disconnects the effective display area from the peripheral circuit area to form the protective layer, and to form the third metal layer film directly opposite The second gate of the second semiconductor active layer.
本公开的一种示例性实施例中，所述第一绝缘层和所述第二绝缘层在接触所述第一栅极和所述遮光层的一侧均为氧化硅薄膜。In an exemplary embodiment of the present disclosure, both the first insulating layer and the second insulating layer are silicon oxide films on a side contacting the first gate and the light shielding layer.
根据本公开的一个方面，提供一种阵列基板的制备方法，包括上述的薄膜晶体管的制备方法；以及，According to one aspect of the present disclosure, there is provided a method for preparing an array substrate, including the above method for preparing a thin film transistor; and,
在第二栅极的上方形成具有第三过孔的平坦层以及通过所述第三过孔与第二漏极电连接的像素电极。A planar layer having a third via hole and a pixel electrode electrically connected to the second drain through the third via hole are formed above the second gate.
根据本公开的一个方面，提供一种阵列基板，包括上述的薄膜晶体管的制备方法而制得的薄膜晶体管；According to one aspect of the present disclosure, there is provided an array substrate, including a thin film transistor manufactured by the above thin film transistor manufacturing method;
第一栅极、第一半导体有源层、第一源极和第一漏极构成所述阵列基板的周边电路区的第一薄膜晶体管；The first gate, the first semiconductor active layer, the first source and the first drain form the first thin film transistor in the peripheral circuit area of the array substrate;
第二栅极、第二半导体有源层、第二源极和第二漏极构成所述阵列基板的有效显示区的第二薄膜晶体管。The second gate, the second semiconductor active layer, the second source and the second drain constitute the second thin film transistor of the effective display area of the array substrate.
本公开的一种示例性实施例中，所述阵列基板还包括：In an exemplary embodiment of the present disclosure, the array substrate further includes:
位于所述第二栅极上方的具有第三过孔的平坦层，以及通过所述第三过孔与所述第二薄膜晶体管的第二漏极电连接的像素电极。A planar layer with a third via hole located above the second gate, and a pixel electrode electrically connected to the second drain of the second thin film transistor through the third via hole.
根据本公开的一个方面，提供一种显示装置，包括上述的阵列基板。According to one aspect of the present disclosure, a display device is provided, including the above-mentioned array substrate.
本公开示例性实施方式所提供的薄膜晶体管和阵列基板的制备方法、阵列基板、以及显示装置，将位于周边电路区10a的薄膜晶体管和位于有效显示区10b的薄膜晶体管设计为顶栅型结构，并采用以上的特殊工艺处理而达到减少构图工艺次数的目的。这样一来，相比于现有技术，本示例实施方式能够有效的减少构图工艺的次数，从而达到提高产能以及节约成本的效果。The manufacturing method of the thin film transistor and the array substrate, the array substrate, and the display device provided in the exemplary embodiment of the present disclosure, the thin film transistor located in the peripheral circuit area 10a and the thin film transistor located in the effective display area 10b are designed as a top-gate structure, And the above special process is adopted to achieve the purpose of reducing the number of patterning processes. In this way, compared with the prior art, this example embodiment can effectively reduce the number of patterning processes, thereby achieving the effects of improving productivity and saving costs.
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.
附图说明Description of drawings
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure. Apparently, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to these drawings without creative efforts.
图1示意性示出本公开示例性实施例中薄膜晶体管的制备流程图；FIG. 1 schematically shows a flow chart of the preparation of a thin film transistor in an exemplary embodiment of the present disclosure;
图2至图6示意性示出本公开示例性实施例中薄膜晶体管的制备过程示意图；2 to 6 schematically show the schematic diagrams of the manufacturing process of the thin film transistor in the exemplary embodiment of the present disclosure;
图7至图11示意性示出本公开示例性实施例中薄膜晶体管的一次半灰阶掩膜工艺的过程示意图；7 to 11 schematically show a schematic diagram of a half-grayscale masking process of a thin film transistor in an exemplary embodiment of the present disclosure;
图12至图16示意性示出本公开示例性实施例中薄膜晶体管的另一次半灰阶掩膜工艺的过程示意图；12 to FIG. 16 schematically show the process diagram of another half-grayscale masking process of the thin film transistor in the exemplary embodiment of the present disclosure;
图17示意性示出本公开示例性实施例中阵列基板的结构示意图；FIG. 17 schematically shows a schematic structural view of an array substrate in an exemplary embodiment of the present disclosure;
图18示意性示出本公开示例性实施例中阵列基板的制备流程图。FIG. 18 schematically shows a flow chart of preparing an array substrate in an exemplary embodiment of the present disclosure.
具体实施方式Detailed ways
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different network and/or processor means and/or microcontroller means.
本示例实施方式提供了一种薄膜晶体管的制备方法，应用于GOA阵列基板的制备。如图1所示，该薄膜晶体管的制备方法可以包括：This exemplary embodiment provides a method for manufacturing a thin film transistor, which is applied to the preparation of a GOA array substrate. As shown in Figure 1, the preparation method of the thin film transistor may include:
S1、如图2所示，在基板的上方通过一次构图工艺形成位于周边电路区10a的第一半导体有源层101；S1. As shown in FIG. 2, a first semiconductor active layer 101 located in the peripheral circuit region 10a is formed on the substrate through a patterning process;
S2、如图3所示，在第一半导体有源层101的上方形成第一绝缘层102，并在第一绝缘层102的上方通过一次构图工艺形成位于有效显示区10b的遮光层103以及正对第一半导体有源层101的第一栅极104；S2. As shown in FIG. 3 , form a first insulating layer 102 above the first semiconductor active layer 101, and form a light shielding layer 103 located in the effective display region 10b and a positive electrode through a patterning process above the first insulating layer 102. to the first gate 104 of the first semiconductor active layer 101;
S3、如图4所示，在遮光层103和第一栅极104的上方形成第二绝缘层105，并通过一次构图工艺形成贯穿于第一绝缘层102和第二绝缘层105的第一过孔106和第二过孔107，该第一过孔106和该第二过孔107分别将第一半导体有源层101的两侧露出；S3. As shown in FIG. 4, a second insulating layer 105 is formed on the light shielding layer 103 and the first gate 104, and a first pass through the first insulating layer 102 and the second insulating layer 105 is formed through a patterning process. A hole 106 and a second via hole 107, the first via hole 106 and the second via hole 107 respectively expose both sides of the first semiconductor active layer 101;
S4、如图5所示，在第二绝缘层105的上方通过一次构图工艺形成通过第一过孔106和第二过孔107分别与第一半导体有源层101的两侧相接触且断开的第二半导体保留图案108、分别位于第二半导体保留图案108上的第一源极109和第一漏极110、正对遮光层103的第二半导体有源层111、以及分别与第二半导体有源层111的两侧相接触的第二源极112和第二漏极113；S4. As shown in FIG. 5 , a first via hole 106 and a second via hole 107 are formed on the second insulating layer 105 through a patterning process, respectively contacting and disconnecting from both sides of the first semiconductor active layer 101 The second semiconductor retention pattern 108, the first source electrode 109 and the first drain electrode 110 respectively located on the second semiconductor retention pattern 108, the second semiconductor active layer 111 facing the light shielding layer 103, and the second semiconductor a second source 112 and a second drain 113 in contact with both sides of the active layer 111;
S5、如图6所示，在第一源极109、第一漏极110、第二源极112和第二漏极113的上方通过一次构图工艺形成保护层114以及正对第二半导体有源层111的第二栅极115。S5. As shown in FIG. 6, a protective layer 114 is formed on the first source 109, the first drain 110, the second source 112, and the second drain 113 through a patterning process and is facing the second semiconductor active layer. The second gate 115 of layer 111.
其中，所述周边电路区10a是指用于设置GOA电路的区域，所述有效显示区10b是指实际用于显示的区域。本示例中，第一半导体有源层101、第一栅极104、第二半导体保留图案108、第一源极109和第一漏极110可构成位于周边电路区10a的第一薄膜晶体管；第二半导体有源层111、第二栅极115、第二源极112和第二漏极113可构成位于有效显示区10b的第二薄膜晶体管。Wherein, the peripheral circuit area 10a refers to the area for setting the GOA circuit, and the effective display area 10b refers to the area actually used for display. In this example, the first semiconductor active layer 101, the first gate 104, the second semiconductor retention pattern 108, the first source 109 and the first drain 110 can constitute a first thin film transistor located in the peripheral circuit region 10a; The second semiconductor active layer 111 , the second gate 115 , the second source 112 and the second drain 113 can constitute a second thin film transistor located in the effective display area 10 b.
需要说明的是：所述一次构图工艺是指一次光刻工艺，其例如可以包括曝光、显影、以及刻蚀等过程。It should be noted that: the one patterning process refers to one photolithography process, which may include, for example, exposure, development, and etching processes.
本公开示例性实施方式所提供的薄膜晶体管的制备方法，将位于周边电路区10a的第一薄膜晶体管和位于有效显示区10b的第二薄膜晶体管设计为顶栅型结构，并采用以上的特殊工艺处理而达到减少构图工艺次数的目的。这样一来，相比于现有技术，本示例实施方式能够有效的减少构图工艺的次数，从而达到提高产能以及节约成本的效果。In the manufacturing method of the thin film transistor provided by the exemplary embodiment of the present disclosure, the first thin film transistor located in the peripheral circuit area 10a and the second thin film transistor located in the effective display area 10b are designed as a top-gate structure, and the above special process is adopted processing to achieve the purpose of reducing the number of patterning processes. In this way, compared with the prior art, this example embodiment can effectively reduce the number of patterning processes, thereby achieving the effects of improving productivity and saving costs.
本示例实施方式中，位于周边电路区10a的第一薄膜晶体管优选采用LTPS薄膜晶体管，以便于实现窄边框设计，而位于有效显示区10b的第二薄膜晶体管优选采用LTPO薄膜晶体管，以便于实现低频驱动。In this exemplary embodiment, the first thin film transistor located in the peripheral circuit area 10a is preferably an LTPS thin film transistor, so as to realize a narrow frame design, and the second thin film transistor located in the effective display area 10b is preferably an LTPO thin film transistor, so as to realize low frequency drive.
基于此，下面结合附图对所述薄膜晶体管的制备方法进行详细的描述。Based on this, the manufacturing method of the thin film transistor will be described in detail below with reference to the accompanying drawings.
在步骤S1中，参考图2所示，在基板的上方通过一次构图工艺形成位于周边电路区10a的第一半导体有源层101。In step S1 , as shown in FIG. 2 , a first semiconductor active layer 101 located in the peripheral circuit region 10 a is formed on the substrate through a patterning process.
这里的基板可以是衬底基板10例如玻璃基板或者柔性基板，但也可以是形成有其它膜层例如缓冲层100的基板。考虑到顶栅型LTPS薄膜晶体管的电流-电压(IV)特性以及稳定性，本实施例优选采用后者即包括有缓冲层100的方案，且该缓冲层100例如可以设置为氧化硅薄膜。The substrate here may be a base substrate 10 such as a glass substrate or a flexible substrate, but may also be a substrate formed with other film layers such as a buffer layer 100 . Considering the current-voltage (IV) characteristics and stability of the top-gate LTPS thin film transistor, this embodiment preferably adopts the latter solution including the buffer layer 100, and the buffer layer 100 can be configured as a silicon oxide film, for example.
示例的，本步骤S1具体可以包括：For example, this step S1 may specifically include:
S101、采用LTPS工艺在形成有缓冲层100的基板上形成多晶硅薄膜；S101, forming a polysilicon thin film on the substrate on which the buffer layer 100 is formed by using an LTPS process;
S102、通过一次构图工艺使该多晶硅薄膜形成位于周边电路区10a的多晶硅有源层，该多晶硅有源层即为第一半导体有源层101。S102 , forming the polysilicon thin film into a polysilicon active layer located in the peripheral circuit region 10 a through a patterning process, and the polysilicon active layer is the first semiconductor active layer 101 .
其中，多晶硅有源层的形成过程例如可以为：在多晶硅薄膜的上方涂覆一层光刻胶，采用掩模板对涂覆有光刻胶的基板进行曝光并对曝光后的基板进行显影，以得到光刻胶保留部分和光刻胶去除部分，该光刻胶保留部分即对应待形成的多晶硅有源层，通过刻蚀工艺将光刻胶去除部分露出的多晶硅薄膜进行刻蚀，以将掩模板的图案转移至该多晶硅薄膜，最后去除剩余的光刻胶，即可得到所需的多晶硅有源层。Wherein, the formation process of the polysilicon active layer may be, for example, coating a layer of photoresist on the polysilicon film, using a mask to expose the substrate coated with the photoresist and developing the exposed substrate to A photoresist reserved part and a photoresist removed part are obtained, the photoresist reserved part corresponds to the polysilicon active layer to be formed, and the polysilicon film exposed by the photoresist removed part is etched through an etching process, so that the mask The pattern of the template is transferred to the polysilicon film, and finally the remaining photoresist is removed to obtain the required polysilicon active layer.
在步骤S2中，参考图3所示，在第一半导体有源层101的上方形成第一绝缘层102，并在第一绝缘层102的上方通过一次构图工艺形成位于有效显示区10b的遮光层103以及正对第一半导体有源层101的第一栅极104。In step S2, as shown in FIG. 3 , a first insulating layer 102 is formed on the first semiconductor active layer 101, and a light shielding layer located in the effective display region 10b is formed on the first insulating layer 102 through a patterning process. 103 and the first gate 104 facing the first semiconductor active layer 101 .
本实施例中，第一绝缘层102可以为单层结构或者多层结构，但为了保证LTPS薄膜晶体管的IV特性以及稳定性，该第一绝缘层102接触遮光层103和第一栅极104的一侧即第一绝缘层102的上表面需要采用氧化硅薄膜。由此可知，第一绝缘层102可以为氧化硅薄膜的单层结构，或者为上层氧化硅薄膜和下层氮化硅薄膜的多层结构。In this embodiment, the first insulating layer 102 can be a single-layer structure or a multi-layer structure, but in order to ensure the IV characteristics and stability of the LTPS thin film transistor, the first insulating layer 102 contacts the light shielding layer 103 and the first gate 104. One side, that is, the upper surface of the first insulating layer 102 needs to use a silicon oxide film. It can be seen from this that the first insulating layer 102 may be a single-layer structure of a silicon oxide film, or a multi-layer structure of an upper layer of silicon oxide film and a lower layer of silicon nitride film.
示例的，本步骤S2具体可以包括：For example, this step S2 may specifically include:
S201、在第一半导体有源层101的上方形成第一绝缘层102，该第一绝缘层的上表面为氧化硅薄膜；S201, forming a first insulating layer 102 above the first semiconductor active layer 101, the upper surface of the first insulating layer is a silicon oxide film;
S202、在第一绝缘层102的上方形成第一金属层薄膜；S202, forming a first metal layer film on the first insulating layer 102;
S203、通过一次构图工艺使该第一金属层薄膜形成位于有效显示区10b的遮光层103以及正对第一半导体有源层101的第一栅极104。S203 , forming the light shielding layer 103 located in the effective display area 10 b and the first gate 104 facing the first semiconductor active layer 101 on the first metal layer thin film through a patterning process.
其中，遮光层103和第一栅极104的形成过程例如可以为：在第一金属层薄膜的上方涂覆一层光刻胶，采用掩模板对涂覆有光刻胶的基板进行曝光并对曝光后的基板进行显影，以得到光刻胶保留部分和光刻胶去除部分，该光刻胶保留部分即对应待形成的遮光层103和第一栅极104，通过刻蚀工艺将光刻胶去除部分露出的第一金属层薄膜进行刻蚀，以将掩模板的图案转移至该第一金属层薄膜，最后去除剩余的光刻胶，即可得到所需的遮光层103和第一栅极104。Wherein, the formation process of the light-shielding layer 103 and the first grid 104 may be, for example, coating a layer of photoresist on the first metal layer film, using a mask to expose the substrate coated with photoresist and The exposed substrate is developed to obtain a photoresist reserved part and a photoresist removed part, and the photoresist reserved part corresponds to the light shielding layer 103 and the first gate 104 to be formed, and the photoresist is removed by an etching process. Removing part of the exposed first metal layer film for etching to transfer the pattern of the mask to the first metal layer film, and finally removing the remaining photoresist to obtain the required light shielding layer 103 and the first gate 104.
由此可知，位于有效显示区10b的遮光层103和位于周边电路区10a的第一栅极104可由同一层金属经过同一次构图工艺而得，二者的材质与厚度均相同。由于有效显示区10b采用的是氧化物薄膜晶体管，而氧化物半导体有源层对光十分敏感，因此本实施例在待形成的氧化物薄膜晶体管的下方先形成一遮光层103，以防氧化物薄膜晶体管受到光照而变性，从而保证氧化物薄膜晶体管的稳定性。It can be seen that the light-shielding layer 103 located in the effective display area 10b and the first gate 104 located in the peripheral circuit area 10a can be obtained from the same layer of metal through the same patterning process, and the material and thickness of both are the same. Since the effective display region 10b uses an oxide thin film transistor, and the oxide semiconductor active layer is very sensitive to light, in this embodiment, a light shielding layer 103 is first formed under the oxide thin film transistor to be formed to prevent the oxide Thin film transistors are denatured by exposure to light, thereby ensuring the stability of oxide thin film transistors.
在步骤S3中，参考图4所示，在遮光层103和第一栅极104的上方形成第二绝缘层105，并通过一次构图工艺形成贯穿于第一绝缘层102和第二绝缘层105的第一过孔106和第二过孔107，该第一过孔106和该第二过孔107分别将第一半导体有源层101的两侧露出。In step S3, as shown in FIG. 4 , a second insulating layer 105 is formed above the light shielding layer 103 and the first gate 104, and a patterning process is performed to form a second insulating layer 102 through the first insulating layer 102 and the second insulating layer 105. The first via hole 106 and the second via hole 107 respectively expose two sides of the first semiconductor active layer 101 .
本实施例中，第二绝缘层105可以为单层结构或者多层结构，该第二绝缘层105背离遮光层103和第一栅极104的一侧即第二绝缘层105的上表面可以采用氧化硅薄膜。由于在第二绝缘层105的上方将会形成第二半导体有源层111例如金属氧化物半导体，而氢含量较高的膜层例如氮化硅薄膜或者氮氧化硅薄膜会使金属氧化物半导体材料导体化，从而导致LTPO薄膜晶体管的性能恶化，因此该第二绝缘层105的上表面需要采用氧化硅薄膜。由此可知，第二绝缘层105可以为氧化硅薄膜的单层结构，或者为上层氧化硅薄膜和下层氮化硅薄膜的多层结构。In this embodiment, the second insulating layer 105 can be a single-layer structure or a multi-layer structure. Silicon oxide film. Since the second semiconductor active layer 111 such as a metal oxide semiconductor will be formed on the second insulating layer 105, and a film layer with a high hydrogen content such as a silicon nitride film or a silicon oxynitride film will make the metal oxide semiconductor material Conductorization will lead to deterioration of the performance of the LTPO thin film transistor, so the upper surface of the second insulating layer 105 needs to use a silicon oxide film. It can be seen that the second insulating layer 105 can be a single-layer structure of silicon oxide film, or a multi-layer structure of an upper layer of silicon oxide film and a lower layer of silicon nitride film.
本步骤中，第一过孔106和第二过孔107的形成过程例如可以为：在第二绝缘层105的上方涂覆一层光刻胶，采用掩模板对涂覆有光刻胶的基板进行曝光并对曝光后的基板进行显影，以得到光刻胶保留部分和光刻胶去除部分，该光刻胶去除部分即对应待形成的第一过孔106和第二过孔107，通过刻蚀工艺将光刻胶去除部分露出的第二绝缘层105和第一绝缘层102进行刻蚀，以将掩模板的图案转移至第二绝缘层105和第一绝缘层102，最后去除剩余的光刻胶，即可得到所需的第一过孔106和第二过孔107。In this step, the formation process of the first via hole 106 and the second via hole 107 may be, for example: coating a layer of photoresist on the second insulating layer 105, and using a mask to pair the substrate coated with the photoresist Exposing and developing the exposed substrate to obtain the photoresist remaining part and the photoresist removing part, the photoresist removing part corresponds to the first via hole 106 and the second via hole 107 to be formed, by etching The etching process will etch the second insulating layer 105 and the first insulating layer 102 exposed by removing the photoresist, so as to transfer the pattern of the mask plate to the second insulating layer 105 and the first insulating layer 102, and finally remove the remaining light Resist, the desired first via hole 106 and second via hole 107 can be obtained.
在步骤S4中，参考如图5所示，在第二绝缘层105的上方通过一次构图工艺形成通过第一过孔106和第二过孔107分别与第一半导体有源层101的两侧相接触且断开的第二半导体保留图案108、分别位于第二半导体保留图案108上的第一源极109和第一漏极110、正对遮光层103的第二半导体有源层111、以及分别与第二半导体有源层111的两侧相接触的第二源极112和第二漏极113。In step S4, as shown in FIG. 5 , a first via hole 106 and a second via hole 107 are respectively formed on the second insulating layer 105 through a patterning process and are connected to both sides of the first semiconductor active layer 101. The second semiconductor reserved pattern 108 that is in contact with and disconnected from, the first source electrode 109 and the first drain electrode 110 respectively located on the second semiconductor reserved pattern 108, the second semiconductor active layer 111 facing the light shielding layer 103, and respectively The second source 112 and the second drain 113 are in contact with two sides of the second semiconductor active layer 111 .
其中，第二半导体保留图案108与第二半导体有源层111的材质可以包括但不限于IGZTO(Indium Gallium Zinc Tin Oxide，铟镓锌锡氧化物)、IGZO(Indium Gallium ZincOxide，铟镓锌氧化物)、ITZO(Indium Tin Zinc Oxide，铟锡锌氧化物)、IGTO(IndiumGallium Tin Oxide，铟镓锡氧化物)、IZO(Indium Zinc Oxide，铟锌氧化物)、以及锌的氮氧化物等。Wherein, the material of the second semiconductor retention pattern 108 and the second semiconductor active layer 111 may include but not limited to IGZTO (Indium Gallium Zinc Tin Oxide, indium gallium zinc tin oxide), IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide ), ITZO (Indium Tin Zinc Oxide, indium tin zinc oxide), IGTO (Indium Gallium Tin Oxide, indium gallium tin oxide), IZO (Indium Zinc Oxide, indium zinc oxide), and zinc oxynitride, etc.
第二半导体保留图案108与第二半导体有源层111形成于同一层，第一源极109和第一漏极110与第二源极112和第二漏极113形成于同一层。The second semiconductor remaining pattern 108 is formed on the same layer as the second semiconductor active layer 111 , and the first source 109 and the first drain 110 are formed on the same layer as the second source 112 and the second drain 113 .
示例的，如图7至图11所示，本步骤S4具体可以包括：For example, as shown in FIGS. 7 to 11 , this step S4 may specifically include:
S401、在第二绝缘层105的上方依次形成金属氧化物半导体薄膜201和第二金属层薄膜202；S401, sequentially forming a metal oxide semiconductor film 201 and a second metal layer film 202 on the second insulating layer 105;
S402、采用半灰阶掩膜工艺使金属氧化物半导体薄膜201形成通过第一过孔106和第二过孔107分别与第一半导体有源层101的两侧相接触且断开的金属氧化物半导体保留图案108、以及正对遮光层103的金属氧化物半导体有源层即第二半导体有源层111，并使第二金属层薄膜202形成分别位于金属氧化物半导体保留图案上的第一源极109和第一漏极110、以及分别与金属氧化物半导体有源层的两侧相接触的第二源极112和第二漏极113。S402. Form the metal oxide semiconductor thin film 201 through the first via hole 106 and the second via hole 107 by using a half-gray scale masking process to form a metal oxide that is in contact with and disconnected from both sides of the first semiconductor active layer 101, respectively. The semiconductor retention pattern 108, and the metal oxide semiconductor active layer facing the light-shielding layer 103, that is, the second semiconductor active layer 111, and the second metal layer film 202 form the first source layer respectively located on the metal oxide semiconductor retention pattern. An electrode 109 and a first drain 110, and a second source 112 and a second drain 113 respectively in contact with two sides of the metal oxide semiconductor active layer.
其中，该半灰阶掩膜工艺的具体过程为：在形成有金属氧化物半导体薄膜201和第二金属层薄膜202的基板上涂覆一层光刻胶200，采用半色调掩模板或者灰色调掩模板对涂覆有光刻胶200的基板进行曝光并对曝光后的基板进行显影，以得到光刻胶完全保留部分20a、光刻胶半保留部分20b和光刻胶去除部分20c，该光刻胶完全保留部分20a即对应待形成的金属氧化物半导体保留图案108、第一源极109和第一漏极110、以及第二源极112和第二漏极113；通过刻蚀工艺将光刻胶去除部分20c露出的第二金属层薄膜202和金属氧化物半导体薄膜201依次进行刻蚀，以得到金属氧化物半导体保留图案108、第一源极109和第一漏极110；通过灰化处理去除光刻胶半保留部分20b的光刻胶20，并通过刻蚀工艺将露出的第二金属层薄膜202进行刻蚀，以得到第二源极112和第二漏极113，以及第二半导体有源层111；最后去除剩余的光刻胶即可得到图5所示的基板。Wherein, the specific process of the half-gray-scale masking process is: coating a layer of photoresist 200 on the substrate formed with the metal oxide semiconductor thin film 201 and the second metal layer thin film 202, using a half-tone mask or gray-tone The mask plate exposes the substrate coated with the photoresist 200 and develops the exposed substrate to obtain a photoresist completely reserved part 20a, a photoresist half-retained part 20b and a photoresist removed part 20c. The resist fully reserved portion 20a corresponds to the metal oxide semiconductor reserved pattern 108 to be formed, the first source electrode 109 and the first drain electrode 110, and the second source electrode 112 and the second drain electrode 113; The second metal layer film 202 and the metal oxide semiconductor film 201 exposed by the resist removal part 20c are etched sequentially to obtain the metal oxide semiconductor remaining pattern 108, the first source electrode 109 and the first drain electrode 110; by ashing Process and remove the photoresist 20 of the photoresist half-retained part 20b, and etch the exposed second metal layer film 202 through an etching process, so as to obtain the second source electrode 112 and the second drain electrode 113, and the second Semiconductor active layer 111 ; finally, the remaining photoresist is removed to obtain the substrate shown in FIG. 5 .
在步骤S5中，参考图6所示，在第一源极109、第一漏极110、第二源极112和第二漏极113的上方通过一次构图工艺形成保护层114以及正对第二半导体有源层111的第二栅极115。In step S5, as shown in FIG. 6 , a protective layer 114 is formed on the first source 109 , the first drain 110 , the second source 112 and the second drain 113 through a patterning process and is facing the second The second gate 115 of the semiconductor active layer 111 .
其中，所述保护层114可以为单层结构或者为多层结构，其具体可以采用树脂形成。Wherein, the protective layer 114 can be a single-layer structure or a multi-layer structure, which can be specifically formed by resin.
示例的，如图12至图16所示，本步骤S5具体可以包括：For example, as shown in Figure 12 to Figure 16, this step S5 may specifically include:
S501、在第一源极109、第一漏极110、第二源极112和第二漏极113的上方依次形成保护层薄膜301和第三金属层薄膜302；S501, sequentially forming a protective layer film 301 and a third metal layer film 302 above the first source electrode 109, the first drain electrode 110, the second source electrode 112, and the second drain electrode 113;
S502、采用半灰阶掩膜工艺在保护层薄膜301中形成使有效显示区10b和周边电路区10a断开的区域以形成保护层114，并使第三金属层薄膜301形成正对第二半导体有源层的第二栅极115。S502, using a half-gray-scale masking process to form a region in the protective layer film 301 that disconnects the effective display region 10b from the peripheral circuit region 10a to form the protective layer 114, and make the third metal layer film 301 face the second semiconductor The second gate 115 of the active layer.
其中，该半灰阶掩膜工艺的具体过程为：在形成有保护层薄膜301和第三金属层薄膜302的基板上涂覆一层光刻胶200，采用半色调掩模板或者灰色调掩模板对涂覆有光刻胶200的基板进行曝光并对曝光后的基板进行显影，以得到光刻胶完全保留部分20a、光刻胶半保留部分20b和光刻胶去除部分20c，该光刻胶完全保留部分20a即对应待形成的第二栅极115；通过刻蚀工艺对光刻胶去除部分20c露出的第三金属层薄膜302和保护层薄膜301进行刻蚀，以得到将有效显示区10b和周边电路区10a断开的保护层114；通过灰化处理去除光刻胶半保留部分20b的光刻胶20，并通过刻蚀工艺将露出的第三金属层薄膜302进行刻蚀，以得到正对第二半导体有源层的第二栅极115；最后去除剩余的光刻胶即可得到图6所示的基板。Wherein, the specific process of the half-gray-scale masking process is: coating a layer of photoresist 200 on the substrate formed with the protective layer film 301 and the third metal layer film 302, using a half-tone mask or a gray-tone mask Expose the substrate coated with photoresist 200 and develop the exposed substrate to obtain photoresist completely reserved part 20a, photoresist half reserved part 20b and photoresist removed part 20c, the photoresist The completely reserved part 20a corresponds to the second gate 115 to be formed; the third metal layer film 302 and the protective layer film 301 exposed by the photoresist removal part 20c are etched by an etching process to obtain the effective display area 10b The protective layer 114 disconnected from the peripheral circuit area 10a; the photoresist 20 of the photoresist half-retained part 20b is removed by ashing treatment, and the exposed third metal layer film 302 is etched by an etching process to obtain facing the second gate 115 of the second semiconductor active layer; finally removing the remaining photoresist to obtain the substrate shown in FIG. 6 .
基于上述过程，通过五次构图工艺即可得到位于周边电路区10a的第一薄膜晶体管和位于有效显示区10b的第二薄膜晶体管。其中，该第一薄膜晶体管可以包括第一半导体有源层101、第一栅极104、第二半导体保留图案108、以及第一源极109和第一漏极110，该第二薄膜晶体管可以包括第二半导体有源层111、第二栅极115、以及第二源极112和第二漏极113。Based on the above process, the first thin film transistor located in the peripheral circuit area 10a and the second thin film transistor located in the effective display area 10b can be obtained through five patterning processes. Wherein, the first thin film transistor may include a first semiconductor active layer 101, a first gate 104, a second semiconductor retention pattern 108, and a first source 109 and a first drain 110, and the second thin film transistor may include The second semiconductor active layer 111 , the second gate 115 , and the second source 112 and the second drain 113 .
本示例实施方式还提供了一种阵列基板的制备方法，如图17所示，包括上述薄膜晶体管的制备方法以及位于有效显示区10b的第二薄膜晶体管的上方形成像素电极117。This exemplary embodiment also provides a manufacturing method of an array substrate, as shown in FIG. 17 , including the manufacturing method of the above thin film transistor and forming a pixel electrode 117 above the second thin film transistor located in the effective display area 10b.
基于此，如图18所示，该阵列基板的制备方法具体可以包括：Based on this, as shown in FIG. 18, the preparation method of the array substrate may specifically include:
S1、参考图2所示，在基板的上方通过一次构图工艺形成位于周边电路区10a的第一半导体有源层101；S1. Referring to FIG. 2 , a first semiconductor active layer 101 located in the peripheral circuit region 10a is formed on the substrate through a patterning process;
S2、参考图3所示，在第一半导体有源层101的上方形成第一绝缘层102，并在第一绝缘层102的上方通过一次构图工艺形成位于有效显示区10b的遮光层103以及正对第一半导体有源层101的第一栅极104；S2. Referring to FIG. 3 , form a first insulating layer 102 above the first semiconductor active layer 101, and form a light-shielding layer 103 located in the effective display area 10b and a positive electrode through a patterning process above the first insulating layer 102. to the first gate 104 of the first semiconductor active layer 101;
S3、参考图4所示，在遮光层103和第一栅极104的上方形成第二绝缘层105，并通过一次构图工艺形成贯穿于第一绝缘层102和第二绝缘层105的第一过孔106和第二过孔107，该第一过孔106和该第二过孔107分别将第一半导体有源层101的两侧露出；S3, as shown in FIG. 4, form a second insulating layer 105 above the light shielding layer 103 and the first gate 104, and form a first pass through the first insulating layer 102 and the second insulating layer 105 through a patterning process. A hole 106 and a second via hole 107, the first via hole 106 and the second via hole 107 respectively expose both sides of the first semiconductor active layer 101;
S4、参考图5所示，在第二绝缘层105的上方通过一次构图工艺形成通过第一过孔106和第二过孔107分别与第一半导体有源层101的两侧相接触且断开的第二半导体保留图案108、分别位于第二半导体保留图案108上的第一源极109和第一漏极110、正对遮光层103的第二半导体有源层111、以及分别与第二半导体有源层111的两侧相接触的第二源极112和第二漏极113；S4. Referring to FIG. 5 , a first via hole 106 and a second via hole 107 are formed on the second insulating layer 105 through a patterning process, respectively contacting and disconnecting from both sides of the first semiconductor active layer 101 The second semiconductor retention pattern 108, the first source electrode 109 and the first drain electrode 110 respectively located on the second semiconductor retention pattern 108, the second semiconductor active layer 111 facing the light shielding layer 103, and the second semiconductor a second source 112 and a second drain 113 in contact with both sides of the active layer 111;
S5、参考图6所示，在第一源极109、第一漏极110、第二源极112和第二漏极113的上方通过一次构图工艺形成保护层114以及正对第二半导体有源层111的第二栅极115。S5. As shown in FIG. 6, a protective layer 114 is formed on the first source electrode 109, the first drain electrode 110, the second source electrode 112 and the second drain electrode 113 through a patterning process and is directly opposite to the second semiconductor active layer. The second gate 115 of layer 111.
S6、参考图18所示，在第二栅极115的上方形成具有第三过孔的平坦层116以及通过第三过孔与第二漏极113电连接的像素电极117。S6 , referring to FIG. 18 , forming a flat layer 116 having a third via hole and a pixel electrode 117 electrically connected to the second drain electrode 113 through the third via hole above the second gate electrode 115 .
需要说明的是：平坦层116中的第三过孔还需穿透保护层114才能实现与第二漏极113之间的电连接，因此在步骤S5中形成保护层114时还可以同时形成该第三过孔。It should be noted that: the third via hole in the planar layer 116 needs to penetrate through the protective layer 114 to realize the electrical connection with the second drain electrode 113, so the protective layer 114 can also be formed at the same time in step S5. The third via.
基于上述步骤S1-S6，即可形成GOA阵列基板，该阵列基板包括位于周边电路区10a的第一薄膜晶体管例如LTPS薄膜晶体管以及位于有效显示区10b的第二薄膜晶体管例如LTPO薄膜晶体管。Based on the above steps S1-S6, the GOA array substrate can be formed, and the array substrate includes first thin film transistors such as LTPS thin film transistors located in the peripheral circuit area 10a and second thin film transistors located in the effective display area 10b such as LTPO thin film transistors.
这样一来，采用本示例实施方式所提供的阵列基板的制备方法制得的阵列基板，不仅能够同时实现窄边框以及降低功耗的功能，而且还能减少GOA阵列基板的构图工艺次数，从而提高产能、降低成本。In this way, the array substrate prepared by using the method for preparing the array substrate provided in this exemplary embodiment can not only realize the function of narrow frame and reduce power consumption at the same time, but also reduce the number of patterning processes of the GOA array substrate, thereby improving production capacity and cost reduction.
基于此，本示例实施方式还提供了一种阵列基板，参考图18所示，包括采用上述薄膜晶体管的制备方法而制得的薄膜晶体管，以及位于有效显示区10b的薄膜晶体管的上方形成像素电极117。Based on this, this exemplary embodiment also provides an array substrate, as shown in FIG. 18 , including a thin film transistor manufactured by the above thin film transistor manufacturing method, and a pixel electrode formed above the thin film transistor in the effective display area 10b 117.
其中，第一半导体有源层101、第一栅极104、第二半导体保留图案108、第一源极109和第一漏极110可构成位于周边电路区10a的第一薄膜晶体管；第二半导体有源层111、第二栅极115、第二源极112和第二漏极113可构成位于有效显示区10b的第二薄膜晶体管。Wherein, the first semiconductor active layer 101, the first gate 104, the second semiconductor retention pattern 108, the first source 109 and the first drain 110 can constitute a first thin film transistor located in the peripheral circuit region 10a; the second semiconductor The active layer 111 , the second gate 115 , the second source 112 and the second drain 113 can form a second thin film transistor located in the effective display area 10 b.
本实施例中，像素电极117可与第二薄膜晶体管的第二漏极113电连接，其例如可以通过穿透平坦层116和保护层114的第三过孔与该第二薄膜晶体管的第二漏极113实现电连接。In this embodiment, the pixel electrode 117 can be electrically connected to the second drain electrode 113 of the second thin film transistor, for example, it can be connected to the second drain electrode 113 of the second thin film transistor through the third via hole penetrating the flat layer 116 and the protective layer 114 . The drain 113 is electrically connected.
该阵列基板不仅可以同时实现窄边框以及降低功耗的功能，而且还能减少GOA阵列基板的构图工艺次数，从而提高产能、降低成本。The array substrate can not only realize the functions of narrow frame and lower power consumption, but also reduce the number of patterning processes of the GOA array substrate, thereby increasing production capacity and reducing costs.
本示例实施方式还提供了一种显示装置，包括上述的阵列基板，该阵列基板为GOA阵列基板。This exemplary embodiment also provides a display device, including the above-mentioned array substrate, where the array substrate is a GOA array substrate.
其中，所述显示装置例如可以包括手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。Wherein, the display device may include, for example, any product or component with a display function such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. Actually, according to the embodiment of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided to be embodied by a plurality of modules or units.
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。In addition, although steps of the methods of the present disclosure are depicted in the drawings in a particular order, there is no requirement or implication that the steps must be performed in that particular order, or that all illustrated steps must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and/or one step may be decomposed into multiple steps for execution, etc.
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, and these modifications, uses or adaptations follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field not disclosed in the present disclosure . The specification and examples are to be considered exemplary only, with the true scope and spirit of the disclosure indicated by the appended claims.
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。It should be understood that the present disclosure is not limited to the precise constructions which have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810040432.3ACN108231671B (en) | 2018-01-16 | 2018-01-16 | Preparation method of thin film transistor and array substrate, array substrate and display device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810040432.3ACN108231671B (en) | 2018-01-16 | 2018-01-16 | Preparation method of thin film transistor and array substrate, array substrate and display device |
| Publication Number | Publication Date |
|---|---|
| CN108231671Atrue CN108231671A (en) | 2018-06-29 |
| CN108231671B CN108231671B (en) | 2020-07-31 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810040432.3AActiveCN108231671B (en) | 2018-01-16 | 2018-01-16 | Preparation method of thin film transistor and array substrate, array substrate and display device |
| Country | Link |
|---|---|
| CN (1) | CN108231671B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109192736A (en)* | 2018-09-04 | 2019-01-11 | 京东方科技集团股份有限公司 | Thin-film transistor array base-plate and preparation method thereof, display device |
| CN109273409A (en)* | 2018-08-24 | 2019-01-25 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN111128874A (en)* | 2019-12-18 | 2020-05-08 | 武汉华星光电半导体显示技术有限公司 | TFT array substrate, preparation method thereof and OLED touch display device |
| CN111668238A (en)* | 2020-06-19 | 2020-09-15 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and manufacturing method thereof |
| WO2020224095A1 (en)* | 2019-05-05 | 2020-11-12 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method, and display apparatus |
| CN113571531A (en)* | 2021-07-12 | 2021-10-29 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN113611712A (en)* | 2021-07-29 | 2021-11-05 | 武汉华星光电技术有限公司 | Array substrate, display panel and manufacturing method thereof |
| CN114068590A (en)* | 2022-01-14 | 2022-02-18 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| WO2022061523A1 (en)* | 2020-09-22 | 2022-03-31 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display apparatus |
| JP2022521108A (en)* | 2019-02-26 | 2022-04-06 | 京東方科技集團股▲ふん▼有限公司 | Display board and its adjustment method, display device |
| WO2022088365A1 (en)* | 2020-10-30 | 2022-05-05 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method therefor |
| US12235557B2 (en) | 2021-06-29 | 2025-02-25 | Boe Technology Group Co., Ltd. | Displaying base plate and manufacturing method thereof, and displaying device |
| US12276890B2 (en) | 2022-01-14 | 2025-04-15 | Boe Technology Group Co., Ltd. | Display panel having support structures being formed in via holes of the interlayer insulating layer |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100182223A1 (en)* | 2009-01-22 | 2010-07-22 | Samsung Mobile Display Co., Ltd. | Organic light emitting display device |
| CN103187417A (en)* | 2011-12-30 | 2013-07-03 | 财团法人工业技术研究院 | Semiconductor device and method for manufacturing the same |
| CN103715196A (en)* | 2013-12-27 | 2014-04-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105408813A (en)* | 2013-08-26 | 2016-03-16 | 苹果公司 | Displays with silicon thin film transistors and semiconductor oxide thin film transistors |
| CN106803510A (en)* | 2015-11-26 | 2017-06-06 | 乐金显示有限公司 | Thin film transistor base plate, display and its manufacture method |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100182223A1 (en)* | 2009-01-22 | 2010-07-22 | Samsung Mobile Display Co., Ltd. | Organic light emitting display device |
| CN103187417A (en)* | 2011-12-30 | 2013-07-03 | 财团法人工业技术研究院 | Semiconductor device and method for manufacturing the same |
| CN105408813A (en)* | 2013-08-26 | 2016-03-16 | 苹果公司 | Displays with silicon thin film transistors and semiconductor oxide thin film transistors |
| CN103715196A (en)* | 2013-12-27 | 2014-04-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN106803510A (en)* | 2015-11-26 | 2017-06-06 | 乐金显示有限公司 | Thin film transistor base plate, display and its manufacture method |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273409A (en)* | 2018-08-24 | 2019-01-25 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| US11257849B2 (en) | 2018-08-24 | 2022-02-22 | Boe Technology Group Co., Ltd. | Display panel and method for fabricating the same |
| CN109192736A (en)* | 2018-09-04 | 2019-01-11 | 京东方科技集团股份有限公司 | Thin-film transistor array base-plate and preparation method thereof, display device |
| JP7417549B2 (en) | 2019-02-26 | 2024-01-18 | 京東方科技集團股▲ふん▼有限公司 | Display substrate, its adjustment method, and display device |
| JP2022521108A (en)* | 2019-02-26 | 2022-04-06 | 京東方科技集團股▲ふん▼有限公司 | Display board and its adjustment method, display device |
| WO2020224095A1 (en)* | 2019-05-05 | 2020-11-12 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method, and display apparatus |
| CN111128874A (en)* | 2019-12-18 | 2020-05-08 | 武汉华星光电半导体显示技术有限公司 | TFT array substrate, preparation method thereof and OLED touch display device |
| CN111668238A (en)* | 2020-06-19 | 2020-09-15 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and manufacturing method thereof |
| CN111668238B (en)* | 2020-06-19 | 2022-09-09 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and manufacturing method thereof |
| WO2022061523A1 (en)* | 2020-09-22 | 2022-03-31 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display apparatus |
| US12022698B2 (en) | 2020-09-22 | 2024-06-25 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Array substrate, display panel, and display device |
| WO2022088365A1 (en)* | 2020-10-30 | 2022-05-05 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method therefor |
| US12235557B2 (en) | 2021-06-29 | 2025-02-25 | Boe Technology Group Co., Ltd. | Displaying base plate and manufacturing method thereof, and displaying device |
| CN113571531A (en)* | 2021-07-12 | 2021-10-29 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN113571531B (en)* | 2021-07-12 | 2023-10-03 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN113611712B (en)* | 2021-07-29 | 2023-10-17 | 武汉华星光电技术有限公司 | Array substrate, display panel and manufacturing method thereof |
| CN113611712A (en)* | 2021-07-29 | 2021-11-05 | 武汉华星光电技术有限公司 | Array substrate, display panel and manufacturing method thereof |
| WO2023134674A1 (en)* | 2022-01-14 | 2023-07-20 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN114068590A (en)* | 2022-01-14 | 2022-02-18 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| US20240241415A1 (en)* | 2022-01-14 | 2024-07-18 | Boe Technology Group Co., Ltd. | Array substrate and display panel |
| US12276890B2 (en) | 2022-01-14 | 2025-04-15 | Boe Technology Group Co., Ltd. | Display panel having support structures being formed in via holes of the interlayer insulating layer |
| US12306509B2 (en)* | 2022-01-14 | 2025-05-20 | Boe Technology Group Co., Ltd. | Array substrate and display panel |
| Publication number | Publication date |
|---|---|
| CN108231671B (en) | 2020-07-31 |
| Publication | Publication Date | Title |
|---|---|---|
| CN108231671B (en) | Preparation method of thin film transistor and array substrate, array substrate and display device | |
| US11087985B2 (en) | Manufacturing method of TFT array substrate | |
| US9711542B2 (en) | Method for fabricating display panel | |
| CN108598089B (en) | TFT substrate manufacturing method and TFT substrate | |
| CN103383945B (en) | The manufacture method of a kind of array base palte, display unit and array base palte | |
| CN109273409A (en) | Display panel, manufacturing method thereof and display device | |
| CN103137558B (en) | A kind of TN type array base palte and preparation method thereof, display device | |
| US20140120657A1 (en) | Back Channel Etching Oxide Thin Film Transistor Process Architecture | |
| CN100578761C (en) | Manufacturing method of thin film transistor array substrate | |
| CN102842587B (en) | Array substrate, manufacturing method thereof, and display device | |
| WO2018201770A1 (en) | Array substrate, preparation method therefor and display device | |
| CN106024813B (en) | A kind of production method and related device of low temperature polycrystalline silicon tft array substrate | |
| US20160027797A1 (en) | Array substrate, manufacturing method thereof, and display device | |
| CN106783737A (en) | Array base palte and its manufacture method, display panel, display device | |
| CN102629608B (en) | Array substrate, a manufacturing method thereof and display device | |
| WO2017020480A1 (en) | Preparation method for thin film transistor and array substrate, array substrate, and display apparatus | |
| CN103681514B (en) | Array base palte and preparation method thereof, display unit | |
| CN106128950A (en) | The manufacture method of display base plate, display base plate and display device | |
| CN106935660A (en) | Thin film transistor (TFT) and preparation method thereof, array base palte and display device | |
| WO2019179128A1 (en) | Manufacturing method for array substrate, array substrate, display panel, and display device | |
| CN105529274A (en) | Manufacturing method of thin film transistor, array substrate and display device | |
| US11049888B1 (en) | Manufacturing method for TFT array substrate | |
| CN105374827A (en) | Display device and method for manufacturing the same | |
| CN107425011B (en) | Array substrate, manufacturing method thereof and display device | |
| CN106129071B (en) | A kind of production method and related device of array substrate |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |