CN108155244B - Trench-type tie-gate transistor and method of making the same - Google Patents
Trench-type tie-gate transistor and method of making the sameDownload PDFInfo
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- CN108155244B CN108155244BCN201711423827.3ACN201711423827ACN108155244BCN 108155244 BCN108155244 BCN 108155244BCN 201711423827 ACN201711423827 ACN 201711423827ACN 108155244 BCN108155244 BCN 108155244B
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- BOTDANWDWHJENH-UHFFFAOYSA-NTetraethyl orthosilicateChemical compoundCCO[Si](OCC)(OCC)OCCBOTDANWDWHJENH-UHFFFAOYSA-N0.000claimsabstractdescription39
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6728—Vertical TFTs
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6733—Multi-gate TFTs
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Translated fromChinese
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor manufacturing processes, in particular to a groove type grid-connected transistor and a manufacturing method thereof.
[ background of the invention ]
The groove type grid-connected transistor is also called UPGAT for short, is a novel power device, has the advantages of MOSFET and BJT at the same time, and has the main characteristics that: the on-resistance is small, the dynamic loss is small, the switching speed is high, the secondary breakdown voltage resistance is high, and the power capacity and the safe working area are large; has negative temperature coefficient, good thermal stability, strong impact resistance and high-frequency radiation resistance.
Under the condition that a high voltage is applied to a collector electrode, a space charge region between a deep junction gate region and a collector region of the coupled gate transistor is transversely expanded to pinch off a channel between the deep gate regions, so that the base region is electrostatically shielded, and the punch-through effect of the base region can be inhibited.
The UPGAT device manufactured by the conventional process has the withstand voltage of over 800V and the current of several amperes, and can be widely applied to the field of AC-DC power supply management.
One typical feature of trench-type gate-tied transistors is that the trenches are used to make the vertical diffusion of impurities deep. When a reverse bias voltage is applied to the collector, the N-EPI between the P-type high-doping regions can be quickly exhausted to play a role in electrostatic shielding of the P-type base region, and when the P-type base region is light and shallow, the P-type base region cannot easily penetrate through. For the above reasons, the device can obtain a larger current gain.
However, in the actual production process of the chip, the large-size and large-depth trench brings some troubles to the process, and in some cases, the reliability problems such as device breakdown creep degradation and the like can be caused by the fact that chemical pollutants such as device glue coating and pattern coating, photoresist in the trench and the like cannot be removed.
[ summary of the invention ]
In view of the above, the present invention provides a trench-type gate-connected transistor and a method for manufacturing the same, which at least solves one of the above technical problems.
A method for manufacturing a trench-type gate-coupled transistor comprises the following steps:
providing an N-type substrate, forming an N-type epitaxial layer on the N-type substrate, forming a P-type base region on the surface of the N-type epitaxial layer, forming a plurality of grooves penetrating through the P-type base region, forming P-type high-doping regions on the inner walls of the grooves, and forming a TEOS (tetraethyl orthosilicate) oxide layer on the P-type base region and the P-type high-doping surfaces;
etching the TEOS oxide layer by using photoresist so as to form an opening which penetrates through the TEOS oxide layer and corresponds to the P-type base region;
removing the photoresist, and forming polycrystalline silicon on the TEOS oxide layer and the P-type base region at the opening, wherein the polycrystalline silicon has N-type impurities;
performing a planarization technology on the polysilicon, thereby removing a part of the polysilicon outside the trench, so that the polysilicon in the trench and in the opening is reserved;
activating and propelling the N-type impurities in the polycrystalline silicon to enable the N-type impurities to be diffused to the surface of the P-type base region, so that an N-type region is formed on the surface of the P-type base region;
etching by using photoresist to remove part of the TEOS oxide layer on the P-type high-doping area;
and forming front metal on the TEOS oxide layer, the P-type high-doping area and the polysilicon, and forming back metal on one side of the N-type substrate, which is far away from the N-type epitaxial layer.
In one embodiment, the implantation element of the P-type base region is B, the implantation dose is generally between 14 powers per square centimeter 1 and 15 powers per square centimeter 1, and the implantation energy is between 50Kev and 200 Kev.
In one embodiment, the trenches have a width in the range of 3um to 10um and a depth in the range of 2um to 10 um.
In an embodiment, the formation in the high doped region of P type is including right trench bottom and lateral wall carry out the P type doping and carry out propulsive step to P type impurity, it is right wherein the injection dosage of lateral wall is less than right the half of the injection dosage of bottom, impel the temperature in the scope of 1000 degrees centigrade to 1200 degrees centigrade, impel the oxidation time in the scope of 1 hour to 6 hours, impel the back, the junction depth in the high doped region of P type of trench bottom is in the scope of 2um to 10um, the junction depth of trench lateral wall is in the scope of 1.5um to 7.5um, the concentration of P type base region is less than the concentration in the high doped region of P type, impel the completion after, the junction depth of P type base region is generally in the scope of 1um to 4 um.
In one embodiment, the TEOS oxide layer is grown by LPCVD to a thickness in a range from 3000 angstroms to 8000 angstroms.
In one embodiment, the polysilicon is grown by LPCVD, and the thickness of the polysilicon is greater than half of the width of the trench, so that the trench is filled; the growth thickness of the polycrystalline silicon is in the range of 2um to 7 um; the N-type impurity of the polysilicon includes P, and the dopant gas includes phosphine PH 3.
In one embodiment, the step of removing the portion of the polysilicon outside the trench includes: and removing part of the polysilicon outside the groove by adopting a chemical mechanical planarization technology or etching back.
In one embodiment, the method further comprises a back side thinning step before forming the back side metal.
In one embodiment, the N-type substrate is an N-type highly doped substrate, and the N-type epitaxial layer is an N-type lowly doped epitaxial layer.
A trench type grid-connected transistor comprises an N-type substrate, an N-type epitaxial layer formed on the N-type substrate, a P-type base region formed on the surface of the N-type epitaxial layer, a plurality of trenches penetrating through the P-type base region, a P-type high-doping region formed on the inner wall of the plurality of trenches, a P-type base region, a TEOS (tetraethyl orthosilicate) oxidation layer formed on the P-type high-doping surface, an opening penetrating through the TEOS oxidation layer and corresponding to the P-type base region, polycrystalline silicon formed in the trench and in the opening, an N-type region formed on the surface of the P-type base region, a TEOS oxidation layer, a P-type high-doping region, front metal formed on the polycrystalline silicon, and back metal formed on one side of the N-type epitaxial layer far away from the N-type substrate.
Compared with the prior art, the groove type grid-connected transistor and the manufacturing method thereof have the following advantages: one-time polysilicon photoetching and etching is omitted, and the manufacturing cost of the device is reduced; after planarization, glue coating and photoetching can be carried out on the plane subsequently, so that the risk that the bottom pattern cannot be exposed due to too thick glue in the traditional process can be avoided; after the planarization, the large groove is completely filled, so that the problem that chemical pollutants accumulate in the groove and the problem of subsequent gluing and pattern coating are not needed to be worried about; the polycrystalline silicon in the groove and the polycrystalline silicon in the emitter region in the opening are disconnected and are not integrated, so that the stress of the polycrystalline silicon film layer to the device is greatly weakened, and the problems of device electric leakage and poor reliability caused by surface stress are solved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive efforts.
Fig. 1 is a flow chart of a method for fabricating a trench-type gate-tied transistor according to the present invention.
Fig. 2-8 are schematic structural diagrams illustrating steps of a method for fabricating the trench-type gate-coupled transistor shown in fig. 1.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-8, fig. 1 is a flow chart illustrating a method for fabricating a trench-type gate-coupled transistor according to the present invention, and fig. 2-8 are schematic structural diagrams illustrating steps of the method for fabricating the trench-type gate-coupled transistor shown in fig. 1. The manufacturing method of the trench-type grid-connected transistor comprises the following steps.
Step S1, referring to fig. 2, providing an N-type substrate, forming an N-type epitaxial layer on the N-type substrate, forming a P-type base region on the surface of the N-type epitaxial layer, forming a plurality of trenches penetrating through the P-type base region, forming P-type highly doped regions on the inner walls of the plurality of trenches, and forming a TEOS (tetraethylorthosilicate) oxide layer on the P-type base region and the P-type highly doped surfaces.
Specifically, the implantation element of the P-type base region is B, the implantation dosage is generally between 14 powers per square centimeter 1 and 15 powers per square centimeter 1, and the implantation energy is between 50Kev and 200 Kev. The width of slot is in the within range of 3um to 10um, and the degree of depth is in the within range of 2um to 10 um. The formation in P type heavily doped region is including right ditch slot bottom and lateral wall carry out P type doping and carry out propulsive step to P type impurity, wherein right the injection dosage of lateral wall is less than right the half of the injection dosage of bottom, impel the temperature at 1000 degrees centigrade to 1200 degrees centigrade within ranges, impel oxidation time at 1 hour to 6 hours within ranges, impel the back, the junction depth in the P type heavily doped region of ditch slot bottom is in 2um to 10um within ranges, the junction depth of ditch slot lateral wall is in 1.5um to 7.5um within ranges, the concentration of P type base region is less than the concentration in P type heavily doped region, impels the back of accomplishing, the junction depth of P type base region is generally in 1um to 4um within ranges. The P-type impurity may be elemental boron B.
Further, in step S1, the TEOS oxide layer is grown by LPCVD, and has a thickness in a range from 3000 angstroms to 8000 angstroms. The TEOS oxide layer is grown by LPCVD, and the thickness is in the range of 3000 angstroms to 8000 angstroms.
In step S2, referring to fig. 3, the TEOS oxide layer is etched by using a photoresist, so as to form an opening penetrating through the TEOS oxide layer and corresponding to the P-type base region. The opening is an emitter region opening.
Step S3, please refer to fig. 4, the photoresist is removed, and polysilicon is formed on the TEOS oxide layer and on the P-type base region at the opening, where the polysilicon has N-type impurities. The polycrystalline silicon is grown by adopting an LPCVD (low pressure chemical vapor deposition) mode, and the thickness of the polycrystalline silicon is more than half of the width of the groove, so that the groove is filled; the growth thickness of the polycrystalline silicon is in the range of 2um to 7 um; the N-type impurity of the polysilicon comprises phosphorus P, and the doping gas comprises phosphine PH3。
In step S4, referring to fig. 5, a planarization technique is performed on the polysilicon to remove a portion of the polysilicon outside the trench, so that the polysilicon in the trench and in the opening is retained. In particular, the planarization technique may be a chemical mechanical planarization technique (CMP) or an etch-back planarization technique.
Step S5, please refer to fig. 6, the N-type impurity in the polysilicon is activated and driven, so that the N-type impurity is diffused to the surface of the P-type base region, thereby forming an N-type region on the surface of the P-type base region. The N-type impurity may include phosphorus P.
In step S6, referring to fig. 7, a photoresist is used to etch and remove a portion of the TEOS oxide layer on the P-type heavily doped region.
In step S7, referring to fig. 8, a front metal is formed on the TEOS oxide layer, the P-type heavily doped region, and the polysilicon, and a back metal is formed on the N-type substrate away from the N-type epitaxial layer. In one embodiment, before forming the back metal, the manufacturing method further includes a step of performing back thinning.
As shown in fig. 8, the trench-type gate-connected transistor obtained by the above manufacturing method includes an N-type substrate, an N-type epitaxial layer formed on the N-type substrate, a P-type base region formed on the surface of the N-type epitaxial layer, a plurality of trenches penetrating through the P-type base region, P-type highly doped regions formed on the inner walls of the plurality of trenches, a TEOS oxide layer formed on the P-type base region and the P-type highly doped surfaces, an opening penetrating through the TEOS oxide layer and corresponding to the P-type base region, polysilicon formed in the trench and in the opening, an N-type region formed on the surface of the P-type base region, front metal formed on the TEOS oxide layer, the P-type highly doped regions and the polysilicon, and back metal formed on a side of the N-type substrate away from the N-type epitaxial layer.
Compared with the prior art, the groove type grid-connected transistor and the manufacturing method thereof have the following advantages: one-time polysilicon photoetching and etching is omitted, and the manufacturing cost of the device is reduced; after planarization, glue coating and photoetching can be carried out on the plane subsequently, so that the risk that the bottom pattern cannot be exposed due to too thick glue in the traditional process can be avoided; after the planarization, the large groove is completely filled, so that the problem that chemical pollutants accumulate in the groove and the problem of subsequent gluing and pattern coating are not needed to be worried about; the polycrystalline silicon in the groove and the polycrystalline silicon in the emitter region in the opening are disconnected and are not integrated, so that the stress of the polycrystalline silicon film layer to the device is greatly weakened, and the problems of device electric leakage and poor reliability caused by surface stress are solved.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A manufacturing method of a groove type grid-connected transistor is characterized by comprising the following steps: the manufacturing method comprises the following steps:
providing an N-type substrate, forming an N-type epitaxial layer on the N-type substrate, forming a P-type base region on the surface of the N-type epitaxial layer, forming a plurality of grooves penetrating through the P-type base region, forming P-type high-doping regions on the inner walls of the grooves, and forming a TEOS (tetraethyl orthosilicate) oxide layer on the P-type base region and the P-type high-doping surfaces;
etching the TEOS oxide layer by using photoresist so as to form an opening which penetrates through the TEOS oxide layer and corresponds to the P-type base region;
removing the photoresist, and forming polycrystalline silicon on the TEOS oxide layer and the P-type base region at the opening, wherein the polycrystalline silicon has N-type impurities;
performing a planarization technology on the polysilicon, thereby removing a part of the polysilicon outside the trench, so that the polysilicon in the trench and in the opening is reserved;
activating and propelling the N-type impurities in the polycrystalline silicon to enable the N-type impurities to be diffused to the surface of the P-type base region, so that an N-type region is formed on the surface of the P-type base region;
etching by using photoresist to remove part of the TEOS oxide layer on the P-type high-doping area;
and forming front metal on the TEOS oxide layer, the P-type high-doping area and the polysilicon, and forming back metal on one side of the N-type substrate, which is far away from the N-type epitaxial layer.
2. The method of claim 1, wherein: the implantation element of the P-type base region is B, and the implantation dosage is 1 multiplied by 1014/cm2-1×1015/cm2And the implantation energy is between 50Kev and 200 Kev.
3. The method of claim 1, wherein: the width of slot is in the within range of 3um to 10um, and the degree of depth is in the within range of 2um to 10 um.
4. The method of claim 1, wherein: the formation in P type heavily doped region is including right ditch slot bottom and lateral wall carry out P type doping and carry out propulsive step to P type impurity, wherein right the injection dosage of lateral wall is less than right the half of the injection dosage of bottom, impel the temperature at 1000 degrees centigrade to 1200 degrees centigrade within ranges, impel oxidation time at 1 hour to 6 hours within ranges, impel the back, the junction depth in 2um to 10 um's the range in the P type heavily doped region of ditch slot bottom, the junction depth of ditch slot lateral wall is in 1.5um to 7.5 um's within range, the concentration of P type base region is less than the concentration in P type heavily doped region promotes the back of accomplishing, the junction depth of P type base region is in 1um to 4 um's within range.
5. The method of claim 1, wherein: the TEOS oxide layer is grown by LPCVD, and the thickness is in the range of 3000 angstroms to 8000 angstroms.
6. The method of claim 1, wherein: the polycrystalline silicon is grown in an LPCVD mode, and the thickness of the polycrystalline silicon is larger than half of the width of the groove, so that the groove is filled; the growth thickness of the polycrystalline silicon is in the range of 2um to 7 um; the N-type impurity of the polysilicon comprises P, and the doping gas comprises phosphine PH3。
7. The method of claim 1, wherein: the step of removing the polysilicon outside the trench includes: and removing part of the polysilicon outside the groove by adopting a chemical mechanical planarization technology or etching back.
8. The method of claim 1, wherein: the manufacturing method further comprises a back thinning step before the back metal is formed.
9. The method of claim 1, wherein: the N-type substrate is an N-type highly doped substrate, and the N-type epitaxial layer is an N-type lowly doped epitaxial layer.
10. A trench-type gate-coupled transistor manufactured by the method for manufacturing a trench-type gate-coupled transistor according to any one of claims 1 to 9, wherein: the groove type grid-connected transistor comprises an N-type substrate, an N-type epitaxial layer formed on the N-type substrate, a P-type base region formed on the surface of the N-type epitaxial layer, a plurality of grooves penetrating through the P-type base region, P-type high-doping regions formed on the inner walls of the grooves, a TEOS (tetraethyl orthosilicate) oxidation layer formed on the P-type base region and the P-type high-doping surfaces, an opening penetrating through the TEOS oxidation layer and corresponding to the P-type base region, polycrystalline silicon formed in the grooves and in the opening, an N-type region formed on the surface of the P-type base region, front metal formed on the TEOS oxidation layer, the P-type high-doping regions and the polycrystalline silicon, and back metal formed on one side, far away from the N-type epitaxial layer, of the N-type substrate.
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| CN109975904A (en)* | 2019-03-22 | 2019-07-05 | 无锡中微掩模电子有限公司 | A kind of reflective DOE diffractive optical element of high-precision and preparation method thereof |
| CN115863398A (en)* | 2023-02-06 | 2023-03-28 | 苏州锴威特半导体股份有限公司 | Silicon carbide MOSFET and manufacturing method thereof |
| CN118507346B (en)* | 2024-07-19 | 2024-10-11 | 上海埃积半导体有限公司 | Latch-up resistant IGBT device and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010061015A (en)* | 1999-12-28 | 2001-07-07 | 박종섭 | Manufacturing method of semiconductor device |
| JP2002009032A (en)* | 2001-04-13 | 2002-01-11 | Sony Corp | Forming method of element separation region, semiconductor device and manufacturing method thereof |
| US6551856B1 (en)* | 2000-08-11 | 2003-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming copper pad redistribution and device formed |
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| CN1135632C (en)* | 2000-02-18 | 2004-01-21 | 李思敏 | Linked-grid transistor |
| CN102751322B (en)* | 2011-07-28 | 2015-02-11 | 李思敏 | Gate associated transistor of groove-shaped gate polycrystalline silicon structure and manufacturing method thereof |
| CN103956377A (en)* | 2014-04-16 | 2014-07-30 | 李思敏 | GAT of double-high-resistance-layer groove shape gate polycrystalline silicon structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20010061015A (en)* | 1999-12-28 | 2001-07-07 | 박종섭 | Manufacturing method of semiconductor device |
| US6551856B1 (en)* | 2000-08-11 | 2003-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming copper pad redistribution and device formed |
| JP2002009032A (en)* | 2001-04-13 | 2002-01-11 | Sony Corp | Forming method of element separation region, semiconductor device and manufacturing method thereof |
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