CN108132894B - Positioning device and method for TLB multi-hit exception in CPU - Google Patents

Abstract

The invention provides a positioning device and a method for TLB multi-hit abnormity in a CPU, wherein the method specifically comprises the following steps: the virtual address to be mapped is compared with matching addresses stored in n TLB table entries in a hit comparison module, wherein the matching addresses are configured in advance, and the matching hit numbers in the table entries are obtained; screening out the numbers of the hit table entries with the minimum number and the maximum number by adopting a multiplexer with a priority, and storing the numbers in a register; the exception handler reads the values of the two registers, locating the TLB entry number that caused the TLB multi-hit. The invention assists the TLB multi-hit exception handling program, and can quickly find out the TLB table entry number in which the TLB multi-hit occurs; two sets of multiplexers with priorities and software accessible registers are adopted, so that the time for processing the TLB multi-hit exception is saved, and the exception checking efficiency is improved.

Description

Positioning device and method for TLB multi-hit exception in CPU

Technical Field

The invention belongs to the technical field of embedded processors in integrated circuits, and particularly relates to a positioning device and method for TLB multi-hit exception in a CPU.

Background

As a functional module commonly used in a CPU (central processing unit), a tlb (translation Lookaside buffer) is responsible for mapping a virtual address in a software program executed by the CPU to a real address on a physical bus. Ideally, each virtual address should be mapped by the TLB to a unique real address.

In practice, however, the mapping table stored in the TLB is implemented by a manual pre-writing program, which may cause some non-uniqueness of the virtual address mapping due to human reasons. As shown in the example of fig. 2; for example, the virtual address segments 0x 00001000-0 x00005000 are mapped to the real address segments 0x 10001000-0 x10005000 and stored in the TLB table entry # 1. The virtual address segments 0x 00004000-0 x00008000 are mapped to real address segments 0x 20004000-0 x20008000 and stored in TLB table entry # 2. Therefore, the virtual address subsections 0x00004000 to 0x00005000 are mapped to the real address subsections 0x10004000 to 0x10005000 by the table entry #1 and mapped to the real address subsections 0x20004000 to 0x20005000 by the table entry # 2. Such overlapping of virtual address segments in different TLB entries may result in non-unique mapping of overlapping segment addresses.

The address mapping that is not unique in a TLB is commonly referred to in the industry as TLB multi hit. Some CPUs such as PowerPC470 have internal circuitry that automatically selects one mapping and discards another mapping according to some built-in rule when TLB multiple-hit occurs. Other CPUs, such as PowerPC460, when a TLB multi-hit occurs, immediately trigger the CPU to enter a TLB multi-hit exception state. The CPU stops the execution of the normal program and jumps to the exception handling program corresponding to the TLB multi-hit programmed in advance to try to correct the error.

Because there are generally many TLB mapping table entries in the CPU, it is cumbersome to check which mapping of two (or more) table entries overlap one by one. The troubleshooting is completed through an exception handling program, so that the complexity of program writing is brought, and the time overhead of troubleshooting and error correction is influenced.

Disclosure of Invention

In view of the above, the present invention is directed to provide a positioning apparatus for TLB multiple hit exception in a CPU, which can quickly and intuitively feedback which two TLB mapping table entries are overlapped when two table entries are hit.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a positioning device for TLB multi-hit exception in CPU comprises a virtual address input module to be mapped, a hit comparison module and a multiplexer which are connected in sequence, wherein the hit comparison module is also connected with two groups of registers through the multiplexer with priority;

the hit comparison module is used for comparing the virtual address to be mapped with the preset matching addresses stored in the n TLB table entries one by one to obtain the number of matching hits in the table entries;

the multiplexer is used for outputting the mapped real address;

and the two groups of registers are used for storing the table entry numbers with the maximum number and the minimum number screened out by the multiplexer with the priority.

Further, the bit width of each group of registers is the binary width of the TLB table entry number.

Further, the two sets of registers are readable by a software program, and the values of the registers are synchronously reset to 0 when the CPU is reset.

Compared with the prior art, the positioning device for the TLB multi-hit exception in the CPU has the following advantages: the invention assists the TLB multi-hit exception handling program, and can quickly find out the TLB table entry number in which the TLB multi-hit occurs; two sets of multiplexers with priorities and software accessible registers are adopted, so that the time for processing the TLB multi-hit exception is saved, and the exception checking efficiency is improved.

Another objective of the present invention is to provide a method for positioning TLB multiple hit exception in CPU, which can quickly and intuitively feedback which two TLB mapping table entries are overlapped when two table entries are hit.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a method for positioning TLB multi-hit exception in CPU includes following steps:

(1) the virtual address to be mapped is compared with matching addresses stored in n TLB table entries in a hit comparison module, wherein the matching addresses are configured in advance, and the matching hit numbers in the table entries are obtained;

(2) screening out the hit table entry number with the minimum number by adopting a multiplexer with priority, and storing the hit table entry number in a register;

(3) screening out the number of the hit table entry with the largest number by adopting a multiplexer with priority, and storing the number in a register;

(4) the exception handler reads the values of the two registers, locating the TLB entry number that caused the TLB multi-hit.

Furthermore, when two or more TLB table entries are hit at the same time, the hit comparison module sets the multi hit flag signal, and the two groups of registers store the numbers of the two hit table entries by using the multi hit flag signal as an enable signal.

The method for positioning the TLB multi-hit abnormity in the CPU has the same beneficial effect as the positioning device for the TLB multi-hit abnormity in the CPU, and is not repeated herein.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic structural diagram of a positioning apparatus for a TLB multi-hit exception in a CPU according to an embodiment of the present invention;

fig. 2 is a diagram illustrating non-uniqueness of virtual address mapping in the prior art.

Detailed Description

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

As shown in fig. 1, in practical application, the virtual address to be mapped is compared with the matching addresses stored in n TLB entries in advance, and after comparison, when only one of the n TLB entries is matched and hit, the number of the hit entry is used as a routing signal of the multiplexer, and the pre-configured real address information corresponding to the hit entry is screened out and output, thereby completing a normal TLB mapping process;

when more than one TLB table entry is hit, the invention provides a diagnosis positioning device and method, which can quickly and intuitively feedback which two TLB mapping table entries are overlapped.

The positioning device comprises a virtual address input module to be mapped, a hit comparison module and a multiplexer which are sequentially connected, wherein the hit comparison module is also connected with two groups of registers through the multiplexer with priority;

the hit comparison module is used for comparing the virtual address to be mapped with the preset matching addresses stored in the n TLB table entries one by one to obtain the number of matching hits in the table entries;

the multiplexer is used for outputting the mapped real address;

and the two groups of registers are used for storing the table entry numbers with the maximum number and the minimum number screened out by the multiplexer with the priority. The bit width of each group of registers is the binary width of the TLB table entry number. When two or more TLB table entries hit at the same time, the comparison circuit sets a multi hit flag signal, and the 2 groups of registers store two hit table entry numbers by using the multi hit flag signal as an enable signal.

The input of the first group of registers adopts a multiplexer with priority to screen out the hit table entry number with the minimum number. And a second group of registers, the input of which adopts a multiplexer with priority to screen out the hit table entry number with the largest number. The two sets of registers are readable by a software program, and the values of the registers are synchronously reset to 0 when the CPU is reset. When the CPU has TLB multi-hit abnormity, the abnormity processing program can directly read the values of the two groups of registers, thereby directly positioning which two groups of TLB table items have mapping overlap, not only saving the troubleshooting program, but also saving the time overhead of one-by-one troubleshooting.

An example of an implementation on the PowerPC460 is given here. The number of TLB entries of PowerPC460 is 64, and a fully associative structure is adopted, and the entry numbers are from #0 to # 63. Each virtual address generated by the CPU running the software program is compared with the preset addresses in the 64 entries to determine which hit. The bit width of each group of the 2 groups of hit table entry number registers added in the invention is 6 bit. When TLB multi hit occurs, the first set of registers filters out the first hit entry in the order #0 to #63 and stores its number. The second set of registers selects the second hit entry in the order #63 to #0 and stores its number. The two sets of registers are software program accessible registers that access bits 26 to 31 and 18 to 23 addressed to the PowerPC460 exception status register ESR. The TLB multi hit exception handler of PowerPC460 may read the last 2 bytes of the ESR directly to locate the TLB entry number that caused the TLB multi-hit.

When more than two items are hit, the two items can be reduced to 2 items hit to process the items pair by pair.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (5)

1. A positioning device for TLB multi-hit exception in CPU is characterized in that: the virtual address mapping device comprises a virtual address input module to be mapped, a hit comparison module and a first multiplexer which are sequentially connected, wherein the hit comparison module is also connected with two groups of registers through second multiplexers with priorities respectively;

the hit comparison module is used for comparing the virtual address to be mapped with the preset matching addresses stored in the n TLB table entries one by one to obtain the number of matching hits in the table entries;

the first multiplexer is used for outputting the mapped real address;

and the two groups of registers are used for storing the table entry numbers with the maximum number and the minimum number screened out by the second multiplexer with the priority.

2. The apparatus for locating a TLB multi-hit exception in a CPU of claim 1, wherein: the bit width of each group of registers is the binary width of the TLB table entry number.

3. The apparatus for locating a TLB multi-hit exception in a CPU of claim 1, wherein: the two sets of registers are readable by a software program, and their values are synchronously reset to 0 upon a CPU reset.

4. A method for locating a TLB multiple hit exception in a CPU using the apparatus for locating a TLB multiple hit exception in a CPU as recited in any one of claims 1 to 3, wherein: the method specifically comprises the following steps:

(1) the virtual address to be mapped is compared with matching addresses stored in n TLB table entries in a hit comparison module, wherein the matching addresses are configured in advance, and the matching hit numbers in the table entries are obtained;

(2) screening out the hit table entry number with the minimum number by adopting a multiplexer with priority, and storing the hit table entry number in a register;

(3) screening out the number of the hit table entry with the largest number by adopting a multiplexer with priority, and storing the number in a register;

(4) the exception handler reads the values of the two registers, locating the TLB entry number that caused the TLB multi-hit.

5. The method for locating a TLB multi-hit exception in a CPU of claim 4, wherein: when two or more TLB table entries are hit at the same time, the hit comparison module sets a multi hit flag signal, and the two groups of registers store two hit table entry numbers by using the multi hit flag signal as an enable signal.

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