CN108121433B - Task scheduling method of GPU (graphics processing Unit) multiprocessor system - Google Patents
Task scheduling method of GPU (graphics processing Unit) multiprocessor systemDownload PDFInfo
- Publication number
- CN108121433B CN108121433BCN201711281085.5ACN201711281085ACN108121433BCN 108121433 BCN108121433 BCN 108121433BCN 201711281085 ACN201711281085 ACN 201711281085ACN 108121433 BCN108121433 BCN 108121433B
- Authority
- CN
- China
- Prior art keywords
- processor
- bit
- processors
- busy
- idle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/329—Power saving characterised by the action undertaken by task scheduling
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Power Sources (AREA)
Abstract
Description
Technical Field
The invention belongs to the field of electronics, and relates to a task scheduling method of a GPU (graphics processing unit) multiprocessor system.
Background
Currently, a plurality of processors are generally used as a system for data processing in a GPU, and a task scheduling method of a GPU multiprocessor system is required in order to exert the functions of all the processors and adapt to different working modes (high performance mode — low power consumption mode) of the GPU.
Disclosure of Invention
The invention aims to provide a task scheduling method of a GPU multiprocessor system, which can schedule the GPU multiprocessor system according to a GPU working mode and ensure the normal operation of the system.
The technical solution of the invention is as follows:
a task scheduling method of a GPU multiprocessor system comprises the following steps:
(1) the following bit segments are provided to the user: the processor comprises a simple-complex mode selection bit, a high-performance-low-power-consumption mode selection bit, a processor starting number bit, current busy-idle state bits of all processors, and starting-closing positions of all processors, wherein a processor user can configure the simple-complex mode selection bit, the high-performance-low-power-consumption mode selection bit and the processor starting number bit by configuring a high bit section;
(2) task scheduling method initialization
(2-1) when the simple-complex mode selection bit is set to be a simple mode, the GPU multiprocessor system is bypassed, the current busy-idle state bits of all processors are set to be idle, and the opening-closing positions of all processors are set to be closed;
(2-2) when the simple-complex mode selection bit is set to be a complex mode, the high-performance-low-power-consumption mode selection bit is set to be a high-performance mode, the opening-closing positions of all processors are set to be opened, and the current busy-idle state bits of all processors are idle;
(2-3) when the simple-complex mode selection bit is set to be the complex mode, the high-performance-low power consumption mode selection bit is set to be the low power consumption mode, and the setting of the starting number bits of the processors is completed, at the moment, the GPU multiprocessor system only sets the current starting-closing state bits of the starting number bits of the processors to be started, and the current starting-closing state bits of the other processors are set to be closed;
(3) task scheduling, when a processor usage request is received,
(3-1) if the setting mode is as in (2-1), the processor use request is not sent to the processor and is directly sent to the next-stage module;
(3-2) if the mode is set as in (2-2), when a processor use request is received, performing task mapping in a high-performance mode, firstly inquiring current busy-idle state bits of all processors, and when the first current busy-idle state bit is found to be an idle processor, sending data to the processor, and then setting the current busy-idle state bit of the processor to be busy; if all processors are busy at present-the idle state bit is busy, waiting for a period to continue inquiring; when a signal of finishing the calculation of the processor is received, setting the current busy-idle state bit of the register to be idle;
(3-3) if the mode is set as in (2-3), when a processor use request is received, performing task mapping in a low power consumption mode, firstly inquiring current busy-idle state bits of all open state processors, if any processor with a current busy-idle state bit being idle is found, sending data to the processor, then setting the current busy-idle state bit of the processor to be busy, if all open processors are busy, inquiring whether the processor with the current open-close state bit being close state exists, if not, waiting for a period to continue inquiring, and if so, setting the open-close state bit of the processor to be open, and setting the current busy-idle state bit of the processor to be busy; when a processor count complete signal is received, the current busy-idle status bit of this register is set to idle.
The invention has the advantages that:
the performance of all processors can be exerted, the working conditions of the GPU in different working modes (high-performance mode-low-power-consumption mode) are adapted, the situation that as few processors as possible participate in processing operation in the low-power-consumption mode is guaranteed, and as many processors as possible participate in processing operation in the high-performance mode is guaranteed.
Drawings
Fig. 1 is a block diagram of a task scheduling method of a GPU multiprocessor system.
Detailed Description
The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and the specific embodiments. It is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than the whole embodiments, and that all other embodiments, which can be derived by a person skilled in the art without inventive step based on the embodiments of the present invention, belong to the scope of protection of the present invention.
As shown in fig. 1, a task scheduling method of a GPU multiprocessor system is characterized by comprising 3 steps: user configuration, task scheduling method initialization, task scheduling, and providing the following bit segments to the user: the method comprises the following steps of (1) selecting a simple-complex mode (determining that a current system works in a simple or complex mode), selecting a high-performance-low-power mode (determining that the current system works in the high-performance-low-power mode), starting a processor number (determining how many processors the current system can be started at most), currently busy-idle state bits (indicating whether all processors are currently used or not), starting-closing states (indicating whether the processors are currently started or not) of all processors, and configuring a processor user by configuring a bit section to enable a task scheduling module to work under the condition of user needs, wherein the scheduling method comprises the following working steps:
(1) the user configures simple-complex mode selection bits, high-performance-low power consumption mode selection bits and processor starting number bits;
(2) the task scheduling method is initialized, i.e.
1) When the simple-complex mode selection bit is set to be a simple mode, the GPU multiprocessor system is bypassed, the current busy-idle state bits of all the processors are set to be idle, and the opening-closing positions of all the processors are set to be closed;
2) when the simple-complex mode selection bit is set to be a complex mode, the high-performance-low-power-consumption mode selection bit is set to be a high-performance mode, the opening-closing positions of all processors are set to be opened, and the current busy-idle state bits of all processors are idle;
3) when the simple-complex mode selection bit is set to be the complex mode, the high-performance-low power consumption mode selection bit is set to be the low power consumption mode, and the setting of the starting number bits of the processors is completed, at the moment, the GPU multiprocessor system only sets the current starting-closing state bits of the starting number bits of the processors to be started, and sets the current starting-closing state bits of the other processors to be closed;
(3) task scheduling, i.e. when a processor usage request is received,
1) if the setting mode is 2-1, the processor use request is not sent to the processor and is directly sent to the next set of modules;
2) if the mode is set as 2-2, when a processor use request is received, task mapping in a high-performance mode is carried out, namely current busy-idle state bits of all processors are firstly inquired, when the first current busy-idle state bit is found to be an idle processor, data are sent to the processors, and then the current busy-idle state bits of the processors are set to be busy; if all processors are busy at present-the idle state bit is busy, waiting for a period to continue inquiring; when a signal of finishing the calculation of the processor is received, setting the current busy-idle state bit of the register to be idle;
3) if the mode is set as 2-3, when a processor use request is received, task mapping in a low power consumption mode is carried out, namely, current busy-idle state bits of all open state processors are firstly inquired, if any processor with the current busy-idle state bit being idle is found, data are sent to the processor, then the current busy-idle state bit of the processor is set to be busy, if the current busy-idle state bits of all open processors are busy, whether the processor with the current open-close state bit being close state exists is inquired, if not, a period is waited for continuous inquiry, if yes, the open-close state bit of the processor is set to be open, and the current busy-idle state bit of the processor is set to be busy; when a processor count complete signal is received, the current busy-idle status bit of this register is set to idle.
Claims (1)
1. A task scheduling method of a GPU multiprocessor system is characterized by comprising the following steps:
(1) the following bit segments are provided to the user: the processor comprises a simple-complex mode selection bit, a high-performance-low-power-consumption mode selection bit, a processor starting number bit, current busy-idle state bits of all processors, and starting-closing positions of all processors, wherein a processor user can configure the simple-complex mode selection bit, the high-performance-low-power-consumption mode selection bit and the processor starting number bit by configuring a high bit section;
(2) task scheduling method initialization
(2-1) when the simple-complex mode selection bit is set to be the simple mode, the GPU multiprocessor system is bypassed, the current busy-idle state bits of all processors are set to be idle, and the opening-closing positions of all processors are set to be closed;
(2-2) when the simple-complex mode selection bit is set to be a complex mode, the high-performance-low-power-consumption mode selection bit is set to be a high-performance mode, the opening-closing positions of all processors are set to be opened, and the current busy-idle state bits of all processors are idle;
(2-3) when the simple-complex mode selection bit is set to be the complex mode, the high-performance-low power consumption mode selection bit is set to be the low power consumption mode, and the setting of the starting number bits of the processors is completed, at the moment, the GPU multiprocessor system only sets the current starting-closing state bits of the starting number bits of the processors to be started, and the current starting-closing state bits of the other processors are set to be closed;
(3) task scheduling, when a processor usage request is received,
(3-1) if the setting mode is as in (2-1), the processor use request is not sent to the processor and is directly sent to the next-stage module;
(3-2) if the mode is set as in (2-2), when a processor use request is received, performing task mapping in a high-performance mode, firstly inquiring current busy-idle state bits of all processors, and when the first current busy-idle state bit is found to be an idle processor, sending data to the processor, and then setting the current busy-idle state bit of the processor to be busy; if all processors are busy at present-the idle state bit is busy, waiting for a period to continue inquiring; when a signal of finishing the calculation of the processor is received, setting the current busy-idle state bit of the register to be idle;
(3-3) if the mode is set as in (2-3), when a processor use request is received, performing task mapping in a low power consumption mode, firstly inquiring current busy-idle state bits of all open state processors, if any processor with a current busy-idle state bit being idle is found, sending data to the processor, then setting the current busy-idle state bit of the processor to be busy, if all open processors are busy, inquiring whether the processor with the current open-close state bit being close state exists, if not, waiting for a period to continue inquiring, and if so, setting the open-close state bit of the processor to be open, and setting the current busy-idle state bit of the processor to be busy; when a processor count complete signal is received, the current busy-idle status bit of this register is set to idle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711281085.5ACN108121433B (en) | 2017-12-06 | 2017-12-06 | Task scheduling method of GPU (graphics processing Unit) multiprocessor system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711281085.5ACN108121433B (en) | 2017-12-06 | 2017-12-06 | Task scheduling method of GPU (graphics processing Unit) multiprocessor system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108121433A CN108121433A (en) | 2018-06-05 |
| CN108121433Btrue CN108121433B (en) | 2021-10-15 |
Family
ID=62229729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711281085.5AActiveCN108121433B (en) | 2017-12-06 | 2017-12-06 | Task scheduling method of GPU (graphics processing Unit) multiprocessor system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108121433B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108897416A (en)* | 2018-06-28 | 2018-11-27 | 郑州云海信息技术有限公司 | It is a kind of to control method, apparatus and computer readable storage medium electric under GPU |
| CN109992385B (en)* | 2019-03-19 | 2021-05-14 | 四川大学 | GPU internal energy consumption optimization method based on task balance scheduling |
| CN110716805A (en)* | 2019-09-27 | 2020-01-21 | 上海依图网络科技有限公司 | Task allocation method and device of graphic processor, electronic equipment and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281639A (en)* | 2008-05-30 | 2008-10-08 | 华硕电脑股份有限公司 | Method for controlling operation mode of graphics processor and graphics processor |
| CN101403982A (en)* | 2008-11-03 | 2009-04-08 | 华为技术有限公司 | Task distribution method, system and equipment for multi-core processor |
| WO2010137233A1 (en)* | 2009-05-28 | 2010-12-02 | パナソニック株式会社 | Power saving control device for multiprocessor system, and mobile terminal |
| CN102866921A (en)* | 2012-08-29 | 2013-01-09 | 惠州Tcl移动通信有限公司 | Method and system for regulating and controlling multi-core central processing unit (CPU) |
| CN104424156A (en)* | 2013-09-09 | 2015-03-18 | 中兴通讯股份有限公司 | Core processing method and device of processor and terminal |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101387952B (en)* | 2008-09-24 | 2011-12-21 | 上海大学 | Single-chip multi-processor task scheduling and managing method |
| US8695008B2 (en)* | 2011-04-05 | 2014-04-08 | Qualcomm Incorporated | Method and system for dynamically controlling power to multiple cores in a multicore processor of a portable computing device |
| KR102110812B1 (en)* | 2013-05-30 | 2020-05-14 | 삼성전자 주식회사 | Multicore system and job scheduling method thereof |
- 2017
- 2017-12-06CNCN201711281085.5Apatent/CN108121433B/enactiveActive
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281639A (en)* | 2008-05-30 | 2008-10-08 | 华硕电脑股份有限公司 | Method for controlling operation mode of graphics processor and graphics processor |
| CN101403982A (en)* | 2008-11-03 | 2009-04-08 | 华为技术有限公司 | Task distribution method, system and equipment for multi-core processor |
| WO2010137233A1 (en)* | 2009-05-28 | 2010-12-02 | パナソニック株式会社 | Power saving control device for multiprocessor system, and mobile terminal |
| CN102866921A (en)* | 2012-08-29 | 2013-01-09 | 惠州Tcl移动通信有限公司 | Method and system for regulating and controlling multi-core central processing unit (CPU) |
| CN104424156A (en)* | 2013-09-09 | 2015-03-18 | 中兴通讯股份有限公司 | Core processing method and device of processor and terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108121433A (en) | 2018-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108121433B (en) | Task scheduling method of GPU (graphics processing Unit) multiprocessor system | |
| US11792264B2 (en) | Multiple sensor data processor interface and relay | |
| EP2580657B1 (en) | Information processing device and method | |
| EP2360548A2 (en) | Method and device for clock gate controlling | |
| US9250690B2 (en) | Low-power modes of microcontroller operation with access to configurable input/output connectors | |
| EP4086776A1 (en) | Syncronization of interrupt processing to reduce power consumption | |
| KR20120096858A (en) | Remote wakeup of application processor of mobile device | |
| US9519338B2 (en) | Task processing apparatus and method including scheduling current and next-level task processing apparatus | |
| EP2746957B1 (en) | Intelligent interrupt distributor | |
| KR20110126407A (en) | System-on-Chip and How It Works | |
| CN105022469B (en) | Portable electronic device and kernel exchange method thereof | |
| US11552892B2 (en) | Dynamic control of latency tolerance reporting values | |
| US20150227187A1 (en) | Data storage device, method thereof, and data processing system including the same | |
| US9841804B2 (en) | Clocking a processor | |
| CN204066009U (en) | A kind of system of fingerprints reducing power consumption and complicacy | |
| CN104516477A (en) | Techniques for entering a low power state | |
| CN106063304B (en) | System and method for message-based fine-grained system-on-chip power gating | |
| US11399344B2 (en) | System and method for SoC idle power state control based on I/O operation characterization | |
| CN105468549A (en) | Chip device and electronic system thereof | |
| CN120122799A (en) | A method and system for realizing low power consumption of PCIe encryption card based on ASPM | |
| CN105468128A (en) | Management method and management device for internal power consumption of SOC (System on Chip) | |
| EP3019952A1 (en) | Method and apparatus for controlling an operating mode of a processing module | |
| CN103455367B (en) | Management unit and method for implementing multi-task scheduling in reconfigurable systems | |
| US10082858B2 (en) | Peripheral device assistance in reducing CPU power consumption | |
| US8954622B1 (en) | Embedded programmable logic for logic stacking on application processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |