CN108008301B - Multi-section battery core protection board disconnection detection circuit - Google Patents

Abstract

The invention discloses a circuit for detecting disconnection of a multi-section battery cell protection board.A narrow pulse signal generating circuit B provides a periodic narrow pulse signal, so that a battery disconnection detecting circuit A detects the disconnection of each battery except the highest battery when the falling edge of the battery disconnection detecting circuit A arrives, and the power consumption of the circuit is effectively reduced; the battery detection circuit can respectively detect the disconnection of each battery except the highest battery, can accurately distinguish the overvoltage or disconnection of the battery, and makes corresponding protection measures, thereby improving the safety and reliability of the lithium battery; the battery detection circuit detects the state of the j-th battery VC_jA source electrode of a high-voltage PMOS tube is connected to make the grid voltage of the PMOS tube be the (j + 1) th battery voltage VC_j+1When the jth battery is disconnected, VC_jIs firstly controlled by the highest battery voltage VC_nDrawing high; when VC is carried out_jRatio (VC)_j+1+V_GS) High voltage PMOS tube is conducted, and VC is pulled down at the moment_jVoltage of so that VC_jThe voltage of the capacitor is not pulled too high, and the problem that the voltage withstanding value of devices in the circuit is not enough is solved.

Description

Multi-section battery core protection board disconnection detection circuit

Technical Field

The invention belongs to the technical field of battery protection, and particularly relates to a circuit for detecting disconnection of a multi-section battery core protection board.

Background

With the development of the related technology of batteries, more and more lithium batteries are applied in various fields, and various abnormal state detection and protection measures of the lithium batteries also become a focus problem concerned by people.

Disclosure of Invention

The invention aims to overcome the defects and provides a circuit for detecting the disconnection of a multi-section battery cell protection plate, which detects the disconnection state through a periodic narrow pulse signal on the premise of not influencing normal charge and discharge and other protection functions, effectively reduces the power consumption of the circuit and solves the defects in the prior art; secondly, the grid and the source of one high-voltage PMOS tube are respectively connected with the positive voltage of two adjacent batteries, and the problem of the withstand voltage value of the device is solved; and the overvoltage or disconnection abnormal state of each battery in the battery pack can be effectively distinguished, and corresponding protective measures are provided, so that the disconnection condition of the battery can be detected in a full range.

In order to achieve the purpose, the invention adopts the technical scheme that the circuit for detecting the disconnection of the multi-section battery CELL protection board comprises a battery disconnection detecting circuit A, a narrow pulse generating circuit B and a plurality of series-connected batteries CELL₁～CELL_nIn the CELL_iThe positive electrode is connected with a corresponding resistor R_iAnd a capacitor C_iCELL of battery_iPositive electrode and resistor R_iOne end connected to a resistor R_iThe other end and a capacitor C_iOne end connected to a capacitor C_iThe other end is grounded, and the battery voltage VC obtained through an RC filter circuit_iI is more than or equal to 1 and less than or equal to n; voltage VC of battery_jAnd a high voltage PMOS transistor M_cjSource electrode of (1) connected, high voltage PMOS transistor M_cjThe grid is controlled by the voltage VC of the last battery_j+1Control, high voltage PMOS transistor M_cjDrain electrode of (1) and DC current source I_bjInput terminals connected to a DC current source I_bjThe output end is grounded, j is more than or equal to 1 and less than or equal to n-1;

highest CELL CELL_nAre sequentially connected with the positive electrodeA diode D and a resistor R are connected to generate a voltage V_DDHVRespectively connected with a DC current source I_a1～I_a(n-1)Is connected to a DC current source I_ajIs passed through a switch SW_jCorresponding high-voltage PMOS tube M_cjIs connected to a source electrode of a switch SW_jThe XCLK signal generated by the narrow pulse generating circuit B passes through the level converting module A₃Generated narrow pulse signal XCLK_HVControlling j to be more than or equal to 1 and less than or equal to n-1;

high-voltage PMOS (P-channel Metal oxide semiconductor) tube M_cjIs connected to the logic OR gate A_a0J is more than or equal to 1 and is less than or equal to n-1, and a logic OR gate A_a0And D flip-flop A_a1Is connected to the input terminal D of a flip-flop A_a1Is controlled by a narrow pulse signal XCLK generated by a narrow pulse generating circuit B, and a flip-flop A_a1Output signal V of output terminal Q_BLDRespectively connected to one input terminal of the logic ORgate 101 and the logic ORgate 102, and the other input terminal of the logic ORgate 101 is connected with V_UVPThe other input terminal of the logic ORgate 102 is connected with V_OVPThe output end of the logic orgate 101 outputs a signal V through thelevel shift unit 103 and theinverter 104_DHCControlling NMOS transistor NM₂The output terminal of the logic orgate 102 outputs a signal V through thelevel shift unit 105 and theinverter 106_CHCControlling NMOS transistor NM₁。

The battery disconnection detection circuit A comprises a high-voltage PMOS tube M_a0～M_a(n-1)Voltage V of_DDHVAnd a high voltage PMOS transistor M_a0～M_a(n-1)Is connected with a source electrode of the high-voltage PMOS transistor M_a0And a high voltage PMOS transistor M_a1～M_a(n-1)Respectively form a current mirror and a high-voltage PMOS tube M_a0Being the source of a current mirror, a direct current source I_A1Is connected to a high-voltage PMOS tube M_a0The drain electrode of the PMOS transistor provides mirror current for the high-voltage PMOS transistor M_a0Drain electrode of (1) and DC current source I_A1Is connected to a DC current source I_A1The output end of the transformer is grounded;

wherein, the high voltage PMOS transistor M_a0And a high voltage PMOS transistor M_ajThe current mirror is used as a DC current source I_ajHigh voltage PMOS transistor M_bjAs a switch SW_jHigh voltage PMOS transistor M_bjSource electrode and high voltage PMOS transistor M_ajIs connected to the drain of the transistor, a narrow pulse signal XCLK_HVControl high-voltage PMOS tube M_bjGrid of (1), high voltage PMOS transistor M_bjThe drain electrode of the PMOS tube M is connected with a high-voltage PMOS tube M_cjSource electrode of (1), high voltage PMOS tube M_cjAnd the drain of (A) is connected with the logic OR gate (A)_a0A high-voltage NMOS tube M is also arranged between the input ends_ejNMOS transistor M_fjAnd an inverter A_jHigh voltage PMOS transistor M_cjThe drain electrode of the NMOS transistor is connected with a high-voltage NMOS transistor M_ejDrain electrode of (1), high voltage NMOS tube M_ejIs connected to a reference voltage V_REGAHigh voltage NMOS transistor M_ejIs connected to the NMOS transistor M_fjGrid and NMOS tube M_gjDrain electrode of (1), NMOS tube M_gjIs grounded, the NMOS tube M_fjIs connected to the PMOS transistor M_djDrain electrode of (1) and inverter A_jInput terminal of (D), PMOS tube M_d0And PMOS transistor M_djForm a current mirror, and a PMOS transistor M_d0And PMOS transistor M_djAre all connected to a reference voltage V_REGAPMOS transistor M_d0Is connected to the NMOS transistor M_h0Drain electrode of (1), NMOS tube M_h0The source of (2) is grounded; NMOS tube M_g0And NMOS tube M_h0And NMOS transistor M_gjForm a current mirror, wherein the NMOS transistor M_g0And NMOS tube M_gjForm a current mirror as a DC current source I_bj(ii) a Reference voltage V_REGAIs connected to a current source I_A2Of the input terminal of, a current source I_A2Is connected to the NMOS transistor M_g0Drain and gate of (1) and NMOS transistor M_gjGrid of (1), NMOS tube M_g0The source of (2) is grounded;

inverter A_jIs passed through a logic or gate a_a0Output is transmitted to D flip-flop A_a1The narrow pulse signal XCLK passes through the inverter A_a4And a delay circuit A_a2To D flip-flop A_a1Clock input terminal CLK, D flip-flop A_a1Output terminal Q of the signal is V_BLDWherein j is more than or equal to 1 and less than or equal to n-1.

The narrow pulse generating circuit B is connected with m D triggersAnd then, the input ends D of all the D flip-flops are connected to the output end XQ of the current D flip-flop, the input ends D of the previous m-1 stage D flip-flops are connected to the clock input end CLK of the next stage D flip-flop, wherein the first stage D flip-flop B₁Clock input terminal CLK is connected with a square wave signal CLK generated by an internal oscillation circuit₁Controlling; d flip-flop B₁The clock input signal terminal CLK and the output terminals Q of all D flip-flops are connected to the input terminal of the logic nand gate, and the output of the logic nand gate is the clock signal XCLK.

The circuit A for detecting the disconnection of the battery comprises a resistor R_a1～R_a(n-1)Voltage V of_DDHVAnd a resistor R_ajIs connected to one end of a resistor R_ajThe other end of the transistor (D) is connected with a high-voltage PMOS (P-channel metal oxide semiconductor) tube M_ajSource connection of (3), resistor R_ajAs a direct current source I_ajHigh voltage PMOS transistor M_ajGate connection control signal XCLK_HVHigh voltage PMOS transistor M_ajThe drain electrode of the PMOS tube M is connected with a high-voltage PMOS tube M_cjSource electrode of (1), high voltage PMOS tube M_cjAnd the drain of (A) is connected with the logic OR gate (A)_a0A high-voltage NMOS tube M is also arranged between the input ends_ejNMOS transistor M_fjAnd an inverter A_jHigh voltage PMOS transistor M_cjThe drain electrode of the NMOS transistor is connected with a high-voltage NMOS transistor M_ejDrain electrode of (1), high voltage NMOS tube M_ejIs connected to a reference voltage V_REGAHigh voltage NMOS transistor M_ejSource electrode of (1) through resistor R_bjGround, resistance R_bjAs a direct current source I_bjAnd a high voltage NMOS transistor M_ejIs connected to the NMOS transistor M_fjGrid of (1), NMOS tube M_fjIs connected to the PMOS transistor M_djDrain electrode of (1) and inverter A_jInput terminal of (D), PMOS tube M_d0And PMOS transistor M_djForm a current mirror, and a PMOS transistor M_d0And PMOS transistor M_djAre all connected to a reference voltage V_REGAPMOS transistor M_d0The drain electrode of the direct current source I is connected to the input end of the direct current source I, and the output end of the direct current source I is grounded;

inverter A_jIs passed through a logic or gate a_a0Output is transmitted to D flip-flop A_a1The narrow pulse signal XCLK is invertedPhoto device A_a4And a delay circuit A_a2To D flip-flop A_a1Clock input terminal CLK, D flip-flop A_a1Output terminal Q of the signal is V_BLDWherein j is more than or equal to 1 and less than or equal to n-1.

The working principle of the invention is as follows: when the battery is broken, the battery is detected and protected, and the highest battery CELL is removed from the battery broken line detection circuit_nEvery outer battery detects whether the battery is disconnected or not, because if the highest battery CELL is connected_nWhen the wire is broken, the normal power supply voltage V can not be provided for the chip_DDHVThe chip will not work normally; highest CELL CELL_nThe anode of the diode is connected with a diode D and a resistor R in sequence to generate a voltage V_DDHVRespectively connected with a DC current source I_a1～I_a(n-1)Is connected to a DC current source I_ajIs passed through a switch SW_jCorresponding high-voltage PMOS tube M_cjIs connected to a source electrode of a switch SW_jThe XCLK signal generated by the narrow pulse generating circuit B passes through the level converting module A₃Generated narrow pulse signal XCLK_HVControlling j to be more than or equal to 1 and less than or equal to n-1;

in CELL of battery_iThe positive electrode is connected with a corresponding resistor R_iAnd a capacitor C_iCELL of battery_iPositive electrode and resistor R_iOne end connected to a resistor R_iThe other end and a capacitor C_iOne end connected to a capacitor C_iThe other end is grounded, and the battery voltage VC obtained through an RC filter circuit_iI is more than or equal to 1 and less than or equal to n; voltage VC of battery_jAnd a high voltage PMOS transistor M_cjSource electrode of (1) connected, high voltage PMOS transistor M_cjThe grid is controlled by the voltage VC of the last battery_j+1Control, high voltage PMOS transistor M_cjDrain electrode of (1) and DC current source I_bjInput terminals connected to a DC current source I_bjThe output end is grounded, j is more than or equal to 1 and less than or equal to n-1; i.e. maximum battery voltage VC_nThe wire breakage condition is not detected;

for example, when the second battery CELL₂When the line is broken, only the narrow pulse signal XCLK is generated_HVWhen the falling edge comes, the switch SW₂When closed, the second battery voltage VC₂Will be the highest battery voltageVC_nIs pulled high when VC is₂Is higher than the third cell voltage VC₃One V higher_GSHigh voltage PMOS transistor M₂On, voltage V₂Is high level and will VC₂The voltage is pulled down a little, so that VC can be realized₂The voltage of the capacitor is not pulled too high, and the problem that the voltage withstanding value of devices in the circuit is not enough is solved. V_MAt high level when the narrow pulse signal XCLK is asserted_HVWhen the falling edge comes, V is output through a D flip-flop_BLDAt a high level, V_UVPSignal indicating undervoltage of battery, V_OVPThe signals indicating the battery is over-voltage are all high level active. When the circuit is under-voltage, V_UVPAt high level, through a logic OR gate OR and a level conversion module, a discharge tube NM₂Closing; when the circuit is over-voltage, V_OVPAt high level, through a logic OR gate OR and a level conversion module, a charging tube NM₁Closing; when the battery is broken, V_BLDAt high level, through a logic OR gate OR and a level conversion module, a discharge tube NM₂And charging tube NM₁And the lithium batteries are all closed, so that the lithium batteries are protected.

Compared with the prior art, the invention has the following beneficial effects:

1. the circuit of the invention adopts a method for detecting whether the battery is disconnected or not by adopting a periodic narrow pulse signal, and only when the narrow pulse signal is XCLK_HVWhen the circuit comes, the broken line battery detection circuit works, and the power consumption of the circuit is effectively reduced.

2. The circuit of the invention adopts the line breakage detection to the multiple batteries respectively, can accurately judge the condition that the line breakage and the overvoltage abnormal state of the batteries occur simultaneously, detects whether the line breakage abnormality occurs to the batteries in the full range, and makes corresponding protective measures, thereby improving the safety, the reliability and the pressure resistance value of the lithium battery;

3. the circuit of the invention is used for converting the broken line battery voltage VC_iConnecting the source electrode of a PMOS tube to make the grid voltage of the PMOS tube be VC_i+1When the battery is disconnected, VC is enabled_iThe voltage can not be pulled up to be too high, and the problem that the voltage withstanding value of the device is not enough is solved.

Drawings

FIG. 1 is a block diagram of the present invention;

fig. 2 is a schematic diagram of a battery disconnection detecting circuit inembodiment 1 of the present invention;

FIG. 3 is a schematic diagram of a narrow pulse generation circuit of the present invention;

FIG. 4 is a schematic diagram of a narrow pulse generation waveform of the present invention;

fig. 5 is a schematic diagram of a battery disconnection detection circuit inembodiment 2 of the present invention.

In the drawings: a-a battery disconnection detection circuit and B-a narrow pulse generation circuit.

Detailed Description

The invention is further illustrated by the following examples and figures.

As shown in fig. 1, the circuit for detecting disconnection of a multi-section battery CELL protection board of the present invention includes a battery disconnection detecting circuit a, a narrow pulse generating circuit B, and a plurality of series-connected batteries CELL₁～CELL_nIn the CELL_iThe positive electrode is connected with a corresponding resistor R_iAnd a capacitor C_iCELL of battery_iPositive electrode and resistor R_iOne end connected to a resistor R_iThe other end and a capacitor C_iOne end connected to a capacitor C_iThe other end is grounded, and the battery voltage VC obtained through an RC filter circuit_iI is more than or equal to 1 and less than or equal to n; voltage VC of battery_jAnd a high voltage PMOS transistor M_cjSource electrode of (1) connected, high voltage PMOS transistor M_cjThe grid is controlled by the voltage VC of the last battery_j+1Control, high voltage PMOS transistor M_cjDrain electrode of (1) and DC current source I_bjInput terminals connected to a DC current source I_bjThe output end is grounded, j is more than or equal to 1 and less than or equal to n-1;

highest CELL CELL_nThe anode of the diode is connected with a diode D and a resistor R in sequence to generate a voltage V_DDHVRespectively connected with a DC current source I_a1～I_a(n-1)Is connected to a DC current source I_ajIs passed through a switch SW_jCorresponding high-voltage PMOS tube M_cjIs connected to a source electrode of a switch SW_jThe XCLK signal generated by the narrow pulse generating circuit B passes through the level converting module A₃Generated byNarrow pulse signal XCLK_HVControlling j to be more than or equal to 1 and less than or equal to n-1.

In example 1 of the present invention:

as shown in fig. 1 and 2, the battery disconnection detecting circuit a includes a high voltage PMOS transistor M_a0～M_a(n-1)Voltage V of_DDHVAnd a high voltage PMOS transistor M_a0～M_a(n-1)Is connected with a source electrode of the high-voltage PMOS transistor M_a0And a high voltage PMOS transistor M_a1～M_a(n-1)Respectively form a current mirror and a high-voltage PMOS tube M_a0Being the source of a current mirror, a direct current source I_A1Is connected to a high-voltage PMOS tube M_a0The drain electrode of the PMOS transistor provides mirror current for the high-voltage PMOS transistor M_a0Drain electrode of (1) and DC current source I_A1Is connected to a DC current source I_A1The output end of the transformer is grounded;

wherein, the high voltage PMOS transistor M_a0And a high voltage PMOS transistor M_ajThe current mirror is used as a DC current source I_ajHigh voltage PMOS transistor M_bjAs a switch SW_jHigh voltage PMOS transistor M_bjSource electrode and high voltage PMOS transistor M_ajIs connected to the drain of the transistor, a narrow pulse signal XCLK_HVControl high-voltage PMOS tube M_bjGrid of (1), high voltage PMOS transistor M_bjThe drain electrode of the PMOS tube M is connected with a high-voltage PMOS tube M_cjSource electrode of (1), high voltage PMOS tube M_cjAnd the drain of (A) is connected with the logic OR gate (A)_a0A high-voltage NMOS tube M is also arranged between the input ends_ejNMOS transistor M_fjAnd an inverter A_jHigh voltage PMOS transistor M_cjThe drain electrode of the NMOS transistor is connected with a high-voltage NMOS transistor M_ejDrain electrode of (1), high voltage NMOS tube M_ejIs connected to a reference voltage V_REGAHigh voltage NMOS transistor M_ejIs connected to the NMOS transistor M_fjGrid and NMOS tube M_gjDrain electrode of (1), NMOS tube M_gjIs grounded, the NMOS tube M_fjIs connected to the PMOS transistor M_djDrain electrode of (1) and inverter A_jInput terminal of (D), PMOS tube M_d0And PMOS transistor M_djForm a current mirror, and a PMOS transistor M_d0And PMOS transistor M_djAre all connected to a reference voltage V_REGAPMOS transistor M_d0Is connected to the NMOS transistor M_h0Drain electrode of (1), NMOS tube M_h0The source of (2) is grounded; NMOS tube M_g0And NMOS tube M_h0And NMOS transistor M_gjForm a current mirror, wherein the NMOS transistor M_g0And NMOS tube M_gjForm a current mirror as a DC current source I_bj(ii) a Reference voltage V_REGAIs connected to a current source I_A2Of the input terminal of, a current source I_A2Is connected to the NMOS transistor M_g0Drain and gate of (1) and NMOS transistor M_gjGrid of (1), NMOS tube M_g0The source electrode of (1) is grounded, wherein j is more than or equal to 1 and less than or equal to n-1;

inverter A_jIs passed through a logic or gate a_a0Output is transmitted to D flip-flop A_a1The narrow pulse signal XCLK passes through the inverter A_a4And a delay circuit A_a2Clock input terminal CLK of D flip-flop, output terminal Q of D flip-flop is V_BLDSignal, D flip-flop A_a1Output signal V of output terminal Q_BLDRespectively connected to one input terminal of the logic ORgate 101 and the logic ORgate 102, and the other input terminal of the logic ORgate 101 is connected with V_UVPThe other input terminal of the logic ORgate 102 is connected with V_OVPThe output end of the logic orgate 101 outputs a signal V through thelevel shift unit 103 and theinverter 104_DHCControlling NMOS transistor NM₂The output terminal of the logic orgate 102 outputs a signal V through thelevel shift unit 105 and theinverter 106_CHCControlling NMOS transistor NM₁。

Referring to FIG. 3, the narrow pulse generating circuit B is composed of a square wave signal CLK with a period of 1mS₁N frequency division is carried out by m D triggers to obtain a period of 2ⁿmS square wave signal, see the signal waveform diagram shown in FIG. 4, then the square wave signal is processed by combinational logic to generate a narrow pulse signal XCLK with 500uS clock, and the signal is processed by a level conversion module A_a3Narrow pulse signal XCLK converted to high voltage_HVIn XCLK_HVStarts to detect whether the battery is disconnected when the falling edge of the battery comes.

As shown in FIG. 3, the narrow pulse generating circuit B is connected by m D flip-flops B₁Is generated by an internal oscillating circuitSquare wave signal CLK of₁Controlling; d flip-flop B₁Is connected with a D flip-flop B₁One of the output terminals XQ and the next D flip-flop B of₂A clock input terminal CLK, D flip-flop B₁The clock input signal end CLK and an output end Q of other m-1D triggers pass through the input end of the logic AND gate, and the output of the logic AND gate is the clock signal XCLK. When the falling edge of the narrow pulse signal XCLK with the pulse width of 500uS occurs, the high-voltage PMOS transistor M in FIG. 2 is caused to occur_b1～M_b(n-1)And conducting. Voltage VC of battery_jAnd a high voltage PMOS transistor M_cjSource electrode of (1) connected, high voltage PMOS transistor M_cjGrid of the grid is the last battery voltage VC_j+1When the jth battery is disconnected, VC_jHigher than (VC)_j+1+V_GS) Make VC_jIs not controlled by the highest battery voltage VC_nPull up too high.

Inembodiment 2 of the present invention, the narrow pulse generating circuit B is the same as that inembodiment 1, and as shown in fig. 5, the battery disconnection detecting circuit a includes a resistor R_a1～R_a(n-1)Voltage V of_DDHVAnd a resistor R_ajIs connected to one end of a resistor R_ajThe other end of the transistor (D) is connected with a high-voltage PMOS (P-channel metal oxide semiconductor) tube M_ajSource connection of (3), resistor R_ajAs a direct current source I_ajHigh voltage PMOS transistor M_ajGate connection control signal XCLK_HVHigh voltage PMOS transistor M_ajThe drain electrode of the PMOS tube M is connected with a high-voltage PMOS tube M_cjSource electrode of (1), high voltage PMOS tube M_cjAnd the drain of (A) is connected with the logic OR gate (A)_a0A high-voltage NMOS tube M is also arranged between the input ends_ejNMOS transistor M_fjAnd an inverter A_jHigh voltage PMOS transistor M_cjThe drain electrode of the NMOS transistor is connected with a high-voltage NMOS transistor M_ejDrain electrode of (1), high voltage NMOS tube M_ejIs connected to a reference voltage V_REGAHigh voltage NMOS transistor M_ejSource electrode of (1) through resistor R_bjGround, resistance R_bjAs a direct current source I_bjAnd a high voltage NMOS transistor M_ejIs connected to the NMOS transistor M_fjGrid of (1), NMOS tube M_fjIs connected to the PMOS transistor M_djDrain electrode of (1) and inverter A_jIs inputtedTerminal PMOS transistor M_d0And PMOS transistor M_djForm a current mirror, and a PMOS transistor M_d0And PMOS transistor M_djAre all connected to a reference voltage V_REGAPMOS transistor M_d0The drain electrode of the direct current source I is connected to the input end of the direct current source I, and the output end of the direct current source I is grounded;

inverter A_jIs passed through a logic or gate a_a0Output is transmitted to D flip-flop A_a1The narrow pulse signal XCLK passes through the inverter A_a4And a delay circuit A_a2To D flip-flop A_a1Clock input terminal CLK, D flip-flop A_a1Output terminal Q of the signal is V_BLDWherein j is more than or equal to 1 and less than or equal to n-1.

As shown in FIG. 4, the narrow pulse generating circuit of the invention can effectively reduce the power consumption of the circuit, and the circuit is composed of a square wave signal CLK with a period of 1mS₁A period of 2 is obtained by dividing by nⁿThe mS square wave signal is processed by combinational logic to obtain a narrow pulse signal XCLK, which is a low voltage pulse varying between 0V and 5V, and the disconnection detection of the multiple batteries requires a higher pulse signal to open the switch tube, so that XCLK is converted into voltage V (V) by the level conversion module in FIG. 1_DDHV-5V) and V_DDHVPulse signal XCLK varying therebetween_HVIn which V is_DDHVThe power supply voltage provided by the highest battery for the chip; the signal waveform is shown in FIG. 4, and is applied to a narrow pulse signal XCLK_HVWhen the falling edge comes, the switch tube hit by the battery disconnection detection circuit is opened to detect whether the battery is disconnected, and the pulse width of the narrow pulse signal is only 500uS, and only when the narrow pulse signal is XCLK_HVThe battery disconnection detection circuit can only work when the falling edge arrives, so the narrow pulse generation circuit adopted by the invention can effectively reduce the power consumption of the circuit, for example, when the period of the narrow pulse signal is T, the input capacitance of each battery is C, the pull-up current is I, and the following components are obtained according to the charge conservation in the time T:

Q＝I×t＝C×V (1)

let C be 0.1uF, V be 5V, T be 500uS, and T be 32S, yielding:

Q＝I×t＝1mA×500μS＝5×10^-7C (5)

wherein P represents the power consumption of the battery disconnection detecting circuit in the unit cycle, and as can be seen from equation (6), the power consumption of the battery disconnection detecting circuit is small, and is 0.02 μ W.

The above are only two preferred embodiments of the present invention, and do not constitute any limitation to the present invention, and it is obvious that various changes and modifications can be made to the circuit thereof under the concept of the present invention, but these are all protected by the present invention.

Claims (3)

1. The circuit for detecting the disconnection of the multi-section battery CELL protection board is characterized by comprising a battery disconnection detection circuit A, a narrow pulse generation circuit B and a plurality of series-connected batteries CELL₁～CELL_nIn the CELL_iThe positive electrode is connected with a corresponding resistor R_iAnd a capacitor C_iCELL of battery_iPositive electrode and resistor R_iOne end connected to a resistor R_iThe other end and a capacitor C_iOne end connected to a capacitor C_iThe other end is grounded, and the battery voltage VC obtained through an RC filter circuit_iI is more than or equal to 1 and less than or equal to n; voltage VC of battery_jAnd a high voltage PMOS transistor M_cjSource electrode of (1) connected, high voltage PMOS transistor M_cjThe grid is controlled by the voltage VC of the last battery_j+1Control, high voltage PMOS transistor M_cjDrain electrode of (1) and DC current source I_bjInput terminals connected to a DC current source I_bjThe output end is grounded, j is more than or equal to 1 and less than or equal to n-1;

highest CELL CELL_nThe anode of the diode is connected with a diode D and a resistor R in sequence to generate a voltage V_DDHVRespectively connected with a DC current source I_a1～I_a(n-1)Is connected to a DC current source I_ajIs passed through a switch SW_jCorresponding high-voltage PMOS tube M_cjIs connected to a source electrode of a switch SW_jThe XCLK signal generated by the narrow pulse generating circuit B passes through the level converting module A₃Generated narrow pulse signal XCLK_HVControlling j to be more than or equal to 1 and less than or equal to n-1;

high-voltage PMOS (P-channel Metal oxide semiconductor) tube M_cjIs connected to the logic OR gate A_a0J is more than or equal to 1 and is less than or equal to n-1, and a logic OR gate A_a0And D flip-flop A_a1Is connected to the input terminal D of a flip-flop A_a1Is controlled by a narrow pulse signal XCLK generated by a narrow pulse generating circuit B, and a flip-flop A_a1Output signal V of output terminal Q_BLDAre respectively connected to one input ends of a first logic OR gate (101) and a second logic OR gate (102), and the other input end of the first logic OR gate (101) is connected with V_UVP，V_UVPA signal indicating the undervoltage of the battery, and the other input end of the second logic OR gate (102) is connected with V_OVP，V_OVPThe output end of the first logic OR gate (101) outputs a signal V through a first level conversion unit (103) and a first inverter (104) according to a signal representing the overvoltage of the battery_DHCControlling NMOS transistor NM₂The output end of the second logic or gate (102) outputs a signal V through a second level conversion unit (105) and a second inverter (106)_CHCControlling NMOS transistor NM₁；

The battery disconnection detection circuit A comprises a high-voltage PMOS tube M_a0～M_a(n-1)Voltage V of_DDHVAnd a high voltage PMOS transistor M_a0～M_a(n-1)Is connected with a source electrode of the high-voltage PMOS transistor M_a0And a high voltage PMOS transistor M_a1～M_a(n-1)Respectively form a current mirror and a high-voltage PMOS tube M_a0Being the source of a current mirror, a direct current source I_A1Is connected to a high-voltage PMOS tube M_a0The drain electrode of the PMOS transistor provides mirror current for the high-voltage PMOS transistor M_a0Drain electrode of (1) and DC current source I_A1Is connected to a DC current source I_A1The output end of the transformer is grounded;

wherein, the high voltage PMOS transistor M_a0And a high voltage PMOS transistor M_ajThe current mirror is used as a DC current source I_ajHigh voltage PMOS transistor M_bjAs a switch SW_jHigh voltage PMOS transistor M_bjSource electrode and high voltage PMOS transistor M_ajIs connected to the drain of the transistor, a narrow pulse signal XCLK_HVControl high-voltage PMOS tube M_bjGrid of (1), high voltage PMOS transistor M_bjThe drain electrode of the PMOS tube M is connected with a high-voltage PMOS tube M_cjSource electrode of (1), high voltage PMOS tube M_cjAnd the drain of (A) is connected with the logic OR gate (A)_a0A high-voltage NMOS tube M is also arranged between the input ends_ejNMOS transistor M_fjAnd an inverter A_jHigh voltage PMOS transistor M_cjThe drain electrode of the NMOS transistor is connected with a high-voltage NMOS transistor M_ejDrain electrode of (1), high voltage NMOS tube M_ejIs connected to a reference voltage V_REGAHigh voltage NMOS transistor M_ejIs connected to the NMOS transistor M_fjGrid and NMOS tube M_gjDrain electrode of (1), NMOS tube M_gjIs grounded, the NMOS tube M_fjIs connected to the PMOS transistor M_djDrain electrode of (1) and inverter A_jInput terminal of (D), PMOS tube M_d0And PMOS transistor M_djForm a current mirror, and a PMOS transistor M_d0And PMOS transistor M_djAre all connected to a reference voltage V_REGAPMOS transistor M_d0Is connected to the NMOS transistor M_h0Drain electrode of (1), NMOS tube M_h0The source of (2) is grounded; NMOS tube M_g0And NMOS tube M_h0And NMOS transistor M_gjForm a current mirror, wherein the NMOS transistor M_g0And NMOS tube M_gjForm a current mirror as a DC current source I_bj(ii) a Reference voltage V_REGAIs connected to a current source I_A2Of the input terminal of, a current source I_A2Is connected to the NMOS transistor M_g0Drain and gate of (1) and NMOS transistor M_gjGrid of (1), NMOS tube M_g0The source of (2) is grounded;

inverter A_jIs passed through a logic or gate a_a0Output is transmitted to D flip-flop A_a1The narrow pulse signal XCLK passes through the inverter A_a4And time delayRoad A_a2To D flip-flop A_a1Clock input terminal CLK, D flip-flop A_a1Output terminal Q of the signal is V_BLDWherein j is more than or equal to 1 and less than or equal to n-1.

2. The circuit for detecting the disconnection of the multi-section battery CELL protection board is characterized by comprising a battery disconnection detection circuit A, a narrow pulse generation circuit B and a plurality of series-connected batteries CELL₁～CELL_nIn the CELL_iThe positive electrode is connected with a corresponding resistor R_iAnd a capacitor C_iCELL of battery_iPositive electrode and resistor R_iOne end connected to a resistor R_iThe other end and a capacitor C_iOne end connected to a capacitor C_iThe other end is grounded, and the battery voltage VC obtained through an RC filter circuit_iI is more than or equal to 1 and less than or equal to n; voltage VC of battery_jAnd a high voltage PMOS transistor M_cjSource electrode of (1) connected, high voltage PMOS transistor M_cjThe grid is controlled by the voltage VC of the last battery_j+1Control, high voltage PMOS transistor M_cjDrain electrode of (1) and DC current source I_bjInput terminals connected to a DC current source I_bjThe output end is grounded, j is more than or equal to 1 and less than or equal to n-1;

highest CELL CELL_nThe anode of the diode is connected with a diode D and a resistor R in sequence to generate a voltage V_DDHVRespectively connected with a DC current source I_a1～I_a(n-1)Is connected to a DC current source I_ajIs passed through a switch SW_jCorresponding high-voltage PMOS tube M_cjIs connected to a source electrode of a switch SW_jThe XCLK signal generated by the narrow pulse generating circuit B passes through the level converting module A₃Generated narrow pulse signal XCLK_HVControlling j to be more than or equal to 1 and less than or equal to n-1;

high-voltage PMOS (P-channel Metal oxide semiconductor) tube M_cjIs connected to the logic OR gate A_a0J is more than or equal to 1 and is less than or equal to n-1, and a logic OR gate A_a0And D flip-flop A_a1Is connected to the input terminal D of a flip-flop A_a1Is controlled by a narrow pulse signal XCLK generated by a narrow pulse generating circuit B, and a flip-flop A_a1Output signal V of output terminal Q_BLDOne input connected to the first logic OR gate (101) and the second logic OR gate (102), respectivelyAn input end, and the other input end of the first logic OR gate (101) is connected with V_UVP，V_UVPA signal indicating the undervoltage of the battery, and the other input end of the second logic OR gate (102) is connected with V_OVP，V_OVPThe output end of the first logic OR gate (101) outputs a signal V through a first level conversion unit (103) and a first inverter (104) according to a signal representing the overvoltage of the battery_DHCControlling NMOS transistor NM₂The output end of the second logic or gate (102) outputs a signal V through a second level conversion unit (105) and a second inverter (106)_CHCControlling NMOS transistor NM₁；

The circuit A for detecting the disconnection of the battery comprises a resistor R_a1～R_a(n-1)Voltage V of_DDHVAnd a resistor R_ajIs connected to one end of a resistor R_ajThe other end of the transistor (D) is connected with a high-voltage PMOS (P-channel metal oxide semiconductor) tube M_ajSource connection of (3), resistor R_ajAs a direct current source I_ajHigh voltage PMOS transistor M_ajGate connection control signal XCLK_HVHigh voltage PMOS transistor M_ajThe drain electrode of the PMOS tube M is connected with a high-voltage PMOS tube M_cjSource electrode of (1), high voltage PMOS tube M_cjAnd the drain of (A) is connected with the logic OR gate (A)_a0A high-voltage NMOS tube M is also arranged between the input ends_ejNMOS transistor M_fjAnd an inverter A_jHigh voltage PMOS transistor M_cjThe drain electrode of the NMOS transistor is connected with a high-voltage NMOS transistor M_ejDrain electrode of (1), high voltage NMOS tube M_ejIs connected to a reference voltage V_REGAHigh voltage NMOS transistor M_ejSource electrode of (1) through resistor R_bjGround, resistance R_bjAs a direct current source I_bjAnd a high voltage NMOS transistor M_ejIs connected to the NMOS transistor M_fjGrid of (1), NMOS tube M_fjIs connected to the PMOS transistor M_djDrain electrode of (1) and inverter A_jInput terminal of (D), PMOS tube M_d0And PMOS transistor M_djForm a current mirror, and a PMOS transistor M_d0And PMOS transistor M_djAre all connected to a reference voltage V_REGAPMOS transistor M_d0The drain electrode of the direct current source I is connected to the input end of the direct current source I, and the output end of the direct current source I is grounded;

inverter A_jIs passed through a logic or gate a_a0Output transferTo D flip-flop A_a1The narrow pulse signal XCLK passes through the inverter A_a4And a delay circuit A_a2To D flip-flop A_a1Clock input terminal CLK, D flip-flop A_a1Output terminal Q of the signal is V_BLDWherein j is more than or equal to 1 and less than or equal to n-1.

3. The circuit for detecting disconnection of a plurality of sections of battery cell protection boards according to claim 1 or 2, wherein the narrow pulse generation circuit B is connected by m D flip-flops, input terminals D of all D flip-flops are connected to an output terminal XQ of a current D flip-flop, and input terminals D of previous m-1 stage D flip-flops are connected to a clock input terminal CLK of a next stage D flip-flop, wherein a first stage D flip-flop B is connected to a clock input terminal CLK of a next stage D flip-flop₁Clock input terminal CLK is connected with a square wave signal CLK generated by an internal oscillation circuit₁Controlling; d flip-flop B₁The clock input signal terminal CLK and the output terminals Q of all D flip-flops are connected to the input terminal of the logic nand gate, and the output of the logic nand gate is the clock signal XCLK.

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