CN107993619B

Movatterモバイル変換

Info

Publication number: CN107993619B
Application number: CN201711079448.7A
Authority: CN
Inventors: 翟应腾; 王丽花; 杨康
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2017-11-06
Filing date: 2017-11-06
Publication date: 2020-08-25
Anticipated expiration: 2037-11-06
Also published as: CN107993619A

Abstract

The invention discloses a scanning circuit and a display panel, wherein the scanning circuit comprises: a plurality of scan circuit units including a plurality of first scan circuit units and a plurality of second scan circuit units; a plurality of multiplexing circuit units; a plurality of first scanning circuit units are sequentially cascaded; the multiplexing circuit unit and the second scanning circuit unit are sequentially and alternately arranged, the control signal input end is used for controlling the conduction of the selection signal output end and the third input end when the shift signal output end of the N-1 st-stage first scanning circuit unit outputs an effective signal, the control selection signal output end is conducted with the first input end when the output of the effective signal from the shift signal output end of the N-1 st-stage first scanning circuit unit is finished, and N is an integer greater than or equal to 2. The invention can solve the problems of scanning circuit scanning time waste and power consumption.

Description

Scanning circuit and display panel

Technical Field

The present invention relates to the field of display technologies, and in particular, to a scan circuit and a display panel.

Background

Fingerprints are unique to each individual. With the development of science and technology, a variety of display devices with fingerprint identification functions appear in the market, such as mobile phones, tablet computers, intelligent wearable devices and the like. Like this, the user just needs to touch display device's fingerprint identification module with the finger before the display device that the operation has the fingerprint identification function, just can carry out the authority and verify, has simplified the authority verification process. In the existing display device with fingerprint identification function, the fingerprint identification module generally detects through the light that the touch main part (for example finger) shines to the fingerprint identification unit, promptly through the ridge and the valley of light detection fingerprint are in order to accomplish the discernment action.

Among the prior art, for the attenuate display device's that has the fingerprint identification function thickness, with the fingerprint identification module integration in display panel, form an integrated light sense display panel, it is concrete, carry out the fingerprint detection at the integrated light sense detector of integrated light sense display panel's display area, set up scanning circuit in integrated light sense display panel's frame district and scan the drive to the light sense detector. Therefore, in the frame area of the integrated light-sensing display panel, two rows of independent scanning circuits are included to respectively scan and drive the display pixels and the light-sensing detectors.

For the integrated photosensitive display panel, the inventor researches and discovers that the scanning circuit for scanning and driving the photosensitive detector is scanned on the whole surface, and the fingerprint pressing area is only present in a local area, so that the whole surface scanning wastes a large amount of scanning time and scanning power consumption.

In essence, the same problem arises with the scanning circuit that requires only partial scanning, as with the scanning circuit that provides full-area scanning.

Therefore, it is an urgent need in the art to provide a scan circuit and a display panel to avoid wasting scan time and scan power consumption of the scan circuit.

Disclosure of Invention

In view of this, the present invention provides a scan circuit and a display panel, which solve the technical problem in the prior art that scan time and scan power consumption are wasted for a scan circuit that only needs local scan.

In order to solve the above technical problem, the present invention further provides a display panel, where the display panel includes any one of the scan circuits provided in the present invention.

Compared with the prior art, the scanning circuit and the display panel of the invention have the following beneficial effects: the second scanning circuit unit of the scanning circuit can realize area scanning, and the second scanning circuit unit does not need whole-area scanning under the condition that only area scanning is needed, so that the scanning time can be saved, and the scanning power consumption can be reduced.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic diagram of a scan circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another scan circuit according to an embodiment of the present invention;

FIG. 3 is a timing diagram of a multiplexing circuit unit in the scan circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a multiplexing circuit unit in the scan circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an internal connection circuit of the multiplexing circuit unit in the scan circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of an internal connection circuit of a scan circuit unit in the scan circuit according to an embodiment of the present invention;

FIG. 7 is a timing diagram of a scan circuit unit in the scan circuit according to an embodiment of the present invention;

fig. 8, 9, 10 and 11 are top views of display panels provided by embodiments of the present invention;

fig. 12 is a schematic diagram of an internal connection circuit of a fingerprint touch detection unit in a display panel according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of another scan circuit provided in an embodiment of the present invention;

fig. 14 is a timing diagram of a display panel according to an embodiment of the invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

An embodiment of the present invention provides a scan circuit including a plurality of scan circuit units and a plurality of multiplexer circuit units. The multiplexing circuit unit comprises a first input end, a third input end, a control signal input end and a selection signal output end. The scanning circuit units of the scanning circuit comprise two types, one type is a first scanning circuit unit, the other type is a second scanning circuit unit, and the two types of scanning circuit units respectively comprise a shifting signal input end, a shifting signal output end and a clock signal input end.

The scanning circuit composed of all the first scanning circuit units can realize progressive sequential scanning, and complete one-time whole-area scanning in each scanning period.

The multiplexing circuit units and the second scanning circuit units are sequentially and alternately arranged, a selection signal output end of the Y-level multiplexing circuit unit is connected with a shift signal input end of the Y-level second scanning circuit unit, a first input end of the 1 st-level multiplexing circuit unit continuously receives an invalid signal, a third input end of the 1 st-level multiplexing circuit unit receives a shift starting signal, from the 2 nd-level multiplexing circuit unit to the last-level multiplexing circuit unit, a first input end of the X-level multiplexing circuit unit is connected with a shift signal output end of the X-1 st-level second scanning circuit unit, a third input end of the X-level multiplexing circuit unit is connected with a shift signal output end of the X-1 st-level first scanning circuit unit, Y is an integer greater than or equal to 1, and X is an integer greater than or equal to 2.

That is, for each second scan circuit unit, the adjacent second scan circuit units are no longer connected in a cascade manner, but are coupled with the first scan circuit unit through the multiplexing circuit unit. The shift signal input end of each second scanning circuit unit is respectively connected with the second scanning circuit unit and the first scanning circuit unit of the previous stage through a multiplexing circuit unit, and the scanning interval of the second scanning circuit unit can be accurately controlled through controlling the multiplexing circuit unit.

For the multiplexing circuit unit, the control signal input end is used for controlling the conduction of the selection signal output end and the third input end when the shift signal output end of the N-1 st-stage first scanning circuit unit outputs an effective signal, at the moment, the Nth-stage second scanning circuit unit receives the effective signal output by the shift signal output end of the N-1 st-stage first scanning circuit unit, and the effective signal is equivalent to the shift starting signal received by the Nth-stage second scanning circuit unit; and then, when the shift signal output end of the (N-1) th-stage first scanning circuit unit outputs an effective signal, controlling the connection of the selection signal output end and the first input end, and at the moment, the shift signal output ends of the (N + 1) th-stage and the following second scanning circuit units all receive the effective signal output by the shift signal output end of the previous second scanning circuit unit, so as to realize the region scanning from the Nth-stage second scanning circuit unit, wherein N is an integer greater than or equal to 2.

The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

Fig. 1 is a schematic diagram of a scan circuit according to an embodiment of the present invention. Referring appropriately to fig. 1, in this embodiment, the scanning circuit includes a plurality of scanning circuit units and a plurality ofmultiplexing circuit units 30. Wherein the plurality of scan circuit units include a plurality of firstscan circuit units 10 and a plurality of secondscan circuit units 20.

The plurality of firstscan circuit units 10 are sequentially the 1 st stage firstscan circuit unit 10, the 2 nd stage firstscan circuit unit 10, the 3 rd stage firstscan circuit unit 10 … … to the last stage firstscan circuit unit 10, and each firstscan circuit unit 10 outputs a first scan signal.

The plurality of secondscan circuit units 20 are sequentially the 1 st stage secondscan circuit unit 20, the 2 nd stage secondscan circuit unit 20, the 3 rd stage secondscan circuit unit 20 … … to the last stage secondscan circuit unit 20, and each secondscan circuit unit 20 outputs a second scan signal.

The plurality ofmultiplexing circuit units 30 are sequentially thestage 1multiplexing circuit unit 30, thestage 2multiplexing circuit unit 30, thestage 3multiplexing circuit unit 30 … … up to the last stagemultiplexing circuit unit 30.

Each of the firstscan circuit units 10 and each of the secondscan circuit units 20 includes a shift signal input terminal IN, a shift signal output terminal and a clock signal input terminal CL-IN, wherein the shift signal output terminal OUT1(1) of the firstscan circuit unit 10 of the 1 st stage, the shift signal output terminal OUT1(2) of the firstscan circuit unit 10 of the 2 nd stage, and the shift signal output terminal OUT1(3) … … of the firstscan circuit unit 10 of the 3 rd stage through the shift signal output terminal OUT1(T) of the firstscan circuit unit 10 of the last stage respectively output the first scan first signal S11, the first scan second signal S12, the first scan third signal S13 … … through the first scan first T signal S1T IN sequence, where T is the number of the firstscan circuit units 10. The second scan first signal S21, the second scan second signal S22, the second scan third signal S23 … …, and the second scan T 'signal S2T' are respectively and sequentially outputted from the shift signal output terminal OUT2(1) of the 1 st-stage secondscan circuit unit 20, the shift signal output terminal OUT2(2) of the 2 nd-stage secondscan circuit unit 20, the shift signal output terminal OUT2(3) … … of the 3 rd-stage secondscan circuit unit 20, and the shift signal output terminal OUT2(T ') of the last-stage secondscan circuit unit 20, where T' is the number of the secondscan circuit units 10.

Eachmultiplexing circuit unit 30 includes a first input terminal IN1, a third input terminal IN3, a control signal input terminal CO-IN, and a selection signal output terminal CH-OUT.

The plurality of firstscan circuit units 10 are sequentially cascaded, and specifically, the shift signal input terminal IN of the 1 st stage firstscan circuit unit 10 receives a shift start signal, and from the 2 nd stage firstscan circuit unit 10 to the last stage firstscan circuit unit 10, the shift signal input terminal IN of each stage firstscan circuit unit 10 is connected to the shift signal output terminal OUT1 of the first stage firstscan circuit unit 10, for example, the shift signal input terminal IN of the 3 rd stage firstscan circuit unit 10 is connected to the shift signal output terminal OUT1(2) of the 2 nd stage firstscan circuit unit 10.

The plurality of firstscanning circuit units 10 thus form a functional subsection of the scanning circuit, which can realize sequential scanning line by line, and in each scanning period, receive a shift start signal to complete a whole-area scanning.

Themultiplexer circuit units 30 and the secondscan circuit units 20 are alternately arranged IN sequence, the selection signal output terminal CH-OUT of the Y-th stagemultiplexer circuit unit 30 is connected to the shift signal input terminal IN of the Y-th stage secondscan circuit unit 30, Y is an integer greater than or equal to 1, that is, the selection signal output terminal CH-OUT of the 1-th stagemultiplexer circuit unit 30 is connected to the shift signal input terminal IN of the 1-th stage secondscan circuit unit 20, the selection signal output terminal CH-OUT of the 2-th stagemultiplexer circuit unit 30 is connected to the shift signal input terminal IN of the 2-th stage secondscan circuit unit 20, the selection signal output terminal CH-OUT of the 3-th stagemultiplexer circuit unit 30 is connected to the shift signal input terminal IN … … of the 3-th stage secondscan circuit unit 20, and so on.

With reference to the drawings and the above description, it can be seen that eachsecond scan cell 20 is connected to one firstscan circuit cell 10 via onemultiplexing circuit cell 30, and thus, in the scan circuit, the number of the secondscan circuit cells 20 is equal to the number of themultiplexing circuit cells 30 and is less than or equal to the number of the firstscan circuit cells 10.

Based on the above line connection structure, the purpose of controlling thesecond scanning unit 20 to realize local scanning can be achieved by controlling the signal of the control signal input terminal CO-IN themultiplexing circuit unit 30. Specifically, the control signal input terminals CO-IN of the multiplexing circuit units 30 receive the same signal, and the control signal input terminals CO-IN control the selection signal output terminals CH-OUT of the multiplexing circuit units 30 to be conductive with the third input terminals IN3 while the shift signal output terminals OUT of the first scan circuit units 10 of the N-1 th stage output valid signals, that is, the selection signal output terminals CH-OUT of the multiplexing circuit units 30 output the signals output from the shift signal output terminals of the first scan circuit units 10, while only the shift signal output terminals OUT1(N-1) of the first scan circuit units 10 of the N-1 th stage output valid signals, then only the selection signal output terminals CH-OUT of the multiplexing circuit units 30 of the N-1 th stage output valid signals, so that the shift signal input terminals IN of the second scan circuit units 20 of the N-1 th stage receive valid signals, the shift signal input terminal IN of the nth stage second scan circuit unit 20 receives the shift start signal, and the shift signal output terminal OUT2(N) of the nth stage second scan circuit unit 20 outputs the second scan nth signal, so as to implement the scan driving on the nth row.

Then, when the shift signal output terminal OUT of the N-1 th stage first scan circuit unit 10 outputs the valid signal, the selection signal output terminal CH-OUT of the nth stage multiplexing circuit unit 30 is controlled by the signal input terminal CO-IN to be conducted with the first input terminal IN1, that is, the selection signal output terminal CH-OUT of each multiplexing circuit unit 30 outputs the signal output from the shift signal output terminal of the second scan circuit unit 20, and the selection signal output terminal CH-OUT of each multiplexing circuit unit 30 is connected with the shift signal input terminal IN of the second scan circuit unit 20, that is, during the time when the selection signal output terminal CH-OUT is conducted with the first input terminal IN1, the cascade connection of the second scan circuit units 20 at each stage is substantially realized, so that after the shift start signal is shifted by the nth stage second scan circuit unit 20, the signal is input to the (N + 1) th-stage second scanning circuit unit 20, and then is input to the (N + 2) th-stage second scanning circuit unit 20 after being shifted by the (N + 1) th-stage second scanning circuit unit 20 until the control signal input terminal CO-IN controls the selection signal output terminal CH-OUT to be not conducted with the first input terminal IN1, so that the scanning driving from the nth row to the (N + M) th row, that is, the area scanning is realized.

Where N is an integer greater than or equal to 2, and the value of M is related to the length of time that the selection signal output terminal CH-OUT and the first input terminal IN1 are on, and the clock signal of the secondscan circuit unit 20. Taking the secondscanning circuit unit 20 to implement the scanning driving of the fingerprint touch detection unit as an example, when the scanning circuit is used for a display panel, the specific values of N and M may be controlled by the integrated circuit chip, for example, when the display panel displays different specific pictures, different fixed areas are taken as areas for receiving fingerprint touch, for example, when the display panel displays a first picture, the first fixed area is taken as an area for receiving fingerprint touch, and when the display panel displays a second picture, the second fixed area is taken as an area for receiving fingerprint touch, so that when the display panel displays the first picture, N, the time length for which the selection signal output terminal CH-OUT and the first input terminal IN1 are turned on are determined according to the position of the first fixed area corresponding to the first picture, thereby implementing the control of the scanning of thesecond scanning unit 20 on the fixed area. When the display panel displays different second pictures, the area scanned by the second scanning unit is changed into a second fixed area. For another example, a touch display device is simultaneously disposed on the display panel, and the integrated circuit chip can determine the area touched by the fingerprint, i.e., determine the values of N and M, through the touch display device.

In summary, according to the embodiment, compared to the prior art in which the second scanning circuit units are directly cascaded, the second scanning circuit unit in the present application can implement area scanning, and for the case that only area scanning is required, the second scanning circuit unit does not need to scan the whole area, so that the scanning time can be saved, and the scanning power consumption can be reduced.

Further, fig. 2 is a schematic diagram of another scan circuit provided by the embodiment of the present invention, and referring to fig. 2 as appropriate, IN an alternative embodiment, themultiplexing circuit unit 30 IN the scan circuit further includes a second input terminal IN2, the second input terminal IN2 continuously receives an inactive signal, and the control signal input terminal is further configured to control the selection signal output terminal CH-OUT to be conductive with the second input terminal IN2 when the selection signal output terminal CH-OUT is not conductive with the first input terminal IN1 and the third input terminal IN 3.

IN the time when the shift signal output terminal OUT1(N-1) of the N-1 th stage firstscan circuit unit 10 outputs the inactive signal and the selection signal output terminal CH-OUT is not conducted with the first input terminal IN1, the selection signal output terminal CH-OUT and the third input terminal IN3 are also not conducted, and by the arrangement of this embodiment, the selection signal output terminal CH-OUT is conducted with the second input terminal IN2 during this time, themultiplexer circuit 30 continuously outputs the inactive signal received by the second input terminal IN2 to the secondscan circuit unit 20, and the secondscan circuit unit 20 is kept not to be triggered by mistake during this time, so that the control of the area scan is more accurate.

Further, with continued reference to fig. 2, IN an alternative embodiment, the control signal inputs include a first control signal input CRT1, a second control signal input CRT2, and a third control signal input CRT3, wherein the selection signal output CH-OUT is conducted to the first input IN1 when the first control signal input CRT1 receives an active signal, the selection signal output CH-OUT is conducted to the second input IN2 when the second control signal input CRT2 receives an active signal, and the selection signal output CH-OUT is conducted to the third input IN3 when the third control signal input CRT3 receives an active signal.

For the scan circuit shown in fig. 2, fig. 3 is a timing diagram of the multiplexing circuit units in the scan circuit according to the embodiment of the present invention, in fig. 3, the second scan duration signal TP-ON is a signal input to the first control signal input terminal CRT1, the second scan OFF signal TP-OFF is a signal input to the second control signal input terminal CRT2, the second scan ON signal TP-STV is a signal input to the third control signal input terminal CRT3, and for the second scan ON signal TP-STV, in each scan period, an effective signal of the second scan ON signal TP-STV is synchronized with an effective signal output from the shift signal output terminal OUT1(N-1) of the N-1 th stage first scan circuit unit 10, that is, while an effective signal is output from the shift signal output terminal OUT1(N-1) of the N-1 th stage first scan circuit unit 10, the second scan start signal TP-STV is an active signal, and at this time, the selection signal output terminal CH-OUT (N) of the nth stage multiplexing circuit unit 30 also outputs an active signal, the shift signal input terminal IN of the nth stage second scan circuit unit 20 receives the active signal, and the shift signal output terminal OUT2(N) of the nth stage second scan circuit unit 20 outputs an active signal when the next clock signal arrives.

In this embodiment, the low-level signal is used as the active signal, but the present invention is not limited thereto, and the high-level signal may be used as the active signal, and specifically, whether the active signal is a low-level signal or a high-level signal may be related to a circuit element used in the circuit.

With continued reference to fig. 3, at the end of the valid signal of the third control signal input terminal CRT3, that is, at the end of the valid signal of the second scan enable signal TP-STV and the output signal of the output terminal OUT1(N-1), the first control signal input terminal CRT1 receives the second scan sustain signal TP-ON and starts to be a valid signal, at this time, the selection signal output terminals CH-OUT of themultiplexing circuit unit 30 are all turned ON with the first input terminals IN1 thereof, the signal output from the shift signal output terminal of each stage of the secondscan circuit unit 20 is transmitted to the shift signal input terminal IN of the next stage of the secondscan circuit unit 20, and during the time when the second scan sustain signal TP-ON continues to be a valid signal, from the shift signal output terminal OUT2(N) of the nth stage of the secondscan circuit unit 20 to the shift signal output terminal OUT2(N + M) of the nth + M stage of the second scan circuit unit, and sequentially outputting effective signals to realize scanning of the region from the Nth row to the (N + M) th row.

With continued reference to fig. 3, when the first control signal input terminal CRT1 and the third control signal input terminal CRT3 simultaneously receive the inactive signal, that is, the second scan start signal TP-STV and the second scan duration signal TP-ON are simultaneously inactive signals, the second scan OFF signal TP-OFF received by the second control signal input terminal CRT2 is an active signal, the selection signal output terminal CH-OUT is connected to the second input terminal IN2, and the second input terminal IN2 continuously receives the inactive signal, so that the selection signal output terminal CH-OUT continuously outputs the inactive signal to the input terminal IN of the secondscan circuit unit 20 at this time, and it is ensured that the secondscan circuit unit 20 is not triggered by mistake during the time, wherein, during the time when the second scan start signal TP-STV is the active signal QIE, the scan duration signal TP-ON is an inactive signal, the second scan OFF signal TP-OFF may be an active signal or an inactive signal.

Further, fig. 4 is a schematic diagram of a multiplexing circuit unit IN the scanning circuit according to the embodiment of the present invention, and IN an alternative embodiment, themultiplexing circuit unit 30 includes afirst switch circuit 31, asecond switch circuit 32 and athird switch circuit 33, where a first terminal of thefirst switch circuit 31 is a first input terminal IN1, a second terminal of thefirst switch circuit 31 is connected to the selection signal output terminal CH-OUT, and a third terminal of thefirst switch circuit 31 is a first control signalinput terminal CRT 1; the first terminal of thesecond switch circuit 32 is a second input terminal IN2, the second terminal of thesecond switch circuit 32 is connected to the selection signal output terminal CH-OUT, and the third terminal of thethird switch circuit 33 is a second control signalinput terminal CRT 2; the first terminal of thethird switch circuit 33 is a third input terminal IN3, the second terminal of thethird switch circuit 33 is connected to the selection signal output terminal CH-OUT, and the third terminal of thethird switch circuit 33 is a third control signalinput terminal CRT 3.

When the third terminal of thefirst switch circuit 31, that is, the first control signal input terminal CRT1 receives the valid signal, the first terminal and the second terminal of thefirst switch circuit 31 are conducted, that is, the selection signal output terminal CH-OUT outputs the signal of the first input terminal IN 1; when the third terminal of thesecond switch circuit 32, i.e. the second control signal input terminal CRT2, receives the valid signal, the first terminal of thesecond switch circuit 32 is connected to the second terminal, i.e. the selection signal output terminal CH-OUT outputs the signal of the second input terminal IN 2; when the third terminal of thethird switch circuit 33, i.e. the third control signal input terminal CRT3, receives the valid signal, the first terminal and the second terminal of thethird switch circuit 33 are turned on, i.e. the selection signal output terminal CH-OUT outputs the signal of the third input terminal IN 3.

Specifically, fig. 5 is a schematic diagram of an internal connection circuit of the multiplexing circuit unit in the scan circuit according to the embodiment of the present invention. In an alternative embodiment, with appropriate reference to fig. 5, the first switch circuit T1, the second switch circuit T2, and the third switch circuit T3 are each transistor switches. In this embodiment, each transistor switch is a P-type transistor switch, and accordingly, the effective signals output and input by themultiplexing circuit unit 30 are low-level signals; alternatively, each transistor switch is an N-type transistor switch, and accordingly, the effective signals output and input by themultiplexing circuit unit 30 are high-level signals.

Specifically, a first terminal of the first transistor switch T1 is a first input terminal IN1, a second terminal of the first transistor switch T1 is connected to the selection signal output terminal CH-OUT, and a switch control terminal of the first transistor switch T1 is a first control signalinput terminal CRT 1; the first end of the second transistor switch T2 is a second input terminal IN2, the second end of the second transistor switch T2 is connected to the selection signal output terminal CH-OUT, and the switch control end of the second transistor switch T2 is a second control signalinput terminal CRT 2; the first terminal of the third transistor switch T3 is a third input terminal CN3, the second terminal of the third transistor switch T3 is connected to the selection signal output terminal CH-OUT, and the switch control terminal of the third transistor switch T3 is a third control signalinput terminal CRT 3.

With the circuit structure of themultiplexing circuit unit 30, when the switch control terminal of the first transistor switch T1, that is, the first control signal input terminal CRT1 receives a low level signal, the selection signal output terminal CH-OUT outputs a signal of the first input terminal IN 1; when the switch control terminal of the second transistor switch T2, i.e., the second control signal input terminal CRT2, receives a low level signal, the selection signal output terminal CH-OUT outputs a signal of the second input terminal IN 2; when the switch control terminal of the third transistor switch T3, i.e., the third control signal input terminal CRT3, receives a low level signal, the selection signal output terminal CH-OUT outputs the signal of the third input terminal IN 3.

Fig. 6 is a schematic diagram of an internal connection circuit of a scan circuit unit in the scan circuit according to the embodiment of the present invention, and fig. 7 is a timing diagram of the scan circuit unit in the scan circuit according to the embodiment of the present invention.

In one embodiment, as shown in fig. 6, the clock signal input terminals of the scan circuit unit include a first clock signal input terminal CK and a second clock signal input terminal CKB, and the scan circuit unit includes eight transistors and two capacitors, wherein in this embodiment, each transistor is a P-type transistor, and accordingly, the effective signals output and input by the scan circuit unit are low-level signals; or, each transistor adopts an N-type transistor, and correspondingly, the effective signals output and input by the scanning circuit unit are high-level signals

Specifically, the connection relationship of the eight transistors MP1 to MP8 and the two capacitors C1 and C2 is described as follows:

Based on the scanning circuit unit with the above circuit structure, the timing diagram of the scanning circuit unit is shown IN fig. 7, and the scanning circuit unit realizes that the shift signal output end OUT shifts and outputs the effective signal received by the shift signal input end IN through the signal of the first clock signal input end CK and the signal of the second clock signal input end CKB.

Specifically, referring to fig. 6 and 7, at a first time t1, the first clock signal input terminal CK receives a low level signal, the second clock signal input terminal CKB receives a high level signal, and the shift signal input terminal IN receives a low level signal, at this time, the low level signal received by the first clock signal input terminal CK turns on the first transistor MP1, and the first transistor MP1 transmits the low level signal received by IN to the Q point, so that the Q point is at a low level; since the control terminal of the third transistor MP3 continuously receives the low level signal VGL, the third transistor MP3 is continuously turned on, and the voltage level at the point Q2 is the same as the voltage level at the point Q, and is also low, so that the first capacitor C1 stores negative charges; since the point Q is at a low potential, the eighth transistor MP8 is turned on, the eighth transistor MP8 transmits a high level signal VGH to the point QB, which is at a high potential, so that the second capacitor C2 stores positive charges. Since the node Q2 is at a low voltage level, the fourth transistor MP4 is turned on, and the shift signal output terminal OUT outputs a high voltage level signal transmitted from the second clock signal input terminal CKB.

At the next time t2, the first clock signal input terminal CK receives a high level signal, the second clock signal input terminal CKB receives a low level signal, and the shift signal input terminal IN receives a high level signal. At this time, the high level signal received by the first clock signal input terminal CK turns off thefirst transistor MP 1; the first capacitor C1 releases the stored negative charge, so that the point Q2 is kept at a low potential, the third transistor MP3 is still continuously turned on under the effect of the valid signal VGL, and the point Q is also kept at a low potential; since the Q point is at the low potential, the eighth transistor MP8 is turned on, the eighth transistor MP8 transmits the high level signal VGH to the QB point, which is still at the high potential, so that the second capacitor C2 continues to store positive charges; the fourth transistor MP4 is turned on by the low level at the Q2 point, and the shift signal output terminal OUT outputs the low level signal output from the second clock signal input terminal CKB, so that the shift signal output terminal OUT shifts and outputs the valid signal received by the shift signal input terminal IN.

At the next time t3, the first clock input terminal CK receives a low level signal, the second clock input terminal CKB receives a high level signal, and the shift signal input terminal IN receives a high level signal. At this time, the low level signal received by the first clock signal input terminal CK turns on the first transistor MP1, the first transistor MP1 transmits the high level signal received by IN to the point Q, so that the point Q is at a high potential, and the third transistor MP3 continuously receives the low level signal VGL, so that the third transistor MP3 is continuously turned on, the point Q2 has a same potential as the point Q and is also at a high potential, so that the fourth transistor MP4 is turned off, and the shift signal output terminal OUT no longer outputs the signal transmitted by the second clock signal input terminal CKB; the seventh transistor MP7 is turned on by a low level signal received by the first clock signal input terminal CK, the QB point is at a low level due to the low level signal being written, so that the fifth transistor MP5 is turned on, the second capacitor C2 releases positive charges, and the shift signal output terminal OUT outputs a high level signal.

Further, in an embodiment, the first scanning circuit unit is a display scanning circuit unit for providing a display control signal, and the second scanning circuit unit is a fingerprint touch scanning circuit unit for providing a fingerprint touch detection signal. When the scanning circuit is applied to the integrated light sensing display panel, the first scanning circuit unit is connected with the scanning lines to realize the scanning of the display pixels; the second scanning circuit unit is connected with the fingerprint touch light sensation detection unit to realize the scanning of fingerprint touch. For the fingerprint touch light sensation detection unit, the power consumption is large, in the embodiment, the second scanning circuit unit realizes the scanning of the local area, and only the fingerprint touch light sensation detection unit in the local area is started, so that the power consumption of the fingerprint touch light sensation detection unit is reduced.

Further, in an embodiment, the frequency of the clock signal received by the clock signal input terminal of the first scan circuit unit is greater than the frequency of the clock signal received by the clock signal input terminal of the second scan circuit unit, that is, in a unit time, the number of clock signals in the first scan circuit unit is greater, the duration of each clock signal is short, and for a full-area scan, one scan cycle can be completed quickly; in unit time, the number of clock signals in the second scanning circuit unit is small, the duration time of each clock signal is long, for fingerprint touch detection, because the time for outputting a detection signal by the fingerprint touch light sensation detection unit is long, the duration time of the clock signal is long, a fingerprint touch light sensation detection unit can be started in a long time, the fingerprint touch light sensation detection unit is ensured to output a detection signal, and the fingerprint touch detection precision is improved.

The above embodiments of the scan circuit provided by the present invention also provide a display panel, where the display panel includes any one of the above scan circuits, and reference may be made to the above embodiments of each scan circuit for related structures and technical effects.

Fig. 8 to 11 are top views of the display panel according to the embodiment of the present invention, wherein fig. 8 shows a display sub-pixel and a related circuit, fig. 9 shows a fingerprint touch detection unit and a related circuit, and fig. 10 shows a common electrode and a related circuit.

Referring to fig. 8 to 10 properly, the display panel has a display area AA and a frame area BA, wherein the frame area BA is disposed around the display area AA, the frame area is disposed with a scan circuit and an integrated circuit chip IC, wherein the scan circuit includes two kinds of scan circuits, one is a display scan circuit VSR1, the display scan circuit VSR1 includes a plurality of first scan circuit units, the other is a fingerprint scan circuit VSR2, and the fingerprint scan circuit VSR2 includes a plurality of second scan circuit units, wherein the second scan circuit units are connected to the first scan circuit unit and the second scan circuit unit on the previous stage through a multiplexing circuit unit (not shown in fig. 8 to 10), and the detailed connection relationship is not repeated herein.

As shown in fig. 8, the display area AA is provided with a plurality of sub-pixels SP arranged in an array, a plurality of scanning lines G and a plurality of data lines D, wherein the sub-pixels SP include pixel electrodes P and display transistor switches, the scanning lines G are connected to control terminals of the display transistor switches and first scanning circuit units in a display scanning circuit VSR1, respectively, the data lines D are connected to first terminals of the display transistor switches and integrated circuit chips IC, respectively, second terminals of the display transistor switches are connected to the pixel electrodes P, the integrated circuit chips IC are used for applying pixel voltages to the pixel electrodes P, each first scanning circuit unit controls the display transistor switches of a row of sub-pixels through one scanning line G, the scanning line G connected to a first scanning circuit unit transmits an effective signal to a row of sub-pixels when the first scanning circuit unit outputs the effective signal, scanning the row of sub-pixels is realized; the pixel voltage is added to the pixel electrode P via the data line D to light the sub-pixels, and display is completed, wherein in each scanning period, each first scanning unit sequentially scans a row of sub-pixels, and the display scanning circuit VSR1 implements line-by-line scanning, and thus, the entire surface scanning of the display panel is completed.

As shown in fig. 9, the display area AA further has a plurality of fingerprint touch detection units TP arranged in an array, wherein the fingerprint touch detection unit TP is connected to a second scanning circuit unit of the fingerprint scanning circuit VSR2 via a driving line TX, connected with the IC chip via a receiving line RX, each second scanning circuit unit controls a row of fingerprint touch detection units TP via a driving line TX, when a second scanning circuit unit outputs an effective signal, the driving line TX connected to the second scanning circuit unit transmits an effective signal to a row of fingerprint touch detection units TP to drive the row of fingerprint touch detection units TP, in the process that the fingerprint touch detection unit TP receives the valid signal of the second scanning circuit unit, and transmitting the detection signal to an integrated circuit chip IC, and carrying out fingerprint detection on the integrated circuit chip according to the detection signal of the fingerprint touch detection unit TP.

In each scanning period, the area scanning from the nth stage second scanning circuit unit, that is, from the nth row of fingerprint touch detection units TP to the nth + mth row of fingerprint touch detection units TP, is realized by controlling the multiplexing circuit unit.

In fig. 8 and 9, the number of rows of the fingerprint touch detection units TP is equal to the number of rows of the sub-pixels SP, the number of the fingerprint touch detection units TP and the number of the sub-pixels in each row may be equal or different, and the scanning lines G and the driving lines TX may be disposed at intervals from the routing layer or disposed on different routing layers.

Further, in an embodiment, as shown in fig. 10, the display area AA is further provided with a plurality of block-shaped common electrodes COM in an array form, where the common electrodes COM and the pixel electrodes P form a pixel capacitor to form an electric field in a display phase, so that liquid crystal molecules are deflected in different field intensities of the electric field to achieve gray scale display, and the common electrodes COM are multiplexed as touch electrodes in a touch phase, and the common electrodes COM are connected to the integrated circuit chip IC, where the integrated circuit chip IC sends a driving signal to the touch electrodes (i.e., the common electrodes COM) and receives a detection signal of the touch electrodes to detect a touch position in the touch phase.

Further, as shown above, in each scanning cycle, by controlling the multiplexing circuit unit, the fingerprint scanning circuit VSR2 scans the area from the nth row of fingerprint touch detection units to the nth + M row of fingerprint touch detection units TP, when the display panel is provided with touch electrodes for detecting touch positions, the integrated circuit chip can determine the pressing position of the finger according to the touch positions detected by the touch electrodes, so as to determine the area to be scanned by the fingerprint scanning circuit VSR2, for example, the pressing position of the finger is from the xth row of sub-pixels to the yth row of sub-pixels, then the integrated circuit control chip determines the value of N less than or equal to X and N + M greater than or equal to Y according to the preset algorithm, so as to ensure that the scanning range marked by the nth row of sub-pixels to the nth + M row of sub-pixels covers the pressing position of the finger marked by the xth row of sub-pixels to the yth row of sub-pixels, the value of M is controlled by the time when the selection signal output end of the scanning circuit is conducted with the first input end.

The number and arrangement of sub-pixels in fig. 8, the number and arrangement of fingerprint touch detection units in fig. 9, and the number and arrangement of common electrodes in fig. 10 are schematically illustrated, and do not limit the display panel in the present application. In one embodiment, one fingerprint touch detection unit TP is disposed in each sub-pixel SP, and the scanning line G and the driving line TX are disposed between two pixel rows in a pair, and the data line D and the receiving line RX are disposed between two pixel columns in a pair.

Fig. 12 is a schematic diagram of an internal connection circuit of the fingerprint touch detection unit in the display panel according to the embodiment of the present invention, and further, in an embodiment, as shown in fig. 11, the fingerprint touch detection unit includes a photodiode V, a storage capacitor C3 and a fingerprint transistor switch MP, wherein a first electrode of the storage capacitor C3 is connected to a positive electrode of the photodiode V, and a second electrode of the storage capacitor C3 is connected to a negative electrode of the photodiode V; the first end of the fingerprint transistor switch MP is connected to the negative electrode of the photodiode V, the second end of the fingerprint transistor switch MP is connected to the integrated circuit chip IC, and the control end of the fingerprint transistor switch MP is connected to the shift signal output terminal OUT2 of the second scanning circuit unit.

With the fingerprint touch detection unit in this embodiment, in the fingerprint identification stage, when the shift signal output terminal OUT2 of the second scanning circuit unit outputs an active signal, the fingerprint transistor switch MP is turned on. When a user presses a finger on the display panel, the ridge in the finger fingerprint of the display panel is pressed to be in surface contact with the display panel, and the valley is not in surface contact with the display panel, so that the current signals output by different fingerprints are different in size, namely the current signals output to the integrated control chip IC are different in size, and the integrated control chip IC can perform fingerprint identification according to the size of the current signals.

Based on the above embodiments, taking the display panel including 8 rows of sub-pixels and 8 rows of fingerprint touch detection units as an example, fig. 13 is a schematic diagram of another scanning circuit provided in the embodiments of the present invention, as shown in fig. 13, the display scanning circuit includes 8 firstscanning circuit units 10, the shift signal output terminals are sequentially OUT1(1) to OUT1(8), and sequentially outputs the first scanning first signal S11 to the first scanning eighth signal S18. The fingerprint scanning circuit includes 8 secondscanning circuit units 20, and the shift signal output terminals are sequentially OUT2(1) to OUT2(8), and sequentially output a second scanning first signal S21 to a second scanning eighth signal S28.

The shift start signal of the firstscan circuit unit 10 is an STV signal, and the circuit structures of the firstscan circuit unit 10 and the secondscan circuit unit 20 can be as shown in fig. 6, wherein the first clock signal input terminal CK of the firstscan circuit unit 10 receives a CK1 signal, the second clock signal input terminal CKB of the firstscan circuit unit 10 receives a CKB1 signal, the first clock signal input terminal CK of the secondscan circuit unit 20 receives a CK2 signal, the second clock signal input terminal CKB of the secondscan circuit unit 20 receives a CKB2 signal, the circuit structure of themultiplexing circuit unit 30 can be as shown in fig. 5, the first control signal input terminal CRT1 receives a TP-ON signal, the second control signal input terminal CRT2 receives a TP-OFF signal, and the third controlsignal input terminal 3 receives a TP-STV signal.

Fig. 14 is a timing diagram of the display panel according to the embodiment of the invention, as shown in fig. 14, in the display scan circuit, after the STV inputs the valid signal in one scan period, the shift signal output terminals OUT1(1) to OUT1(8) of the 8 firstscan circuit units 10 sequentially output the valid signal, that is, a low level signal sequentially appears from the signal S11 to the signal S18, so as to sequentially scan the sub-pixels in the first to eighth rows.

For the fingerprint scanning circuit, during the first time period T1 when the STV inputs the valid signal and the TP-OFF signal is the valid signal, the selection signal output terminal CH-OUT of the multiplexingunit 30 is connected to the second input terminal IN2 (at this time, the signals inputted from the first input terminal IN1 and the third input terminal IN3 have no effect on the multiplexing unit 30), the second input terminal IN2 of the multiplexingunit 30 continuously receives the invalid signal, so that the selection signal output terminal CH-OUT of the multiplexingunit 30 continuously outputs the invalid signal, and at this time, the shift signal output terminal of each secondscanning circuit unit 30 outputs the invalid signal.

During the second time period T2 when the TP-STV signal is the valid signal, the selection signal output terminal CH-OUT of the multiplexingunit 30 is turned on with the third input terminal IN3 (at this time, the signals inputted from the first input terminal IN1 and the second input terminal IN2 have no influence on the multiplexing unit 30), and the third input terminal IN3 of the multiplexingunit 30 receives the signal from the shift signal output terminal of the firstscan circuit unit 10, so that the selection signal output terminal CH-OUT of the multiplexingunit 30 outputs the signal from the shift signal output terminal of the firstscan circuit unit 10.

As shown in fig. 14, the timing for controlling the TP-STV signal to be the valid signal is synchronized with the timing for outputting the valid signal from the shift signal output terminal OUT1(2) of the 2 nd stage firstscan circuit unit 10, that is, the TP-STV signal is made to be the valid signal only when the valid signal is output from the shift signal output terminal OUT1(2) of the 2 nd stage firstscan circuit unit 10, and at this time, the signal from the shift signal output terminal of the firstscan circuit unit 10 is output from themultiplexing circuit unit 30.

At this time, for each firstscan circuit unit 10, only the shift signal output terminal OUT1(2) of the 2 nd stage firstscan circuit unit 10 outputs the valid signal, then, as for therespective multiplexing units 30 that output the signals of the shift signal output terminals of the firstscan circuit unit 10 at this time, only the selection signal output terminals CH-OUT of the multiplexingunits 30 of the 3 rd stage output valid signals, for each secondscan circuit unit 20 having an input terminal IN connected to the selection signal output terminal CH-OUT of the multiplexingunit 30, only the input terminal IN of the 3 rd stage secondscan circuit unit 20 receives the valid signal, so that the shift signal output terminal OUT2(3) of the 3 rd stage second scan circuit unit can shift the valid signal at the input terminal IN, and then output the valid signal when the next clock pulse arrives.

IN a third time period T3 when the TP-STV signal is an inactive signal and the TP-ON signal is an active signal, the selection signal output terminal CH-OUT of the multiplexingunit 30 is connected to the first input terminal IN1 (at this time, the signals inputted from the third input terminal IN3 and the second input terminal IN2 have no effect ON the multiplexing unit 30), the first input terminal IN1 of the multiplexingunit 30 receives the signal from the shift signal output terminal of the secondscan circuit unit 20, so that the selection signal output terminal CH-OUT of the multiplexingunit 30 outputs the signal from the shift signal output terminal of the secondscan circuit unit 10, which is equivalent to the cascade connection of the secondscan circuit units 20.

In summary, with the clock frequency of the clock signal CKB2, the shift signal output terminal of the secondscan circuit unit 20 sequentially outputs valid signals, so that the fingerprint scan circuit only scans the 3 rd to 6 th rows of fingerprint touch detection units.

During the fourth time period T4 when the STV inputs the valid signal and the TP-OFF signal is the valid signal, the selection signal output terminal CH-OUT of the multiplexingunit 30 is turned on with the second input terminal IN2 (at this time, the signals inputted from the first input terminal IN1 and the third input terminal IN3 have no effect on the multiplexing unit 30), the second input terminal IN2 of the multiplexingunit 30 continuously receives the inactive signal, so that the selection signal output terminal CH-OUT of the multiplexingunit 30 continuously outputs the inactive signal, and at this time, the shift signal output terminals of the secondscan circuit units 30 each output the inactive signal.

The clock frequency of the first scan circuit unit 10 (i.e. the clock frequency of the signal CK1 and the clock frequency of the signal CKB) is greater than the clock frequency of the second scan circuit unit 20 (i.e. the clock frequency of the signal CK2 and the clock frequency of the signal CKB 2), so that the duration of the shift signal output end of the secondscan circuit unit 20 outputting an effective signal is greater than the duration of the output end of the firstscan circuit unit 10 outputting an effective signal, which is favorable for fingerprint touch detection.

In summary, the scanning circuit and the display panel provided by the invention have the following technical effects: the second scanning circuit unit of the scanning circuit can realize area scanning, and the second scanning circuit unit does not need whole-area scanning under the condition that only area scanning is needed, so that the scanning time can be saved, and the scanning power consumption is reduced.

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A scan circuit, comprising:

a plurality of scan circuit units including a shift signal input terminal, a shift signal output terminal, and a clock signal input terminal, wherein the plurality of scan circuit units include a plurality of first scan circuit units and a plurality of second scan circuit units;

a plurality of multiplexing circuit units including a first input terminal, a third input terminal, a control signal input terminal, and a selection signal output terminal;

the plurality of first scanning circuit units are sequentially cascaded, a shifting signal input end of the 1 st stage of first scanning circuit unit receives a shifting starting signal, and the shifting signal input end of each stage of first scanning circuit unit is connected with a shifting signal output end of the first scanning circuit unit at the upper stage from the first scanning circuit unit at the 2 nd stage to the first scanning circuit unit at the last stage;

the multiplexing circuit units and the second scanning circuit units are alternately arranged in sequence, a selection signal output end of the Y-th-stage multiplexing circuit unit is connected with a shift signal input end of the Y-th-stage second scanning circuit unit, a first input end of the 1-st-stage multiplexing circuit unit continuously receives a non-effective signal, a third input end of the 1-st-stage multiplexing circuit unit receives the shift starting signal, in the multiplexing circuit units from the 2-th-stage multiplexing circuit unit to the last-stage multiplexing circuit unit, a first input end of the X-th-stage multiplexing circuit unit is connected with a shift signal output end of the X-1-th-stage second scanning circuit unit, a third input end of the X-th-stage multiplexing circuit unit is connected with a shift signal output end of the X-1-th-stage first scanning circuit unit, and Y is an integer greater than or equal to 1, x is an integer greater than or equal to 2,

the control signal input end is used for controlling the conduction of the selection signal output end and the third input end while the shift signal output end of the first scanning circuit unit at the (N-1) th stage outputs an effective signal, and controlling the conduction of the selection signal output end and the first input end when the shift signal output end of the first scanning circuit unit at the (N-1) th stage outputs an effective signal, wherein N is an integer greater than or equal to 2.

2. The scan circuit of claim 1,

the multiplexing circuit unit further comprises a second input end which continuously receives the non-effective signal;

the control signal input end is also used for controlling the conduction of the selection signal output end and the second input end when the selection signal output end is not conducted with the first input end and the third input end.

3. The scan circuit of claim 2,

the control signal input end comprises a first control signal input end, a second control signal input end and a third control signal input end, wherein when the first control signal input end receives an effective signal, the selection signal output end is conducted with the first input end, when the second control signal input end receives an effective signal, the selection signal output end is conducted with the second input end, and when the third control signal input end receives an effective signal, the selection signal output end is conducted with the third input end;

the effective signal received by the third control signal input terminal is synchronous with the effective signal output by the shift signal output terminal of the first scan circuit unit of the (N-1) th stage,

when the effective signal of the third control signal input end is finished, the first control signal input end receives an effective signal, and when the first control signal input end and the third control signal input end simultaneously receive a non-effective signal, the second control signal input end receives an effective signal.

4. The scan circuit of claim 3, wherein the multiplexing circuit unit comprises:

a first switch circuit, wherein a first end of the first switch circuit is the first input end, a second end of the first switch circuit is connected to the selection signal output end, and a switch control end of the first switch circuit is the first control signal input end;

a second switch circuit, wherein a first end of the second switch circuit is the second input end, a second end of the second switch circuit is connected to the selection signal output end, and a switch control end of the second switch circuit is the second control signal input end;

and a third switch circuit, wherein a first end of the third switch circuit is the third input end, a second end of the third switch circuit is connected to the selection signal output end, and a switch control end of the third switch circuit is the third control signal input end.

5. The scan circuit according to claim 4, wherein the first switch circuit, the second switch circuit, and the third switch circuit are transistor switches.

6. The scan circuit of claim 1, wherein the clock signal input terminals comprise a first clock signal input terminal and a second clock signal input terminal, and wherein the scan circuit unit comprises eight transistors and two capacitors, wherein,

a first transistor, a first terminal of which is connected to the shift signal input terminal, and a control terminal of which is connected to the first clock signal input terminal;

a second end of the second transistor is connected with a second end of the first transistor, and a control end of the second transistor is connected with the second clock signal input end;

a third transistor, a first end of the third transistor being connected to a second end of the first transistor, a control end of the third transistor continuously receiving an active signal;

a fourth transistor, a first end of the fourth transistor is connected to the shift signal output end, a second end of the fourth transistor is connected to the second clock signal input end, and a control end of the fourth transistor is connected to the second end of the third transistor;

a fifth transistor, a second terminal of the fifth transistor being connected to the shift signal output terminal;

a sixth transistor, a first end of which continuously receives an inactive signal, a second end of which is connected to the first end of the second transistor, and a control end of which is connected to the control end of the fifth transistor;

a seventh transistor, a first end of which continuously receives an active signal, a second end of which is connected to a control end of the sixth transistor, and a control end of which is connected to the first clock signal input end;

a first end of the eighth transistor is connected with a control end of the sixth transistor, a second end of the eighth transistor continuously receives an inactive signal, and a control end of the eighth transistor is connected with a second end of the first transistor;

a first capacitor, a first end of which is connected to the second end of the third transistor, and a second end of which is connected to the shift signal output terminal;

and a first end of the second capacitor is connected with the control end of the fifth transistor, and a second end of the second capacitor is connected with the first end of the fifth transistor.

7. The scan circuit of claim 6,

the transistor is a P-type transistor, the effective signal is a low level signal, and the ineffective signal is a high level signal; or,

the transistor is an N-type transistor, the effective signal is a high level signal, and the ineffective signal is a low level signal.

8. The scan circuit of claim 1,

the first scanning circuit unit is a display scanning circuit unit and is used for providing a display control signal;

the second scanning circuit unit is a fingerprint touch scanning circuit unit and is used for providing a fingerprint touch detection signal.

9. The scan circuit of claim 1,

the frequency of the clock signal received by the clock signal input end of the first scanning circuit unit is greater than the frequency of the clock signal received by the clock signal input end of the second scanning circuit unit.

10. A display panel comprising the scanning circuit according to any one of claims 1 to 9.

11. The display panel of claim 10, wherein the display panel has a display area and a bezel area, wherein,

the frame area is provided with the scanning circuit and an integrated circuit chip;

the display area is provided with a plurality of sub-pixels, a plurality of scanning lines and a plurality of data lines, wherein the sub-pixels comprise pixel electrodes and display transistor switches, the scanning lines are respectively connected with control ends of the display transistor switches and first scanning circuit units of the scanning circuits, the data lines are respectively connected with first ends of the display transistor switches and the integrated circuit chip, second ends of the display transistor switches are connected with the pixel electrodes, and the integrated circuit chip is used for applying pixel voltages to the pixel electrodes;

the display area is further provided with a plurality of fingerprint touch detection units, wherein the fingerprint touch detection units are respectively connected with the second scanning circuit unit of the scanning circuit and the integrated circuit chip, and the integrated circuit chip is further used for fingerprint detection according to detection signals of the fingerprint touch detection units.

12. The display panel of claim 11, wherein the fingerprint touch detection unit comprises:

a photodiode;

a storage capacitor, wherein a first electrode of the storage capacitor is connected with an anode of the photodiode, and a second electrode of the storage capacitor is connected with a cathode of the photodiode;

the first end of the fingerprint transistor switch is connected with the negative electrode of the photosensitive diode, the second end of the fingerprint transistor switch is connected with the integrated circuit chip, and the control end of the fingerprint transistor switch is connected with the second scanning circuit unit.

13. The display panel according to claim 11,

the display area is also provided with a plurality of blocky common electrodes, wherein the common electrodes and the pixel electrodes form a pixel capacitor in a display stage, and the common electrodes are reused as touch electrodes in a touch stage;

the common electrode is connected with the integrated circuit chip, wherein the integrated circuit chip is further used for sending a driving signal to the touch electrode, receiving a detection signal of the touch electrode to detect a touch position, and determining N and the time for conducting a selection signal output end and a first input end in the scanning circuit according to the detected touch position; and N represents that the scanning circuit starts scanning from the Nth row of fingerprint touch detection units.