The content of the invention
The embodiment of the present invention provides a kind of service board and electronic equipment, can improve the electricity of main business processing unit circuitThe stability of source power supply.
First aspect, there is provided a kind of service board, including power on power domain and main circuit power domain in advance；
The pre- power domain that powers on includes：Power on power supply, microprocessor, power supply control chip, logic gate device in advance；It is describedMain circuit power domain includes：At least one branch power supply, at least one main business processing unit circuit, primary processor and complexityProgrammable logic device (CPLD)；
The pre- power supply that powers on connects the microprocessor, the power supply control chip, the logic gate；It is described micro-At least one signal output part of processor is connected one by one with least one signal input part of the power supply control chip；It is describedThe either signal output terminal of microprocessor connects the first input end of the logic gate device；The power supply control chip is at leastOne signal output part is connected one by one with least one branch power supply；The power supply control chip either signal output terminal connectsConnect the second input terminal of the logic gate device；The output terminal of the logic gate device connects the clock of the power supply control chipSignal input part；
At least one branch power supply is used to supply at least one main business processing unit circuit, primary processor and CPLDElectricity；One general-purpose interface of the primary processor connects the 3rd input terminal of the logic gate device, the primary processorDescribed in the connection of UART (Universal Asynchronous Receiver/Transmitter, UART Universal Asynchronous Receiver Transmitter) interfaceThe UART interface of microprocessor；The primary processor is also connected with the CPLD；Described in the general-purpose interface connection of the CPLD4th input terminal of logic gate device；
Wherein, it is described it is pre- power on power supply, for the microprocessor, the power supply control chip, the logic gate devicePart is powered；
The microprocessor connects the power supply control chip, for controlling the power supply control chip to the main circuitAt least one branch power supply output of power domain is turned on and off signal；
The microprocessor is used for the first input end input clock signal to the logic gate；
After the primary processor sends normal operation signal by UART interface to the microprocessor, the microprocessorIt is additionally operable to control the power supply control chip to input first control signal to the second input terminal of the logic gate device；
The primary processor is additionally operable to input second control signal to the 3rd input terminal of the logic gate device；
The primary processor is additionally operable to the 3rd control of the 4th input terminal input for controlling the CPLD to the logic gate deviceSignal processed；
The logic gate device be used for according to the first control signal, second control signal, the 3rd control signal andThe clock signal generates locking signal, and exports to the clock signal input terminal of the power supply control chip, the power supply controlCoremaking piece exports the state of signal according to the current each signal output part of locking signal locking.
In such scheme, based on the structure of above-mentioned service board, due to when primary processor by UART interface to micro- placeAfter managing device transmission normal operation signal, microprocessor can control second input terminal of the power supply control chip to logic gate device defeatedEnter first control signal；Primary processor can input second control signal to the 3rd input terminal of logic gate device；Primary processorCPLD can also be controlled to input the 3rd control signal to the 4th input terminal of logic gate device；Logic gate device can be according to firstControl signal, second control signal, the 3rd control signal and clock signal generation locking signal, and export to power supply and control coreThe clock signal of piece, power supply control chip export the state of signal according to the current each signal output part of locking signal locking, fromAnd after service board normal operation so that each branch power supply is to corresponding device from powering on the device of power domain in advance(for example, microprocessor) influences, so as to improve the stability of the power supply of main business processing unit circuit power supply.
Embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, completeSite preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based onEmbodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative workEmbodiment, belongs to the scope of protection of the invention.
With reference to shown in Fig. 1, the structure of the service board included to the electronic equipment of the embodiment of the present invention offer carries outDescribe in detail, which includes：Including powering on power domain C1 and main circuit power domain C2 in advance.
Powering on power domain C1 in advance includes：Power on power supply 11, microprocessor 12, power supply control chip 13, logic gate device in advance14；Main circuit power domain C2 includes：At at least one branch power supply 21 (21-1,21-2 ... 21-n), at least one main businessManage element circuit 22 (22-1,22-2 ... 22-n), primary processor 23 and complex programmable logic device (CPLD) 24.Wherein,The main power source of pre- at least one branch power supply 21 connection for powering on power supply 11 and main circuit power domain parallel to logic gate device andThe power supply control chip is powered.Wherein, powering on power supply 11 and at least one branch power supply 21 in advance can turn comprising direct currentDC power supply DC/DC, exemplary, powering on power supply 11 and at least one branch power supply 21 in advance can use+12V power supplys to power,Electricity of the pre- DC/DC powered in power supply 11 by the voltage conversion of main power source for the pre- device voltage requirement for powering on power domain C1 of satisfactionPressure is for example
The voltage conversion of+12V power supplys is to meet in the C2 of main circuit power domain by+3.3V, DC/DC in branch power supply 21The voltage of the voltage requests of circuit such as each main business processing unit circuit, primary processor, CPLD, including main circuit power domain C2Middle+3.3V the main power sources used：VCCmain-3V3.
The pre- power supply 11 that powers on connects microprocessor 12, power supply control chip 13, logic gate 14；Microprocessor 12 is extremelyA few signal output part is connected one by one with least one signal input part of power supply control chip 13；Any of microprocessor 12Signal output part connects the first input end in1 of logic gate device 14；At least one signal output part of power supply control chip 13It is connected one by one with least one branch power supply 21；The of 13 either signal output terminal of power supply control chip connection logic gate device 14Two input terminal in2；The clock signal input terminal of the output terminal out connections power supply control chip 13 of logic gate device 14.
At least one branch power supply 21 is used at least one main business processing unit 22, primary processor 23 and CPLD24Power supply；The 3rd input terminal in3, the UART of primary processor 23 of the general-purpose interface connection logic gate device 14 of primary processor 23Interface connects the UART interface of microprocessor 12；Primary processor 23 is also connected with CPLD24；The general-purpose interface connection of CPLD244th input terminal in4 of logic gate device 14.It should be noted that at least one main business processing unit 22, primary processor 23And CPLD24 may be univoltage value or multivoltage value power supply device, therefore at least one main business processing unit 22, main placeThe magnitude of voltage that managing device 23 and CPLD24 can be provided by one or more of at least one branch power supply 21 is powered.
Wherein, power supply 11 is powered in advance, for powering to microprocessor 12, power supply control chip 13, logic gate device 14；It is micro-Processor 12 connects power supply control chip 13, for controlling at least one branch of the power supply control chip 13 to main circuit power domainThe output of power supply 21 is turned on and off signal.
Microprocessor 12 is used for the first input end in1 input clock signals to logic gate 14.
After primary processor 23 sends normal operation signal by UART interface to microprocessor 12, microprocessor 12 is additionally operable toPower supply control chip 13 is controlled to input first control signal to the second input terminal in2 of logic gate device 14.
Primary processor 23 is additionally operable to input second control signal to the 3rd input terminal in3 of logic gate device 14.
Primary processor 23, which is additionally operable to fourth input terminal in4 input threeth controls of the control CPLD24 to logic gate device 14, to be believedNumber.
Logic gate device 14 is used to be believed according to first control signal, second control signal, the 3rd control signal and clockNumber generation locking signal, and export to power supply control chip 13 clock signal input terminal, power supply control chip 13 is according to lockingThe state of semaphore lock currently each signal output part output signal.
In such scheme, based on the structure of above-mentioned service board, due to when primary processor by UART interface to micro- placeAfter managing device transmission normal operation signal, microprocessor can control second input terminal of the power supply control chip to logic gate device defeatedEnter first control signal；Primary processor can input second control signal to the 3rd input terminal of logic gate device；Primary processorCPLD can also be controlled to input the 3rd control signal to the 4th input terminal of logic gate device；Logic gate device can be according to firstControl signal, second control signal, the 3rd control signal and clock signal generation locking signal, and export to power supply and control coreThe clock signal of piece, power supply control chip export the state of signal according to the current each signal output part of locking signal locking, fromAnd after service board normal operation so that each branch power supply is to corresponding device from powering on the device of power domain in advance(for example, microprocessor) influences, so as to improve the stability of the power supply of main business processing unit circuit power supply.
In 23 failure of primary processor, primary processor 23 is additionally operable to the 3rd input terminal in3 inputs to logic gate device 145th control signal；Primary processor 23 is additionally operable to control CPLD24 and inputs the 6th to the 4th input terminal in4 of logic gate device 14Control signal.
Logic gate device 14 is used to be believed according to the clock that the 5th control signal, the 6th control signal export microprocessor 12Number output to power supply control chip 14 clock signal input terminal, power supply control chip 14 is according to the clock signal, in Wei ChuManage the state that each signal output part is adjusted under the control of device 12.
If desired for power supply is actively closed, then microprocessor 12 sends power-off to primary processor 23 by UART interface and refers toShow；Primary processor 23 is sent to microprocessor 12 by UART interface and closes response；Primary processor 23 is additionally operable to be closed according to power supplyClose instruction and input the 7th control signal to the 3rd input terminal in3 of logic gate device 14；Primary processor 23 is additionally operable to controlCPLD24 inputs the 8th control signal to the 4th input terminal in4 of logic gate device 14；Microprocessor 12 is additionally operable to according to closingResponse control power supply control chip 13 inputs the 9th control signal to the second input terminal in2 of logic gate device 14；Logic gate deviceThe clock that part 14 is used to be exported microprocessor 12 according to the 7th control signal, the 8th control signal and the 9th control signal is believedNumber output to power supply control chip 13 clock signal input terminal, power supply control chip 13 is according to clock signal, in microprocessorThe state of each signal output part output signal is adjusted under 12 control, to control the power supply control chip to described at least oneA branch power supply exports shutdown signal.
With reference to shown in Fig. 2, logic gate 14 includes：With door module 141 and OR gate module 142；Wherein, with door module141 include first and door G3 and second and door G4, and first is connected the second defeated of logic gate device 14 with the first input end of door G3Enter and hold in2, first is connected the 3rd input terminal in3 of logic gate device 14 with the second input terminal of door G3；Second and the of door G4One input terminal connects the second input terminal in2 of logic gate device 14, and second is connected logic gate device with the second input terminal of door G414 the 4th input terminal in4 OR gates module 142 includes the first OR gate G1 and the second OR gate G2, wherein, the first of the first OR gate G1The second input terminal of the first input end in1, the first OR gate G1 of input terminal connection logic gate device 14 connect the second OR gate G2'sOutput terminal, the output terminal out of the output terminal connection logic gate device 14 of the first OR gate G1；The first input end of second OR gate G2 connectsConnect the output terminal of first and door G3, the output terminal of the second input terminal connection second and door G4 of the second OR gate G2.
With reference to shown in Fig. 1, power supply 11 is powered in advance microprocessor 12, power supply control chip 13 and logic gate device 14 are adoptedPowered with following manner：The first end of the power interface connection first switch transistor Q1 of power supply control chip 13, first switchThe second end connection of transistor Q1 powers on power supply 11 in advance, and the control terminal of first switch transistor Q1 is grounded by first resistor R1GND；The reseting interface of power supply control chip 13 passes through the first end of second resistance R2 connection first switch transistors Q1, power supply controlThe reseting interface of coremaking piece 13 is grounded by capacitance C1；The first end connection first switch transistor Q1 of second switch transistor Q2First end, the control terminal of second switch transistor Q2 is grounded by 3rd resistor R3, the second end of second switch transistor Q2Connect the main power source of at least one branch power supply connection in main circuit power domain.The power interface connection first of logic gate device 14The first end of switching transistor Q1.
In a kind of example, power supply control chip 13 can use 74HC273 latch, OR gate module 142 to use74HC32 OR gates, 74HC32 OR gates include G1 and G2, use 74HC08 and door with door module 141,74HC08 and door include G3 andG4, microprocessor 12 can use MCU, primary processor 23 to use PNP triode using CPU, Q1 and Q2, then to above-mentioned electricityThe connection relation of each device is described as follows in sub- equipment：
74HC273 latch, 74HC32 OR gates, the power interface VDD of 74HC08 and door be connected at the same time safety+3.3V power supply：On Vgood, wherein, the VCCpre-3V3 for powering on power domain C1 in advance is connected to Vgood by PNP triode Q1, electricityResistance R1 provides enough saturation conduction base current drivings for Q1.Wherein, with the output terminal of door G3 and G4, it is connected respectively to OR gateTwo input terminals of G2.The output terminal of OR gate G2, is connected to another input terminal of OR gate G1.Master in the C2 of main circuit power domainPower supply VCCmain-3V3 is connected to Vgood by PNP triode Q2, and resistance R3 provides enough saturation conduction base stage electricity for Q2Stream driving.
The signal output part Q [6 of 74HC273 latch：0], it is connected respectively to 7 branch power supplys in the C2 of main circuit power domain(such as：DC/DC ON/OFF Enable Pin), is turned on and off signal (On/off) to the output of branch power supply and is used for controlling brancher electricityOpen and power on interval time in a predetermined sequence in source.The signal output part Q7 of 74HC273 latch, for exporting LOCK lettersNumber (i.e. first control signal), is connected to an input terminal of 74HC08 and door G3 and G4, for 74HC273 latch clocksThe clock signal of signal input part (CLOCK) from lock control.Resistance R2 and capacitance C1 are connected in series on Vgood power supplys, resistance R2The reseting interface (Clear) of 74HC273 latch is connected between capacitance C1, electrification reset letter is provided for 74HC273 latchNumber.The signal output part GPIO [7 of MCU：0] pin (totally 8 pin 8*GIPO), is connected respectively to the letter of 74HC273 latchNumber input terminal D [7：0] pin, control signal and generation LOCK latch signals are enabled for transmitting branch electric power on/off.
The GPIO8 pins of MCU are connected to an input pin of 74HC32 OR gates G1, and the output of G1 is connected to 74HC273The clock signal input terminal CLOCK of latch, for D [7：0] the latch control of information is inputted.The UART interface of MCU, passes throughUART-BUS buses, are connected to and " in the C2 " of main circuit power domain in the UART interface of CPU, for the two intercommunication, transmitNecessary control information.
A general-purpose interface (such as GPIO pin) of CPU in the C2 of main circuit power domain be connected to door G3 anotherInput terminal, it can send control signal, such as：Second control signal CPU-ctl, the 4th resistance R4 of one end ground connection GND connectIt is connected to the GPIO pin of CPU so that CPU-ctl signals are defaulted as low level." CPLD in the C2 " of main circuit power domain, usesOne general-purpose interface (such as GPIO pin) is connected to another input terminal with door G4, it can send control signal, such as：3rd control signal CPLD-ctl, the 5th resistance R5 of one end ground connection GND are connected in the GPIO pin of CPLD, make the signalCPLD-ctl is defaulted as low level.Cbus communication bus is connected between CPU and CPLD, is passed for necessary information between two devicesPass.Cbus communication bus can be most common SPI (Serial Peripheral Interface, serial type Peripheral Interface) totalLine, LPC (Low Pin Count, low pin count communication interface) bus, Local_Bus (local communications bus) bus etc..
Based on the connection relation of above-mentioned electronic equipment, the workflow of the electronic equipment provided the embodiment of the present inventionIt is described as follows：
Process one：The procedure declaration that main circuit power domain C2 is powered on first is as follows：+ 12V the voltage stabilizations that main power source providesAfter normal, power on power supply 11 in advance and start to work, change out VCCpre-3V3 power supplys be initially supplied it is pre- power on it is each in power domain C1A device.And each branch power supply 21 (21-1,21-2 ... 21-n) in the C2 of main circuit power domain is although be also connected to main electricitySource, but since the enabled control terminal of branch power supply 21 is in disarmed state, it is completely in closed mode so that main circuitEach circuits of power domain C2 are all temporarily in electroless state.After MCU12 obtains the power supply of VCCpre-3V3 power supplys, start to start fortuneOK.
Meanwhile VCCpre-3V3 power supplys by Q1 produce Vgood power supplys, also begin to 74HC273 latch, 74HC32 orDoor, 74HC08 and door are powered.The resistance R2 being connected on Vgood power supplys charges capacitance C1, and when C1 meets predetermined voltage,Reset operation is carried out to 74HC273 latch by Clear pins, makes 74HC273 latch after the power is turned on, it exports Q [7：0]=0, it is completely in stable low level state.When the Q7 outputs of 74HC273 latch are 0, i.e. signal LOCK=0, then compelMake with the output of door G3 and G4 all 0 (unrelated with the level value of CPU-ctl signals and CPLD-ctl signals), OR gate G2's is defeatedIt is also 0 to go out, the GPIO8 output signals equivalent to MCU：The clock signal that GPIO-CLK is directly connected to 74HC273 latch is defeatedEnter end (CLOCK).
, will be GPIO [8 after MCU start completions：0] signal output part, the UART controller initialization of MCU are all configured toFor state can be used directly.According to set strategy, will control in next step main circuit power domain C2 each branch power supply 21 (21-1,21-2 ... 21-n) unlatching, it is assumed that the opening sequence of each branch power supply is 1/2/3/4/5/6/7, and each branch power supply is openedOpen at intervals of 10 milliseconds, it is specific as follows：
S1, MCU set the GPIO-CLK signal outputs high level 1 of GPIO8, and keep.
S2, MCU set GPIO0 to export high level 1, and keep.
S3, MCU set the GPIO-CLK signal outputs low level 0 of GPIO8, after 10 milliseconds of delay, then setting GPIO8'sGPIO-CLK signal outputs high level 1, and keep；At this time, the branch power supply 22-1 of main circuit power domain C2 works on power.
Then, MCU is delayed 10 milliseconds, starts the unlatching control of next branch power supply 22-2, respectively for GPIO1/GPIO2/GPIO3/GPIO4/GPIO5/GPIO6, repeats step S1-S3, so will be branch power supply 22-2 to branch electricitySource 22-7 is opened successively, main circuit power domain C2 is entered regular traffic starting state.It is each on MCU control main circuit powers domain C2After branch power supply electrifying, the other monitor tasks of start to process, while the confirmation message of waiting for CPU loopback " normal operation ".
Process two：CPU starts to start in the C2 of main circuit power domain, and controls other circuits in power domain C2 to be carried out at the same timeStart.After CPU start completions, its general-purpose interface GPIO2 pins will be initialized as exporting, and export high level 1, i.e., at this timeCPU-ctl signals are high level 1.Also by the cbus communication bus by being connected with CPLD, general CPLD connects CPU at the same timeMouth GPIO3 is arranged to output high level 1, i.e., CPLD-ctl signals are high level 1 at this time.Afterwards, CPU is total by UART-BUSLine, normal operation signal is sent to MCU.
After MCU receives the normal operation signal of CPU transmissions, it will be considered that each circuit unit in the C2 of main circuit power domain isThrough completely normal, MCU performs following operation at this time：
S1, MCU set GPIO7 to export high level 1, and keep.
S2, MCU set the GPIO-CLK signal outputs low level 0 of GPIO8, are delayed 10 milliseconds, set the GPIO- of GPIO8CLK signal exports high level 1, and keeps；At this time, the Q7 outputs of 74HC273 latch will be changed into high level 1, i.e. signal LOCK=1.
So with all high level 1 of all input signals of door G3 and G4 so that their output signal：G3SIG andG4SIG is also by all high level 1, so that the output signal of OR gate G2：G2SIG is changed into high level 1.When signal G2SIG is changed intoDuring high level 1, the output of OR gate G1 by it is constant be high level 1, make the CLOCK of 74HC273 latch no longer by the GPIO8 of MCUExport signal control, at this time no matter MCU occur which type of catastrophe failure (including restart, chaotic operation, power down etc.) will notAny influence is produced on the branch power unit in the C2 of main circuit power domain, makes the main business processing unit of main circuit power domain C2Remain normal operation.
Process three：When CPU breaks down, the hardware watchdog circuit for CPU configurations will carry out hardware reset behaviour to CPUMake, while also CPU-ctl signals and CPLD-ctl signals can all be resetted output low level 0, at this time signal G3SIG=G4SIG=G2SIG=0, the GPIO8 output signals equivalent to MCU：GPIO-CLK be directly connected to 74HC273 latch when, there is the time window that a MCU can control 74HC273 latch in clock signal input part (CLOCK).When CPU restartsAfter the completion of, CPU-ctl signals and CPLD-ctl signals will all be set output high level 1 again, as described in process two, thisWhen signal G3SIG=G4SIG=G2SIG=1, the time window of MCU control 74HC273 latch is closed, and MCU will not be to masterBranch power unit in the C2 of circuit power domain produces any influence, makes the main business processing unit of main circuit power domain C2 all the timeKeep normal operation.
Process four：When MCU and CPU is all worked normally, if necessary to actively close the institute in the C2 of main circuit power domainThere is branch power supply, processing procedure is as follows：
S1, MCU send power-off to CPU by UART-BUS and indicate, after CPU receives power-off instruction,CPU-ctl signals and CPLD-ctl signals all set output low level 0, are then replied by UART-BUS and close response extremelyMCU, at this time, G3SIG=G4SIG=G2SIG=0, MCU retrieve the control of 74HC273 latch.
The Q7 outputs of 74HC273 latch are arranged to 0 by S2, MCU, that is, keep signal LOCK=0.
S3, MCU carry out according to this various branch power supplys in the C2 of main circuit power domain according to set lower electric order requirementsShutoff operation.
After the various branch power-offs operation in the C2 of main circuit power domain is fully completed, MCU enters low power consumpting stateOperation.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, anyThose familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be containedCover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.