技术领域technical field
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元、移位寄存器电路、显示面板。The present disclosure relates to the field of display technology, and in particular to a shift register unit, a shift register circuit, and a display panel.
背景技术Background technique
随着光学技术和半导体技术的发展，以液晶显示器(Liquid Crystal Display，LCD)和有机发光二极管显示器(Organic Light Emitting Diode，OLED)为代表的平板显示器具有轻薄、能耗低、反应速度快、色纯度佳、以及对比度高等特点，在显示领域占据了主导地位。近些年来显示装置呈现出了高集成度以及低成本的发展趋势。以阵列基板行驱动(Gate Driver on Array，GOA)技术为代表，利用GOA技术将栅极驱动电路集成于阵列基板的周边区域，可在实现窄边框设计的同时，有效降低显示装置的制造成本、提升模组工艺产量。GOA技术的设计要点是移位寄存器单元的结构和该移位寄存器单元的信耐度。With the development of optical technology and semiconductor technology, flat panel displays represented by liquid crystal display (Liquid Crystal Display, LCD) and organic light emitting diode display (Organic Light Emitting Diode, OLED) have the advantages of light and thin, low energy consumption, fast response speed, color The characteristics of good purity and high contrast ratio occupy a dominant position in the display field. In recent years, display devices have shown a development trend of high integration and low cost. Represented by Gate Driver on Array (GOA) technology, GOA technology is used to integrate the gate driver circuit in the peripheral area of the array substrate, which can effectively reduce the manufacturing cost of the display device while realizing the narrow frame design. Improve module process output. The design points of GOA technology are the structure of the shift register unit and the reliability of the shift register unit.
目前，为了保证移位寄存器单元的信耐度，例如常采用如图1所示的移位寄存器单元的结构，该移位寄存器单元通过交替响应第一电源信号VDD1和第二电源信号VDD2交替控制第一下拉模块和第二下拉模块对移位寄存器单元中的上拉节点PU和信号输出端OUTPUT降噪。显然，上述结构的移位寄存器单元中的开关元件的数量较多，占用空间大。At present, in order to ensure the reliability of the shift register unit, for example, the structure of the shift register unit shown in Figure 1 is often used, and the shift register unit alternately controls the The first pull-down module and the second pull-down module reduce noise on the pull-up node PU and the signal output terminal OUTPUT in the shift register unit. Apparently, the number of switching elements in the shift register unit with the above structure is relatively large, and occupies a large space.
因此，需要在保证信耐度的基础上，提供一种开关元件数量较少的移位寄存器单元。Therefore, it is necessary to provide a shift register unit with fewer switching elements on the basis of ensuring reliability.
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。It should be noted that the information disclosed in the above background section is only for enhancing the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art.
发明内容Contents of the invention
本公开的目的在于提供一种移位寄存器单元、移位寄存器电路、显示面板，以解决现有技术中移位寄存器单元中开关元件数量较多占用空间大的问题。The purpose of the present disclosure is to provide a shift register unit, a shift register circuit, and a display panel, so as to solve the problem in the prior art that the number of switching elements in the shift register unit is too large to occupy a large space.
本公开的一种示例性实施例中，包括：In an exemplary embodiment of the present disclosure, including:
输入模块，连接信号输入端、上拉节点，用于响应输入信号以将所述输入信号传输至所述上拉节点；an input module, connected to a signal input terminal and a pull-up node, for transmitting the input signal to the pull-up node in response to an input signal;
输出模块，连接所述上拉节点、时钟信号端、信号输出端，用于响应所述上拉节点的电压信号以将时钟信号传输至所述信号输出端；an output module, connected to the pull-up node, a clock signal terminal, and a signal output terminal, for transmitting a clock signal to the signal output terminal in response to the voltage signal of the pull-up node;
下拉控制模块，连接所述上拉节点、参考信号端、第一下拉节点、第二下拉节点、第一电源信号端、第二电源信号端，用于响应所述上拉节点的电压信号以将参考信号分别传输至所述第一下拉节点和第二下拉节点，以及交替响应第一电源信号和第二电源信号，将所述第一电源信号传输至所述第一下拉节点，将所述第二电源信号传输至所述第二下拉节点；The pull-down control module is connected to the pull-up node, the reference signal terminal, the first pull-down node, the second pull-down node, the first power signal terminal, and the second power signal terminal, and is used to respond to the voltage signal of the pull-up node to transmitting the reference signal to the first pull-down node and the second pull-down node respectively, and alternately responding to the first power supply signal and the second power supply signal, transmitting the first power supply signal to the first pull-down node, and The second power signal is transmitted to the second pull-down node;
第一下拉模块，连接所述第一下拉节点、所述第二下拉节点、所述参考信号端、所述信号输出端，用于交替响应所述第一下拉节点和所述第二下拉节点的电压信号以将所述参考信号传输至所述信号输出端；The first pull-down module is connected to the first pull-down node, the second pull-down node, the reference signal terminal, and the signal output terminal, and is used to alternately respond to the first pull-down node and the second pull-down node pulling down a voltage signal at a node to transmit the reference signal to the signal output terminal;
第二下拉模块，连接所述上拉节点、所述信号输出端、所述时钟信号端，用于响应所述时钟信号以将所述信号输出端的电压信号周期性的传输至所述上拉节点；The second pull-down module is connected to the pull-up node, the signal output terminal, and the clock signal terminal, and is used to periodically transmit the voltage signal of the signal output terminal to the pull-up node in response to the clock signal ;
其中，所述第二下拉模块包括第一开关元件，控制端连接所述时钟信号端，第一端连接所述信号输出端，第二端连接所述上拉节点；所述第一电源信号与所述第二电源信号为同频反向信号。Wherein, the second pull-down module includes a first switch element, the control terminal is connected to the clock signal terminal, the first terminal is connected to the signal output terminal, and the second terminal is connected to the pull-up node; the first power signal and The second power signal is a same-frequency reverse signal.
本公开的一种示例性实施例中，所述输入模块包括：In an exemplary embodiment of the present disclosure, the input module includes:
第二开关元件，控制端和第一端均连接所述信号输入端、第二端连接所述上拉节点。For the second switch element, the control terminal and the first terminal are both connected to the signal input terminal, and the second terminal is connected to the pull-up node.
本公开的一种示例性实施例中，所述下拉控制模块包括：In an exemplary embodiment of the present disclosure, the pull-down control module includes:
第一下拉控制单元，连接所述上拉节点、所述参考信号端、第一下拉控制节点、所述第一下拉节点，用于响应所述上拉节点的电压信号以将所述参考信号分别传输至所述第一下拉控制节点和所述第一下拉节点；The first pull-down control unit is connected to the pull-up node, the reference signal terminal, the first pull-down control node, and the first pull-down node, and is used to respond to the voltage signal of the pull-up node to set the transmitting reference signals to the first pull-down control node and the first pull-down node respectively;
第二下拉控制单元，连接所述上拉节点、所述参考信号端、第二下拉控制节点、所述第二下拉节点，用于响应所述上拉节点的电压信号以将所述参考信号分别传输至所述第二下拉控制节点和所述第二下拉节点；The second pull-down control unit is connected to the pull-up node, the reference signal terminal, the second pull-down control node, and the second pull-down node, and is used to respond to the voltage signal of the pull-up node to convert the reference signals respectively transmitted to the second pull-down control node and the second pull-down node;
第三下拉控制单元，连接所述第一电源信号端、所述第一下拉控制节点、所述第一下拉节点，用于响应所述第一电源信号以将所述第一电源信号传输至所述第一下拉控制节点和所述第一下拉节点；A third pull-down control unit, connected to the first power signal terminal, the first pull-down control node, and the first pull-down node, for transmitting the first power signal in response to the first power signal to said first pull-down control node and said first pull-down node;
第四下拉控制单元，连接所述第二电源信号端、所述第二下拉控制节点、所述第二下拉节点，用于响应所述第二电源信号以将所述第二电源信号传输至所述第二下拉控制节点和所述第二下拉节点。A fourth pull-down control unit, connected to the second power signal terminal, the second pull-down control node, and the second pull-down node, for transmitting the second power signal to the second power signal in response to the second power signal The second pull-down control node and the second pull-down node.
本公开的一种示例性实施例中，In an exemplary embodiment of the present disclosure,
所述第一下拉控制单元包括：The first pull-down control unit includes:
第三开关元件，控制端连接所述上拉节点、第一端连接所述第一下拉控制节点、第二端连接所述参考信号端；A third switch element, the control end of which is connected to the pull-up node, the first end of which is connected to the first pull-down control node, and the second end of which is connected to the reference signal end;
第四开关元件，控制端连接所述上拉节点、第一端连接所述第一下拉节点、第二端连接所述参考信号端；For a fourth switch element, the control end is connected to the pull-up node, the first end is connected to the first pull-down node, and the second end is connected to the reference signal end;
所述第二下拉控制单元包括：The second pull-down control unit includes:
第五开关元件，控制端连接所述上拉节点、第一端连接所述第二下拉控制节点、第二端连接所述参考信号端；For a fifth switch element, the control end is connected to the pull-up node, the first end is connected to the second pull-down control node, and the second end is connected to the reference signal end;
第六开关元件，控制端连接所述上拉节点、第一端连接所述第二下拉节点、第二端连接所述参考信号端；The sixth switch element, the control terminal is connected to the pull-up node, the first terminal is connected to the second pull-down node, and the second terminal is connected to the reference signal terminal;
所述第三下拉控制单元包括：The third pull-down control unit includes:
第七开关元件，控制端和第一端连接所述第一电源信号端、第二端连接所述第一下拉控制节点；A seventh switch element, the control terminal and the first terminal are connected to the first power signal terminal, and the second terminal is connected to the first pull-down control node;
第八开关元件，控制端连接所述第一下拉控制节点、第一端连接所述第一电源信号端、第二端连接所述第一下拉节点；An eighth switch element, the control terminal is connected to the first pull-down control node, the first terminal is connected to the first power signal terminal, and the second terminal is connected to the first pull-down node;
所述第四下拉控制单元包括：The fourth pull-down control unit includes:
第九开关元件，控制端和第一端连接所述第二电源信号端、第二端连接所述第二下拉控制节点；The ninth switch element, the control terminal and the first terminal are connected to the second power signal terminal, and the second terminal is connected to the second pull-down control node;
第十开关元件，控制端连接所述第二下拉控制节点、第一端连接所述第二电源信号端、第二端连接所述第二下拉节点。The tenth switch element has a control terminal connected to the second pull-down control node, a first terminal connected to the second power signal terminal, and a second terminal connected to the second pull-down node.
本公开的一种示例性实施例中，所述第一下拉模块包括：In an exemplary embodiment of the present disclosure, the first pull-down module includes:
第十一开关元件，控制端连接所述第一下拉节点、第一端连接所述信号输出端、第二端连接所述参考信号端；An eleventh switch element, the control terminal is connected to the first pull-down node, the first terminal is connected to the signal output terminal, and the second terminal is connected to the reference signal terminal;
第十二开关元件，控制端连接所述第二下拉节点、第一端连接所述信号输出端、第二端连接所述参考信号端。In a twelfth switch element, a control terminal is connected to the second pull-down node, a first terminal is connected to the signal output terminal, and a second terminal is connected to the reference signal terminal.
本公开的一种示例性实施例中，所述输出模块包括：In an exemplary embodiment of the present disclosure, the output module includes:
第十三开关元件，控制端连接所述上拉节点、第一端连接所述时钟信号端、第二端连接所述信号输出端；A thirteenth switch element, the control terminal is connected to the pull-up node, the first terminal is connected to the clock signal terminal, and the second terminal is connected to the signal output terminal;
存储电容，连接在所述上拉节点和所述信号输出端之间。The storage capacitor is connected between the pull-up node and the signal output terminal.
本公开的一种示例性实施例中，所述移位寄存器单元还包括：In an exemplary embodiment of the present disclosure, the shift register unit further includes:
复位模块，连接复位信号端、所述参考信号端、所述上拉节点、所述信号输出端，用于响应复位信号以将参考信号传输至所述上拉节点和所述信号输出端。A reset module, connected to a reset signal terminal, the reference signal terminal, the pull-up node, and the signal output terminal, is used for transmitting a reference signal to the pull-up node and the signal output terminal in response to a reset signal.
本公开的一种示例性实施例中，所述复位信号端包括第一复位信号端和第二复位信号端；In an exemplary embodiment of the present disclosure, the reset signal terminal includes a first reset signal terminal and a second reset signal terminal;
所述复位模块包括：The reset module includes:
第十四开关元件，控制端连接所述第一复位信号端、第一端连接所述上拉节点、第二端连接所述参考信号端；A fourteenth switch element, the control terminal is connected to the first reset signal terminal, the first terminal is connected to the pull-up node, and the second terminal is connected to the reference signal terminal;
第十五开关元件，控制端连接所述第二复位信号端、第一端连接所述信号输出端、第二端连接所述参考信号端。In a fifteenth switch element, a control terminal is connected to the second reset signal terminal, a first terminal is connected to the signal output terminal, and a second terminal is connected to the reference signal terminal.
本公开的一种示例性实施例中，包括多个级联的权利要求1-8任一项所述的移位寄存器单元；In an exemplary embodiment of the present disclosure, a plurality of cascaded shift register units according to any one of claims 1-8 are included;
在复位信号端包括第一复位信号端和第二复位信号端时，When the reset signal terminal includes a first reset signal terminal and a second reset signal terminal,
第N-3级所述移位寄存器单元的信号输出端连接第N级所述移位寄存器单元的信号输入端；The signal output end of the shift register unit of the N-3th stage is connected to the signal input end of the shift register unit of the Nth stage;
第N+3级所述移位寄存器单元的信号输出端连接第N级所述移位寄存器单元的第二复位信号端；The signal output end of the shift register unit in the N+3th stage is connected to the second reset signal end of the shift register unit in the Nth stage;
第N+4级所述移位寄存器单元的信号输出端连接第N级所述移位寄存器单元的第一复位信号端；The signal output end of the shift register unit in the N+4th stage is connected to the first reset signal end of the shift register unit in the Nth stage;
其中，N为整数且N≥1。Wherein, N is an integer and N≥1.
本公开的一种示例性实施例中，所述周边区域设置有权利要求9所述的移位寄存器电路。In an exemplary embodiment of the present disclosure, the peripheral area is provided with the shift register circuit as claimed in claim 9 .
本公开示例性实施方式提供一种移位寄存器单元、移位寄存器电路、以及显示面板。该移位寄存器的第二下拉模块仅包括第一开关元件，其控制端连接时钟信号端，第一端连接信号输出端，第二端连接上拉节点，基于此，通过时钟信号周期性打开第二下拉模块(即，第一开关元件)，间接的通过信号输出端对上拉节点进行降噪，相比于现有技术，在保证了移位寄存器单元的信耐度和正常输出的基础上，在对上拉节点的降噪中减少了一个开关元件节省了空间。Exemplary embodiments of the present disclosure provide a shift register unit, a shift register circuit, and a display panel. The second pull-down module of the shift register only includes the first switch element, the control end of which is connected to the clock signal end, the first end is connected to the signal output end, and the second end is connected to the pull-up node. Based on this, the clock signal is used to periodically turn on the first switching element. The second pull-down module (that is, the first switch element) indirectly reduces the noise of the pull-up node through the signal output terminal, compared with the prior art, on the basis of ensuring the reliability and normal output of the shift register unit , reducing the noise of the pull-up node by reducing a switching element to save space.
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.
附图说明Description of drawings
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure. Apparently, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to these drawings without creative efforts.
图1示意性示出相关技术中移位寄存器单元的结构示意图；FIG. 1 schematically shows a schematic structural diagram of a shift register unit in the related art;
图2示意性示出本公开示例性实施例中移位寄存器单元的时序信号图；FIG. 2 schematically shows a timing signal diagram of a shift register unit in an exemplary embodiment of the present disclosure;
图3示意性示出本公开示例性实施例中第一电源信号和第二电源信号的时序信号图；FIG. 3 schematically shows a timing signal diagram of a first power supply signal and a second power supply signal in an exemplary embodiment of the present disclosure;
图4示意性示出本公开示例性实施例中移位寄存器单元的结构框图；Fig. 4 schematically shows a structural block diagram of a shift register unit in an exemplary embodiment of the present disclosure;
图5示意性示出本公开示例性实施例中移位寄存器单元的结构示意图；FIG. 5 schematically shows a schematic structural diagram of a shift register unit in an exemplary embodiment of the present disclosure;
图6示意性示出本公开示例性实施例中移位寄存器单元的输出信号模拟效果图；FIG. 6 schematically shows a simulation effect diagram of an output signal of a shift register unit in an exemplary embodiment of the present disclosure;
图7示意性示出本公开示例性实施例中移位寄存器电路的级联结构图。FIG. 7 schematically shows a cascaded structure diagram of a shift register circuit in an exemplary embodiment of the present disclosure.
具体实施方式Detailed ways
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different network and/or processor means and/or microcontroller means.
图1中示出了一种相关的现有技术中的移位寄存器单元，该移位寄存器单元可以包括：输入模块10、下拉控制模块30、第一下拉模块40、第二下拉模块50、输出模块20以及复位模块60，其中：A related prior art shift register unit is shown in FIG. 1, and the shift register unit may include: an input module 10, a pull-down control module 30, a first pull-down module 40, a second pull-down module 50, Output module 20 and reset module 60, wherein:
输入模块10可以包括：The input module 10 may include:
第二开关元件M2，控制端和第一端均连接信号输入端Input、第二端连接上拉节点PU。For the second switch element M2, the control terminal and the first terminal are both connected to the signal input terminal Input, and the second terminal is connected to the pull-up node PU.
下拉控制模块30可以包括：第一下拉控制单元31、第二下拉控制单元32、第三下拉控制单元33以及第四下拉控制单元34，其中：The pull-down control module 30 may include: a first pull-down control unit 31, a second pull-down control unit 32, a third pull-down control unit 33, and a fourth pull-down control unit 34, wherein:
第一下拉控制单元31可以包括：The first pull-down control unit 31 may include:
第三开关元件M3，控制端连接上拉节点PU、第一端连接第一下拉控制节点PDCN1、第二端连接参考信号端VSS；The third switch element M3 has a control terminal connected to the pull-up node PU, a first terminal connected to the first pull-down control node PDCN1, and a second terminal connected to the reference signal terminal VSS;
第四开关元件M4，控制端连接上拉节点PU、第一端连接第一下拉节点PD1、第二端连接参考信号端VSS；The fourth switch element M4 has a control terminal connected to the pull-up node PU, a first terminal connected to the first pull-down node PD1, and a second terminal connected to the reference signal terminal VSS;
第二下拉控制单元32可以包括：The second pull-down control unit 32 may include:
第五开关元件M5，控制端连接上拉节点PU、第一端连接第二下拉控制节点PDCN2、第二端连接参考信号端VSS；The fifth switch element M5 has a control terminal connected to the pull-up node PU, a first terminal connected to the second pull-down control node PDCN2, and a second terminal connected to the reference signal terminal VSS;
第六开关元件M6，控制端连接上拉节点PU、第一端连接第二下拉节点PD2、第二端连接参考信号端VSS。The sixth switch element M6 has a control terminal connected to the pull-up node PU, a first terminal connected to the second pull-down node PD2, and a second terminal connected to the reference signal terminal VSS.
第三下拉控制单元33可以包括：The third pull-down control unit 33 may include:
第七开关元件M7，控制端和第一端连接第一电源信号端VDD1、第二端连接第一下拉控制节点PDCN1；The seventh switch element M7, the control terminal and the first terminal are connected to the first power signal terminal VDD1, and the second terminal is connected to the first pull-down control node PDCN1;
第八开关元件M8，控制端连接第一下拉控制节点PDCN1、第一端连接第一电源信号端VDD1、第二端连接第一下拉节点PD1。The eighth switch element M8 has a control terminal connected to the first pull-down control node PDCN1, a first terminal connected to the first power signal terminal VDD1, and a second terminal connected to the first pull-down node PD1.
第四下拉控制单元34可以包括：The fourth pull-down control unit 34 may include:
第九开关元件M9，控制端和第一端连接第二电源信号端VDD2、第二端连接第二下拉控制节点PDCN2；The ninth switch element M9, the control terminal and the first terminal are connected to the second power signal terminal VDD2, and the second terminal is connected to the second pull-down control node PDCN2;
第十开关元件M10，控制端连接第二下拉控制节点PDCN2、第一端连接第二电源信号端VDD2、第二端连接第二下拉节点PD2。The tenth switching element M10 has a control terminal connected to the second pull-down control node PDCN2, a first terminal connected to the second power signal terminal VDD2, and a second terminal connected to the second pull-down node PD2.
第一下拉模块40可以包括：The first pull-down module 40 may include:
第十一开关元件M11，控制端连接第一下拉节点PD1、第一端连接信号输出端Output、第二端连接参考信号端VSS；The eleventh switch element M11, the control terminal is connected to the first pull-down node PD1, the first terminal is connected to the signal output terminal Output, and the second terminal is connected to the reference signal terminal VSS;
第十二开关元件M12，控制端连接第二下拉节点PD2、第一端连接信号输出端Output、第二端连接参考信号端VSS。The twelfth switch element M12 has a control terminal connected to the second pull-down node PD2, a first terminal connected to the signal output terminal Output, and a second terminal connected to the reference signal terminal VSS.
第二下拉模块50可以包括：The second pull-down module 50 may include:
第一开关元件M1，控制端连接第二下拉节点PD2，第一端连接上拉节点PU，第二端连接参考信号端VSS；The first switch element M1 has a control terminal connected to the second pull-down node PD2, a first terminal connected to the pull-up node PU, and a second terminal connected to the reference signal terminal VSS;
第十六开关元件M16，控制端连接第一下拉节点PD1，第一端连接上拉节点PU，第二端连接参考信号端VSS。The sixteenth switch element M16 has a control terminal connected to the first pull-down node PD1, a first terminal connected to the pull-up node PU, and a second terminal connected to the reference signal terminal VSS.
输出模块20可以包括：Output module 20 may include:
第十三开关元件M13，控制端连接上拉节点PU、第一端连接时钟信号端CLK、第二端连接信号输出端Output；The thirteenth switch element M13, the control terminal is connected to the pull-up node PU, the first terminal is connected to the clock signal terminal CLK, and the second terminal is connected to the signal output terminal Output;
存储电容C，连接在上拉节点PU和信号输出端Output之间。The storage capacitor C is connected between the pull-up node PU and the signal output terminal Output.
复位模块60可以包括：Reset module 60 may include:
第十四开关元件M14，控制端连接第一复位信号端Reset1、第一端连接上拉节点PU、第二端连接参考信号端VSS；The fourteenth switch element M14, the control terminal is connected to the first reset signal terminal Reset1, the first terminal is connected to the pull-up node PU, and the second terminal is connected to the reference signal terminal VSS;
第十五开关元件M15，控制端连接第二复位信号端Reset2、第一端连接信号输出端Output、第二端连接参考信号端VSS。The fifteenth switching element M15 has a control terminal connected to the second reset signal terminal Reset2, a first terminal connected to the signal output terminal Output, and a second terminal connected to the reference signal terminal VSS.
基于上述结构，以所有开关元件均为NMOS为例，结合图2所示的时序信号图对图1中的移位寄存器单元的工作过程进行具体的说明。其中，参考信号端VSS的参考信号为低电平信号VL；如图3所示，第一电源信号端VDD1的第一电源信号和第二电源信号端VDD2的第二电源信号互为同频反向信号，即始终有一个在工作，这里以第一电源信号端VDD1的第一电源信号的高电平时段为例进行说明。Based on the above structure, taking all switching elements as NMOS as an example, the working process of the shift register unit in FIG. 1 will be described in detail in combination with the timing signal diagram shown in FIG. 2 . Wherein, the reference signal of the reference signal terminal VSS is a low-level signal VL; as shown in FIG. Direction signals, that is, one of them is always working. Here, the high-level period of the first power signal of the first power signal terminal VDD1 is taken as an example for illustration.
在像素保持阶段(即T1阶段)，第一复位信号端Reset1的第一复位信号、第二复位信号端Reset2的第二复位信号、信号输入端Input的输入信号、第二电源信号端VDD2的第二电源信号均为低电平VL，第一电源信号端VDD1的第一电源信号为高电平VH，此时，第七开关元件M7在第一电源信号的作用下导通，将第一电源信号传输至第一下拉控制节点PDCN1，第八开关元件M8在传输至第一下拉控制节点PDCN1的第一电源信号的作用下导通，将第一电源信号传输至第一下拉节点PD1，第十六开关元件M16和第十一开关元件M11在传输至第一下拉节点PD1的第一电源信号的作用下导通，将参考信号分别通过第十六开关元件M16和第十一开关元件M11传输至上拉节点PU和信号输出端Output，以对上拉节点PU和信号输出端Output持续降噪，即上拉节点PU的信号和信号输出端Output的输出信号均为低电平VL。In the pixel holding phase (i.e. T1 phase), the first reset signal of the first reset signal terminal Reset1, the second reset signal of the second reset signal terminal Reset2, the input signal of the signal input terminal Input, the second power supply signal terminal VDD2 of the first reset signal Both power supply signals are low level VL, and the first power supply signal of the first power supply signal terminal VDD1 is high level VH. At this time, the seventh switching element M7 is turned on under the action of the first power supply signal, and the first power supply The signal is transmitted to the first pull-down control node PDCN1, the eighth switch element M8 is turned on under the action of the first power signal transmitted to the first pull-down control node PDCN1, and the first power signal is transmitted to the first pull-down node PD1 , the sixteenth switch element M16 and the eleventh switch element M11 are turned on under the action of the first power signal transmitted to the first pull-down node PD1, and the reference signal passes through the sixteenth switch element M16 and the eleventh switch respectively The element M11 is transmitted to the pull-up node PU and the signal output terminal Output to continuously reduce the noise of the pull-up node PU and the signal output terminal Output, that is, the signal of the pull-up node PU and the output signal of the signal output terminal Output are both low level VL.
在充电阶段(即T2阶段)，信号输入端Input的输入信号为高点平VH，第二开关元件M2在输入信号的作用下导通，将输入信号传输至上拉节点PU，以对电容C充电，第三开关元件M3、第四开关元件M4、第五开关元件M5、第六开关元件M6分别在传输至上拉节点PU的输入信号的作用下导通，将参考信号分别通过第三开关元件M3、第四开关元件M4、第五开关元件M5、第六开关元件M6传输至第一下拉控制节点PDCN1、第一下拉节点PD1、第二下拉控制节点PDCN2、第二下拉节点PD2，同时，第十三开关元件M13在传输至上拉节点PU的输入信号的作用下导通，将时钟信号端CLK的时钟信号传输至信号输出端Output，由于此时时钟信号为低电平，信号输出端Output的输出信号也为低电平VL。In the charging stage (that is, the T2 stage), the input signal of the signal input terminal Input is a high level VH, the second switching element M2 is turned on under the action of the input signal, and the input signal is transmitted to the pull-up node PU to charge the capacitor C , the third switch element M3, the fourth switch element M4, the fifth switch element M5, and the sixth switch element M6 are respectively turned on under the action of the input signal transmitted to the pull-up node PU, and the reference signal is respectively passed through the third switch element M3 , the fourth switch element M4, the fifth switch element M5, and the sixth switch element M6 are transmitted to the first pull-down control node PDCN1, the first pull-down node PD1, the second pull-down control node PDCN2, and the second pull-down node PD2. At the same time, The thirteenth switching element M13 is turned on under the action of the input signal transmitted to the pull-up node PU, and transmits the clock signal of the clock signal terminal CLK to the signal output terminal Output. Since the clock signal is at a low level at this time, the signal output terminal Output The output signal is also low level VL.
在自举阶段(即T3阶段)，时钟信号端CLK的时钟信号为高电平VH，在上拉节点PU的作用下，第十三开关元件M13导通，将时钟信号传输至信号输出端Output，此时信号输出端Output的输出信号为高电平信号VH，同时通过存储电容C的自举作用使得上拉节点PU的电位自举至大约2VH。In the bootstrap stage (that is, the T3 stage), the clock signal at the clock signal terminal CLK is at a high level VH, and under the action of the pull-up node PU, the thirteenth switching element M13 is turned on, and the clock signal is transmitted to the signal output terminal Output At this time, the output signal of the signal output terminal Output is a high-level signal VH, and at the same time, the potential of the pull-up node PU is bootstrapped to about 2VH through the bootstrap function of the storage capacitor C.
在复位阶段(即T4阶段)，时钟信号端CLK的时钟信号为低电平VL，此时信号输出端Output的输出信号为低电平信号VL，同时，由于时钟信号为低电平VL，通过存储电容C的自举作用使得上拉节点PU的电位自举至VH。In the reset phase (that is, the T4 phase), the clock signal of the clock signal terminal CLK is a low level VL, and at this time, the output signal of the signal output terminal Output is a low level signal VL, and at the same time, because the clock signal is a low level VL, through The bootstrap function of the storage capacitor C makes the potential of the pull-up node PU bootstrap to VH.
需要说明的是，第二电源信号端VDD2的第二电源信号的高电平时段的移位寄存器单元的工作原理与上述第一电源信号端VDD1的第一电源信号的高电平时段的移位寄存器单元的工作原理相同，因此此处不再举例说明。It should be noted that the working principle of the shift register unit during the high-level period of the second power supply signal at the second power supply signal terminal VDD2 is the same as the shift of the high-level period of the first power supply signal at the first power supply signal terminal VDD1. The register unit works the same, so no examples are given here.
由上可知，在像素保持阶段(即T1阶段)，第一电源信号端VDD1的第一电源信号和第二电源信号端VDD2的第二电源信号交替对上拉节点PU和信号输出端Output持续降噪，即通过交替打开的第一开关元件M1和第十六开关元件M16对上拉节点PU进行降噪，通过交替打开的第十一开关元件M11和第十二开关元件M12对信号输出端Output持续降噪，保证了移位寄存器单元的信耐度，在充电阶段(即T2阶段)、自举阶段(即T3阶段)以及复位阶段(即T4阶段)，信号输出端Output的输出信号由时钟信号端CLK的时钟信号决定，保证了移位寄存器单元的正常输出。然而，上述结构的移位寄存器单元中开关元件的数量较多，占用空间大。It can be seen from the above that in the pixel holding phase (that is, the T1 phase), the first power signal of the first power signal terminal VDD1 and the second power signal of the second power signal terminal VDD2 alternately continuously lower the pull-up node PU and the signal output terminal Output. Noise, that is, through the alternately turned on first switch element M1 and the sixteenth switch element M16 to reduce the noise of the pull-up node PU, through the alternately turned on eleventh switch element M11 and the twelfth switch element M12 to the signal output terminal Output Continuous noise reduction ensures the reliability of the shift register unit. In the charging phase (ie T2 phase), bootstrap phase (ie T3 phase) and reset phase (ie T4 phase), the output signal of the signal output terminal Output is controlled by the clock The clock signal of the signal terminal CLK is determined to ensure the normal output of the shift register unit. However, the number of switching elements in the shift register unit with the above structure is relatively large and occupies a large space.
为了解决现有技术中移位寄存器单元中开关元件数量较多，占用空间大的问题，本示例实施方式提供了一种移位寄存器单元，用于提供栅极驱动信号；如图4和图5所示，所述移位寄存器单元可以包括：In order to solve the problem of large number of switching elements and large space occupation in the shift register unit in the prior art, this example embodiment provides a shift register unit for providing gate drive signals; as shown in Figure 4 and Figure 5 As shown, the shift register unit may include:
输入模块10，连接信号输入端Input、上拉节点PU，用于响应输入信号以将所述输入信号传输至所述上拉节点PU；The input module 10 is connected to the signal input terminal Input and the pull-up node PU, and is used to transmit the input signal to the pull-up node PU in response to the input signal;
输出模块20，连接所述上拉节点PU、时钟信号端CLK、信号输出端Output，用于响应所述上拉节点PU的电压信号以将时钟信号传输至所述信号输出端Output；The output module 20 is connected to the pull-up node PU, the clock signal terminal CLK, and the signal output terminal Output, and is used to transmit the clock signal to the signal output terminal Output in response to the voltage signal of the pull-up node PU;
下拉控制模块30，连接所述上拉节点PU、参考信号端VSS、第一下拉节点PD1、第二下拉节点PD2、第一电源信号端VDD1、第二电源信号端VDD2，用于响应所述上拉节点PU的电压信号以将参考信号分别传输至所述第一下拉节点PD1和第二下拉节点PD2，以及交替响应第一电源信号和第二电源信号，将所述第一电源信号传输至所述第一下拉节点PD1，将所述第二电源信号传输至所述第二下拉节点PD2；The pull-down control module 30 is connected to the pull-up node PU, the reference signal terminal VSS, the first pull-down node PD1, the second pull-down node PD2, the first power signal terminal VDD1, and the second power signal terminal VDD2, for responding to the pull up the voltage signal of the node PU to transmit the reference signal to the first pull-down node PD1 and the second pull-down node PD2 respectively, and alternately respond to the first power signal and the second power signal to transmit the first power signal to the first pull-down node PD1, and transmit the second power signal to the second pull-down node PD2;
具体的，所述下拉控制模块30可以包括：Specifically, the pull-down control module 30 may include:
第一下拉控制单元31，连接所述上拉节点PU、所述参考信号端VSS、第一下拉控制节点PDCN1、所述第一下拉节点PD1，用于响应所述上拉节点PU的电压信号以将所述参考信号分别传输至所述第一下拉控制节点PDCN1和所述第一下拉节点PD1；The first pull-down control unit 31 is connected to the pull-up node PU, the reference signal terminal VSS, the first pull-down control node PDCN1, and the first pull-down node PD1, for responding to the pull-up node PU voltage signal to transmit the reference signal to the first pull-down control node PDCN1 and the first pull-down node PD1 respectively;
第二下拉控制单元32，连接所述上拉节点PU、所述参考信号端VSS、第二下拉控制节点PDCN2、所述第二下拉节点PD2，用于响应所述上拉节点PU的电压信号以将所述参考信号分别传输至所述第二下拉控制节点PDCN2和所述第二下拉节点PD2；The second pull-down control unit 32 is connected to the pull-up node PU, the reference signal terminal VSS, the second pull-down control node PDCN2, and the second pull-down node PD2, for responding to the voltage signal of the pull-up node PU to transmitting the reference signal to the second pull-down control node PDCN2 and the second pull-down node PD2 respectively;
第三下拉控制单元33，连接第一电源信号端VDD1、所述第一下拉控制节点PDCN1、所述第一下拉节点PD1，用于响应所述第一电源信号以将所述第一电源信号传输至所述第一下拉控制节点PDCN1和所述第一下拉节点PD1；The third pull-down control unit 33 is connected to the first power signal terminal VDD1, the first pull-down control node PDCN1, and the first pull-down node PD1, and is used to respond to the first power signal to turn the first power supply signal transmission to the first pull-down control node PDCN1 and the first pull-down node PD1;
第四下拉控制单元34，连接第二电源信号端VDD2、所述第二下拉控制节点PDCN2、所述第二下拉节点PD2，用于响应所述第二电源信号以将所述第二电源信号传输至所述第二下拉控制节点PDCN2和所述第二下拉节点PD2。The fourth pull-down control unit 34 is connected to the second power signal terminal VDD2, the second pull-down control node PDCN2, and the second pull-down node PD2, and is used to transmit the second power signal in response to the second power signal to the second pull-down control node PDCN2 and the second pull-down node PD2.
第一下拉模块40，连接所述第一下拉节点PD1、所述第二下拉节点PD2、所述参考信号端VSS、所述信号输出端Output，用于交替响应所述第一下拉节点PD1和所述第二下拉节点PD2的电压信号以将所述参考信号传输至所述信号输出端Output；The first pull-down module 40 is connected to the first pull-down node PD1, the second pull-down node PD2, the reference signal terminal VSS, and the signal output terminal Output, for alternately responding to the first pull-down node PD1 and the voltage signal of the second pull-down node PD2 to transmit the reference signal to the signal output terminal Output;
第二下拉模块50，连接所述上拉节点PU、所述信号输出端Output所述时钟信号端CKL，用于响应所述时钟信号以将所述信号输出端Output的电压信号周期性的传输至所述上拉节点PU；The second pull-down module 50 is connected to the pull-up node PU, the signal output terminal Output and the clock signal terminal CKL, and is used to periodically transmit the voltage signal of the signal output terminal Output to the The pull-up node PU;
其中，所述第二下拉模块50包括第一开关元件M1，控制端连接所述时钟信号端CKL，第一端连接所述信号输出端Output，第二端连接所述上拉节点PU；如图3所示，所述第一电源信号VDD1与所述第二电源信号VDD2为同频反向信号。Wherein, the second pull-down module 50 includes a first switch element M1, the control terminal is connected to the clock signal terminal CKL, the first terminal is connected to the signal output terminal Output, and the second terminal is connected to the pull-up node PU; 3, the first power signal VDD1 and the second power signal VDD2 are the same frequency and opposite signals.
此外，所述移位寄存器单元还可以包括：In addition, the shift register unit may also include:
复位模块60，连接复位信号端Reset、所述参考信号端VSS、所述上拉节点PU、所述信号输出端Output，用于响应复位信号以将参考信号传输至所述上拉节点PU和所述信号输出端Output。The reset module 60 is connected to the reset signal terminal Reset, the reference signal terminal VSS, the pull-up node PU, and the signal output terminal Output, and is used to transmit the reference signal to the pull-up node PU and the signal output terminal Output in response to the reset signal. The above-mentioned signal output terminal Output.
需要说明的是，所述输入信号为信号输入端Input的电压信号，所述时钟信号为时钟信号端CLK的电压信号，所述复位信号为复位信号端Reset的电压信号，所述参考信号为参考信号端VSS的电压信号，第一电源信号为第一电源信号端VDD1的电压信号，第二电源信号第二电源信号端VDD2的电压信号。It should be noted that the input signal is the voltage signal of the signal input terminal Input, the clock signal is the voltage signal of the clock signal terminal CLK, the reset signal is the voltage signal of the reset signal terminal Reset, and the reference signal is the reference The voltage signal of the signal terminal VSS, the first power signal is the voltage signal of the first power signal terminal VDD1, and the second power signal is the voltage signal of the second power signal terminal VDD2.
本公开示例性实施方式所提供的移位寄存器单元的第二下拉模块50仅包括第一开关元件M1，其控制端连接时钟信号端CLK，第一端连接信号输出端Output，第二端连接上拉节点PU，基于此，通过时钟信号周期性打开第二下拉模块50(即，第一开关元件M1)，间接的通过信号输出端Output对上拉节点PU进行降噪，相比于现有技术，在保证了移位寄存器单元的信耐度和正常输出的基础上，在对上拉节点PU的降噪中减少了一个开关元件(即图1中的第十六开关元件M16)节省了空间。The second pull-down module 50 of the shift register unit provided by the exemplary embodiment of the present disclosure only includes the first switch element M1, the control terminal of which is connected to the clock signal terminal CLK, the first terminal is connected to the signal output terminal Output, and the second terminal is connected to the The pull-up node PU, based on this, periodically turns on the second pull-down module 50 (that is, the first switch element M1) through the clock signal, and indirectly performs noise reduction on the pull-up node PU through the signal output terminal Output, compared with the prior art , on the basis of ensuring the reliability and normal output of the shift register unit, one switching element (ie, the sixteenth switching element M16 in Figure 1) is reduced in the noise reduction of the pull-up node PU to save space .
下面，结合图5对移位寄存器单元的结构进行详细的说明。Next, the structure of the shift register unit will be described in detail with reference to FIG. 5 .
所述输入模块10可以包括：The input module 10 may include:
第二开关元件M2，控制端和第一端均连接所述信号输入端Input、第二端连接所述上拉节点PU。For the second switch element M2, the control terminal and the first terminal are both connected to the signal input terminal Input, and the second terminal is connected to the pull-up node PU.
所述第一下拉控制单元31可以包括：The first pull-down control unit 31 may include:
第三开关元件M3，控制端连接所述上拉节点PU、第一端连接所述第一下拉控制节点PDCN1、第二端连接所述参考信号端VSS；The third switch element M3 has a control terminal connected to the pull-up node PU, a first terminal connected to the first pull-down control node PDCN1, and a second terminal connected to the reference signal terminal VSS;
第四开关元件M4，控制端连接所述上拉节点PU、第一端连接所述第一下拉节点PD1、第二端连接所述参考信号端VSS；The fourth switch element M4 has a control terminal connected to the pull-up node PU, a first terminal connected to the first pull-down node PD1, and a second terminal connected to the reference signal terminal VSS;
所述第二下拉控制单元32可以包括：The second pull-down control unit 32 may include:
第五开关元件M5，控制端连接所述上拉节点PU、第一端连接所述第二下拉控制节点PDCN2、第二端连接所述参考信号端VSS；The fifth switch element M5 has a control terminal connected to the pull-up node PU, a first terminal connected to the second pull-down control node PDCN2, and a second terminal connected to the reference signal terminal VSS;
第六开关元件M6，控制端连接所述上拉节点PU、第一端连接所述第二下拉节点PD2、第二端连接所述参考信号端VSS。The sixth switch element M6 has a control terminal connected to the pull-up node PU, a first terminal connected to the second pull-down node PD2, and a second terminal connected to the reference signal terminal VSS.
所述第三下拉控制单元33可以包括：The third pull-down control unit 33 may include:
第七开关元件M7，控制端和第一端连接所述第一电源信号端VDD1、第二端连接所述第一下拉控制节点PDCN1；The seventh switch element M7, the control terminal and the first terminal are connected to the first power signal terminal VDD1, and the second terminal is connected to the first pull-down control node PDCN1;
第八开关元件M8，控制端连接所述第一下拉控制节点PDCN1、第一端连接所述第一电源信号端VDD1、第二端连接所述第一下拉节点PD1。The eighth switch element M8 has a control terminal connected to the first pull-down control node PDCN1, a first terminal connected to the first power signal terminal VDD1, and a second terminal connected to the first pull-down node PD1.
所述第四下拉控制单元34可以包括：The fourth pull-down control unit 34 may include:
第九开关元件M9，控制端和第一端连接所述第二电源信号端VDD2、第二端连接所述第二下拉控制节点PDCN2；The ninth switch element M9, the control terminal and the first terminal are connected to the second power signal terminal VDD2, and the second terminal is connected to the second pull-down control node PDCN2;
第十开关元件M10，控制端连接所述第二下拉控制节点PDCN2、第一端连接所述第二电源信号端VDD2、第二端连接所述第二下拉节点PD2。The tenth switch element M10 has a control terminal connected to the second pull-down control node PDCN2, a first terminal connected to the second power signal terminal VDD2, and a second terminal connected to the second pull-down node PD2.
所述第一下拉模块40可以包括：The first pull-down module 40 may include:
第十一开关元件M11，控制端连接所述第一下拉节点PD1、第一端连接所述信号输出端Output、第二端连接所述参考信号端VSS；The eleventh switch element M11, the control terminal is connected to the first pull-down node PD1, the first terminal is connected to the signal output terminal Output, and the second terminal is connected to the reference signal terminal VSS;
第十二开关元件M12，控制端连接所述第二下拉节点PD2、第一端连接所述信号输出端Output、第二端连接所述参考信号端VSS。The twelfth switch element M12 has a control terminal connected to the second pull-down node PD2, a first terminal connected to the signal output terminal Output, and a second terminal connected to the reference signal terminal VSS.
所述输出模块20可以包括：The output module 20 may include:
第十三开关元件M13，控制端连接所述上拉节点PU、第一端连接所述时钟信号端CLK、第二端连接所述信号输出端Output；The thirteenth switch element M13, the control terminal is connected to the pull-up node PU, the first terminal is connected to the clock signal terminal CLK, and the second terminal is connected to the signal output terminal Output;
存储电容C，连接在所述上拉节点PU和所述信号输出端Output之间。The storage capacitor C is connected between the pull-up node PU and the signal output terminal Output.
所述复位信号端Reset包括第一复位信号端Reset1和第二复位信号端Reset2；The reset signal terminal Reset includes a first reset signal terminal Reset1 and a second reset signal terminal Reset2;
所述复位模块60可以包括：The reset module 60 may include:
第十四开关元件M14，控制端连接所述第一复位信号端Reset1、第一端连接所述上拉节点PU、第二端连接所述参考信号端VSS；The fourteenth switch element M14, the control terminal is connected to the first reset signal terminal Reset1, the first terminal is connected to the pull-up node PU, and the second terminal is connected to the reference signal terminal VSS;
第十五开关元件M15，控制端连接所述第二复位信号端Reset2、第一端连接所述信号输出端Output、第二端连接所述参考信号端VSS。The fifteenth switch element M15 has a control terminal connected to the second reset signal terminal Reset2, a first terminal connected to the signal output terminal Output, and a second terminal connected to the reference signal terminal VSS.
在本示例实施方式中，所有开关元件均可以采用MOS(Metal OxideSemiconductor，金属-氧化物-半导体场效应晶体管)场效应晶体管，其具体可以均采用P型MOS管或者均采用N型MOS管。需要说明的是：针对不同的晶体管类型，各个信号端的电平信号需要相应的调整变化。In this exemplary embodiment, all switching elements may use MOS (Metal Oxide Semiconductor, Metal-Oxide-Semiconductor Field Effect Transistor) field effect transistors, which may specifically all use P-type MOS transistors or all use N-type MOS transistors. It should be noted that: for different transistor types, the level signals of each signal terminal need to be adjusted and changed accordingly.
基于上述结构，以所有开关元件均为NMOS为例，结合图2所示的时序信号图对图5中的移位寄存器单元的工作过程进行具体的说明。其中，参考信号端VSS的参考信号为低电平信号VL；第一电源信号端VDD1的第一电源信号和第二电源信号端VDD2的第二电源信号互为同频反向信号，即始终有一个在工作，这里以第一电源信号端VDD1的第一电源信号的高电平时段为例进行说明。Based on the above structure, taking all switching elements as NMOS as an example, the working process of the shift register unit in FIG. 5 will be described in detail in combination with the timing signal diagram shown in FIG. 2 . Wherein, the reference signal of the reference signal terminal VSS is a low-level signal VL; the first power signal of the first power signal terminal VDD1 and the second power signal of the second power signal terminal VDD2 are mutually same-frequency reverse signals, that is, there is always One is working. Here, the high-level period of the first power signal of the first power signal terminal VDD1 is taken as an example for illustration.
在像素保持阶段(即T1阶段)，第一复位信号端Reset1的第一复位信号、第二复位信号端Reset2的第二复位信号、信号输入端Input的输入信号、第二电源信号端VDD2的第二电源信号均为低电平VL，第一电源信号端VDD1的第一电源信号和时钟信号端CLK的时钟信号均为高电平VH，此时，第七开关元件M7在第一电源信号的作用下导通，将第一电源信号传输至第一下拉控制节点PDCN1，第八开关元件M8在传输至第一下拉控制节点PDCN1的第一电源信号的作用下导通，将第一电源信号传输至第一下拉节点PD1，第十一开关元件M11在传输至第一下拉节点PD1的第一电源信号的作用下导通，将参考信号通过第十一开关元件M11传输至信号输出端Output，以对信号输出端Output持续降噪，即信号输出端Output的输出信号均为低电平VL，第一开关元件M1在时钟信号的作用下导通，将信号输出端Output与上拉节点PU连通，间接的通过信号输出端Output对上拉节点PU进行降噪。In the pixel holding phase (i.e. T1 phase), the first reset signal of the first reset signal terminal Reset1, the second reset signal of the second reset signal terminal Reset2, the input signal of the signal input terminal Input, the second power supply signal terminal VDD2 of the first reset signal The two power supply signals are both low level VL, the first power supply signal at the first power supply signal terminal VDD1 and the clock signal at the clock signal terminal CLK are both high level VH, at this time, the seventh switching element M7 is at the first power supply signal is turned on under the action of the first power supply signal to the first pull-down control node PDCN1, and the eighth switch element M8 is turned on under the action of the first power supply signal transmitted to the first pull-down control node PDCN1, and the first power supply signal is transmitted to the first pull-down control node PDCN1. The signal is transmitted to the first pull-down node PD1, and the eleventh switch element M11 is turned on under the action of the first power signal transmitted to the first pull-down node PD1, and the reference signal is transmitted to the signal output through the eleventh switch element M11 Terminal Output, to continuously reduce the noise of the signal output terminal Output, that is, the output signals of the signal output terminal Output are all low level VL, the first switch element M1 is turned on under the action of the clock signal, and the signal output terminal Output and the pull-up The node PU is connected, and the pull-up node PU is indirectly denoised through the signal output terminal Output.
在充电阶段(即T2阶段)，信号输入端Input的输入信号为高点平VH，第二开关元件M2在输入信号的作用下导通，将输入信号传输至上拉节点PU，以对电容C充电，第三开关元件M3、第四开关元件M4、第五开关元件M5、第六开关元件M6分别在传输至上拉节点PU的输入信号的作用下导通，将参考信号分别通过第三开关元件M3、第四开关元件M4、第五开关元件M5、第六开关元件M6传输至第一下拉控制节点PDCN1、第一下拉节点PD1、第二下拉控制节点PDCN2、第二下拉节点PD2，同时，第十三开关元件M13在传输至上拉节点PU的输入信号的作用下导通，将时钟信号传输至信号输出端Output，由于此时时钟信号为低电平VL，信号输出端Output的输出信号也为低电平VL，且第一开关元件M1关闭。In the charging stage (that is, the T2 stage), the input signal of the signal input terminal Input is a high level VH, the second switching element M2 is turned on under the action of the input signal, and the input signal is transmitted to the pull-up node PU to charge the capacitor C , the third switch element M3, the fourth switch element M4, the fifth switch element M5, and the sixth switch element M6 are respectively turned on under the action of the input signal transmitted to the pull-up node PU, and the reference signal is respectively passed through the third switch element M3 , the fourth switch element M4, the fifth switch element M5, and the sixth switch element M6 are transmitted to the first pull-down control node PDCN1, the first pull-down node PD1, the second pull-down control node PDCN2, and the second pull-down node PD2. At the same time, The thirteenth switching element M13 is turned on under the action of the input signal transmitted to the pull-up node PU, and transmits the clock signal to the signal output terminal Output. Since the clock signal is at a low level VL at this time, the output signal of the signal output terminal Output is also is low level VL, and the first switching element M1 is turned off.
在自举阶段(即T3阶段)，时钟信号端CLK的时钟信号为高电平VH，在上拉节点PU的作用下，第十三开关元件M13导通，将时钟信号传输至信号输出端Output，此时信号输出端Output的输出信号为高电平信号VH，同时通过存储电容C的自举作用使得上拉节点PU电位自举至大约2VH，由于此时第一开关元件的控制端和第二端之间的电压为VH-2VH＝-VH<0，因此，第一开关元件M1关闭，即不影响移位寄存器单元的正常输出。In the bootstrap stage (that is, the T3 stage), the clock signal at the clock signal terminal CLK is at a high level VH, and under the action of the pull-up node PU, the thirteenth switching element M13 is turned on, and the clock signal is transmitted to the signal output terminal Output At this time, the output signal of the signal output terminal Output is a high-level signal VH, and at the same time, the potential of the pull-up node PU is bootstrapped to about 2VH through the bootstrap function of the storage capacitor C, because at this time, the control terminal of the first switching element and the second The voltage between the two terminals is VH-2VH=-VH<0, therefore, the first switching element M1 is turned off, that is, the normal output of the shift register unit is not affected.
在复位阶段(即T4阶段)，时钟信号端CLK的时钟信号为低电平VL，此时信号输出端Output的输出信号为低电平信号VL，且第一开关元件M1关闭，同时，由于时钟信号为低电平VL，通过存储电容C的自举作用使得上拉节点PU的电位自举至VH。In the reset phase (that is, the T4 phase), the clock signal of the clock signal terminal CLK is a low level VL, at this time, the output signal of the signal output terminal Output is a low level signal VL, and the first switching element M1 is turned off. At the same time, due to the clock The signal is low level VL, and the potential of the pull-up node PU is bootstrapped to VH through the bootstrap function of the storage capacitor C.
需要说明的是，第二电源信号端VDD2的第二电源信号的高电平时段的移位寄存器单元的工作原理与上述第一电源信号端VDD1的第一电源信号的高电平时段的移位寄存器单元的工作原理相同，因此此处不再举例说明。It should be noted that the working principle of the shift register unit during the high-level period of the second power supply signal at the second power supply signal terminal VDD2 is the same as the shift of the high-level period of the first power supply signal at the first power supply signal terminal VDD1. The register unit works the same, so no examples are given here.
由上可知，在像素保持阶段(即T1阶段)，第一电源信号端VDD1的第一电源信号和第二电源信号端VDD2的第二电源信号通过第十一开关元件M11和第十二开关元件M12交替对信号输出端Output持续降噪，同时，通过时钟信号端CLK的时钟信号周期性打开第一开关元件M1，以间接的通过信号输出端Output对上拉节点PU进行降噪，保证了移位寄存器单元的信耐度，在充电阶段(即T2阶段)、自举阶段(即T3阶段)以及复位阶段(即T4阶段)，信号输出端Output的输出信号由时钟信号端CLK的时钟信号决定，保证移位寄存器单元可以正常输出。It can be seen from the above that in the pixel holding phase (that is, the T1 phase), the first power signal of the first power signal terminal VDD1 and the second power signal of the second power signal terminal VDD2 pass through the eleventh switching element M11 and the twelfth switching element M12 alternately denoises the signal output terminal Output continuously. At the same time, the clock signal of the clock signal terminal CLK periodically turns on the first switch element M1 to indirectly denoise the pull-up node PU through the signal output terminal Output, ensuring that the The reliability of the bit register unit, in the charging phase (that is, the T2 phase), the bootstrap phase (that is, the T3 phase) and the reset phase (that is, the T4 phase), the output signal of the signal output terminal Output is determined by the clock signal of the clock signal terminal CLK , to ensure that the shift register unit can output normally.
具体的运行图5中的移位寄存器单元的输出信号模拟效果图如图6所示，从图6中可知，保证了移位寄存器单元的信耐度和正常输出。The output signal simulation effect diagram of the specific operation of the shift register unit in FIG. 5 is shown in FIG. 6. It can be seen from FIG. 6 that the reliability and normal output of the shift register unit are guaranteed.
显然，在上述移位寄存器单元中，仅仅通过时钟信号控制的周期性打开的第一开关元件M1，间接的通过信号输出端Output对上拉节点PU进行降噪，相比于现有技术，在保证了移位寄存器单元的信耐度和正常输出的基础上，在对上拉节点PU的降噪中减少了一个开关元件(即图1中的第十六开关元件M16)，节省了空间。Apparently, in the above shift register unit, only the first switch element M1 that is turned on periodically controlled by the clock signal indirectly denoises the pull-up node PU through the signal output terminal Output. Compared with the prior art, in On the basis of ensuring the reliability and normal output of the shift register unit, one switching element (namely the sixteenth switching element M16 in FIG. 1 ) is reduced in the noise reduction of the pull-up node PU, which saves space.
本示例实施方式还提出了一种移位寄存器电路，可用作栅极驱动电路。参考图7所示，所述移位寄存器电路可以包括多个级联的上述移位寄存器单元；在复位信号端包括第一复位信号端和第二复位信号端时，第N-3级所述移位寄存器单元的信号输出端连接第N级所述移位寄存器单元的信号输入端；第N+3级所述移位寄存器单元的信号输出端连接第N级所述移位寄存器单元的第二复位信号端；第N+4级所述移位寄存器单元的信号输出端连接第N级所述移位寄存器单元的第一复位信号端；其中，N为整数且N≥1。其中，第1-3级移位寄存器单元的输入信号可以由起始信号STV提供。This example embodiment also proposes a shift register circuit that can be used as a gate driving circuit. As shown in FIG. 7, the shift register circuit may include a plurality of cascaded above-mentioned shift register units; when the reset signal end includes a first reset signal end and a second reset signal end, the N-3th stage The signal output end of the shift register unit is connected to the signal input end of the shift register unit of the Nth stage; the signal output end of the shift register unit of the N+3 stage is connected to the first shift register unit of the Nth stage Two reset signal terminals; the signal output terminal of the shift register unit of the N+4th stage is connected to the first reset signal terminal of the shift register unit of the Nth stage; wherein, N is an integer and N≥1. Wherein, the input signal of the first-third stage shift register unit can be provided by the start signal STV.
本示例实施方式中，所述移位寄存器电路级联结构的信号端连接方式不限于此，其可以根据实际情况进行调整，这里不做具体限定。In this example embodiment, the connection mode of the signal terminals of the shift register circuit cascaded structure is not limited thereto, it can be adjusted according to actual conditions, and is not specifically limited here.
需要说明的是：所述移位寄存器电路中的各模块单元的具体细节已经在对应的移位寄存器单元中进行了详细的描述，因此这里不再赘述。It should be noted that: the specific details of each module unit in the shift register circuit have been described in detail in the corresponding shift register unit, so details will not be repeated here.
本示例实施方式还提出了一种显示面板，包括显示区域和周边区域；其中，所述显示面板的周边区域可以设置上述的移位寄存器电路。在此基础上，所述显示面板的显示区域可以包括横纵交错的多条栅线和多条数据线，以及由相邻所述栅线和相邻所述数据线限定的多个像素单元：其中，所述栅线用于传输所述移位寄存器电路提供的扫描信号，所述数据线用于传输源极驱动器提供的数据信号。This exemplary embodiment also provides a display panel, including a display area and a peripheral area; wherein, the above-mentioned shift register circuit may be provided in the peripheral area of the display panel. On this basis, the display area of the display panel may include a plurality of gate lines and a plurality of data lines criss-crossing, and a plurality of pixel units defined by adjacent gate lines and adjacent data lines: Wherein, the gate line is used to transmit the scan signal provided by the shift register circuit, and the data line is used to transmit the data signal provided by the source driver.
本示例实施方式利用GOA技术将移位寄存器电路集成于显示面板的周边，从而在实现窄边框面板设计的同时，还可有效降低显示面板的制造成本、提升显示模组的工艺产量。In this exemplary embodiment, the shift register circuit is integrated on the periphery of the display panel by using the GOA technology, so as to realize the panel design with a narrow frame, effectively reduce the manufacturing cost of the display panel, and improve the process output of the display module.
本示例实施方式中，所述显示面板具体可以为LCD显示面板、OLED显示面板、PLED(Polymer Light-Emitting Diode，高分子发光二极管)显示面板、PDP(Plasma DisplayPanel，等离子显示面板)等，这里对于显示面板的适用不做具体的限制。In this exemplary embodiment, the display panel may specifically be an LCD display panel, an OLED display panel, a PLED (Polymer Light-Emitting Diode, polymer light-emitting diode) display panel, a PDP (Plasma Display Panel, a plasma display panel), etc. Here, for The application of the display panel is not specifically limited.
本示例实施方式还提供一种显示装置，包括上述的显示面板。其中，所述显示装置例如可以包括手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。This example embodiment also provides a display device including the above-mentioned display panel. Wherein, the display device may include, for example, any product or component with a display function such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. Actually, according to the embodiment of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided to be embodied by a plurality of modules or units.
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。In addition, although steps of the methods of the present disclosure are depicted in the drawings in a particular order, there is no requirement or implication that the steps must be performed in that particular order, or that all illustrated steps must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and/or one step may be decomposed into multiple steps for execution, etc.
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、移动终端、或者网络设备等)执行根据本公开实施方式的方法。Through the description of the above implementations, those skilled in the art can easily understand that the example implementations described here can be implemented by software, or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of software products, and the software products can be stored in a non-volatile storage medium (which can be CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to make a computing device (which may be a personal computer, a server, a mobile terminal, or a network device, etc.) execute the method according to the embodiments of the present disclosure.
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。Other embodiments of the present disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, and these modifications, uses or adaptations follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field not disclosed in the present disclosure . The specification and examples are to be considered exemplary only, with the true scope and spirit of the disclosure indicated by the appended claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810032531.7ACN107978294A (en) | 2018-01-12 | 2018-01-12 | Shift register cell, shift-register circuit, display panel |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810032531.7ACN107978294A (en) | 2018-01-12 | 2018-01-12 | Shift register cell, shift-register circuit, display panel |
| Publication Number | Publication Date |
|---|---|
| CN107978294Atrue CN107978294A (en) | 2018-05-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810032531.7APendingCN107978294A (en) | 2018-01-12 | 2018-01-12 | Shift register cell, shift-register circuit, display panel |
| Country | Link |
|---|---|
| CN (1) | CN107978294A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108831403A (en)* | 2018-08-29 | 2018-11-16 | 合肥鑫晟光电科技有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN108877716A (en)* | 2018-07-20 | 2018-11-23 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN110517622A (en)* | 2019-09-05 | 2019-11-29 | 合肥鑫晟光电科技有限公司 | Shift register unit and driving method thereof, gate driving circuit, and display device |
| WO2020034856A1 (en)* | 2018-08-13 | 2020-02-20 | 京东方科技集团股份有限公司 | Shift register unit, driving method, gate driving circuit, and display device |
| CN110910852A (en)* | 2019-12-19 | 2020-03-24 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit and display device |
| CN111477193A (en)* | 2020-05-25 | 2020-07-31 | 京东方科技集团股份有限公司 | Shift register and its driving method |
| US11393378B2 (en) | 2020-10-27 | 2022-07-19 | Boe Technology Group Co., Ltd. | Gate driving circuit unit, gate driving circuit and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093647A (en)* | 2006-06-21 | 2007-12-26 | 三星电子株式会社 | Gate driving circuit and display apparatus having the same |
| CN102629459A (en)* | 2011-10-26 | 2012-08-08 | 北京京东方光电科技有限公司 | Gate line driving method, shift register and gate line driving device |
| CN105185349A (en)* | 2015-11-04 | 2015-12-23 | 京东方科技集团股份有限公司 | Shifting register, grid electrode integrated driving circuit and display device |
| CN105702225A (en)* | 2016-04-27 | 2016-06-22 | 京东方科技集团股份有限公司 | Grid driving circuit and driving method thereof, array substrate and display device |
| CN205564251U (en)* | 2016-04-26 | 2016-09-07 | 北京京东方显示技术有限公司 | Shift register , gate drive circuit, array substrate |
| CN105938711A (en)* | 2016-06-06 | 2016-09-14 | 京东方科技集团股份有限公司 | Gate driver on array (GOA) circuit and driving method |
| US20170018244A1 (en)* | 2015-07-16 | 2017-01-19 | Hannstar Display (Nanjing) Corporation | Shift register and display device |
| CN106847211A (en)* | 2017-02-22 | 2017-06-13 | 京东方科技集团股份有限公司 | Shift register and its driving method, gate driving circuit and display device |
| US20170249893A1 (en)* | 2016-02-29 | 2017-08-31 | Samsung Display Co., Ltd. | Gate driver and display apparatus including the same |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093647A (en)* | 2006-06-21 | 2007-12-26 | 三星电子株式会社 | Gate driving circuit and display apparatus having the same |
| CN102629459A (en)* | 2011-10-26 | 2012-08-08 | 北京京东方光电科技有限公司 | Gate line driving method, shift register and gate line driving device |
| US20170018244A1 (en)* | 2015-07-16 | 2017-01-19 | Hannstar Display (Nanjing) Corporation | Shift register and display device |
| CN105185349A (en)* | 2015-11-04 | 2015-12-23 | 京东方科技集团股份有限公司 | Shifting register, grid electrode integrated driving circuit and display device |
| US20170249893A1 (en)* | 2016-02-29 | 2017-08-31 | Samsung Display Co., Ltd. | Gate driver and display apparatus including the same |
| CN205564251U (en)* | 2016-04-26 | 2016-09-07 | 北京京东方显示技术有限公司 | Shift register , gate drive circuit, array substrate |
| CN105702225A (en)* | 2016-04-27 | 2016-06-22 | 京东方科技集团股份有限公司 | Grid driving circuit and driving method thereof, array substrate and display device |
| CN105938711A (en)* | 2016-06-06 | 2016-09-14 | 京东方科技集团股份有限公司 | Gate driver on array (GOA) circuit and driving method |
| CN106847211A (en)* | 2017-02-22 | 2017-06-13 | 京东方科技集团股份有限公司 | Shift register and its driving method, gate driving circuit and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108877716B (en)* | 2018-07-20 | 2021-01-26 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN108877716A (en)* | 2018-07-20 | 2018-11-23 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| US10984879B2 (en) | 2018-07-20 | 2021-04-20 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register unit and method for driving the same, gate driving circuit and display apparatus |
| WO2020034856A1 (en)* | 2018-08-13 | 2020-02-20 | 京东方科技集团股份有限公司 | Shift register unit, driving method, gate driving circuit, and display device |
| US10978168B2 (en) | 2018-08-13 | 2021-04-13 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register unit, method of driving the same, gate driving circuit and display device |
| CN108831403B (en)* | 2018-08-29 | 2020-09-04 | 合肥鑫晟光电科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN108831403A (en)* | 2018-08-29 | 2018-11-16 | 合肥鑫晟光电科技有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN110517622A (en)* | 2019-09-05 | 2019-11-29 | 合肥鑫晟光电科技有限公司 | Shift register unit and driving method thereof, gate driving circuit, and display device |
| CN110910852A (en)* | 2019-12-19 | 2020-03-24 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit and display device |
| CN110910852B (en)* | 2019-12-19 | 2021-10-29 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit and display device |
| CN111477193A (en)* | 2020-05-25 | 2020-07-31 | 京东方科技集团股份有限公司 | Shift register and its driving method |
| CN111477193B (en)* | 2020-05-25 | 2022-04-26 | 京东方科技集团股份有限公司 | Shift register and driving method thereof |
| US11393378B2 (en) | 2020-10-27 | 2022-07-19 | Boe Technology Group Co., Ltd. | Gate driving circuit unit, gate driving circuit and display device |
| Publication | Publication Date | Title |
|---|---|---|
| CN108288460B (en) | Shifting register, driving method thereof and grid driving circuit | |
| CN105529009B (en) | Shift register and its driving method, gate driving circuit and display device | |
| EP3333843B1 (en) | Shift register, gate driving circuit, display panel driving method, and display device | |
| CN107978294A (en) | Shift register cell, shift-register circuit, display panel | |
| US9779680B2 (en) | Shift register unit, gate driving circuit and display apparatus | |
| CN112216249B (en) | Grid driving circuit and display device | |
| US10923060B2 (en) | Shift register unit with power signal terminals having same frequencies and reverse phases, shift register circuit and display panel | |
| CN110930942B (en) | Shift register, control method thereof and display panel | |
| US10984700B1 (en) | Shift register unit, shift register circuit and driving method, and display panel | |
| CN108320692B (en) | Shifting register unit, driving method, grid driving circuit and display panel | |
| CN108564930A (en) | Shift register and its driving method, gate driving circuit and display device | |
| CN106875913A (en) | Shift register cell and its driving method, gate driving circuit | |
| CN105047174A (en) | Shifting register unit and driving method, grid driving device and display device thereof | |
| CN202650488U (en) | Shift register, gate driving device and display device | |
| CN102831860A (en) | Shifting register, drive method thereof, gate driver and display device | |
| CN106448536A (en) | Shifting register, grid driving circuit, display panel and driving method | |
| CN106710564A (en) | Shifting register unit, shifting register circuit and driving method thereof and display panel | |
| CN106601208A (en) | Shift register unit, driving method thereof, grid drive circuit and display device | |
| CN108564912A (en) | Shift-register circuit and driving method, display device | |
| CN111710281A (en) | A shift register, its driving method, gate driving circuit, and display device | |
| US20190130806A1 (en) | Shift register, driving method thereof, gate line integrated driving circuit and display device | |
| CN115938324A (en) | GOA circuit and display panel | |
| CN110223653B (en) | Shifting register, driving method thereof and grid driving circuit | |
| CN107909960B (en) | Shift register unit, shift register circuit and display panel | |
| CN106057161B (en) | Shift register, grid line integrated drive electronics, array substrate and display device |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | Application publication date:20180501 | |
| RJ01 | Rejection of invention patent application after publication |