The interconnected method of parallel bus between a kind of veneerTechnical field
The present invention is a kind of interconnected method of parallel bus between veneer, is related to circuit design field, especially communication equipmentThe interconnected method of parallel bus between upper master control borad and interface board.
Background technology
There are multiple card slot positions, groove position in communication of distributed system equipment, in an equipment to be divided into master control groove position, interfaceBoard slot position etc., different groove positions are interconnected by backboard, and whole system is managed by master control borad.Master control borad management interfacePlate, is generally realized by parallel bus.Typical system architecture is mainly made of three master control borad, backboard, interface board parts,Master control borad is one piece, interface board polylith.Management for interface board, the CPU of master control borad are produced parallel bus, are visited by CPLDAsk the CPLD on interface board, complete the access of register, interrupt, the processing of reset signal, and be converted into SMI, I2C interface pairAccess operation of interface board chip etc..Parallel bus signal, according to 8 position datawires, 10 bit address lines, along with control signal,Parallel signal bus will up to twenties, seriously occupies the number of pin of back panel connector.
The content of the invention
In view of the deficienciess of the prior art, it is an object of the present invention to provide a kind of interconnected method of parallel bus between veneer,To solve the problems mentioned in the above background technology.
To achieve these goals, the present invention is to realize by the following technical solutions：Parallel bus between a kind of veneerInterconnected method, including master control borad interface module and interface board interface module, the parallel bus of master control borad interface module and CPUInterface connects, and is connected with interface board interface module by backboard, completes the mutual conversion between parallel bus and Serdes buses；
Interface board interface module is connected with master control borad interface module by backboard, receives the serial Serdes that master control borad is sentData, and after being parsed, interface board interface module is operated accordingly, meanwhile, also by inside interface board interface moduleControl, address and data message are converted to serial SerDes data, give master control borad interface module.
Further, master control borad interface module includes：Parallel interface module and SerDes interface modules；
Parallel interface module, is connected with the parallel bus of CPU, and parallel interface module is according to the address on parallel bus, numberAccording to and control signal, generate address bit, data bit and control bit, and formed parallel data frame, meanwhile, parallel interface moduleAccording to the parallel data frame received from SerDes interface modules, corresponding address, data and control information, by simultaneously are parsedRow bus, and CPU communications；
SerDes interface modules, are connected with parallel interface module, for by being received from the parallel interface module andRow data frame is converted into serial SerDes data, and interface board is sent to by SerDes buses, since SerDes interface modules willThe parallel signal of the DC characteristics of long-distance cable interconnection and topology is not supported, is converted into the SerDes interfaces of AC characteristics, so as toTo support long range High-Speed PCB cabling and topology, the high speed interconnection between plate is realized, while receive the string that SerDes buses are sentRow SerDes data, convert thereof into parallel data frame, give parallel interface module.
Further, interface board interface module includes parallel data processing module and SerDes interface modules；
SerDes interface modules, connect SerDes buses, receive serial SerDes data, and SerDes data are converted toParallel data frame, SerDes interface modules, also from the SerDes data received, recover clock CLK, are used for FPGA,The parallel data frame of parallel data processing module transmission is received at the same time, is sent to after converting thereof into serial SerDes dataSerDes buses；
Parallel data processing module, the parallel data frame that SerDes interface modules are changed out are parsed into order, address andData message, and according to different addresses and command information, operate FPGA internal registers, complete configuration to interface board andInterface board state is read；By SMI interface modules and I2C interface module, there is provided SMI and I2C buses, are completed to interface board coreThe access function of piece, meanwhile, also by the control inside FPGA, address and data message, parallel data frame is formed, gives SerDesInterface module.
Beneficial effects of the present invention：The interconnected method of parallel bus, master control borad interface module between a kind of veneer of the present inventionAnd the interconnection between interface board interface module saves signal pin by the way of SerDes universal serial bus.By reasonableData format definition, SerDes universal serial bus between master control borad and interface board can not only be used for transmitting parallel busSignal, can also be used to transmit other control signals, such as interrupt signal etc., and further reduction master control borad and interface board interconnectSignal pin.
Brief description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, further feature of the invention,Objects and advantages will become more apparent upon：
The system block diagram of Fig. 1 interconnected methods of parallel bus between a kind of veneer of the present invention；
The master control borad interface module functional block diagram of Fig. 2 interconnected methods of parallel bus between a kind of veneer of the present invention；
The parallel data frame format figure of Fig. 3 interconnected methods of parallel bus between a kind of veneer of the present invention；
The interface board interface module functional block diagram of Fig. 4 interconnected methods of parallel bus between a kind of veneer of the present invention；
Embodiment
To make the technical means, the creative features, the aims and the efficiencies achieved by the present invention easy to understand, with reference toEmbodiment, the present invention is further explained.
The present invention provides a kind of technical solution：Including master control borad interface module 201 and interface board interface module 203, such asShown in Fig. 1, master control borad interface module 201, is connected with 205 interface of parallel bus of CPU200, logical with interface board interface module 203Cross backboard 202 to connect, complete the mutual conversion between parallel bus 205 and Serdes buses 206.
Interface board interface module 203, and master control borad interface module 201 are connected by backboard 202, receive what master control borad was sentSerial Serdes data, and after being parsed, interface board interface module 203 is operated accordingly.Meanwhile also by interface boardControl inside interface module 203, address and data message, are converted to serial SerDes data, give master control borad interface module201。
Master control borad interface module 201 can use FPGA209, and (field-programmable controls gate arrayFieldProgrammableGateArray) realize.As shown in Fig. 2, the present embodiment includes：301 He of parallel interface moduleSerDes interface modules 302.
Parallel interface module 301, is connected with the parallel bus 305 of CPU.Parallel interface module 301 is according to parallel bus 305On address, data and control signal, generate address bit, data bit and control bit, and are formed parallel data frame 306.TogetherWhen, parallel interface module 301 parses corresponding address according to the parallel data frame 306 received from SerDes interface modules,Data and control information, is communicated by parallel bus 305, and CPU.
The form of parallel data frame is as shown in Figure 3.The data format of every group of parallel data frame all includes：
Start field, for identifying the starting of parallel data frame.
Payload field, for preserving the information transmitted in parallel interface, comprising address field, control field and data wordSection.
Check field, carries out payload for preserving the check value of even-odd check.
Trailer field, for identifying the end of parallel data frame.
SerDes interface modules 302, are connected with parallel interface module 301, for will be connect from the parallel interface module 301Received parallel data frame 306 is converted into serial SerDes data, and interface board is sent to by SerDes buses 307.Due toSerDes interface modules 302 will not support the parallel signal of the DC characteristics of long-distance cable interconnection and topology, be converted into AC characteristicsSerDes interfaces, so as to support long range High-Speed PCB cabling and topology, realize between plate high speed interconnection.Connect at the same timeThe serial SerDes data that SerDes buses 307 are sent are received, parallel data frame 306 is converted thereof into, gives parallel interface module301。
Interface board interface module 203, is realized by FPGA210.As shown in figure 4, the module includes parallel data processing module402 and SerDes interface modules 401.
SerDes interface modules 401, connection SerDes buses 407 receive serial SerDes data, and by SerDes dataBe converted to parallel data frame 408.SerDes interface modules 401, also from the SerDes data received, recover clockCLK411, uses for FPGA400.The parallel data frame 408 of the transmission of parallel data processing module 402 is received at the same time, is convertedSerDes buses 407 are sent to after into serial SerDes data.
Parallel data processing module 402, the parallel data frame 408 that SerDes interface modules 401 are changed out, parses order already issuedOrder, address and data message, and according to different addresses and command information, operation FPGA internal registers 403, are completed to interfaceThe configuration of plate and to interface board state read；By SMI interface modules 404 and I2C interface module 405, there is provided SMI409 andI2C410 buses, complete the access function to interface board chip 406.Meanwhile also by the control inside FPGA, address sum number it is believed thatBreath, composition parallel data frame 408, gives SerDes interface modules 401.
The basic principles, main features and the advantages of the invention have been shown and described above, for this area skillFor art personnel, it is clear that the invention is not restricted to the details of above-mentioned one exemplary embodiment, and without departing substantially from the present invention spirit orIn the case of essential characteristic, the present invention can be realized in other specific forms.Therefore, in all respects, should all incite somebody to actionEmbodiment regards exemplary as, and is non-limiting, the scope of the present invention by appended claims rather than on stateBright restriction, it is intended that including all changes fallen in the implication and scope of the equivalency of claim in the present inventionIt is interior.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each embodiment is only wrappedContaining an independent technical solution, this narrating mode of specification is only that those skilled in the art should for clarityUsing specification as an entirety, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the artIt is appreciated that other embodiment.