技术领域technical field
本发明涉及显示技术领域，尤其是涉及一种阵列基板及其制备方法。The present invention relates to the field of display technology, in particular to an array substrate and a preparation method thereof.
背景技术Background technique
随着社会进步与人们需求的提升，显示器也向着大尺寸、高分辨率的方向发展，采用高导布线的薄膜晶体管阵列基板可以提高显示器的分辨率和尺寸。然而使用高导材料(如铜)进行布线时往往会遇到金属原子扩散的问题，导致器件性能劣化。因此，在金属布线层与有源层之间通常需要插入中间层以解决高导布线层的附着力与扩散问题。With the progress of society and the improvement of people's needs, displays are also developing in the direction of large size and high resolution. The resolution and size of displays can be improved by using thin film transistor array substrates with high conductivity lines. However, when using high-conductivity materials (such as copper) for wiring, it often encounters the problem of diffusion of metal atoms, which leads to degradation of device performance. Therefore, it is usually necessary to insert an intermediate layer between the metal wiring layer and the active layer to solve the problem of adhesion and diffusion of the high-conductivity wiring layer.
现有技术中，中间层的制备工序复杂，具有中间层的阵列基板形成薄膜晶体管与像素电极的过程需要经历多次掩模及构图工艺，导致产品的制备成本高，生产周期长。In the prior art, the preparation process of the intermediate layer is complicated, and the process of forming thin film transistors and pixel electrodes on the array substrate with the intermediate layer needs to undergo multiple masking and patterning processes, resulting in high manufacturing costs and long production cycles.
发明内容Contents of the invention
本发明要解决的技术问题是提供一种阵列基板及其制备方法，用以解决现有技术中阵列基板的制备过程需要经历多次掩模及构图工艺，导致产品的制备成本高，生产周期长的问题。The technical problem to be solved by the present invention is to provide an array substrate and its preparation method, which is used to solve the problem that the preparation process of the array substrate in the prior art needs to undergo multiple masking and patterning processes, resulting in high preparation costs and long production cycles. The problem.
为解决上述技术问题，本发明提供一种阵列基板的制备方法，包括：In order to solve the above technical problems, the present invention provides a method for preparing an array substrate, including:
在基板表面形成第一金属层；forming a first metal layer on the surface of the substrate;
在所述第一金属层背离所述基板一侧依次沉积栅极绝缘层、有源层、中间层、第二金属层及光阻层，所述栅极绝缘层隔离所述第一金属层与所述有源层；A gate insulating layer, an active layer, an intermediate layer, a second metal layer and a photoresist layer are sequentially deposited on the side of the first metal layer away from the substrate, and the gate insulating layer isolates the first metal layer from the substrate. the active layer;
使用半色调掩膜板曝光显影，所述半色调掩膜板包括第一透光部和第二透光部，所述光阻层对应所述第一透光部形成第一光阻区，所述光阻层对应所述第二透光部形成第二光阻区；Use a half-tone mask for exposure and development, the half-tone mask includes a first light-transmitting portion and a second light-transmitting portion, and the photoresist layer forms a first photoresist region corresponding to the first light-transmitting portion, so The photoresist layer forms a second photoresist region corresponding to the second light-transmitting portion;
在所述第一光阻区处，去除所述光阻层、所述第二金属层和所述中间层，使所述有源层外露，以形成沟道及源极和漏极；At the first photoresist area, removing the photoresist layer, the second metal layer and the intermediate layer to expose the active layer to form a channel, source and drain;
在所述第二光阻区处，去除所述光阻层、所述第二金属层，使所述中间层外露，形成像素电极。At the second photoresist area, the photoresist layer and the second metal layer are removed to expose the intermediate layer to form a pixel electrode.
一种实施方式中，所述半色调掩膜板还包括非透光部，所述光阻层对应所述非透光部形成第三光阻区，所述第一光阻区位于两个所述第三光阻区之间，所述阵列基板的制备方法还包括去除所述第三光阻区的所述光阻层，露出所述源极和所述漏极。In one embodiment, the half-tone mask further includes a non-transparent portion, the photoresist layer forms a third photoresist area corresponding to the non-transmittance portion, and the first photoresist area is located between the two Between the third photoresist area, the preparation method of the array substrate further includes removing the photoresist layer in the third photoresist area to expose the source and the drain.
一种实施方式中，在所述基板表面形成所述第一金属层后，在所述第一金属层上沉积所述栅极绝缘层之前，所述阵列基板的制备方法还包括图案化所述第一金属层形成栅极和第一电容极板，所述第一电容极板对应所述第三光阻区。In one embodiment, after forming the first metal layer on the surface of the substrate, before depositing the gate insulating layer on the first metal layer, the method for preparing the array substrate further includes patterning the The first metal layer forms a gate and a first capacitor plate, and the first capacitor plate corresponds to the third photoresist region.
阵列基板一种实施方式中，所述光阻层还包括第四光阻区，使用半色调掩膜板曝光显影的同时，所述阵列基板的制备方法还包括曝光所述第四光阻区的所述光阻层，并刻蚀对应所述第四光阻区的所述第二金属层、所述中间层及所述有源层，图案化所述第二金属层、所述中间层及所述有源层形成源漏极和第二电容极板。In one embodiment of the array substrate, the photoresist layer further includes a fourth photoresist region, and while exposing and developing the array substrate using a halftone mask, the preparation method of the array substrate further includes exposing the fourth photoresist region the photoresist layer, and etch the second metal layer, the intermediate layer and the active layer corresponding to the fourth photoresist region, and pattern the second metal layer, the intermediate layer and the The active layer forms source and drain electrodes and a second capacitive plate.
一种实施方式中，去除所有光阻层后，所述阵列基板的制备方法还包括沉积钝化层保护所述阵列基板。In one embodiment, after removing all photoresist layers, the method for preparing the array substrate further includes depositing a passivation layer to protect the array substrate.
一种实施方式中，沉积所述钝化层后，所述阵列基板的制备方法还包括刻蚀所述像素电极表面的所述钝化层，露出所述像素电极。In one embodiment, after depositing the passivation layer, the method for preparing the array substrate further includes etching the passivation layer on the surface of the pixel electrode to expose the pixel electrode.
一种实施方式中，所述第一透光部和所述第二透光部的透过率不同，对应形成的所述第一光阻区与所述第二光阻区的光阻层的厚度不同。In one embodiment, the transmittance of the first light-transmitting portion and the second light-transmitting portion are different, and the corresponding formation of the first photoresist region and the photoresist layer of the second photoresist region The thickness varies.
一种实施方式中，所述中间层为透明导电金属氧化物、石墨烯或碳纳米管薄膜。In one embodiment, the intermediate layer is a transparent conductive metal oxide, graphene or carbon nanotube film.
一种实施方式中，所述中间层通过磁控溅射方法成膜，并通过湿法工艺刻蚀；或所述中间层通过溶液法制备，并通过干法工艺刻蚀。In one embodiment, the intermediate layer is formed by magnetron sputtering and etched by a wet process; or the intermediate layer is prepared by a solution process and etched by a dry process.
本发明还提供一种阵列基板，包括栅极、栅极绝缘层、有源层、中间层、源极及漏极，所述栅极、所述栅极绝缘层及所述有源层依次层叠设置，所述栅极绝缘层隔绝所述栅极与所述有源层，所述源极和所述漏极位于所述有源层背离所述栅极的一侧，所述中间层包括相互隔绝的第一部分与第二部分，所述第一部分位于所述源极与所述有源层之间，所述第二部分位于所述漏极与所述有源层之间，所述中间层用于阻隔所述源极或所述漏极向所述有源层扩散金属原子，并且所述第一部分或所述第二部分用作像素电极。The present invention also provides an array substrate, including a gate, a gate insulating layer, an active layer, an intermediate layer, a source and a drain, and the gate, the gate insulating layer and the active layer are sequentially stacked It is set that the gate insulating layer isolates the gate from the active layer, the source and the drain are located on the side of the active layer away from the gate, and the intermediate layer includes mutual an isolated first part and a second part, the first part is located between the source electrode and the active layer, the second part is located between the drain electrode and the active layer, and the intermediate layer It is used to prevent the source electrode or the drain electrode from diffusing metal atoms to the active layer, and the first part or the second part is used as a pixel electrode.
本发明的有益效果如下：利用半色调掩膜板曝光显影，显影第一透光部形成的第一光阻区去除对应的第二金属层和中间层、保留有源层形成沟道，从而形成薄膜晶体管，显影第二透光部形成的第二光阻区去除对应的第二金属层后露出透明的中间层，并以中间层作为像素电极，即经过一次掩模工艺形成薄膜晶体管与像素电极，简化了阵列基板的制备过程，降低了产品的制备成本，缩短了生产周期。The beneficial effects of the present invention are as follows: use a halftone mask to expose and develop, develop the first photoresist area formed by the first light-transmitting part, remove the corresponding second metal layer and intermediate layer, and retain the active layer to form a channel, thereby forming For thin film transistors, the second photoresist area formed by developing the second light-transmitting part removes the corresponding second metal layer to expose the transparent intermediate layer, and the intermediate layer is used as the pixel electrode, that is, the thin film transistor and the pixel electrode are formed through a mask process , which simplifies the preparation process of the array substrate, reduces the preparation cost of the product, and shortens the production cycle.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的明显变形方式。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other obvious deformations can also be obtained according to these drawings without creative efforts.
图1为本发明实施例提供的阵列基板的制备方法的流程图。FIG. 1 is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present invention.
图2为本发明实施例提供的阵列基板的制备方法的步骤S101的示意图。FIG. 2 is a schematic diagram of step S101 of the method for preparing an array substrate provided by an embodiment of the present invention.
图3为本发明实施例提供的阵列基板的制备方法的步骤S102的示意图。FIG. 3 is a schematic diagram of step S102 of the method for preparing an array substrate provided by an embodiment of the present invention.
图4为本发明实施例提供的阵列基板的制备方法的步骤S103的示意图。FIG. 4 is a schematic diagram of step S103 of the method for preparing an array substrate provided by an embodiment of the present invention.
图5和图6为发明实施例提供的阵列基板的制备方法的步骤S104的示意图。5 and 6 are schematic diagrams of step S104 of the method for preparing an array substrate provided by an embodiment of the invention.
图7和图8为发明实施例提供的阵列基板的制备方法的步骤S105的示意图。7 and 8 are schematic diagrams of step S105 of the method for preparing an array substrate provided by an embodiment of the invention.
图9为发明实施例提供的阵列基板的制备方法的步骤S106的示意图。FIG. 9 is a schematic diagram of step S106 of the method for preparing an array substrate provided by an embodiment of the invention.
图10为发明实施例提供的阵列基板的结构示意图。FIG. 10 is a schematic structural diagram of an array substrate provided by an embodiment of the invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明实施例提供的阵列基板的制备方法用于制备阵列基板，具体的，阵列基板包括薄膜晶体管(Thin-film transistor，TFT)、像素电极、数据线、扫描线等元件，其中，扫描线电连接至薄膜晶体管的栅极，数据线和像素电极分别电连接至薄膜晶体管的源极或漏极之一，扫描线提供扫描信号控制源极与漏极的连通或断开状态，当源极与漏极连通时，数据线传递数据信号控制像素电极的电压大小从而控制液晶显示面板显示图像的内容。The method for preparing an array substrate provided in an embodiment of the present invention is used to prepare an array substrate. Specifically, the array substrate includes elements such as thin-film transistors (Thin-film transistors, TFTs), pixel electrodes, data lines, and scanning lines. Connected to the gate of the thin film transistor, the data line and the pixel electrode are respectively electrically connected to one of the source or drain of the thin film transistor, and the scan line provides a scan signal to control the connection or disconnection of the source and the drain. When the drain is connected, the data line transmits a data signal to control the voltage of the pixel electrode so as to control the content of the image displayed by the liquid crystal display panel.
请参阅图1，本发明实施例提供的阵列基板10的制备方法的步骤如下：Please refer to FIG. 1 , the steps of the method for preparing the array substrate 10 provided by the embodiment of the present invention are as follows:
S101、在基板10表面形成第一金属层20。S101 , forming a first metal layer 20 on the surface of the substrate 10 .
请参阅图2，本实施例中，基板10为玻璃基板10或其他透明的非导电基板10，基板10作为阵列基板10的主要承载体，阵列基板10的各膜层和结构均设置于基板10之上。Please refer to FIG. 2, in this embodiment, the substrate 10 is a glass substrate 10 or other transparent non-conductive substrate 10, the substrate 10 is used as the main carrier of the array substrate 10, and each film layer and structure of the array substrate 10 are all arranged on the substrate 10. above.
一种实施方式中，第一金属层20可为Cu、Mo、Ti、Al、Cr、Ag、Au等金属材料，或氧化铟锡(ITO)、氧化铟锌(IZO)、铝掺杂的氧化锌(AZO)、铟镓锌氧化物(IGZO)、氧化锌锡(ZTO)等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构，并且第一金属层20的厚度可为500A～20000A。In one embodiment, the first metal layer 20 can be metal materials such as Cu, Mo, Ti, Al, Cr, Ag, Au, or indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped oxide Zinc (AZO), Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO) and other multi-element metal oxide conductive materials stacked structure of one or more multi-element metal oxide conductive materials, and the first metal layer The thickness of 20 may be from 500A to 20000A.
本实施例中，在基板10表面形成第一金属层20后，图案化第一金属层20形成栅极22和第一极板24，第一极板24对应后续形成的第三光阻区76。具体的，栅极22与第一极板24相互隔绝，栅极22电连接至阵列基板10上用于传递扫描信号的扫描线，第一极板24与后续步骤形成的第二极板66相对以形成电容。In this embodiment, after the first metal layer 20 is formed on the surface of the substrate 10, the first metal layer 20 is patterned to form the grid 22 and the first plate 24, and the first plate 24 corresponds to the third photoresist region 76 formed subsequently. . Specifically, the grid 22 is isolated from the first plate 24, and the gate 22 is electrically connected to the scanning line for transmitting the scanning signal on the array substrate 10, and the first plate 24 is opposite to the second plate 66 formed in a subsequent step. to form a capacitor.
本实施例中，第一金属层20可通过物理气相沉积(Physical Vapor Deposition，PVD)方法成膜于基板10上，并且可通过湿法工艺进行刻蚀成型以形成栅极22和第一极板24。一种实施方式中，第一金属层20材料为Cu，厚度为300nm，由磁控溅射方法成膜，通过湿法刻蚀(铜酸)方式实现图形化。In this embodiment, the first metal layer 20 can be formed on the substrate 10 by a physical vapor deposition (Physical Vapor Deposition, PVD) method, and can be etched and shaped by a wet process to form the gate 22 and the first plate. twenty four. In one embodiment, the first metal layer 20 is made of Cu with a thickness of 300 nm, formed by magnetron sputtering, and patterned by wet etching (copper acid).
第一金属层20的制作方法简单易实现，为后续形成薄膜晶体管和像素电极52做准备。The manufacturing method of the first metal layer 20 is simple and easy to implement, and is a preparation for the subsequent formation of the thin film transistor and the pixel electrode 52 .
S102、在第一金属层20背离基板10一侧依次沉积栅极绝缘层30、有源层40、中间层50、第二金属层60及光阻层70，栅极绝缘层30隔离第一金属层20与有源层40。S102, sequentially depositing a gate insulating layer 30, an active layer 40, an intermediate layer 50, a second metal layer 60 and a photoresist layer 70 on the side of the first metal layer 20 away from the substrate 10, the gate insulating layer 30 isolates the first metal layer 20 and active layer 40.
请结合图3，本实施例中，栅极绝缘层30覆盖第一金属层20的表面，不仅将第一金属层20与有源层40隔离以绝缘，还将第一金属层20中的栅极22与第一极板24相互隔离以绝缘。具体的，栅极绝缘层30可为SiOx、SiNx、HfO2、Al2O3等绝缘介电材料中的一种或多种绝缘介电材料的叠层结构，栅极绝缘层30的厚度可为100A～10000A，并且可通过化学气相沉积(Chemical Vapor Deposition，CVD)方法成膜。一种实施方式中，栅极绝缘层30为SiNx与SiOx的叠层结构，SiNx的厚度为100nm，SiOx的厚度为300nm，并且通过由等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)方法成膜。Please refer to FIG. 3. In this embodiment, the gate insulating layer 30 covers the surface of the first metal layer 20, not only isolating the first metal layer 20 from the active layer 40 for insulation, but also insulating the gate in the first metal layer 20. The pole 22 is isolated from the first pole plate 24 for insulation. Specifically, the gate insulating layer 30 can be a stacked structure of one or more insulating dielectric materials in insulating dielectric materials such as SiOx , SiNx , HfO2 , Al2 O3 , etc., and the gate insulating layer 30 The thickness may be 100A˜10000A, and the film may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD). In one embodiment, the gate insulating layer 30 is a laminated structure ofSiNx andSiOx , the thickness ofSiNx is 100nm, and the thickness ofSiOx is 300nm, and is formed by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) method of film formation.
本实施例中，有源层40为氧化物半导体，具体的，有源层40可为铟镓锌氧化物(IGZO)、铝掺杂的氧化锌(AZO)、氧化铟锌(IZO)、铟镓锌氧化物(IGTO)、氧化锌锡(ZTO)等透明氧化物半导体材料。有源层40的厚度可为300A～1000A。一种实施方式中，有缘层材料为IGZO，厚度为50nm，由磁控溅射方法成膜，并通过湿法工艺刻蚀。In this embodiment, the active layer 40 is an oxide semiconductor. Specifically, the active layer 40 can be indium gallium zinc oxide (IGZO), aluminum-doped zinc oxide (AZO), indium zinc oxide (IZO), indium Transparent oxide semiconductor materials such as gallium zinc oxide (IGTO) and zinc tin oxide (ZTO). The active layer 40 may have a thickness of 300A˜1000A. In one embodiment, the material of the active layer is IGZO with a thickness of 50 nm, which is formed by magnetron sputtering and etched by a wet process.
本实施例中，中间层50可为氧化铟锡(ITO)、氧化铟锌(IZO)、铝掺杂的氧化锌(AZO)、铟镓锌氧化物(IGZO)等透明导电金属氧化物材料，或石墨烯、碳纳米管薄膜等透明导电材料。中间层50材料透明导电，且与有源层40材料和第二金属层60材料之间需具有一定刻蚀比，以作为像素电极52功能使用。一种实施方式中，中间层50为IZO，厚度30nm，由磁控溅射方法成膜，通过湿法工艺刻蚀。In this embodiment, the intermediate layer 50 can be a transparent conductive metal oxide material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), indium gallium zinc oxide (IGZO), etc. Or transparent conductive materials such as graphene and carbon nanotube films. The material of the intermediate layer 50 is transparent and conductive, and must have a certain etching ratio with the material of the active layer 40 and the material of the second metal layer 60 to function as the pixel electrode 52 . In one embodiment, the intermediate layer 50 is made of IZO with a thickness of 30 nm, formed by magnetron sputtering, and etched by a wet process.
本实施例中，第二金属层60可为Cu、Mo、Ti、Al、Cr、Ag、Au等金属材料，或氧化铟锡(ITO)、氧化铟锌(IZO)、铝掺杂的氧化锌(AZO)、铟镓锌氧化物(IGZO)、氧化锌锡(ZTO)等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构，并且第二金属层60的厚度可为500A～20000A。一种实施方式中，第二金属层60材料为Cu，厚度为300nm，由磁控溅射方法成膜，通过湿法工艺(铜酸)刻蚀。In this embodiment, the second metal layer 60 can be metal materials such as Cu, Mo, Ti, Al, Cr, Ag, Au, or indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO) and other multi-element metal oxide conductive materials stacked structure of one or more multi-element metal oxide conductive materials, and the second metal layer 60 The thickness can be 500A ~ 20000A. In one embodiment, the second metal layer 60 is made of Cu with a thickness of 300 nm, formed by magnetron sputtering, and etched by a wet process (cupric acid).
本实施例中，光阻层70为光刻胶，光阻层70在后续通过半色调掩膜板80的曝光显影过程中形成厚度不同的光阻区，从而形成对应的结构。In this embodiment, the photoresist layer 70 is a photoresist, and the photoresist layer 70 forms photoresist regions with different thicknesses during subsequent exposure and development through the halftone mask 80 , thereby forming corresponding structures.
S103、使用半色调掩膜板80曝光显影。S103 , exposing and developing using the halftone mask 80 .
请结合图4，本实施例中，半色调掩膜板80包括第一透光部82和第二透光部84，光阻层70对应第一透光部82形成第一光阻区72，光阻层70对应第二透光部84形成第二光阻区74。具体的，第一透光部82和第二透光部84的透过率不同，对应形成的第一光阻区72与第二光阻区74的光阻层70的厚度不同。通过半色调掩膜板80图案化光阻层70以用于后续蚀刻对应区域的膜层(第二金属层60、中间层50、有源层40中的一种或多种)形成对应的器件结构。一种实施方式中，第一透光部82的透过率大于第二透光部84的透过率，对应形成的第一光阻区72的厚度小于第二光阻区74的厚度。本实施例中，第一光阻区72后续对应形成单向连接源极64和漏极62的沟道，第二光阻区74后续对应形成像素电极52。利用半色调掩膜板80曝光显影，显影第一透光部82形成的第一光阻区72去除对应的第二金属层60和中间层50、保留有源层40形成沟道，从而形成薄膜晶体管，显影第二透光部84形成的第二光阻区74去除对应的第二金属层60后露出透明的中间层50，并以中间层50作为像素电极52，即经过一次掩模工艺形成薄膜晶体管与像素电极52，简化了阵列基板10的制备过程，降低了产品的制备成本，缩短了生产周期。Please refer to FIG. 4 , in this embodiment, the halftone mask 80 includes a first light-transmitting portion 82 and a second light-transmitting portion 84 , and the photoresist layer 70 forms a first light-resisting region 72 corresponding to the first light-transmitting portion 82 , The photoresist layer 70 forms a second photoresist region 74 corresponding to the second light-transmitting portion 84 . Specifically, the transmittance of the first light-transmitting portion 82 and the second light-transmitting portion 84 are different, and the correspondingly formed first photoresist region 72 and the second photoresist region 74 have different thicknesses of the photoresist layer 70 . Pattern the photoresist layer 70 through the half-tone mask 80 for subsequent etching of the film layer in the corresponding region (one or more of the second metal layer 60, the intermediate layer 50, and the active layer 40) to form a corresponding device structure. In one embodiment, the transmittance of the first light-transmitting portion 82 is greater than that of the second light-transmitting portion 84 , and the thickness of the correspondingly formed first photoresist region 72 is smaller than the thickness of the second photoresist region 74 . In this embodiment, the first photoresist region 72 corresponds to subsequently forming a channel for unidirectionally connecting the source 64 and the drain 62 , and the second photoresist region 74 corresponds to subsequently forming the pixel electrode 52 . Use the halftone mask 80 to expose and develop, and develop the first photoresist region 72 formed by the first light-transmitting portion 82 to remove the corresponding second metal layer 60 and intermediate layer 50, and retain the active layer 40 to form a channel, thereby forming a thin film Transistor, the second photoresist region 74 formed by developing the second light-transmitting portion 84 removes the corresponding second metal layer 60 to expose the transparent intermediate layer 50, and the intermediate layer 50 is used as the pixel electrode 52, that is, it is formed through a mask process The thin film transistor and the pixel electrode 52 simplifies the manufacturing process of the array substrate 10 , reduces the manufacturing cost of the product, and shortens the production cycle.
本实施例中，半色调掩膜板80还包括非透光部86，光阻层70对应非透光部86形成第三光阻区76，第一光阻区72位于两个第三光阻区76之间。具体的，非透光部86为半色调掩膜板80不透光的部分，用于曝光的光线无法穿过非透光区，第三光阻区76保持光阻层70涂覆时的厚度，即第三光阻区76的厚度最大。一种实施方式中，第三光阻区76的数量为三个，其中，第一光阻区72位于两个第三光阻区76之间，该两个第三光阻区76用于后续对应形成源极64和漏极62，第一光阻区72用于后续对应形成沟道，从而形成薄膜晶体管；另一个第三光阻区76对应第一极板24的位置，用于后续形成电容。利用半色调掩膜板80曝光显影，非透光部86对应形成源极64、漏极62及电容，从而形成阵列基板10，即经过一次掩模工艺形成薄膜晶体管与像素电极52，简化了阵列基板10的制备过程，降低了产品的制备成本，缩短了生产周期。In this embodiment, the halftone mask 80 further includes a non-transparent portion 86, the photoresist layer 70 forms a third photoresist region 76 corresponding to the non-transmissive portion 86, and the first photoresist region 72 is located between the two third photoresist regions. Between District 76. Specifically, the non-transparent portion 86 is an opaque portion of the halftone mask 80, the light used for exposure cannot pass through the non-transmissive area, and the third photoresist region 76 maintains the thickness of the photoresist layer 70 when it is coated. , that is, the thickness of the third photoresist region 76 is the largest. In one embodiment, the number of the third photoresist regions 76 is three, wherein the first photoresist region 72 is located between two third photoresist regions 76, and the two third photoresist regions 76 are used for subsequent The source electrode 64 and the drain electrode 62 are formed correspondingly, and the first photoresist region 72 is used for subsequent corresponding channel formation, thereby forming a thin film transistor; another third photoresist region 76 corresponds to the position of the first electrode plate 24, and is used for subsequent formation capacitance. The half-tone mask 80 is used for exposure and development, and the non-transparent part 86 forms the source 64, the drain 62 and the capacitor correspondingly, thereby forming the array substrate 10, that is, the thin film transistor and the pixel electrode 52 are formed through a mask process, which simplifies the array. The preparation process of the substrate 10 reduces the preparation cost of the product and shortens the production cycle.
本实施例中，光阻层70还包括第四光阻区710，使用半色调掩膜板80曝光显影的同时，曝光第四光阻区710的光阻层70。具体的，半色调掩膜板80未覆盖第四光阻区710，在利用半色调掩膜板80曝光第一光阻区72和第二光阻区74的同时，曝光光线直接照射第四光阻区710的光阻层70，将第四光阻区710的光阻层70全部曝光显影，露出第四光阻区710的第二金属层60。后续去除对应第四光阻区710的第二金属层60、中间层50及有源层40以实现膜层图案化。In this embodiment, the photoresist layer 70 further includes a fourth photoresist region 710 , and the photoresist layer 70 in the fourth photoresist region 710 is exposed while exposing and developing using the halftone mask 80 . Specifically, the half-tone mask 80 does not cover the fourth photoresist region 710, and when the half-tone mask 80 is used to expose the first photoresist region 72 and the second photoresist region 74, the exposure light directly irradiates the fourth photoresist region 710. The photoresist layer 70 in the resisting area 710 exposes and develops the photoresist layer 70 in the fourth photoresisting area 710 completely, exposing the second metal layer 60 in the fourth photoresisting area 710 . Subsequently, the second metal layer 60 , the intermediate layer 50 and the active layer 40 corresponding to the fourth photoresist region 710 are removed to realize film layer patterning.
利用半色调掩膜板80经过一次曝光显影同时形成了第一光阻区72、第二光阻区74、第三光阻区76、第四光阻区710，用于后续对应形成薄膜晶体管、像素电极52及电容等器件结构，简化了阵列基板10的制备过程，降低了产品的制备成本，缩短了生产周期。The first photoresist region 72, the second photoresist region 74, the third photoresist region 76, and the fourth photoresist region 710 are simultaneously formed by using the halftone mask 80 through one exposure and development, for subsequent corresponding formation of thin film transistors, Device structures such as pixel electrodes 52 and capacitors simplify the manufacturing process of the array substrate 10 , reduce the manufacturing cost of the product, and shorten the production cycle.
S104、在第一光阻区72处，去除光阻层70、第二金属层60和中间层50，使有源层40外露，以形成沟道及源极64和漏极62。S104 , at the first photoresist region 72 , remove the photoresist layer 70 , the second metal layer 60 and the intermediate layer 50 to expose the active layer 40 to form a channel, source 64 and drain 62 .
请结合图5，本实施例中，形成沟道之前，还要刻蚀去除第四光阻区710的第二金属层60、中间层50及有源层40。一种实施方式中，第二金属层60材料为Cu，厚度为300nm，由磁控溅射方法成膜，通过湿法工艺(铜酸)刻蚀，中间层50为IZO，厚度30nm，由磁控溅射方法成膜，通过湿法工艺刻蚀，有缘层材料为IGZO，厚度为50nm，由磁控溅射方法成膜，通过湿法工艺刻蚀。具体的，第四光阻区710用于进行膜层图案化，以实现阵列基板10的整体图案。Referring to FIG. 5 , in this embodiment, before forming the channel, the second metal layer 60 , the intermediate layer 50 and the active layer 40 of the fourth photoresist region 710 are etched and removed. In one embodiment, the material of the second metal layer 60 is Cu with a thickness of 300nm, which is formed by magnetron sputtering and etched by a wet process (copper acid). The intermediate layer 50 is IZO with a thickness of 30nm. The film is formed by the sputtering method and etched by the wet process. The material of the insulating layer is IGZO with a thickness of 50nm. The film is formed by the magnetron sputtering method and etched by the wet process. Specifically, the fourth photoresist region 710 is used for patterning the film layer, so as to realize the overall pattern of the array substrate 10 .
请结合图6，本实施例中，首先采用O2等离子体刻蚀灰化光阻层70，从而去除第一光阻区72的光阻层70，露出第二金属层60，再刻蚀去除对应第一光阻区72的第二金属层60和中间层50，保留有源层40形成沟道。一种实施方式中，第二金属层60材料为Cu，厚度为300nm，由磁控溅射方法成膜，通过湿法工艺(铜酸)刻蚀，中间层50为IZO，厚度30nm，由磁控溅射方法成膜，通过湿法工艺刻蚀。Please refer to FIG. 6. In this embodiment, firstly, the photoresist layer 70 is ashed byO2 plasma etching, thereby removing the photoresist layer 70 in the first photoresist region 72, exposing the second metal layer 60, and then etching and removing Corresponding to the second metal layer 60 and the intermediate layer 50 of the first photoresist region 72 , the active layer 40 remains to form a channel. In one embodiment, the material of the second metal layer 60 is Cu with a thickness of 300nm, which is formed by magnetron sputtering and etched by a wet process (copper acid). The intermediate layer 50 is IZO with a thickness of 30nm. The film is formed by controlled sputtering method and etched by wet process.
S105、在第二光阻区74处，去除光阻层70、第二金属层60，使中间层50外露，形成像素电极52。S105 , at the second photoresist region 74 , remove the photoresist layer 70 and the second metal layer 60 to expose the intermediate layer 50 to form the pixel electrode 52 .
请结合图7，本实施例中，首先采用O2等离子体刻蚀灰化光阻层70，从而去除第二光阻区74的光阻层70，露出第二金属层60，再刻蚀去除对应第二光阻区74的第二金属层60，保留中间层50形成像素电极52。一种实施方式中，第二金属层60材料为Cu，厚度为300nm，由磁控溅射方法成膜，通过湿法工艺(铜酸)刻蚀。Please refer to FIG. 7. In this embodiment, the photoresist layer 70 is first ashed byO2 plasma etching, thereby removing the photoresist layer 70 in the second photoresist region 74, exposing the second metal layer 60, and then etching and removing Corresponding to the second metal layer 60 of the second photoresist region 74 , the intermediate layer 50 is left to form the pixel electrode 52 . In one embodiment, the second metal layer 60 is made of Cu with a thickness of 300 nm, formed by magnetron sputtering, and etched by a wet process (cupric acid).
请结合图8，本实施例中，形成所述像素电极52后，还要去除第三光阻区76的光阻层70，露出第二金属层60。具体的，第一光阻区72两侧的两个第三光阻区76对应的第二金属层60分别形成源极64和漏极62，源极64和漏极62通过有源层40单向连通。一种实施方式中，源极64与形成像素电极52的中间层50接触并电连接，漏极62与数据线电连接，从而当源极64与漏极62导通时数据线传递的数据信号控制像素电压的电压变化，从而控制显示设备显示图像的内容。第三光阻区76对应的第二金属层60形成第二极板66，第二极板66与第一极板24对应形成电容，电容起到充放电的作用从而对像素电极52进行影响。Referring to FIG. 8 , in this embodiment, after the formation of the pixel electrode 52 , the photoresist layer 70 of the third photoresist region 76 should be removed to expose the second metal layer 60 . Specifically, the second metal layer 60 corresponding to the two third photoresist regions 76 on both sides of the first photoresist region 72 forms the source electrode 64 and the drain electrode 62 respectively, and the source electrode 64 and the drain electrode 62 are separated by the active layer 40 To connect. In one embodiment, the source electrode 64 is in contact with and electrically connected to the intermediate layer 50 forming the pixel electrode 52, and the drain electrode 62 is electrically connected to the data line, so that when the source electrode 64 and the drain electrode 62 are turned on, the data signal transmitted by the data line Control the voltage change of the pixel voltage, thereby controlling the content of the image displayed by the display device. The second metal layer 60 corresponding to the third photoresist region 76 forms a second plate 66 , and the second plate 66 corresponds to the first plate 24 to form a capacitor, which is charged and discharged to affect the pixel electrode 52 .
S106、沉积钝化层90保护阵列基板10，刻蚀像素电极52表面的钝化层90，露出像素电极52。S106 , depositing a passivation layer 90 to protect the array substrate 10 , and etching the passivation layer 90 on the surface of the pixel electrode 52 to expose the pixel electrode 52 .
请结合图9，钝化层90用于保护器件，本实施例中，钝化层90可为SiOx、SiNx、HfO2、Al2O3等绝缘材料中的一种或多种绝缘材料的叠层结构，钝化层90厚度可为1000A～10000A，并可通过CVD方法成膜。一种实施方式中，栅极绝缘层30为SiOx和SiNx叠层结构，SiOx的厚度为300nm，SiNx的厚度为100nm，栅极绝缘层30由PECVD方法成膜，并通过干法工艺进行刻蚀。Please refer to FIG. 9, the passivation layer 90 is used to protect the device. In this embodiment, the passivation layer 90 can be one or more insulating materials such asSiOx ,SiNx ,HfO2 ,Al2O3, etc. The thickness of the passivation layer 90 can be 1000A-10000A, and can be formed by CVD. In one embodiment, the gate insulating layer 30 is a stacked structure ofSiOx andSiNx , the thickness ofSiOx is 300nm, the thickness ofSiNx is 100nm, the gate insulating layer 30 is formed by PECVD method, and is dried process for etching.
本实施例中，刻蚀钝化层90露出像素电极52的过程经历了一次掩膜工艺，形成薄膜晶体管和像素电极52经历了一次掩模工艺，故在阵列基板10的制备过程中最少只需两次掩模工艺即可实现薄膜晶体管和像素电极52区域的所有图形化工艺，简化了阵列基板10的制备过程，降低了产品的制备成本，缩短了生产周期。In this embodiment, the process of etching the passivation layer 90 to expose the pixel electrode 52 has undergone a masking process, and the formation of the thin film transistor and the pixel electrode 52 has undergone a masking process. Therefore, in the preparation process of the array substrate 10, at least All the patterning processes of the thin film transistor and the pixel electrode 52 area can be realized by two masking processes, which simplifies the preparation process of the array substrate 10 , reduces the preparation cost of the product, and shortens the production cycle.
请参阅图10，本发明实施例还提供一种阵列基板100，阵列基板100由本发明实施例提供的阵列基板100的制备方法制备。阵列基板100包括栅极22、栅极绝缘层30、有源层40、中间层50、源极62及漏极64，栅极22、栅极绝缘层30及有源层40依次层叠设置，栅极绝缘层30隔绝栅极22与有源层40，源极62和漏极64位于有源层40背离栅极22的一侧，中间层50包括相互隔绝的第一部分502与第二部分504，具体的，中间层50为导电材料，并且第一部分502与第二部分504通过同一道气相沉积后形成。第一部分502位于源极62与有源层40之间，第二部分504位于漏极64与有源层40之间，中间层50用于阻隔源极62或漏极64向有源层40扩散金属原子，并且第一部分502或第二部分504用作像素电极。具体的，第一部分502与第二部分504为中间层50经过蚀刻后形成，第一部分502与第二部分504相互不导通。一种实施方式中，第二部分504作为像素电极，漏极64通过第二部分504电连接至有源层40，源极62通过第一部分502电连接至有源层40，当栅极22导通时，源极62通过有源层40单向导通至漏极64，即驱动信号从源极62传递至漏极64，进而对像素电极(第二部分504)充电。其他实施方式中，第一部分502也可以作为像素电极。中间层50阻挡了高导材料的源极62或漏极64向有源层40扩散金属原子，避免器件性能劣化，提高阵列基板100的使用寿命，同时，第一部分502或第二部分504还作为像素电极，结构简单，不增加阵列基板100的制作过程降低了产品的制备成本，缩短了生产周期。Please refer to FIG. 10 , the embodiment of the present invention also provides an array substrate 100 , and the array substrate 100 is prepared by the method for manufacturing the array substrate 100 provided in the embodiment of the present invention. The array substrate 100 includes a gate 22, a gate insulating layer 30, an active layer 40, an intermediate layer 50, a source 62, and a drain 64. The gate 22, the gate insulating layer 30, and the active layer 40 are stacked in sequence. The insulating layer 30 isolates the gate 22 from the active layer 40, the source 62 and the drain 64 are located on the side of the active layer 40 away from the gate 22, the intermediate layer 50 includes a first part 502 and a second part 504 isolated from each other, Specifically, the intermediate layer 50 is a conductive material, and the first part 502 and the second part 504 are formed by the same vapor deposition. The first part 502 is located between the source electrode 62 and the active layer 40, the second part 504 is located between the drain electrode 64 and the active layer 40, and the intermediate layer 50 is used to prevent the source electrode 62 or the drain electrode 64 from diffusing to the active layer 40. metal atoms, and the first part 502 or the second part 504 serves as a pixel electrode. Specifically, the first portion 502 and the second portion 504 are formed after the intermediate layer 50 is etched, and the first portion 502 and the second portion 504 are not electrically connected to each other. In one embodiment, the second part 504 is used as a pixel electrode, the drain 64 is electrically connected to the active layer 40 through the second part 504, and the source 62 is electrically connected to the active layer 40 through the first part 502. When the gate 22 conducts When turned on, the source electrode 62 is unidirectionally conducted to the drain electrode 64 through the active layer 40 , that is, the driving signal is transmitted from the source electrode 62 to the drain electrode 64 , thereby charging the pixel electrode (second part 504 ). In other implementation manners, the first portion 502 may also serve as a pixel electrode. The intermediate layer 50 prevents the source electrode 62 or the drain electrode 64 of the high-conductivity material from diffusing metal atoms to the active layer 40, avoiding device performance degradation, and improving the service life of the array substrate 100. At the same time, the first part 502 or the second part 504 also serves as The pixel electrode has a simple structure, does not increase the manufacturing process of the array substrate 100, reduces the manufacturing cost of the product, and shortens the production cycle.
以上所揭露的仅为本发明几种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。The above disclosures are only several preferred embodiments of the present invention, and of course the scope of rights of the present invention cannot be limited by this. Those of ordinary skill in the art can understand all or part of the processes for realizing the above embodiments, and according to the rights of the present invention The equivalent changes required still belong to the scope covered by the invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711091327.4ACN107871753B (en) | 2017-11-08 | 2017-11-08 | Array substrate and preparation method thereof |
| Application Number | Priority Date | Filing Date | Title |
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| CN201711091327.4ACN107871753B (en) | 2017-11-08 | 2017-11-08 | Array substrate and preparation method thereof |
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| CN107871753Atrue CN107871753A (en) | 2018-04-03 |
| CN107871753B CN107871753B (en) | 2020-11-06 |
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| CN201711091327.4AActiveCN107871753B (en) | 2017-11-08 | 2017-11-08 | Array substrate and preparation method thereof |
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| CN (1) | CN107871753B (en) |
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