本申请是于2016年6月23日提交的美国专利申请号15/190,749的部分继续申请，所述美国专利申请是于2015年9月22日提交的美国专利申请号14/861,951，现在的美国专利号9,401,216的继续申请。This application is a continuation-in-part of U.S. Patent Application No. 15/190,749, filed June 23, 2016, which is U.S. Patent Application No. 14/861,951, filed September 22, 2015, now U.S. Continuation of Patent No. 9,401,216.
背景技术Background technique
本申请涉及对可重新编程非易失性存储器(比如，半导体闪存、电阻式存储器、相变存储器等)的操作。The present application relates to the operation of reprogrammable non-volatile memory (eg, semiconductor flash memory, resistive memory, phase change memory, etc.).
能够对电荷进行非易失性存储的固态存储器(特别是采取被封装为小形状因数卡的EEPROM和闪速EEPROM的形式)已经变成各种移动和手持式设备(尤其是信息电器和消费者电子产品)中的精选存储设备。不像同样作为固态存储器的RAM(随机存取存储器)，闪存是非易失性的并且甚至在关掉电源之后保留其存储数据。而且，不像ROM(只读存储器)，类似于磁盘存储设备，闪存是可重写的。Solid-state memory capable of non-volatile storage of charge, especially in the form of EEPROM and flash EEPROM packaged as small form-factor cards, has become a major part of mobile and handheld devices, especially information appliances and consumer Select storage devices in Electronics). Unlike RAM (Random Access Memory), which is also a solid-state memory, flash memory is non-volatile and retains its stored data even after the power is turned off. Also, unlike ROM (read only memory), flash memory is rewritable, similar to magnetic disk storage devices.
闪速EEPROM类似于EEPROM(电可擦除可编程只读存储器)，因为它是可以被擦除的并且使新数据写入或“编程”到其存储器单元中的非易失性存储器。两者都利用场效应晶体管结构中被定位在半导体衬底中在源极区域与漏极区域之间的沟道区域之上的浮置(未连接的)导电栅极。然后，通过浮栅提供控制栅极。晶体管的阈值电压特性由保留在浮栅上的电荷的量控制。也就是说，对于浮栅上的给定电荷水平，在“接通”晶体管以便允许其源极区域与漏极区域之间导电之前，存在将向控制栅极施加的相应电压(阈值)。如闪速EEPROM等闪存允许同时擦除整个存储器单元块。Flash EEPROM is similar to EEPROM (Electrically Erasable Programmable Read Only Memory) in that it is a non-volatile memory that can be erased and have new data written or "programmed" into its memory cells. Both utilize a floating (unconnected) conductive gate in a field effect transistor structure positioned over a channel region in a semiconductor substrate between a source region and a drain region. Then, a control gate is provided through a floating gate. The threshold voltage characteristics of a transistor are controlled by the amount of charge retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that will be applied to the control gate before the transistor is "turned on" to allow conduction between its source and drain regions. Flash memory, such as flash EEPROM, allows an entire block of memory cells to be erased at the same time.
浮栅可以保持一些电荷，并且因此可以被编程到阈值电压窗口内的任何阈值电压水平。阈值电压窗口的大小由设备的最小和最大阈值水平界定，所述最小和最大阈值水平进而与可以编程到浮栅上的所述一些电荷相对应。阈值窗口通常取决于存储器设备的特性、操作条件和历史。原则上，窗口内的每个不同的可分解阈值电压水平范围可以用于指定单元的确切存储器状态。The floating gate can hold some charge and thus can be programmed to any threshold voltage level within the threshold voltage window. The size of the threshold voltage window is bounded by the minimum and maximum threshold levels of the device, which in turn correspond to the amount of charge that can be programmed onto the floating gate. The threshold window typically depends on the characteristics, operating conditions and history of the memory device. In principle, each distinct range of resolvable threshold voltage levels within the window can be used to specify the exact memory state of the cell.
非易失性存储器设备还由具有用于存储或“俘获”电荷的介电层的存储器单元制成。使用介电层而不是此前描述的导电浮栅元件。ONO介电层延伸跨过源极扩散与漏极扩散之间的沟道。一个数据位的电荷被定位在与漏极相邻的介电层中，而另一个数据位的电荷被定位在与源极相邻的介电层中。通过分别读取电介质内的空间分离电荷储存区域的二进制状态来实施多状态数据存储。Non-volatile memory devices are also made from memory cells that have a dielectric layer for storing or "trapping" charge. A dielectric layer is used instead of the previously described conductive floating gate elements. The ONO dielectric layer extends across the channel between the source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
许多非易失性存储器沿着衬底(例如，硅衬底)表面形成为二维(2D)或平面存储器。其他非易失性存储器是三维(3D)存储器，所述3D存储器单片地形成于具有被布置在衬底上方的有源区域的一个或多个物理存储器单元级中。Many non-volatile memories are formed as two-dimensional (2D) or planar memories along the surface of a substrate (eg, a silicon substrate). Other non-volatile memories are three-dimensional (3D) memories formed monolithically in one or more levels of physical memory cells with active regions arranged above a substrate.
发明内容Contents of the invention
在三维存储器系统中，块可由可分别选择的部分形成。例如，在NAND闪存中，串集合可以共享选择线，从而使得块中的这种串集合是可分别选择的。在其他存储器中，其他安排可以导致可分别选择的部分，所述可分别选择的部分可能具有可以测量并且可以用于标识什么时候对对应部分的操作参数(比如，编程电压)进行调整的特性。在电阻式存储器(例如，ReRAM)，局部位线可以与水平地延伸的字线以及不同级处的局部位线与字线之间延伸的电阻式存储器元件垂直地延伸。一行这种局部位线可由行选择线一起选择。类似安排可以用于如相变存储器等其他存储器元件。可以被称为“交叉点存储器”的替代性安排包括以在衬底表面上方的不同高度并且在与在字线与位线之间垂直地延伸的存储器元件不同(例如，正交)的方向上水平地延伸的字线和位线。存储器元件可以是电阻式元件、电荷存储或俘获元件、相变元件或任何其他适当的存储器元件。In a three-dimensional memory system, a block can be formed from separately selectable parts. For example, in NAND flash memory, sets of strings can share a select line so that such sets of strings in a block are individually selectable. In other memories, other arrangements may result in individually selectable portions that may have characteristics that can be measured and used to identify when adjustments to operating parameters (eg, programming voltages) of corresponding portions are made. In resistive memory (eg, ReRAM), local bit lines may extend vertically with horizontally extending word lines and resistive memory elements extending between the local bit lines and word lines at different levels. A row of such local bitlines can be selected together by a row select line. Similar arrangements can be used for other memory elements such as phase change memory. An alternative arrangement, which may be referred to as "cross-point memory," involves memory elements at different heights above the substrate surface and in a different (e.g., orthogonal) direction than the memory elements extending vertically between word lines and bit lines. Horizontally extending word lines and bit lines. The memory elements may be resistive elements, charge storage or trapping elements, phase change elements, or any other suitable memory elements.
三维非易失性存储器中的块可以包括多个可分别选择的NAND串集合，所述多个可分别选择的NAND串集合中的一些可分别选择的NAND串集合可以具有在NAND串的特性的正常范围之外的特性，这可能使它们在某个点(或者在测试期间或者在操作期间)失败。例如，因为在擦除验证期间流过可分别选择的NAND串集合的电流由于与被擦除存储器单元串联的电阻而很低，所以可能发生擦除失败。这种电阻可能例如由于NAND串与位线之间或者NAND串与共用源极之间的不良连接，或者可能由于一个或多个选择晶体管或其他某个元件。可以通过施加更高的位线电压来克服由于这种电阻而造成的低电流。可以在逐串的基础上、逐列的基础上(其中，列包括多条位线)或者针对整个可分别选择的NAND串集合而完成这一点。可以保持用于指示要使用的位线电压的记录。可以通过施加增大的选择线电压来使由选择晶体管引起的低电流达到可接受水平。在块的需要经修改的参数(比如，增大的位线或选择线电压)的部分中存储的数据可以以增大的冗余率来进行存储以便确保安全地维护数据。A block in a three-dimensional nonvolatile memory may include a plurality of individually selectable sets of NAND strings, and some of the plurality of individually selectable sets of NAND strings may have characteristics within the range of NAND strings. Characteristics outside the normal range, which may cause them to fail at some point (either during testing or during operation). For example, erase failures may occur because the current flowing through the individually selectable sets of NAND strings during erase verify is low due to the resistance in series with the erased memory cells. This resistance may be due, for example, to a bad connection between the NAND string and the bit line or between the NAND string and the common source, or it may be due to one or more select transistors or some other element. The low current due to this resistance can be overcome by applying a higher bit line voltage. This can be done on a string-by-string basis, a column-by-column basis (where a column includes multiple bit lines), or for an entire set of individually selectable NAND strings. A record may be kept indicating which bit line voltage to use. The low current drawn by the select transistor can be brought to an acceptable level by applying an increased select line voltage. Data stored in portions of the block that require modified parameters (eg, increased bit line or select line voltages) can be stored with increased redundancy to ensure that the data is safely maintained.
一种三维非易失性存储器系统的示例包括：三维非易失性存储器块，所述三维非易失性存储器块包含多个可分别选择的部分，单独的可分别选择的部分包含垂直于衬底表面而延伸的多条位线；读出单元，所述读出单元被配置成用于读出所述块的所述多个可分别选择的部分的位线的位线电流和/或电压并且用于将针对单独的可分别选择的部分的读出的对应结果与参考进行比较；以及调整单元，所述调整单元与所述读出单元通信，所述调整单元被配置成用于响应于对所述块的所述多个可分别选择的部分中的一个或多个可分别选择的部分的对应结果与所述参考的所述比较而单独地修改所述块的所述多个可分别选择的部分中的所述一个或多个可分别选择的部分的操作参数。An example of a three-dimensional non-volatile memory system includes a three-dimensional non-volatile memory block comprising a plurality of individually selectable portions, the individual individually selectable portions comprising a plurality of bit lines extending from the bottom surface; a sense unit configured to sense bit line currents and/or voltages of the bit lines of the plurality of respectively selectable portions of the block and for comparing the corresponding results of the readouts for the individual respectively selectable portions with a reference; and an adjustment unit in communication with the readout unit, the adjustment unit being configured to respond to individually modifying said plurality of respectively selectable portions of said block for said comparison of a corresponding result of one or more of said plurality of respectively selectable portions of said block with said reference Operating parameters of the one or more respectively selectable sections of the selected sections.
所述三维非易失性存储器块和所述读出单元可以位于存储器裸片中并且所述调整单元可以位于控制器裸片中。多条全局位线可以在第一方向上平行于所述衬底表面而延伸的，并且所述多条位线可以通过多个选择晶体管而连接至所述多条全局位线。选择线可以在正交于所述第一方向的第二方向上平行于所述衬底表面而延伸，所述选择线耦合至所述多个选择晶体管以便分别选择所述多条位线。单独的位线可以延伸穿过多个字线水平并且可以在所述多个字线水平中的每个字线水平处形成单独的存储器元件。所述存储器元件可以是电荷存储或电荷俘获元件、电阻式元件或相变存储器元件。所述调整单元可以被配置成用于响应于所述比较而单独地修改所述多个可分别选择的部分中的每个可分别选择的部分的编程电压和/或选择电压。可以向所述调整单元提供温度输入，并且所述调整单元可以被进一步配置成用于响应于所述温度输入而修改操作参数。The three-dimensional non-volatile memory block and the readout unit may be located in a memory die and the adjustment unit may be located in a controller die. A plurality of global bit lines may extend parallel to the substrate surface in a first direction, and the plurality of bit lines may be connected to the plurality of global bit lines through a plurality of selection transistors. Select lines may extend parallel to the substrate surface in a second direction orthogonal to the first direction, the select lines coupled to the plurality of select transistors to select the plurality of bit lines, respectively. Individual bit lines may extend across multiple word line levels and individual memory elements may be formed at each of the multiple word line levels. The memory elements may be charge storage or charge trapping elements, resistive elements or phase change memory elements. The adjustment unit may be configured for individually modifying the programming voltage and/or the selection voltage of each of the plurality of respectively selectable parts in response to the comparison. A temperature input may be provided to the adjustment unit, and the adjustment unit may be further configured to modify an operating parameter in response to the temperature input.
一种三维非易失性存储器的示例包括：多条第一线，所述多条第一线以超过衬底表面的第一高度沿着第一方向延伸；多条第二线，所述多条第二线以超过所述衬底表面的第二高度沿着第二方向延伸，所述第二方向与所述第一方向正交；多个存储器元件，单独的存储器元件从在所述第一高度处的第一线延伸到在所述第二高度处的第二线；读出单元，所述读出单元被配置成用于读出所述第一线的电流和/或电压并且用于将所述读出的结果与参考进行比较；以及调整单元，所述调整单元与所述读出单元通信，所述调整单元被配置成用于响应于所述比较而修改连接至所述第一线的存储器元件的操作参数。An example of a three-dimensional nonvolatile memory includes: a plurality of first lines extending along a first direction at a first height exceeding a surface of a substrate; a plurality of second lines extending in a first direction A second line extends along a second direction at a second height beyond the substrate surface, the second direction being orthogonal to the first direction; a plurality of memory elements, individual memory elements extending from the first height The first line at the second height extends to the second line at the second height; the readout unit is configured to read out the current and/or voltage of the first line and to convert the comparing a result of the readout with a reference; and an adjustment unit in communication with the readout unit, the adjustment unit being configured to modify a signal connected to the first line in response to the comparison. Operating parameters of the memory element.
所述调整单元可以被配置成用于响应于所述比较而修改连接至所述第一线的存储器元件的编程电压。所述调整单元可以被配置成用于响应于所述比较而修改连接至所述第一线的存储器元件的读取电压。所述多个存储器元件可以是电阻式存储器元件、相变存储器元件或电荷存储元件。附加第一线可以以超过所述衬底表面的附加高度在第一方向上延伸，附加第二线可以以超过所述衬底表面的附加高度在第二方向上延伸，并且附加存储器元件可以从所述附加第一线延伸到所述附加第二线，并且所述调整单元可以被配置成用于根据被定位在超过所述衬底表面的多个不同高度处的存储器元件的对应高度来改变所述存储器元件的操作参数。可以向所述调整单元提供温度输入，并且所述调整单元可以被进一步配置成用于响应于所述温度输入而修改操作参数。所述多条第一线、所述多条第二线、所述多个存储器元件以及所述读出单元可以位于第一裸片中，并且所述调整单元可以位于第二裸片中，所述调整单元的所述输入由所述第二裸片中的温度传感器生成。The adjustment unit may be configured to modify a programming voltage of a memory element connected to the first line in response to the comparison. The adjustment unit may be configured to modify a read voltage of a memory element connected to the first line in response to the comparison. The plurality of memory elements may be resistive memory elements, phase change memory elements, or charge storage elements. Additional first lines may extend in a first direction with an additional height above the substrate surface, additional second lines may extend in a second direction with an additional height above the substrate surface, and additional memory elements may extend from the The additional first line extends to the additional second line, and the adjustment unit may be configured to vary the Operating parameters of the memory element. A temperature input may be provided to the adjustment unit, and the adjustment unit may be further configured to modify an operating parameter in response to the temperature input. The plurality of first lines, the plurality of second lines, the plurality of memory elements, and the readout unit may be located in a first die, and the adjustment unit may be located in a second die, the The input to the adjustment unit is generated by a temperature sensor in the second die.
一种对包括块中的多个可分别选择的部分的三维非易失性存储器进行操作的方法的示例包括：测量通过可分别选择的部分中的导线的电流；将所述电流与预定标准进行比较；如果所述电流不满足所述预定标准，则计算一个或多个电压偏移；以及随后，在向所述块的其他可分别选择的部分施加的其他电压在访问所述块的所述其他可分别选择的部分时保持未被调整的同时，在访问所述可分别选择的部分中的存储器元件时，将向所述可分别选择的部分中的线施加的电压调整所述一个或多个电压偏移。An example of a method of operating a three-dimensional nonvolatile memory including a plurality of individually selectable portions in a block includes: measuring a current through a wire in the individually selectable portions; comparing the current with a predetermined standard comparing; if the current does not meet the predetermined criteria, calculating one or more voltage offsets; and subsequently, applying other voltages to other respectively selectable portions of the block before accessing the While the other individually selectable portions remain unadjusted, the voltages applied to the lines in the individually selectable portions are adjusted while the memory elements in the individually selectable portions are being accessed by the one or more a voltage offset.
可以将所述可分别选择的部分的所述一个或多个电压偏移记录在表中，并且随后可以在访问所述可分别选择的部分之前从所述表中获得所述一个或多个电压偏移。可以将增强型冗余方案应用于在不满足所述预定标准的可分别选择的部分中存储的数据，所述增强型冗余方案提供比应用于在满足所述预定标准的串集合中所存储的数据的通常冗余方案更高程度的纠错能力。可以测量所述三维非易失性存储器的温度，并且可以根据所述所测量的温度来调整向所述可分别选择的部分中以及其他可分别选择的部分中的线施加的电压。The one or more voltage offsets of the individually selectable portions may be recorded in a table, and the one or more voltages may subsequently be obtained from the table prior to accessing the individually selectable portions offset. An enhanced redundancy scheme may be applied to the data stored in the respectively selectable portions that do not meet said predetermined criteria, said enhanced redundancy scheme providing a higher degree of redundancy than applied to data stored in the set of strings meeting said predetermined criteria. A higher degree of error correction capability for the usual redundancy schemes of the data. The temperature of the three-dimensional nonvolatile memory may be measured, and voltages applied to the lines in the individually selectable sections and in other individually selectable sections may be adjusted according to the measured temperatures.
一种三维非易失性存储器系统的示例包括：块，所述块包含多个可分别选择的NAND串集合；位线电流读出单元，所述位线电流读出单元被配置成用于读出所述块的可分别选择的NAND串集合的位线电流并且用于将所述位线电流与最小电流进行比较；以及位线电压调整单元，所述位线电压调整单元与所述位线电流读出单元通信，所述位线电压调整单元被配置成用于向具有比所述最小电流更大的位线电流的可分别选择的NAND串集合施加第一位线电压，并且被配置成用于向具有比所述最小电流更小的位线电流的可分别选择的NAND串集合施加第二位线电压，所述第二位线电压大于所述第一位线电压。An example of a three-dimensional nonvolatile memory system includes: a block containing a plurality of individually selectable sets of NAND strings; a bit line current sense unit configured to read outputting the bit line current of the individually selectable set of NAND strings of the block and for comparing the bit line current with a minimum current; and a bit line voltage adjustment unit which is connected to the bit line a current sense unit in communication, the bit line voltage adjustment unit configured to apply a first bit line voltage to a set of individually selectable NAND strings having a bit line current greater than the minimum current, and configured to for applying a second bit line voltage to a respectively selectable set of NAND strings having a bit line current less than said minimum current, said second bit line voltage being greater than said first bit line voltage.
可以在对所述块的编程、读取或擦除期间施加所述第一和第二位线电压。所述位线电流读出单元可以被配置成用于读出所述块的所述多个可分别选择的NAND串集合中的每个可分别选择的NAND串集合的位线电流并且用于将所述位线电流中的每个位线电流与所述最小电流进行比较，并且所述位线电压调整单元可以被配置成用于至少向所述块中的所述多个可分别选择的NAND串集合中具有比所述最小电流更小的位线电流的任何可分别选择的NAND串集合施加所述第二位线电压。表可以记录至少接收所述第二位线电压的每个可分别选择的NAND串集合的条目，条目指示要向相应可分别选择的NAND串集合施加的位线电压。选择线电压读出单元可以被配置成用于读出选择线阈值电压并且用于将选择线阈值电压与最小阈值电压进行比较；并且选择线电压调整单元可以被配置成用于对具有比所述最小阈值电压更小的选择线阈值电压的选择线的选择线电压进行调整。表可以记录具有比所述最小阈值电压更小的选择线阈值电压的每个可分别选择的NAND串集合的条目，表中的条目指示待向相应可分别选择的NAND串集合中的选择线施加的选择线电压。自适应数据编码单元可以在存储之前使用可变冗余来对数据进行编码，所述自适应数据编码单元可以被配置成用于将第一冗余方案应用于在具有比所述最小电流更大的位线电流的可分别选择的NAND串集合中存储的数据并且被配置成用于将第二冗余方案应用于在具有比所述最小电流更小的位线电流的可分别选择的NAND串集合中存储的数据。表可以记录具有比所述最小电流更小的位线电流的每个可分别选择的NAND串集合的条目，所述表中的条目指示待应用于在相应可分别选择的NAND串集合中存储的数据的冗余方案。The first and second bit line voltages may be applied during programming, reading or erasing of the block. The bit line current sensing unit may be configured to sense the bit line current of each respectively selectable set of NAND strings of the plurality of individually selectable sets of NAND strings of the block and to Each of the bit line currents is compared to the minimum current, and the bit line voltage adjustment unit may be configured to provide at least one of the plurality of individually selectable NANDs in the block. Any respectively selectable set of NAND strings in the set of strings having a bit line current less than the minimum current applies the second bit line voltage. The table may record an entry for each individually selectable set of NAND strings receiving at least said second bit line voltage, the entry indicating the bit line voltage to be applied to the respective respectively selectable set of NAND strings. The selection line voltage readout unit may be configured to read out a selection line threshold voltage and to compare the selection line threshold voltage with a minimum threshold voltage; and the selection line voltage adjustment unit may be configured to compare The selection line voltage of the selection line whose minimum threshold voltage is smaller than the selection line threshold voltage is adjusted. The table may record an entry for each set of individually selectable NAND strings having a select line threshold voltage smaller than said minimum threshold voltage, the entry in the table indicating that a select line in the corresponding set of respectively selectable NAND strings is to be applied The choice of line voltage. An adaptive data encoding unit may encode data using variable redundancy prior to storage, the adaptive data encoding unit may be configured to apply a first redundancy scheme to data stored in the set of individually selectable NAND strings of bit line currents and configured for applying the second redundancy scheme to the individually selectable NAND strings having bit line currents less than said minimum current The data stored in the collection. A table may record an entry for each respectively selectable set of NAND strings having a bit line current less than said minimum current, the entry in said table indicating the Data redundancy scheme.
一种三维非易失性存储器的示例包括：块中的第一可分别选择的NAND串集合，使用第一冗余级来对所述第一可分别选择的NAND串集合中的数据进行编码；以及所述块中的第二可分别选择的NAND串集合，使用第二冗余级来对所述第二可分别选择的NAND串集合中的数据进行编码，所述第二冗余级提供比所述第一冗余级更高程度的纠错能力。An example of a three-dimensional non-volatile memory includes: a first individually selectable set of NAND strings in a block, encoding data in the first individually selectable set of NAND strings using a first level of redundancy; and a second respectively selectable set of NAND strings in the block, data in the second respectively selectable set of NAND strings is encoded using a second redundancy level that provides a ratio of The first redundancy level has a higher degree of error correction capability.
自适应编码器/解码器可以被配置成用于根据存储数据的可分别选择的NAND串集合的特性使用可变冗余级来对数据进行编码和解码。位线调整单元可以被配置成用于向所述第一可分别选择的NAND串集合中的位线施加第一位线电压，并且用于向所述第二可分别选择的NAND串集合中的位线施加第二位线电压。对所述自适应编码器/解码器的配置以及将所述位线调整单元配置成用于施加所述第一位线电压和所述第二位线电压可以是对所述第一和第二可分别选择的NAND串集合的测试的响应。选择线调整单元可以被配置成用于向所述第一可分别选择的NAND串集合中的第一选择线施加第一选择电压，并且用于向所述第二可分别选择的NAND串集合中的第二选择线施加第二选择电压。所述第一冗余级和所述第二冗余级可以分别根据所述第一可分别选择的NAND串集合和所述第二可分别选择的NAND串集合的特性来确定。The adaptive encoder/decoder may be configured to encode and decode data using variable levels of redundancy according to the characteristics of the respectively selectable sets of NAND strings storing the data. The bit line adjustment unit may be configured to apply a first bit line voltage to the bit lines in the first respectively selectable set of NAND strings and to apply a first bit line voltage to the bit lines in the second respectively selectable set of NAND strings. A second bit line voltage is applied to the bit line. Configuring the adaptive encoder/decoder and configuring the bit line adjustment unit to apply the first bit line voltage and the second bit line voltage may be a combination of the first and second Responses to tests for individually selectable sets of NAND strings. The selection line adjusting unit may be configured to apply a first selection voltage to a first selection line in the first set of individually selectable NAND strings, and to apply a first selection voltage to a first selection line in the second set of respectively selectable NAND strings. A second selection voltage is applied to the second selection line. The first redundancy level and the second redundancy level may be determined according to characteristics of the first respectively selectable set of NAND strings and the second respectively selectable set of NAND strings.
一种对包括块中的多个可分别选择的NAND串集合的三维非易失性存储器进行操作的方法的示例包括：测量通过具有共用选择线的可分别选择的NAND串集合的电流；将所述电流与预定标准进行比较；如果所述电流不满足所述预定标准，则计算一个或多个位线电压偏移；以及随后，在向其他可分别选择的NAND串集合施加的其他位线电压保持未被调整的同时，对向连接至所述可分别选择的NAND串集合的位线施加的位线电压进行调整。An example of a method of operating a three-dimensional nonvolatile memory including a plurality of individually selectable sets of NAND strings in a block includes: measuring current through the individually selectable sets of NAND strings having a common select line; comparing said current with predetermined criteria; if said current does not meet said predetermined criteria, calculating one or more bit line voltage offsets; While remaining unadjusted, the bit line voltages applied to the bit lines connected to the respectively selectable sets of NAND strings are adjusted.
可以记录所述可分别选择的NAND串集合的所述一个或多个位线电压偏移。所述一个或多个位线电压偏移可以记录在包含具有不满足所述预定标准的测量电流的每个可分别选择的NAND串集合的计算位线电压偏移的表中。可以将增强型冗余方案应用于在不满足所述预定标准的串集合中存储的数据，所述增强型冗余方案提供比应用于在满足所述预定标准的串集合中所存储的数据的通常冗余方案更高程度的纠错能力。可以读出可分别选择的NAND串集合中的选择线的选择栅极阈值电压；可以将所述选择栅极阈值电压与最小阈值电压进行比较；可以计算具有比所述最小阈值电压更小的选择线阈值电压的可分别选择的NAND串集合的选择线电压偏移；并且可以将所述选择线电压偏移应用于随后在访问所述可分别选择的NAND串集合时向所述选择线施加的选择线电压。The one or more bit line voltage offsets for the respectively selectable sets of NAND strings may be recorded. The one or more bit line voltage offsets may be recorded in a table containing calculated bit line voltage offsets for each respectively selectable set of NAND strings having measured currents that do not meet the predetermined criteria. An enhanced redundancy scheme may be applied to data stored in sets of strings that do not meet said predetermined criteria, said enhanced redundancy scheme providing greater Usually redundancy schemes have a higher degree of error correction capability. Select gate threshold voltages of select lines in individually selectable sets of NAND strings can be read; said select gate threshold voltages can be compared to a minimum threshold voltage; select gate voltages with less than said minimum threshold voltage can be calculated; a select line voltage offset for an individually selectable set of NAND strings of line threshold voltages; and the select line voltage offset may be applied to the select line subsequently applied when accessing the individually selectable set of NAND strings Select line voltage.
可以记录所述可分别选择的NAND串集合的所述选择线电压偏移，并且可以记录其他可分别选择的NAND串集合的附加选择线电压偏移。待存储在所述可分别选择的NAND串集合中的数据可以使用增强型编码方案来加以编码。The select line voltage offset may be recorded for the individually selectable set of NAND strings, and additional select line voltage offsets may be recorded for other individually selectable sets of NAND strings. Data to be stored in the respectively selectable sets of NAND strings may be encoded using an enhanced encoding scheme.
各种方面、优点、特征和实施例包括在其示例性示例的以下描述中，所述描述应当结合附图进行。Various aspects, advantages, features and embodiments are included in the following description of illustrative examples thereof, which description should be taken in conjunction with the accompanying drawings.
附图说明Description of drawings
图1示意性地展示了存储器系统的主要硬件部件。Figure 1 schematically shows the main hardware components of the memory system.
图2示意性地展示了非易失性存储器单元。Figure 2 schematically illustrates a non-volatile memory cell.
图3展示了浮栅可以存储的四种不同电荷Q1至Q4的源极-漏极电流ID与控制栅极电压VCG之间的关系。FIG. 3 shows the relationship between the source-drain current ID of four different charges Q1 toQ4 that can be stored in the floating gate and the control gate voltage VCG .
图4A示意性地展示了组织成NAND串的存储器单元串。Figure 4A schematically illustrates a string of memory cells organized into a NAND string.
图4B展示了存储器单元的NAND阵列210的示例，所述NAND阵列由NAND串50(如图4A中所示出的NAND串)构成。Figure 4B shows an example of a NAND array 210 of memory cells comprised of NAND strings 50 such as the one shown in Figure 4A.
图5展示了以NAND构型来组织的被并行读出或编程的存储器单元页。Figure 5 shows a page of memory cells being read or programmed in parallel organized in a NAND configuration.
图6A至图6C展示了对存储器单元群进行编程的示例。6A-6C illustrate an example of programming a population of memory cells.
图7示出了3D NAND串的物理结构的示例。Figure 7 shows an example of the physical structure of a 3D NAND string.
图8示出了U形3D NAND串的物理结构的示例。FIG. 8 shows an example of the physical structure of a U-shaped 3D NAND string.
图9在y-z平面中示出了具有U形NAND串的3D NAND存储器阵列的横截面的示例。Figure 9 shows an example of a cross-section of a 3D NAND memory array with U-shaped NAND strings in the y-z plane.
图10A至图10C展示了具有块中的多个可分别选择的串集合的3-D NAND存储器的示例。10A-10C illustrate an example of a 3-D NAND memory with multiple individually selectable string sets in a block.
图11A和图11B展示了垂直NAND串。Figures 11A and 11B illustrate vertical NAND strings.
图12展示了垂直NAND串与共用源极的连接。Figure 12 shows the connection of the vertical NAND strings to the common source.
图13示出了具有四个可分别选择的NAND串集合的块的示例。Figure 13 shows an example of a block with four individually selectable sets of NAND strings.
图14A和图14B示出了电流测量电路的示例。14A and 14B show examples of current measurement circuits.
图15示出了用于检查和维护可分别选择的NAND串集合的方案的示例。Figure 15 shows an example of a scheme for checking and maintaining a set of individually selectable NAND strings.
图16展示了存储器系统的示例。Figure 16 shows an example of a memory system.
图17示出了NAND闪存块中的可分别选择的串的示例。FIG. 17 shows an example of individually selectable strings in a NAND flash memory block.
图18示意性地展示了三维存储器阵列的示例。Figure 18 schematically illustrates an example of a three-dimensional memory array.
图19示出了三维存储器结构的示例。Fig. 19 shows an example of a three-dimensional memory structure.
图20示出了电阻式存储器元件的示例。FIG. 20 shows an example of a resistive memory element.
图21A和图21B示出了具有电阻式元件的三维存储器的细节。21A and 21B show details of a three-dimensional memory with resistive elements.
图22A和图22B展示了交叉点存储器阵列的示例。22A and 22B illustrate examples of cross-point memory arrays.
图23展示了对存储器系统进行操作的方法。Figure 23 illustrates a method of operating a memory system.
具体实施方式Detailed ways
存储器系统memory system
半导体存储器设备包括易失性存储器设备(比如，动态随机存取存储器(“DRAM”)或静态随机存取存储器(“SRAM”))、非易失性存储器设备(比如，电阻式随机存取存储器(“ReRAM”)、电可擦除可编程只读存储器(“EEPROM”)、闪存(其还可以被考虑为EEPROM的子集)、铁电随机存取存储器(“FRAM”)和磁阻式随机存取存储器(“MRAM”))以及能够存储信息的其他半导体元件。每种类型的存储器设备可以具有不同构型。例如，闪存设备可以以NAND或NOR构型来进行配置。Semiconductor memory devices include volatile memory devices such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”), nonvolatile memory devices such as resistive random access memory ("ReRAM"), Electrically Erasable Programmable Read-Only Memory ("EEPROM"), Flash (which can also be considered a subset of EEPROM), Ferroelectric Random Access Memory ("FRAM"), and magnetoresistive Random Access Memory ("MRAM")) and other semiconductor components capable of storing information. Each type of memory device can have a different configuration. For example, flash memory devices may be configured in NAND or NOR configurations.
存储器设备可由无源和/或有源元件以任何组合来形成。通过非限制性示例的方式，无源半导体存储器元件包括ReRAM设备元件，在一些实施例中，所述元件包括如反熔丝相变材料等电阻率切换存储元件以及(可选地)如二极管等操控元件。进一步通过非限制性示例的方式，有源半导体存储器元件包括EEPROM和闪存设备元件，在一些实施例中，所述元件包括如浮栅、导电纳米颗粒或电荷存储介电材料等包含了电荷存储区域的元件。A memory device may be formed from any combination of passive and/or active elements. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements which, in some embodiments, include resistivity switching memory elements such as antifuse phase change materials and (optionally) diodes, etc. Control elements. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements which, in some embodiments, include charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials. components.
多个存储器元件可以被配置成使得它们串联连接或使得每个元件是可单独访问的。通过非限制性示例的方式，采用NAND构型(NAND存储器)的闪存设备通常包含串联连接的存储器元件。NAND存储器阵列可以被配置成使得阵列包括多个存储器串，其中，串包括共享单条位线并作为整体而被访问的多个存储器元件。可替代地，存储器元件可以被配置成使得每个元件都是可单独访问的(例如，NOR存储器阵列)。NAND和NOR存储器构型是示例性的，并且存储器元件可以以其他方式配置。Multiple memory elements may be configured such that they are connected in series or such that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array can be configured such that the array includes a plurality of memory strings, where a string includes a plurality of memory elements that share a single bit line and are accessed as a whole. Alternatively, the memory elements may be configured such that each element is individually accessible (eg, a NOR memory array). NAND and NOR memory configurations are exemplary, and memory elements may be configured in other ways.
位于衬底内和/或上方的半导体存储器元件可以被安排在两个或三个维度中(比如，二维存储器结构或三维存储器结构)。Semiconductor memory elements located in and/or over a substrate may be arranged in two or three dimensions (eg, a two-dimensional memory structure or a three-dimensional memory structure).
在二维存储器结构中，半导体存储器元件被安排在单个平面或单个存储器设备级中。通常，在二维存储器结构中，存储器元件被安排在基本上平行于支撑存储器元件的衬底的主要表面而延伸的平面中(例如，在x-z方向平面中)。衬底可以是在其上方或在其中形成存储器元件层的晶片，或者其可以是在形成存储器元件之后附接至其上的载体衬底。作为非限制性示例，衬底可以包括如硅等半导体。In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or level of a single memory device. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane extending substantially parallel to a major surface of a substrate supporting the memory elements (eg, in an x-z direction plane). The substrate may be a wafer over or in which the memory element layer is formed, or it may be a carrier substrate attached to it after the memory elements are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.
可以在单个存储器设备级中将存储器元件安排成有序阵列，如在多个行和/或列中。然而，可以采用非规则或非正交构型来排列存储器元件。存储器元件中的每个存储器元件可以具有两个或更多个电极或接触线，比如，位线和字线。Memory elements may be arranged in an ordered array, such as in rows and/or columns, within a single memory device level. However, the memory elements may be arranged in a non-regular or non-orthogonal configuration. Each of the memory elements may have two or more electrodes or contact lines, such as bit lines and word lines.
三维存储器阵列被安排成使得存储器元件占据多个平面或多个存储器设备级，由此在三个维度(即，在x方向、y方向和z方向上，其中，y方向基本上垂直于并且x和z方向基本上平行于衬底的主表面)中形成结构。A three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple levels of memory devices such that in three dimensions (i.e., in the x-direction, y-direction, and z-direction, where the y-direction is substantially perpendicular to and the x-direction and the z direction are substantially parallel to the main surface of the substrate) to form the structure.
作为非限制性示例，三维存储器结构可以被垂直地安排为多个二维存储器设备级的堆叠。作为另一个非限制性示例，三维存储器阵列可以被安排为多个垂直列(例如，基本上垂直于衬底的主表面而延伸的列，即，在y方向上)，每个列具有每个列中的多个存储器元件。可以采用二维构型(例如，在x-z平面中)来安排所述列，从而导致存储器元件的三维安排，元件位于多个垂直堆叠的存储器平面上。存储器元件在三个维度中的其他构型也可以构成三维存储器阵列。As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged in a plurality of vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), each column having each multiple memory elements in a column. The columns can be arranged in a two-dimensional configuration (eg, in the x-z plane), resulting in a three-dimensional arrangement of memory elements, with elements located on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also make up a three-dimensional memory array.
通过非限制性示例的方式，在三维NAND存储器阵列中，存储器元件可以耦合在一起以便在单个水平(例如，x-z)存储器设备级内形成NAND串。可替代地，存储器元件可以耦合在一起以便形成横跨多个水平存储器设备级的垂直NAND串。可以设想其他三维构型，其中，一些NAND串包含单个存储器级中的存储器元件，而其他串包含跨越多个存储器级的存储器元件。还可以采用NOR构型和ReRAM构型来设计三维存储器阵列。By way of non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (eg, x-z) memory device level. Alternatively, memory elements may be coupled together to form a vertical NAND string spanning multiple horizontal memory device levels. Other three-dimensional configurations are envisioned where some NAND strings contain memory elements in a single memory level, while other strings contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed using NOR configurations and ReRAM configurations.
通常，在单片式三维存储器阵列中，在单个衬底上方形成一个或多个存储器设备级。可选地，单片式三维存储器阵列还可以具有至少部分地处于单个衬底内的一个或多个存储器层。作为非限制性示例，衬底可以包括如硅等半导体。在单片式三维阵列中，构成阵列的每个存储器设备级的层通常在阵列的基础存储器设备级的层上形成。然而，单片式三维存储器阵列的相邻存储器设备级的层可以被共享或在存储器设备级之间具有中间层。Typically, in a monolithic three-dimensional memory array, one or more levels of memory devices are formed over a single substrate. Optionally, a monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers of each memory device level that make up the array are typically formed on the layers of the array's base memory device level. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or have intermediate layers between memory device levels.
然后，再次，二维阵列可以被分别形成并且然后封装在一起以便形成具有多个存储器层的非单片式存储器设备。例如，非单片式堆叠存储器可以通过在单独衬底上形成存储器级然后将存储器级堆叠在彼此顶上来构造。可以减薄衬底或者可以在堆叠之前将其从存储器设备级中移除，但是因为存储器设备级最初地在单独衬底上方形成，所以所产生的存储器阵列不是单片式三维存储器阵列。此外，多个二维存储器阵列或三维存储器阵列(单片式或非单片式)可以在单独芯片上形成然后封装在一起以便形成堆叠芯片存储器设备。Then, again, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, non-monolithically stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate can be thinned or removed from the memory device levels prior to stacking, but because the memory device levels are initially formed over separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. In addition, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.
对存储器元件的操作以及与存储器元件的通信通常需要相关联电路系统。作为非限制性示例，存储器设备可以具有用于控制和驱动存储器元件完成如编程和读取等功能的电路系统。此相关联电路系统可以处于与存储器元件相同的衬底上和/或处于单独衬底上。例如，用于存储器读-写操作的控制器可以位于单独控制器芯片上和/或位于与存储器元件相同的衬底上。Operating on and communicating with memory elements typically requires associated circuitry. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory elements to perform functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, the controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.
在其他实施例中，可以使用除了此处所描述的二维和三维示例性结构以外的存储器类型。In other embodiments, memory types other than the two-dimensional and three-dimensional exemplary structures described herein may be used.
图1示意性地展示了适合于实施此处所描述的技术中的一些技术的存储器系统的主要硬件部件。存储器系统90通常通过主机接口与主机80一起操作。存储器系统可以采用如存储器卡等可移除存储器的形式或者可以采用嵌入式存储器系统的形式。存储器系统90包括存储器102，所述存储器的操作由控制器100控制。存储器102包括分布在一个或多个集成电路芯片上的一个或多个非易失性存储器单元阵列。控制器100可以包括接口电路110、处理器120、ROM(只读存储器)122、RAM(随机存取存储器)130、可编程非易失性存储器124以及附加部件。控制器通常被形成为ASIC(专用集成电路)，并且包括在这种ASIC中的部件通常取决于特定应用。在各种不同环境中，存储器系统可以与各种主机一起使用。例如，主机可以是移动设备，比如，蜂窝电话、膝上型计算机、音乐播放器(例如，MP3播放器)、全球定位系统(GPS)设备、平板计算机等。这种存储器系统可以是在长时段内不活跃且没有电力的，在所述长时段期间，它们可能经受包括高温、振动、电磁场等各种状况。可以为了宽范围环境条件(例如，宽温度范围)下的低功耗、高数据保留以及可靠性而选择这种主机的存储器系统(无论是可移除的还是嵌入式的)。其他主机可以是固定的。例如，用于互联网应用的服务器可以使用非易失性存储器系统来存储通过互联网发送和接收的数据。这种系统可以在延长的时段(例如，一年或更多)内保持上电而不中断，并且可以贯穿这些时段被频繁地访问。单独块可以被频繁写入和擦除，从而使得耐久性可能是主要关注问题。Figure 1 schematically illustrates the major hardware components of a memory system suitable for implementing some of the techniques described herein. Memory system 90 typically operates with host 80 through a host interface. The memory system may take the form of removable memory such as a memory card or may take the form of an embedded memory system. The memory system 90 includes a memory 102 whose operation is controlled by a controller 100 . Memory 102 includes one or more arrays of non-volatile memory cells distributed over one or more integrated circuit chips. The controller 100 may include an interface circuit 110, a processor 120, a ROM (Read Only Memory) 122, a RAM (Random Access Memory) 130, a programmable non-volatile memory 124, and additional components. Controllers are usually formed as ASICs (Application Specific Integrated Circuits), and the components included in such ASICs usually depend on the particular application. A memory system can be used with a variety of hosts in a variety of different environments. For example, a host may be a mobile device such as a cellular phone, laptop computer, music player (eg, MP3 player), Global Positioning System (GPS) device, tablet computer, or the like. Such memory systems may be inactive and without power for long periods of time during which they may be subjected to various conditions including high temperatures, vibrations, electromagnetic fields, and the like. Such host memory systems (whether removable or embedded) can be selected for low power consumption, high data retention, and reliability over a wide range of environmental conditions (eg, wide temperature range). Other hosts can be fixed. For example, a server for Internet applications may use a non-volatile memory system to store data sent and received over the Internet. Such a system can remain powered on without interruption for extended periods of time (eg, a year or more), and can be frequently accessed throughout these periods. Individual blocks may be written and erased frequently so that endurance may be a major concern.
物理存储器结构physical memory structure
图2示意性地展示了非易失性存储器单元。存储单元10可以由具有电荷存储单元20的场效应晶体管实施，比如，浮栅或电荷俘获(介电)层。存储器单元10还包括源极14、漏极16和控制栅极30。Figure 2 schematically illustrates a non-volatile memory cell. The memory cell 10 may be implemented by a field effect transistor with a charge storage cell 20, such as a floating gate or a charge trapping (dielectric) layer. Memory cell 10 also includes source 14 , drain 16 and control gate 30 .
在实践中，通常通过在向控制栅极施加参考电压时读出单元的源极电极与漏极电极之间的传导电流来读取单元的存储器状态。因此，对单元的浮栅上的每个给定电荷，可以检测关于固定参考控制栅极电压的相应传导电流。类似地，可编程到浮栅上的电荷的范围限定相应阈值电压窗口或相应传导电流窗口。In practice, the memory state of a cell is typically read by sensing the conduction current between the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the cell's floating gate, a corresponding conduction current with respect to a fixed reference control gate voltage can be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.
可替代地，代替在划分的电流窗口当中检测传导电流，有可能在控制栅极处设置测试中的给定存储器状态的阈值电压，并且在传导电流低于或高于阈值电流(单元读取参考电流)时进行检测。在一种实施方式中，通过检查传导电流释放通过位线的电容的速率来完成对相对于阈值电流的传导电流的检测。Alternatively, instead of detecting the conduction current among divided current windows, it is possible to set the threshold voltage at the control gate for a given memory state under test, and to set the threshold voltage when the conduction current is below or above the threshold current (cell read reference current) is detected. In one embodiment, detecting the conduction current relative to the threshold current is accomplished by examining the rate at which the conduction current discharges the capacitance through the bit line.
图3展示了浮栅可以在任何时候选择性地存储的四种不同电荷Q1至Q4的源极-漏极电流ID与控制栅极电压VCG之间的关系。对于固定漏极电压偏置，四条实线ID对VCG曲线表示可以编程到存储器单元的浮栅上的七种可能电荷水平中分别对应于四种可能存储器状态的四种可能电荷水平。作为示例，单元群的阈值电压窗口的范围可以为从0.5V到3.5V。可以通过以各自0.5V的间隔将阈值窗口划分成区域来界定七种可能的编程存储器状态“0”、“1”、“2”、“3”、“4”、“5”、“6”以及擦除状态(未示出)。例如，如果使用如所示出的2μA的参考电流I参考，则使用Q1来编程的单元可以被视为处于存储器状态“1”，因为其曲线与I参考相交于由VCG＝0.5V和1.0V界定的阈值窗口区域中。类似地，Q4处于存储器状态“5”。FIG. 3 shows the relationship between the source-drain current ID andthe control gate voltage V CGof four different charges Q1 to Q4 that the floating gate can selectively store at any time. For a fixed drain voltage bias, the four solidID vs.VCG curves represent four possible charge levels that can be programmed onto the floating gate of a memory cell, corresponding to the four possible memory states, respectively. As an example, the threshold voltage window of a cell population may range from 0.5V to 3.5V. Seven possible programmed memory states "0", "1", "2", "3", "4", "5", "6" can be defined by dividing the threshold window into regions at intervals of 0.5V each and erase status (not shown). For example, if a reference current Iref of 2 μAis used as shown, a cell programmed using Q1 can be considered to be in the memory state "1" because its curveintersects Iref at points defined by VCG = 0.5V and 1.0V within the defined threshold window region. Similarly, Q4 is in memory state "5".
如从以上描述中可看出的，使存储器单元存储的状态越多，其阈值电压窗口被划分得越精细。例如，存储器设备可以具有存储器单元，所述存储器单元具有范围为从-1.5V到5V的阈值电压窗口。这提供了6.5V的最大宽度。如果存储器单元用于存储16种状态，则每种状态在阈值窗口中可以占据从200mV到300mV。这将需要编程和读取操作的更高精度，以便能够达到所需要的分辨率。As can be seen from the above description, the more states a memory cell is made to store, the finer its threshold voltage window is divided. For example, a memory device may have memory cells with a threshold voltage window ranging from -1.5V to 5V. This provides a maximum width of 6.5V. If a memory cell is used to store 16 states, each state may occupy from 200mV to 300mV in the threshold window. This will require higher precision in programming and reading operations in order to be able to achieve the required resolution.
NAND结构NAND structure
图4A示意性地展示了组织成NAND串的存储器单元串。NAND串50包括通过其源极和漏极菊链的存储器晶体管M1、M2、...、Mn(例如，n＝4、8、16或更高)系列。选择晶体管S1、S2对控制存储器晶体管链的分别经由NAND串的源极端子54和漏极端子56连接至外界。在存储器阵列中，当源极选择晶体管S1接通时，源极端子耦合至源极线(见图4B)。类似地，当漏极选择晶体管S2接通时，NAND串的漏极端子耦合至存储器阵列的位线。链中的每个存储器晶体管10充当存储器单元。其具有用于存储给定量的电荷的电荷存储元件20以便表示预期存储器状态。每个存储器晶体管的控制栅极30允许对读取和写入操作进行控制。如在图4B中将看到的，NAND串行的相应存储器晶体管的控制栅极30全部连接至同一字线。类似地，选择晶体管S1、S2中的每个选择晶体管的控制栅极32提供对分别经由其源极端子54和漏极端子56对NAND串的访问的控制。同样地，NAND串行的相应选择晶体管的控制栅极32全部连接至同一选择线。Figure 4A schematically illustrates a string of memory cells organized into a NAND string. NAND string 50 includes a series of memory transistors M1, M2, . . . , Mn (eg, n=4, 8, 16 or higher) daisy-chained through their sources and drains. The pair of selection transistors S1 , S2 controlling the chain of memory transistors are connected to the outside world via source terminal 54 and drain terminal 56 of the NAND string, respectively. In a memory array, when source select transistor S1 is turned on, the source terminal is coupled to the source line (see FIG. 4B ). Similarly, when drain select transistor S2 is on, the drain terminal of the NAND string is coupled to the bit line of the memory array. Each memory transistor 10 in the chain acts as a memory cell. It has a charge storage element 20 for storing a given amount of charge in order to represent the desired memory state. A control gate 30 of each memory transistor allows control of read and write operations. As will be seen in Figure 4B, the control gates 30 of the respective memory transistors of the NAND string are all connected to the same word line. Similarly, the control gate 32 of each of the select transistors Sl, S2 provides control of access to the NAND string via its source terminal 54 and drain terminal 56, respectively. Likewise, the control gates 32 of the respective select transistors of the NAND string are all connected to the same select line.
当在编程期间读取或验证NAND串内的寻址存储器晶体管10时，其控制栅极30被供应有适当的电压。同时，NAND串50中的非寻址存储器晶体管的剩余部分通过在其控制栅极上应用足够的电压而被完全接通。以此方式，有效地创建从单独存储器晶体管的源极到NAND串的源极端子54的导电路径，并且对单独存储器晶体管的漏极到单元的漏极端子56同样如此。When an addressed memory transistor 10 within a NAND string is read or verified during programming, its control gate 30 is supplied with the appropriate voltage. At the same time, the remainder of the non-addressed memory transistors in NAND string 50 are fully turned on by applying sufficient voltage on their control gates. In this way, a conductive path is effectively created from the source of the individual memory transistor to the source terminal 54 of the NAND string, and likewise for the drain of the individual memory transistor to the drain terminal 56 of the cell.
图4B展示了存储器单元的NAND阵列210的示例，所述NAND阵列由NAND串50(如图4A中所示出的NAND串)构成。沿着每个NAND串列，位线(比如，位线36)耦合至每个NAND串的漏极端子56。沿着个NAND串排，源极线(比如，源极线34)耦合至每个NAND串的源极端子54。而且，沿着NAND串排中的存储器单元行的控制栅极连接至字线(比如，字线42)。沿着NAND串排中的选择晶体管行的控制栅极连接至选择线(比如，选择线44)。NAND串排中的整个存储器单元行可以通过所述NAND串排的字线和选择线上的适当电压而被寻址。Figure 4B shows an example of a NAND array 210 of memory cells comprised of NAND strings 50 such as the one shown in Figure 4A. Along each NAND string, a bit line, such as bit line 36, is coupled to the drain terminal 56 of each NAND string. Along the NAND strings, a source line (eg, source line 34 ) is coupled to source terminal 54 of each NAND string. Also, the control gates along the row of memory cells in the NAND string are connected to a word line (eg, word line 42). The control gates along the row of select transistors in the NAND string are connected to a select line (eg, select line 44). An entire row of memory cells in a NAND string can be addressed by appropriate voltages on the word and select lines of the NAND string.
图5展示了以NAND构型来组织的被并行读出或编程的存储器单元页。图5本质上示出了图4B的存储器阵列210中的NAND串50排，其中，像图4A中那样明确地示出了每个NAND串的细节。物理页(比如，页60)是能够并行读出或编程的存储器单元组。这通过读出放大器212的相应页完成。将读出结果锁存在相应锁存器组214中。每个读出放大器可以经由位线耦合至NAND串。页由页的单元的共用连接至字线42的控制栅极使能，并且每个单元可由读出放大器访问，所述读出放大器可经由位线36访问。作为示例，当分别读出或编程单元60的页时，分别将读出电压或编程电压连同位线上的适当电压一起施加到共用字线WL3上。Figure 5 shows a page of memory cells being read or programmed in parallel organized in a NAND configuration. Figure 5 essentially shows the rows of NAND strings 50 in the memory array 210 of Figure 4B, with details of each NAND string being explicitly shown as in Figure 4A. A physical page (eg, page 60) is a group of memory cells that can be read or programmed in parallel. This is done through the corresponding pages of sense amplifiers 212 . The read results are latched in the corresponding set of latches 214 . Each sense amplifier can be coupled to a NAND string via a bit line. A page is enabled by a control gate common to the cells of the page connected to word line 42 , and each cell is accessible by a sense amplifier, which is accessible via bit line 36 . As an example, when reading or programming a page of cells 60, respectively, a read or program voltage is applied to common word line WL3 along with an appropriate voltage on the bit line, respectively.
存储器的物理组织physical organization of memory
闪存与其他类型的存储器之间的一个差别是闪存单元通常从擦除状态编程。也就是说，通常排空浮栅的电荷。然后编程将期望量的电荷添加回至浮栅中。闪存通常支持从浮栅中移除电荷的一部分以便从更多编程状态到更少编程状态。这意味着更新的数据无法覆写现有数据，并且相反写入到之前的未写入位置。One difference between flash memory and other types of memory is that flash memory cells are usually programmed from an erased state. That is, the charge of the floating gate is usually drained. Programming then adds the desired amount of charge back into the floating gate. Flash memory typically supports removing a portion of the charge from the floating gate in order to go from a more programmed state to a less programmed state. This means that newer data cannot overwrite existing data and is instead written to previously unwritten locations.
此外，擦除用于将所有电荷从浮栅中排空，并且通常花费相当多的时间。由于这个原因，逐单元或者甚至逐页地擦除将是繁琐且非常慢的。在实践中，存储器单元阵列被分成大量存储器单元块。如对于闪速EEPROM系统普通的，块是擦除单位。也就是说，每个块包含同时被擦除的最小数量的存储器单元。尽管在待擦除块中并行地聚合大量单元将提高擦除性能，但是大尺寸块还需要处理大量更新和过时数据。Also, erasing is used to drain all charge from the floating gate and usually takes quite a bit of time. For this reason, erasing cell by cell or even page by page would be tedious and very slow. In practice, an array of memory cells is divided into a large number of blocks of memory cells. As is common for flash EEPROM systems, a block is the unit of erase. That is, each block contains the minimum number of memory cells that are simultaneously erased. Although aggregating a large number of cells in parallel in a block to be erased will improve erase performance, large-sized blocks also require processing a large number of updates and obsolete data.
每个块通常被划分成许多物理页。逻辑页是包含等于物理页中的单元数量的许多位的编程或读取的单位。在每单元存储一个位的存储器中(单级单元，或“SLC”存储器)，一个物理页存储一个逻辑页的数据。在每单元存储两个位的存储器中，物理页存储两个逻辑页。存储在物理页中的逻辑页的数量因此反映每单元存储的位的数量。术语多级单元(或“MLC”)通常用于指每单元存储多于一个位的存储器，包括每单元存储三个位(TLC)、每单元存储四个位、或每单元存储更多位的存储器。在一个实施例中，单独的页可以被划分成多个段，并且每个段可以包含作为基本编程操作一次写入的最小数量的单元。一个或多个逻辑页的数据通常存储在一个存储器单元行中。页可以存储一个或多个扇区。扇区包括用户数据和开销数据。Each block is usually divided into many physical pages. A logical page is a unit of programming or reading that contains a number of bits equal to the number of cells in a physical page. In a memory that stores one bit per cell (single-level cell, or "SLC" memory), one physical page stores one logical page of data. In a memory that stores two bits per cell, a physical page stores two logical pages. The number of logical pages stored in a physical page thus reflects the number of bits stored per cell. The term multi-level cell (or "MLC") is often used to refer to memories that store more than one bit per cell, including three bits per cell (TLC), four bits per cell, or more memory. In one embodiment, individual pages may be divided into segments, and each segment may contain the minimum number of cells written at one time as a basic programming operation. Data for one or more logical pages is typically stored in one row of memory cells. A page can store one or more sectors. A sector includes user data and overhead data.
MLC编程MLC programming
图6A至图6C展示了对4状态存储器单元群进行编程的示例。图6A展示了可编程到分别表示存储器状态“E”、“A”、“B”和“C”的阈值电压的四种不同分布中的存储器单元群。图6B展示了擦除存储器的“擦除”阈值电压的初始分布。图6C展示了在存储器单元中的许多存储器单元已经被编程之后的存储器的示例。实质上，单元最初具有“擦除”阈值电压，并且编程将其移动到更高值进入由验证水平vV1、vV2和vV3界定的三个区域中的一个区域中。以此方式，每个存储器单元可以被编程到三种编程状态“A”、“B”和“C”之一或者在“擦除”状态下保持未编程。随着存储器得到更多编程，如图6B中所示出的“擦除”状态的初始分布将变得更窄，并且擦除状态由“0”状态表示。6A-6C illustrate an example of programming a population of 4-state memory cells. Figure 6A shows populations of memory cells programmable into four different distributions of threshold voltages representing memory states "E", "A", "B" and "C", respectively. Figure 6B shows the initial distribution of "erased" threshold voltages for an erased memory. Figure 6C shows an example of the memory after many of the memory cells have been programmed. Essentially, the cell initially has an "erase" threshold voltage, and programming moves it to a higher value into one of the three regions bounded by verify levels vV1 , vV2 and vV3 . In this way, each memory cell can be programmed to one of three programmed states "A", "B" and "C" or remain unprogrammed in the "erased" state. As the memory gets more programmed, the initial distribution of "erased" states as shown in Figure 6B will become narrower, and the erased states will be represented by the "0" state.
具有低位和高位的2位代码可以用于表示四种存储器状态中的每种存储器状态。例如，“E”、“A”、“B”和“C”状态分别由“11”、“01”、“00”和“10”表示。可以通过在“完整序列”模式下进行读出来从存储器中读取2位数据，在所述模式下，通过分别相对于三个子通带中的读取界定阈值rV1、rV2和rV3进行读出来一起读出这两个位。A 2-bit code with low and high bits can be used to represent each of the four memory states. For example, states "E", "A", "B" and "C" are represented by "11", "01", "00" and "10", respectively. 2-bit data can be read from memory by reading in "full sequence" mode by defining thresholds rV1 , rV2 and rV3 with respect to read in the three sub-passbands, respectively. Read out to read out the two bits together.
3D NAND结构3D NAND structure
常规二维(2D)NAND阵列的替代性安排是三维(3D)阵列。相比于2D NAND阵列(其沿着半导体晶片的平面表面形成)，3D阵列从晶片表面向上延伸并且通常包括向上延伸的存储器单元堆或列。各种3D安排是可能的。在一种安排中，与晶片表面处的一端(例如，源极)以及顶部的另一端(例如，漏极)垂直地形成NAND串。在另一种安排中，以U形形状来形成NAND串，从而使得可以在顶部访问NAND串的两端，从而促进这种串之间的连接。An alternative arrangement to conventional two-dimensional (2D) NAND arrays is a three-dimensional (3D) array. In contrast to 2D NAND arrays (which are formed along the planar surface of a semiconductor wafer), 3D arrays extend upward from the wafer surface and typically include upwardly extending stacks or columns of memory cells. Various 3D arrangements are possible. In one arrangement, NAND strings are formed perpendicularly with one end at the wafer surface (eg, source) and the other end at the top (eg, drain). In another arrangement, the NAND strings are formed in a U-shape so that both ends of the NAND strings are accessible at the top, facilitating connections between such strings.
图7示出了在垂直于衬底的x-y平面的垂直方向上延伸(即，在z方向上延伸)的NAND串701的第一示例。在垂直位线(局部位线)703穿过字线(例如，WL0、WL1等)的地方形成存储器单元。局部位线与字线之间的电荷俘获层存储电荷，所述电荷影响由耦合至其所包围的垂直位线(沟道)的字线(栅极)形成的晶体管的阈值电压。可以通过形成字线堆叠并且然后蚀刻出要在其处形成存储器单元的存储器孔来形成这种存储器单元。然后，将存储器孔衬以电荷俘获层并填充以适当的局部位线/沟道材料(填充以适当的介电层以便进行隔离)。Figure 7 shows a first example of a NAND string 701 extending in a vertical direction perpendicular to the x-y plane of the substrate, ie extending in the z-direction. Memory cells are formed where vertical bit lines (local bit lines) 703 cross word lines (eg, WL0, WL1, etc.). The charge-trapping layer between the local bitline and wordline stores charges that affect the threshold voltage of the transistor formed by the wordline (gate) coupled to the vertical bitline (channel) it surrounds. Such memory cells may be formed by forming a word line stack and then etching a memory hole where the memory cell is to be formed. The memory hole is then lined with a charge trapping layer and filled with a suitable local bitline/channel material (filled with a suitable dielectric layer for isolation).
与平面NAND串一样，选择栅极705、707被定位在串的任一端处以便允许NAND串选择性地连接至外部元件709、711或与其隔离。这种外部元件通常为导线(比如，为大量NAND串服务的共用源极线)。可以以与平面NAND串类似的方式来操作垂直NAND串并且单级单元(SLC)或多级单元(MLC)两者都是可能的。虽然图7示出了具有串联连接的32个单元(0至31)的NAND串的示例，但是NAND串中的单元数可以是任何适当数量。为了清晰起见，未示出所有单元。将理解的是，在字线3至29(未示出)与局部垂直位线相交的地方形成附加单元。As with planar NAND strings, select gates 705, 707 are positioned at either end of the strings to allow the NAND strings to be selectively connected to or isolated from external elements 709, 711. Such external components are typically wires (eg, a common source line serving a large number of NAND strings). Vertical NAND strings can be operated in a similar manner to planar NAND strings and both single-level cells (SLC) or multi-level cells (MLC) are possible. Although FIG. 7 shows an example of a NAND string having 32 cells (0 to 31 ) connected in series, the number of cells in a NAND string may be any suitable number. For clarity, not all units are shown. It will be appreciated that additional cells are formed where word lines 3 to 29 (not shown) intersect local vertical bit lines.
图8示出了在垂直方向(z方向)上延伸的NAND串815的第二示例。在这种情况下，NAND串815形成U形形状，与位于结构顶部的外部元件(源极线“SL”和位线“BL”)连接。连接NAND串815的两个翼816A、816B的可控制栅极(背栅“BG”)处于NAND串815的底部。在字线WL0至WL63与垂直局部位线817相交的地方形成总共64个单元(尽管在其他示例中，可以提供其他数量的单元)。选择栅极SGS、SGD被定位在NAND串815的任一端处以便控制对NAND串815的连接/隔离。FIG. 8 shows a second example of NAND strings 815 extending in the vertical direction (z-direction). In this case, NAND string 815 forms a U-shape, connected to external elements (source line "SL" and bit line "BL") located on top of the structure. At the bottom of the NAND string 815 is a controllable gate (back gate “BG”) connecting the two wings 816A, 816B of the NAND string 815 . A total of 64 cells are formed where word lines WL0 through WL63 intersect vertical local bit lines 817 (although in other examples other numbers of cells may be provided). Select gates SGS, SGD are positioned at either end of the NAND string 815 to control the connection/isolation of the NAND string 815 .
垂直NAND串可以被安排成以各种方式形成3D NAND阵列。图9示出了块中的多个U形NAND串连接至位线的示例。在这种情况下，在块中存在连接至位线(“BL”)的n个可分别选择的串集合(串1至串n)。“n”的值可以是任何适当数字，例如，8、12、16、32或更多。串在取向上与其源极连接处于左方的奇数串以及其源极处于右方的偶数串交替。这种安排是合宜的但不是必要的，并且其他图案也是可能的。Vertical NAND strings can be arranged in various ways to form 3D NAND arrays. FIG. 9 shows an example where multiple U-shaped NAND strings in a block are connected to bit lines. In this case, there are n individually selectable sets of strings (String 1 to String n) connected to a bit line ("BL") in the block. The value of "n" can be any suitable number, eg, 8, 12, 16, 32 or more. Strings alternate in orientation with odd strings with their source connections to the left and even strings with their sources to the right. Such an arrangement is convenient but not necessary, and other patterns are possible.
共用源极线“SL”连接至每个NAND串的一端(与连接至位线的端相反)。可以将这视为NAND串的源极端，将位线端视为NAND串的漏极端。可以将共用源极线连接成使得块的所有源极线可由外围电路一起控制。因此，块的NAND串在一端在位线之间平行地延伸并且在另一端在共用源极线之间平行的延伸。A common source line "SL" is connected to one end of each NAND string (opposite the end connected to the bit line). Think of this as the source terminal of the NAND string and the bit line terminal as the drain terminal of the NAND string. A common source line can be connected such that all source lines of a block can be controlled together by peripheral circuits. Thus, the NAND strings of the block run in parallel between the bit lines at one end and between the common source lines at the other end.
图10A以沿着位线方向(沿着y方向)的横截面示出了存储器结构，其中，直线垂直NAND串从衬底中或附近的共用源极连接延伸至在存储器单元的物理级上延伸的全局位线(GBL0至GBL3)。在块中的给定物理级中的字线由导电材料片形成。存储器孔结构向下延伸穿过这些导电材料片以便形成通过垂直位线(BL0至BL3)垂直地(沿着z方向)串联连接的存储器单元从而形成垂直NAND串。在给定块内，存在连接至给定全局位线的多个NAND串(例如，GBL0与多个BL0连接)。NAND串被分组成共享共用选择线的串集合。因此，例如，可以将由源极选择线SGS0和漏极选择线SGD0选择的NAND串视为NAND串集合并且可以将其指定为串0，而可以将由源极选择线SGS1和漏极选择线SGD1选择的NAND串视为另一个NAND串集合并且可以将其指定为如所示出的串1。块可以由任何适当数量的这种可分别选择的串集合组成。将理解的是，图10A仅示出了GBL0至GBL3的部分，并且这些位线进一步在y方向上延伸并且可以与所述块中以及其他块中的附加NAND串连接。此外，附加位线与GBL0至GBL3平行地延伸(例如，在沿着x轴的不同位置处，在图10A的横截面的位置前面或后面)。Figure 10A shows the memory structure in cross-section along the bit line direction (along the y-direction), where straight vertical NAND strings extend from a common source connection in or near the substrate to the physical level of the memory cell. global bit lines (GBL0 to GBL3). The word lines in a given physical level in the block are formed from sheets of conductive material. Memory hole structures extend down through the sheets of conductive material to form memory cells connected vertically in series (along the z-direction) by vertical bit lines (BL0 to BL3) to form vertical NAND strings. Within a given block, there are multiple NAND strings connected to a given global bit line (eg, GBL0 is connected to multiple BL0s). NAND strings are grouped into sets of strings that share a common select line. Thus, for example, the NAND string selected by source select line SGS0 and drain select line SGD0 can be considered a set of NAND strings and can be designated as string 0, while the NAND string selected by source select line SGS1 and drain select line SGD1 can be considered as a set of NAND strings and can be designated as string 0. The NAND string of is considered another set of NAND strings and can be designated as string 1 as shown. A block may consist of any suitable number of such individually selectable sets of strings. It will be appreciated that Figure 10A shows only part of GBL0 to GBL3, and that these bit lines extend further in the y-direction and can be connected with additional NAND strings in that block as well as in other blocks. Furthermore, additional bit lines run parallel to GBL0-GBL3 (eg, at different positions along the x-axis, before or after the position of the cross-section of FIG. 10A ).
图10B示意性地展示了图10A的可分别选择的NAND串集合。可以看到，全局位线(GBL0至GBL3)中的每条全局位线连接至所示出的块的部分中的多个可分别选择的NAND串集合(例如，GBL0连接至串0的垂直位线BL0并且还连接至串1的垂直位线BL0)。在一些情况下，块的所有串的字线电连接，例如，串0中的WL0可以连接至串1、串2等的WL0。可以将这种字线形成为延伸穿过块的所有串集合的连续导电材料片。源极线还可以为块的所有串所共用。例如，可以对衬底的一部分进行掺杂以便形成在块下面的与在其他块下面的类似导电区域隔离的连续导电区域，从而允许进行分别偏置以便作为整体而擦除块。源极和漏极选择线并不由不同串集合共享，从而使得例如可以对SGD0和SGS0进行偏置以便选择串0，而无需以类似方式对SGD1和SGS1进行偏置。因此，可以在串1(以及其他串集合)保持与全局位线和共用源极隔离的同时单独选择串0(连接至全局位线和共用源极)。在编程和读取操作期间访问块中的存储器单元通常包括向选择线对(例如，SGS0和SGD0)施加选择电压，同时向块的所有其他选择线(例如，SGS1和SGD1)施加取消选择电压。然后，向块的字线施加适当电压，从而使得可以访问所选串集合中的特定字线(例如，向特定字线施加读取电压，同时向其他字线施加读取通过电压)。可以对整个块(块中的所有串集合)而不是对块中的特定串集合应用擦除操作。FIG. 10B schematically illustrates the individually selectable sets of NAND strings of FIG. 10A . It can be seen that each of the global bit lines (GBL0 to GBL3) is connected to a plurality of individually selectable sets of NAND strings in the portion of the block shown (e.g., GBL0 is connected to the vertical bit line of string 0). line BL0 and is also connected to the vertical bit line BL0 of string 1). In some cases, the word lines of all strings of a block are electrically connected, eg, WL0 in string 0 may be connected to WL0 in string 1, string 2, and so on. Such a word line can be formed as a continuous sheet of conductive material that extends through all sets of strings of the block. A source line can also be common to all strings of a block. For example, a portion of the substrate may be doped to form a continuous conductive region under a block isolated from similar conductive regions under other blocks, allowing individual biasing to erase the block as a whole. The source and drain select lines are not shared by different sets of strings so that, for example, SGD0 and SGS0 can be biased to select string 0 without biasing SGD1 and SGS1 in a similar manner. Thus, string 0 (connected to the global bit line and common source) can be individually selected while string 1 (and other sets of strings) remain isolated from the global bit line and common source. Accessing memory cells in a block during program and read operations typically involves applying a select voltage to a pair of select lines (eg, SGS0 and SGD0 ), while applying a deselect voltage to all other select lines of the block (eg, SGS1 and SGD1 ). Appropriate voltages are then applied to the word lines of the block such that specific word lines in the selected set of strings can be accessed (eg, read voltages are applied to specific word lines while read pass voltages are applied to other word lines). The erase operation can be applied to the entire block (all sets of strings in the block) rather than to a specific set of strings in the block.
图10C以沿着X-Z平面的横截面示出了图10A和图10B的可分别选择的NAND串集合(串0)。可以看到，每条全局位线(GBL0至GBLm)连接至串0中的一个垂直NAND串(垂直位线BL0至BLm)。可以通过向选择线SGD0和SGS0施加适当电压来选择串0。其他串集合在沿着Y方向的不同位置处以类似方式连接至全局位线(GBL0至GBLm)并且与在选择了串0时可以接收取消选择电压的不同选择线连接。Figure 10C shows the respectively selectable set of NAND strings (String 0) of Figures 10A and 10B in cross-section along the X-Z plane. It can be seen that each global bit line (GBLO to GBLm) is connected to one vertical NAND string in string 0 (vertical bit line BL0 to BLm). String 0 can be selected by applying appropriate voltages to select lines SGD0 and SGS0. The other sets of strings are similarly connected to global bit lines (GBLO to GBLm) at different locations along the Y direction and to different select lines that can receive deselect voltages when string 0 is selected.
坏块、坏列、坏行bad block, bad column, bad row
在存储器系统中，对坏块进行检测和标记，从而使得随后不将它们用于存储用户数据。例如，对坏块的检测和标记可以在工厂测试期间执行。坏块可以是未能满足与例如读取、写入和/或擦除相关的一组标准(例如，未能在时间限制内进行读取、写入或擦除)的、具有过高错误率或过量坏单元的和/或未能满足其他标准的块。如果特定裸片具有多于阈值数量的坏块，则可以丢弃所述裸片。在一些情况下，可以根据裸片所包含的坏块的数量来对它们进行分类。通常，因为存储器的数据存储容量通过坏块的数量减小，所以具有更少坏块的裸片是优选的。In memory systems, bad blocks are detected and marked so that they are not subsequently used to store user data. For example, detection and marking of bad blocks can be performed during factory testing. A bad block can be one that fails to meet a set of criteria related to, for example, reading, writing, and/or erasing (e.g., failing to read, write, or erase within a time limit) with an excessively high error rate or excess bad cells and/or blocks that fail to meet other criteria. If a particular die has more than a threshold number of bad blocks, that die may be discarded. In some cases, dies may be classified according to the number of bad blocks they contain. In general, a die with fewer bad blocks is preferred because the data storage capacity of the memory is reduced by the number of bad blocks.
在一些情况下，块可以具有一些不可操作部件，而其他部件保持可操作。例如，可能发现块中的一个或多个列不可操作，并且其可由备用列替代。类似地，在一些情况下，可以替代一个或多个存储器单元行。少量坏单元可以是可接受的，条件是由这种坏单元产生的错误率低得足以允许通过纠错码(ECC)或其他某种冗余形式来进行纠正。In some cases, a block may have some non-operable parts while other parts remain operable. For example, one or more columns in a block may be found to be inoperable and may be replaced by spare columns. Similarly, in some cases, one or more rows of memory cells may be replaced. A small number of bad cells may be acceptable provided that the error rate produced by such bad cells is low enough to allow correction by error correcting code (ECC) or some other form of redundancy.
在示例中，对具有多个可分别选择的串集合的被标识为“坏”块的块进行进一步测试以便判定块中是否存在可操作的串集合(例如，即使块作为整体并不满足测试标准，但是一些串集合可能满足所述标准)。虽然一些失败模式可能导致不具有可操作单元的坏块，但是其他失败模式可能影响块的特定部分并且可能留下至少一些可操作存储器单元。一些失败模式可能影响块内的单独的可分别选择的NAND串集合，而其他NAND串集合保持可操作。对被标识为“坏”块的块的测试可以标识包含可操作和不可操作部分的混合的许多块。在一些情况下，随后可以将这种部分坏块用于存储数据，由此增大存储器的容量。在一些情况下，可以对块的未能满足测试标准的部分进行重新配置，从而使得它们满足测试标准。例如，存储器的在使用默认操作参数时未能通过测试的一部分可以在使用一些经修改的操作参数时通过。In an example, a block identified as a "bad" block with multiple separately selectable string sets is further tested to determine whether there is an operational string set in the block (e.g., even if the block as a whole does not meet the test criteria , but some sets of strings may satisfy the criteria). While some failure modes may result in bad blocks with no operable units, other failure modes may affect specific parts of the block and may leave at least some operable memory units. Some failure modes may affect individual individually selectable sets of NAND strings within a block, while other sets of NAND strings remain operational. Testing of blocks identified as "bad" blocks can identify many blocks containing a mix of operable and inoperable portions. In some cases, such partial bad blocks can then be used to store data, thereby increasing the capacity of the memory. In some cases, portions of the blocks that fail to meet the test criteria may be reconfigured such that they meet the test criteria. For example, a portion of memory that fails a test using default operating parameters may pass using some modified operating parameters.
在未能擦除块或块的一部分时，可能遇到一种失败模式。可以在测试期间或在某种显著使用(例如，在已经使用块来存储用户数据某个时间段之后)之后检测到这种擦除失败。通常，在块经受擦除步骤之后，使用擦除验证步骤来判定存储器单元是否处于被擦除状况，或者是否需要进一步擦除。虽然擦除步骤可以将擦除状况应用于块的所有存储器单元从而使得块作为整体而被擦除，但是可以将擦除验证应用于块的一部分。例如，一次可以选择块中的一个可分别选择的NAND串集合用于擦除验证。通过向块的选择线施加适当的选择和取消选择电压，可以选择特定NAND串集合，同时取消选择其他NAND串集合。可以向所有字线施加适当的擦除验证电压，从而使得接通所有单元，这应当允许通过NAND串的电流。可以测量此电流以便判定是否擦除存储器单元。如果所选NAND串集合中未被充分擦除(例如，不具有比最小电路更大的电流)的NAND串的数量大于最大允许数量，则可以执行另一个擦除步骤，紧接着是另一个擦除验证步骤。通常，重复擦除步骤和擦除验证步骤，直到达到最大时间或最大数量的循环为止。当达到这种最大值时，可能报告擦除失败，并且可以将NAND串集合视为坏的(并且在一些情况下，可以将块视为坏块)。One failure mode may be encountered upon failure to erase a block or a portion of a block. Such erasure failures may be detected during testing or after some significant use (eg, after a block has been used to store user data for a certain period of time). Typically, after a block is subjected to an erase step, an erase verify step is used to determine whether the memory cells are in an erased condition, or require further erasure. While the erase step may apply erase conditions to all memory cells of the block such that the block as a whole is erased, erasure verification may be applied to a portion of the block. For example, one individually selectable set of NAND strings in a block can be selected for erase verification at a time. By applying appropriate select and deselect voltages to the block's select lines, a particular set of NAND strings can be selected while deselecting other sets of NAND strings. Appropriate erase verify voltages can be applied to all word lines so that all cells are turned on, which should allow current flow through the NAND string. This current can be measured in order to determine whether to erase a memory cell. If the number of NAND strings in the selected set of NAND strings that are not sufficiently erased (e.g., do not have more current than the minimum circuit) is greater than the maximum allowable number, another erase step may be performed, followed by another erase step. except verification steps. Typically, the erase step and erase verify step are repeated until a maximum time or a maximum number of cycles is reached. When this maximum is reached, an erase failure may be reported, and the set of NAND strings (and in some cases, blocks may be considered bad).
在一些情况下，因为甚至在多个擦除循环之后未能擦除(保持被编程)存储器单元，所以发生擦除失败。在其他情况下，可能由于其他原因而发生擦除失败。即使充分擦除了存储器单元，NAND串也可能无法通过擦除验证步骤。例如，通过NAND串的电流可能由于除了存储器单元以外对NAND串的电阻作出显著贡献的某个部件而保持很低，所述电阻使通过NAND串的电流保持低于最小电流。例如，在一些情况下，选择晶体管可以贡献显著电阻。在一些情况下，在NAND串的端部处的连接可能贡献显著电阻。例如，在NAND串连接至共用源极或连接至全局位线的地方可能存在不良连接，所述不良连接可以提供减小通过NAND串的电流的相对高电阻。In some cases, erase failures occur because memory cells fail to erase (remain programmed) even after multiple erase cycles. In other cases, wipe failures may have occurred for other reasons. Even if the memory cells are sufficiently erased, the NAND string may fail the erase verification step. For example, the current through the NAND string may be kept low due to some component other than the memory cells that contributes significantly to the resistance of the NAND string, which keeps the current through the NAND string below a minimum current. For example, select transistors can contribute significant resistance in some cases. In some cases, the connections at the ends of the NAND strings can contribute significant resistance. For example, there may be poor connections where the NAND strings are connected to a common source or to a global bit line, which may provide a relatively high resistance that reduces current flow through the NAND strings.
图11A展示了包括可分别选择的NAND串集合的3D NAND串块的一部分。金属触点(例如，触点150)在漏极选择晶体管(选择栅极“SG”)与全局位线(“GBL”)之间延伸。在一些情况下，这些触点可以例如由于过程相关变化而具有比正常情况更高的电阻，这可能导致通过相应NAND串的更低电流。FIG. 11A shows a portion of a 3D NAND string block including individually selectable sets of NAND strings. A metal contact (eg, contact 150 ) extends between the drain select transistor (select gate "SG") and the global bit line ("GBL"). In some cases, these contacts may have a higher resistance than normal, eg, due to process-related variations, which may result in lower current through the corresponding NAND string.
图11B展示了图11A的单独NAND串，所述单独NAND串包括其与相应全局位线(“GBL”)的连接以及其通过底层衬底和通过垂直导体的源极连接，或者将衬底中的源极线与存储器的源极端子连接的局部互连(“LI”)。在沿着所示出的电流路径的任何点处的电阻可能导致通过NAND串的低电流。例如，在NAND串在触点150处连接至全局位线(GBL)的NAND串顶部处、在NAND串连接至衬底中的源极区域或者衬底中的源极区域与垂直共用源极连接(LI)连接的NAND串底部处的电阻。电阻还可能由有缺陷的选择晶体管(或者源极选择晶体管或者漏极选择晶体管)或有缺陷的虚拟单元产生。增大的电阻可以特定于单独NAND串，例如，由于NAND串与全局位线之间的不良连接引起的电阻。增大的电阻对于多个NAND串来说可能是共同的，例如，由于衬底中的源极区域与垂直共用源极连接之间的不良连接引起的电阻可能影响整个可分别选择的NAND串集合。Figure 11B shows the individual NAND strings of Figure 11A including their connections to corresponding global bit lines ("GBLs") and their source connections through the underlying substrate and through vertical The local interconnect ("LI") where the source line of the memory is connected to the source terminal of the memory. Resistance at any point along the current path shown may result in low current through the NAND string. For example, at the top of the NAND string where the NAND string is connected to the global bit line (GBL) at contact 150, where the NAND string is connected to a source region in the substrate or where the source region in the substrate is connected to a vertical common source (LI) Resistance at the bottom of the connected NAND string. Resistance may also result from defective select transistors (either source select transistors or drain select transistors) or defective dummy cells. The increased resistance may be specific to an individual NAND string, for example, resistance due to a poor connection between the NAND string and the global bit line. Increased resistance may be common to multiple NAND strings, e.g. resistance due to poor connections between source regions in the substrate and a vertical common source connection may affect the entire set of individually selectable NAND strings .
图12展示了连接至衬底中的共用源极区域154的存储器孔(“MH”)的示例。电流流过在源极端子(“ST”)中通过N+掺杂区域(共用源极区域154)形成的垂直局部互连(“LI”)，并且流过在存储器孔中形成的垂直NAND串的沟道。通过给定存储器孔的电流由选择晶体管(例如，所示出的源极选择晶体管156)控制。虚拟字线(“DWL”)对与存储用户数据的存储器单元串联连接的虚拟存储器单元进行控制。Figure 12 shows an example of a memory hole ("MH") connected to a common source region 154 in the substrate. Current flows through the vertical local interconnect ("LI") formed in the source terminal ("ST") through the N+ doped region (common source region 154) and through the vertical NAND string formed in the memory hole ditch. The current through a given memory hole is controlled by a select transistor (eg, source select transistor 156 as shown). A dummy word line ("DWL") controls dummy memory cells connected in series with memory cells storing user data.
低位线电流low line current
图13示意性地展示了块的四个可分别选择的NAND串集合(串0至串3)。用于回收这种块的坏部分的操作的示例一次可以针对一个NAND串集合，并且可以将不同解决方案应用于不同NAND串集合。例如，当未能擦除块时(例如，擦除验证指示超过最大数量的具有不能接受地低的电流的NAND串数量)，则可以通过单独地测试NAND串集合来调查这种低电流的原因。在这种测试期间，通过在相同块的其他选择线接收取消选择电压的同时施加适当选择线电压来选择串集合。可以逐字线地进行读取操作以便判定存储器单元是否处于被擦除状态。当通过NAND串的电流很低，并且擦除了存储器单元中的所有或基本上所有存储器单元时，这通常指示低电流由另一个元件(比如，另一个部件的电阻)引起。通过标识这种电阻，可以标识并应用适当的解决方案，从而使得可以回收NAND串并且随后将其用于存储数据。Figure 13 schematically illustrates four separately selectable sets of NAND strings (string 0 to string 3) for a block. An example of an operation for reclaiming bad portions of such a block may be for one set of NAND strings at a time, and different solutions may be applied to different sets of NAND strings. For example, when a block fails to be erased (e.g., erase verification indicates that the maximum number of NAND strings with an unacceptably low current has been exceeded), then the cause of this low current can be investigated by testing the set of NAND strings individually . During such testing, a set of strings is selected by applying an appropriate select line voltage while other select lines of the same block receive deselect voltages. A read operation may be performed on a word-line basis to determine whether a memory cell is in an erased state. When the current through the NAND string is low, and all or substantially all of the memory cells are erased, this typically indicates that the low current is caused by another element (eg, a resistance of another component). By identifying this resistance, an appropriate solution can be identified and applied, allowing the NAND string to be recycled and subsequently used to store data.
在一些情况下，可以通过施加更高位线电压来克服通过NAND串的低电流。在默认位线电压由于某个电阻而未能生成所需电流时，根据等式V＝IR，增大的位线电压可能足以提供所需电流。因此，一种解决方案可以包括向具有低电流的NAND串的全局位线施加更高的位线电压。在可分别选择的NAND串集合中的相对少量(例如，少于阈值数量)NAND串具有低电流的情况下，可以在逐位线的基础上完成这一点。在一些存储器系统中，位线被分组成列，其中，其中，列可以包括例如8条、16条、32条或更多位线。可以在逐列的基础上施加更高的位线电压。在可分别选择的NAND串集合中的相对大量NAND串(例如，大于阈值数量)具有低电流的一些情况下，则可以向NAND串集合中的所有NAND串施加增大的位线电压。可以保持用于指示要在访问可分别选择的NAND串集合时施加的经修改的位线电压的记录。可以贯穿这种集合而使用单个增大的位线电压，或者可以将不同增大的位线电压用于不同列或用于单独NAND串，例如，可以获得不同位线电压偏移的集合以便调整不同位线电压从而提供充足电流。记录可以具有可分别选择的NAND串集合的单个条目或者可以具有列(所述列可以包括多条位线)的条目或者可以具有需要增大的电压的位线的单独条目。条目可以是指示增大的位线电压的一位条目，或者可以是指示增大的位线电压的幅度的更大条目。In some cases, the low current through the NAND string can be overcome by applying a higher bit line voltage. When the default bit line voltage fails to generate the required current due to some resistance, the increased bit line voltage may be sufficient to provide the required current according to the equation V=IR. Therefore, a solution may include applying a higher bit line voltage to the global bit line of the NAND string with low current. This may be done on a bit-line-by-bit-line basis where a relatively small number (eg, less than a threshold number) of NAND strings in the respectively selectable set of NAND strings have low current. In some memory systems, bit lines are grouped into columns, where a column may include, for example, 8, 16, 32 or more bit lines. Higher bit line voltages can be applied on a column by column basis. In some cases where a relatively large number of NAND strings (eg, greater than a threshold number) of a respectively selectable set of NAND strings have low current, then an increased bit line voltage may be applied to all of the NAND strings of the set of NAND strings. A record may be maintained indicating the modified bit line voltages to be applied when accessing the individually selectable sets of NAND strings. A single increased bit line voltage can be used throughout such a set, or different increased bit line voltages can be used for different columns or for individual NAND strings, for example, a set of different bit line voltage offsets can be obtained to adjust different bit line voltages to provide sufficient current. A record may have a single entry for a set of individually selectable NAND strings or may have an entry for a column (which may include multiple bit lines) or may have individual entries for bit lines requiring increased voltages. The entry may be a one-bit entry indicating the increased bit line voltage, or may be a larger entry indicating the magnitude of the increased bit line voltage.
图14A和图14B示出了用于测试NAND串或存储器阵列的其他部分的电路的示例。当可分别选择的NAND串集合中的存储器单元被读取且被确定为被擦除时，此电路可以用于测量电流并且用于标识可以提供通过NAND串或存储器阵列的其他单元的充足电流的增大的位线电压。在此电路图中示出的电阻401是被测部件并且可以包括一个或多个NAND串(存储器单元接通)连同与NAND串串联连接的部件。数模转换器(DAC)对连接至固定电压(在此示例中，2伏特)的晶体管的栅极进行控制以便控制通过NAND串的电流。比较器405将输入节点403处的电压与预定电压(在图14A的示例中，0.5*VCCQ或1伏特)进行比较。如果输入节点处的电压超过一伏特，则通过NAND串的电流低于通过/失败边界。通过对向输入节点403施加的电压进行修改(通过晶体管)，可以发现提供通过NAND串的充足电流的适当电压。可以通过在施加固定电流时找到输入节点的电压来获得NAND串的电阻，从而使得可以施加适当电压以便生成所需电流。例如，NAND串可以具有五百到一百千欧姆(500kΩ到1MΩ)的电阻。更高电阻的NAND串可以接收被增大以便对增大的电阻进行补偿的位线电压(即，对于给定R值，根据I＝V/R，某个V值可以产生充足电流)。14A and 14B show examples of circuits for testing NAND strings or other portions of a memory array. When memory cells in individually selectable sets of NAND strings are read and determined to be erased, this circuit can be used to measure current and to identify those that can provide sufficient current through the NAND strings or other cells of the memory array increased bit line voltage. Resistor 401 shown in this circuit diagram is the component under test and may include one or more NAND strings (memory cells turned on) along with components connected in series with the NAND strings. A digital-to-analog converter (DAC) controls the gates of transistors connected to a fixed voltage (in this example, 2 volts) in order to control the current through the NAND strings. Comparator 405 compares the voltage at input node 403 to a predetermined voltage (in the example of FIG. 14A , 0.5*VCCQ or 1 volt). If the voltage at the input node exceeds one volt, the current through the NAND string falls below the pass/fail boundary. By modifying the voltage applied to the input node 403 (through the transistor), an appropriate voltage can be found to provide sufficient current through the NAND string. The resistance of the NAND string can be obtained by finding the voltage of the input node when a fixed current is applied so that the appropriate voltage can be applied in order to generate the desired current. For example, a NAND string may have a resistance of five hundred to one hundred thousand ohms (500 kΩ to 1 MΩ). Higher resistance NAND strings can receive bit line voltages that are increased to compensate for the increased resistance (ie, for a given value of R, a certain value of V can produce sufficient current according to I=V/R).
可以在不同条件下执行测试，并且可以将测试结果与包括各种不同条件下的电流的各种标准进行比较。例如，如在图14B中所示出的，低功率测试可以施加相对低电流，从而使得在输入节点处的预期电压相应地更小，并且比较器电压减小(在此示例中，减小至0.25VCCQ或0.5伏特)。测试不同条件可以允许更精确地使用位线电压偏移。例如，位线电压偏移可以用于一些操作而不是用于其他操作。例如，位线电压偏移可以用于进行擦除(相对高电流)但不可以用于进行读取(相对低电流)。可以根据在访问存储器时使用的电流(即，用于擦除、读取和写入操作的电流)来应用适当测试方案。Tests can be performed under different conditions, and the test results can be compared to various standards including currents under various different conditions. For example, as shown in FIG. 14B , a low power test may apply a relatively low current so that the expected voltage at the input node is correspondingly smaller and the comparator voltage decreases (in this example, to 0.25VCCQ or 0.5 volts). Testing different conditions may allow more accurate use of the bit line voltage offset. For example, bit line voltage offsets may be used for some operations but not others. For example, a bit line voltage offset can be used for erasing (relatively high current) but not for reading (relatively low current). Appropriate testing schemes can be applied depending on the currents used when accessing the memory (ie, the currents used for erase, read and write operations).
在一些情况下，单元的增大电阻(例如，NAND串电阻)可能由选择晶体管引起。通常，因为可分别选择的NAND串集合中的所有NAND串由选择线共享，所以选择线问题可能影响可分别选择的NAND串集合的大部分或所有NAND串。在示例中，对示出了具有低电流(高电阻)的大量NAND串的NAND串集合进行测试以便查看更高的选择线电压是否可以克服问题。可以对增大的选择线电压进行测试以便查看高电阻NAND串的数量是否可以减小至可接受数量。如果增大的选择线电压充分减小了高电阻NAND串的数量，则这指示选择晶体管是电阻的实质原因。随后，对NAND串集合的访问可以将增大的选择线电压用于至少一条选择线。可以保持用于指示此可分别选择的NAND串集合需要增大的选择线电压并且随后的访问操作可以相应地使用增大的选择线电压的记录。在一些情况下，单个增大的选择线电压可以用于可以以此方式固定的任何可分别选择的NAND串集合。在其他情况下，可以根据测试结果而将选择线电压增大不同量。可能优选的是，在可能的情况下使用更低的选择线电压，从而使得可以根据在不同可分别选择的NAND串集合中遇到的问题的严重性而施加一系列选择线电压。In some cases, the increased resistance of the cell (eg, NAND string resistance) may be caused by the select transistor. Typically, select line issues may affect most or all of the NAND strings in the set of individually selectable NAND strings because all of the NAND strings in the set of individually selectable NAND strings are shared by the select line. In an example, a set of NAND strings showing a large number of NAND strings with low current (high resistance) was tested to see if a higher select line voltage could overcome the problem. An increased select line voltage can be tested to see if the number of high resistance NAND strings can be reduced to an acceptable number. If the increased select line voltage sufficiently reduces the number of high resistance NAND strings, this is an indication that the select transistors are substantially responsible for the resistance. Subsequently, an access to the set of NAND strings may use an increased select line voltage for at least one select line. A record may be maintained indicating that this individually selectable set of NAND strings requires an increased select line voltage and that subsequent access operations may use the increased select line voltage accordingly. In some cases, a single increased select line voltage can be used for any set of individually selectable NAND strings that can be fixed in this way. In other cases, the select line voltage may be increased by different amounts depending on the test results. It may be preferable to use lower select line voltages where possible, so that a range of select line voltages can be applied depending on the severity of the problem encountered in different sets of individually selectable NAND strings.
在一些情况下，可以通过组合方式(例如，通过施加增大的选择线电压以及增大位线电压)来回收块的一部分。将理解的是，这些方式不是排他性的并且可以以任何有效的方式(包括通过与其他方式组合)来加以应用。In some cases, a portion of a block may be reclaimed in a combination (eg, by applying an increased select line voltage and increasing the bit line voltage). It will be understood that these means are not exclusive and may be applied in any effective way, including by combination with other means.
在块的一部分疑似在某种程度上是有缺陷的一些示例中，可以采取附加步骤来保护在这种部分中存储的数据。例如，可以将更高冗余级应用于在除了其他部分之外的这种部分中存储的数据。可以使用具有某种纠错能力的默认编码方案来对数据进行编码的存储器系统可以使用具有更高纠错能力的增强型编码方案来对待存储于可疑区域中的数据进行编码。例如，可以将第一纠错码(ECC)方案作为默认方案而应用于在存储器阵列中存储的数据，而可以将具有更高冗余率(以及因此，更大的纠错能力)的第二ECC方案应用于在可疑区域中存储的数据。在一些情况下，可以将附加冗余方案应用于在可疑部分中存储的数据。例如，除了默认ECC方案以外，可以将另一个冗余方案添加到特定数据部分。这种附加方案的示例是应用于许多数据部分的并且允许从其他部分和冗余数据中重新计算所述部分之一的排他性OR(XOR)方案。增大的冗余率可能是增强型冗余方案或选择性地应用于可疑区域中的数据的附加冗余方案的结果。In some examples where a portion of a block is suspected to be defective in some way, additional steps may be taken to protect data stored in such portion. For example, higher levels of redundancy may be applied to data stored in such sections among other sections. A memory system that can encode data using a default encoding scheme with some error correction capabilities can encode data to be stored in a suspect area using an enhanced encoding scheme with higher error correction capabilities. For example, a first error-correcting code (ECC) scheme can be applied as a default scheme to data stored in a memory array, while a second one with higher redundancy (and thus, greater error correction capability) can be applied. An ECC scheme is applied to data stored in the suspect area. In some cases, additional redundancy schemes may be applied to the data stored in the suspect portion. For example, in addition to the default ECC scheme, another redundancy scheme may be added to a specific data section. An example of such an additional scheme is an exclusive OR (XOR) scheme applied to many data parts and allowing recomputation of one of the parts from other parts and redundant data. The increased redundancy ratio may be the result of an enhanced redundancy scheme or an additional redundancy scheme selectively applied to data in the suspect region.
可以将区域视为可疑，并且在所述区域中存储的数据可能由于许多原因而经受附加测量。在块的一部分(比如，可分别选择的NAND串集合)未能满足某些标准的情况下(比如，具有大量低电流NAND串)，可以将所述部分视为可疑。可以使用比通常情况更高的选择线电压和/或可以施加比通常情况更高的位线电压和/或可以将更高的冗余率应用于所存储的数据。可以保持指示块的哪些部分应当具有使用增大的冗余率来编码的数据的表。在一些情况下，可以将这种表与指示其他操作参数(比如，增大的位线电压和/或增大的选择线电压)的表组合。在块包含可疑部分时，访问时间可能增大(例如，由于附加编码和配置时间)，并且数据丢失风险可能更高。因此，可以将这种块作为仅在不存在可用的良好块时使用的备用块而维护。因此，在使用所有良好块之后，用户数据可以仅存储于这种块中，从而使得性能不受影响。Areas may be considered suspect, and data stored in said areas may be subject to additional measurements for a number of reasons. Where a portion of a block (eg, a separately selectable set of NAND strings) fails to meet certain criteria (eg, has a large number of low current NAND strings), that portion may be considered suspect. A higher than usual select line voltage can be used and/or a higher than usual bit line voltage can be applied and/or a higher redundancy ratio can be applied to the stored data. A table may be maintained indicating which parts of a block should have data encoded with an increased redundancy rate. In some cases, such tables may be combined with tables indicating other operating parameters, such as increased bit line voltage and/or increased select line voltage. When a block contains suspect parts, access times may increase (eg, due to additional encoding and configuration time), and the risk of data loss may be higher. Therefore, such blocks can be maintained as spare blocks to be used only when no good blocks are available. Thus, after all good blocks are used, user data can be stored only in such blocks, leaving performance unaffected.
图15展示了检查三维NAND块的部分并相应地应用某些维护步骤的方案的示例。在针对存储器孔连接性的检查例程中，在对存储器单元进行检查以便确保它们被充分擦除之后通过测量存储器孔(“MH”)的导电性503来检查存储器孔的导电性501。如果存储器孔具有低电流(高电阻)，则确认存储器孔问题505，并发起手指维护507(术语“手指”可应用于像一组手指一样平行地延伸的可分别选择的NAND串集合)。在另一个检查例程中，确定选择栅极的阈值电压(VT)分布511，并将其与目标阈值电压范围进行比较513以便标识问题。可替代地，可以对所读取的逻辑1和逻辑0位的数量进行计数(例如，通过直接存储器计数器“DMC”)以便标识有问题的选择晶体管。如果坏串的数量(带有具有在期望范围之外的阈值电压的选择栅极的串)不大于阈值515，则可以将块的部分视为正常并且可以使用默认操作参数来对其进行操作517。如果坏串的数量超过阈值数量515，则可以将此可分别选择的NAND串集合视为可疑并且可以将其与待进行手指维护的可疑集合列表进行比较519。如果手指不在列表上，则将其添加至列表中521。在手指维护507期间，可以计算可分别选择的串集合的一个或多个经修改的操作参数，比如，增大的位线电压、增大的选择线电压、增大的冗余率或其他参数。Figure 15 shows an example of a scheme for inspecting portions of a 3D NAND block and applying certain maintenance steps accordingly. In the inspection routine for memory hole connectivity, the conductivity of the memory hole ("MH") is checked 501 by measuring the conductivity 503 of the memory hole ("MH") after the memory cells are inspected to ensure they are sufficiently erased. If the memory hole has low current (high resistance), then the memory hole problem is confirmed 505 and finger maintenance is initiated 507 (the term "finger" can be applied to a separately selectable set of NAND strings extending in parallel like a set of fingers). In another inspection routine, the threshold voltage (VT ) distribution of the select gates is determined 511 and compared 513 to a target threshold voltage range in order to identify problems. Alternatively, the number of logic 1 and logic 0 bits read can be counted (eg, by a direct memory counter "DMC") in order to identify problematic select transistors. If the number of bad strings (strings with select gates having threshold voltages outside the expected range) is not greater than a threshold 515, then the portion of the block may be considered normal and may be operated 517 using default operating parameters . If the number of bad strings exceeds a threshold number 515, this individually selectable set of NAND strings can be considered suspect and can be compared 519 to a list of suspect sets to be finger maintained. If the finger is not on the list, it is added 521 to the list. During finger maintenance 507, one or more modified operating parameters may be calculated for separately selectable sets of strings, such as increased bit line voltages, increased select line voltages, increased redundancy ratios, or other parameters .
随后，当访问手指时，作出关于访问是否为编程操作的确定525。如果其是编程操作，则对被编程字线(WL)的条件进行调整527，例如，通过增大一个或多个选择线电压和/或增大一个或多个位线电压和/或将更高冗余率应用于被存储数据(通过在手指中提供附加奇偶性数据531)。Then, when the finger is accessed, a determination is made 525 as to whether the access is a programming operation. If it is a programming operation, the condition of the programmed word line (WL) is adjusted 527, for example, by increasing one or more select line voltages and/or increasing one or more bit line voltages and/or changing the High redundancy is applied to the stored data (by providing additional parity data 531 in the fingers).
如果所述操作不是编程操作，则作出关于其是否为主机读取操作的确定535。如果其是主机读取操作，则可以对选择栅极(SG)电压和/或位线(BL)电压进行调整537以便执行读取。调整可由记录条目指示。在读取数据并将其返回至主机之后，可以将数据重新定位539至更安全位置(例如，不需要经调整的电压的手指)。If the operation is not a program operation, then a determination is made 535 as to whether it is a host read operation. If it is a host read operation, the select gate (SG) voltage and/or bit line (BL) voltage may be adjusted 537 to perform the read. Adjustments may be indicated by log entries. After the data is read and returned to the host, the data can be relocated 539 to a safer location (eg, a finger that does not require a regulated voltage).
如果操作不是编程或主机写入操作，则作出关于其是否为擦除操作的确定545。如果其是擦除操作，则可以对选择栅极(SG)电压和/或位线(BL)电压进行调整547。调整可由记录条目指示。然后，使用经调整的电压来进行擦除操作549。If the operation is not a program or host write operation, then a determination is made 545 as to whether it is an erase operation. If it is an erase operation, an adjustment 547 may be made to the select gate (SG) voltage and/or bit line (BL) voltage. Adjustments may be indicated by log entries. Then, an erase operation 549 is performed using the adjusted voltage.
如果操作不是编程、主机写入或擦除操作，则执行对手指的健康进行测量(例如，对具有相同干扰水平的单元的数量进行测量)并且可以对干扰量进行测量的读取擦洗操作555。可以使用经修改的参数(比如，选择线电压和位线电压)来执行读取擦洗。将数据重新定位557到另一个位置(使用ECC来纠正数据中的任何错误)。If the operation is not a program, host write or erase operation, a read scrub operation 555 is performed that measures the health of the finger (eg, the number of cells with the same disturbance level) and may measure the amount of disturbance. Read scrubbing can be performed using modified parameters such as select line voltage and bit line voltage. Relocate 557 the data to another location (using ECC to correct any errors in the data).
图16示出了存储器系统601的连接至主机80的部件的示例。存储器系统601包括存储器控制器603和存储器裸片605(以及附加存储器裸片)。存储器裸片605包括许多可单独擦除的存储器块(例如，3D NAND闪存块)。每个块具有可分别选择的部分(例如，NAND串集合)。一些块被标识为坏块(“坏”)并且不被使用。一些块具有不满足一些标准的至少一个可分别选择的部分(例如，NAND串集合)(例如，块607包含四个可分别选择的NAND串集合，串609未能满足一些标准)。存储器裸片605还包括位线驱动器611，所述位线驱动器可配置成用于在访问不同可分别选择的NAND串集合时施加不同位线电压(例如，在访问串609时施加更高位线电压)。位线读出单元613被配置成用于读出位线电流并将位线电流与阈值电流进行比较。选择线读出单元615被配置成用于读出选择线阈值电压并且用于将其与最小阈值电压进行比较。存储器控制器603包括可以结合存储器裸片605中的外围电路而控制对存储器裸片605的访问的编程电路617、读取电路619以及擦除电路621。位线电压(VBL)调整单元623被配置成用于向不同可分别选择的NAND串集合(结合位线驱动器611)施加不同位线电压。位线电压调整单元623与位线电压表625通信，所述位线电压表记录要在访问不同可分别选择的NAND串时使用的位线电压(或偏移)。选择栅极电压(VSG)调整单元627被配置成用于结合存储器裸片605中的外围电路而向块中的不同可分别选择的NAND串集合施加不同选择线电压(例如，向除了块607的其他串之外的串609施加更高选择线电压)。选择栅极电压调整单元627与选择栅极电压表629通信，所述选择栅极电压表记录不同串集合的选择栅极电压(或偏移)。自适应冗余单元631被配置成用于将不同冗余率应用于在存储器块的不同区域中存储的数据(例如，将更高冗余率应用于在除了块607中的其他集合以外的NAND串集合609中存储的数据)。自适应冗余单元可以包括具有可变冗余的ECC引擎。自适应冗余单元可以包括用于应用不同方案的不同部件(例如，ECC引擎和XOR电路)。自适应冗余单元631与冗余表633通信，所述冗余表记录待用于在块的不同部分中存储的数据的冗余率。FIG. 16 shows an example of components of a memory system 601 connected to a host 80 . Memory system 601 includes memory controller 603 and memory die 605 (and additional memory die). Memory die 605 includes a number of individually erasable memory blocks (eg, 3D NAND flash memory blocks). Each block has individually selectable portions (eg, a set of NAND strings). Some blocks are marked as bad blocks ("bad") and are not used. Some blocks have at least one separately selectable portion (eg, a set of NAND strings) that does not meet some criteria (eg, block 607 contains four separately selectable sets of NAND strings, string 609 fails to meet some criteria). Memory die 605 also includes a bitline driver 611 configurable to apply different bitline voltages when accessing different sets of respectively selectable NAND strings (e.g., apply a higher bitline voltage when accessing string 609 ). The bit line sensing unit 613 is configured to sense the bit line current and compare the bit line current with a threshold current. The select line readout unit 615 is configured for sensing the select line threshold voltage and for comparing it with the minimum threshold voltage. Memory controller 603 includes programming circuitry 617 , read circuitry 619 , and erase circuitry 621 that may control access to memory die 605 in conjunction with peripheral circuitry in memory die 605 . The bit line voltage (VBL) adjustment unit 623 is configured to apply different bit line voltages to different respectively selectable sets of NAND strings (in conjunction with the bit line driver 611 ). The bit line voltage adjustment unit 623 is in communication with a bit line voltage table 625 which records the bit line voltage (or offset) to be used when accessing different respectively selectable NAND strings. Select gate voltage (VSG) adjustment unit 627 is configured to apply different select line voltages to different sets of individually selectable NAND strings in a block in conjunction with peripheral circuitry in memory die 605 (e.g., to all but block 607 Strings 609 other than the other strings apply a higher select line voltage). The select gate voltage adjustment unit 627 is in communication with a select gate voltage table 629 which records the select gate voltages (or offsets) for different sets of strings. Adaptive redundancy unit 631 is configured to apply different redundancy rates to data stored in different regions of a memory block (e.g., apply higher redundancy rates to NAND data stored in string set 609). The adaptive redundancy unit may include an ECC engine with variable redundancy. The adaptive redundancy unit may include different components (eg, ECC engines and XOR circuits) for applying different schemes. The adaptive redundancy unit 631 communicates with a redundancy table 633 that records redundancy rates to be used for data stored in different parts of a block.
图17示出了包括共享源极连接(局部互连)的可分别选择的串集合(串0至串3)的3D NAND存储器的另一个示例。因为串集合与局部互连相距不同距离，所以在每个串集合的源极侧处的串联电阻是不同的。例如，访问串0时的串联电阻大于访问串3时的串联电阻。在这些差异显著的情况下，对访问电压(读取电压、写入电压和擦除电压)的某种调整可能是适当的。例如，访问串0时的一些电压可能比访问串3时更高，以便补偿增大的串联电阻。FIG. 17 shows another example of a 3D NAND memory comprising individually selectable sets of strings (String 0 to String 3 ) that share source connections (local interconnects). Because the string sets are at different distances from the local interconnect, the series resistance at the source side of each string set is different. For example, the series resistance when string 0 is accessed is greater than the series resistance when string 3 is accessed. Where these differences are significant, some adjustment to the access voltages (read voltage, write voltage, and erase voltage) may be appropriate. For example, some voltages may be higher when accessing string 0 than when accessing string 3 in order to compensate for the increased series resistance.
除了各串的变化以外，可能存在NAND存储器的其他变化(比如，这种变化)。例如，在此实例中，NAND串的沟道形成于存储器孔中，并且这种存储器孔的直径通常由于蚀刻化学而随着深度增大而减小。因此，在存储器单元之间可能存在作为在衬底上方的高度的函数的可预测差异。在一些情况下，可以检测到这种差异并且可以根据存储器孔直径来作出某种调整。测量和调整不限于串集合或任何其他单元并且可以应用于除了三维NAND闪存以外的各种存储器。In addition to string variations, there may be other variations of NAND memory such as this variation. For example, in this example, the channel of the NAND string is formed in a memory hole, and the diameter of such a memory hole typically decreases with increasing depth due to etch chemistry. Therefore, there may be predictable differences between memory cells as a function of height above the substrate. In some cases, this difference can be detected and some adjustment can be made based on the memory hole diameter. The measurements and adjustments are not limited to sets of strings or any other cells and can be applied to various memories other than 3D NAND flash.
电阻式存储器和其他存储器Resistive and other memories
除了NAND闪存以外，各种其他存储器可以包括块中的可分别选择的部分，并且可以得益于此处所描述的结构和技术。初始地参照图18，以三维存储器10的一部分的等效电路的形式来示意性地且总体上展示了这种存储器的架构。这是三维阵列的特定示例。标准三维矩形坐标系11用作参考，向量x、y和z中的每个向量的方向与其他两个向量正交。In addition to NAND flash memory, various other memories may include individually selectable portions of blocks and may benefit from the structures and techniques described herein. Referring initially to FIG. 18 , the architecture of such a memory is shown schematically and generally in the form of an equivalent circuit of a portion of a three-dimensional memory 10 . This is a specific example of a 3D array. A standard three-dimensional rectangular coordinate system 11 is used as a reference, and the direction of each of the vectors x, y, and z is orthogonal to the other two.
用于选择性地将内部存储器元件与外部数据电路连接的电路可以形成于半导体衬底13中。在此特定示例中，利用了选择或切换设备Qxy的二维阵列，其中，x给出了设备在x方向上的相对位置并且y给出了其在y方向上的相对位置。作为示例，单独的设备Qxy可以是选择栅极或选择晶体管。全局位线(GBLx)在y方向上延长并且在x方向上具有由下标指示的相对位置。尽管在读取期间并且通常还在编程期间，一次仅接通与特定全局位线连接的一个选择设备，但是全局位线(GBLx)可以与在x方向上具有相同位置的选择设备Q的源极或漏极单独连接。单独选择设备Q的源极或漏极中的另一者与局部位线(LBLxy)之一连接。局部位线在z方向上垂直地延长，并且在x(行)和y(列)方向上形成规则阵列。Circuits for selectively connecting internal memory elements with external data circuits may be formed in the semiconductor substrate 13 . In this particular example, a two-dimensional array of selection or switching devices Qxy is utilized, where x gives the relative position of the devices in the x direction and y gives their relative position in the y direction. As an example, individual devices Qxy may be select gates or select transistors. The global bit lines (GBLx) are elongated in the y-direction and have relative positions indicated by subscripts in the x-direction. Although only one select device connected to a particular global bit line is turned on at a time during read and often also during programming, the global bit line (GBLx) can be the source of select device Q with the same position in the x direction or the drain is connected separately. The other of the source or the drain of the individually selected device Q is connected to one of the local bit lines (LBLxy). The local bit lines extend vertically in the z direction and form regular arrays in the x (row) and y (column) directions.
为了将一组局部位线(在此示例中，被指定为一行)与相应全局位线连接，控制栅极线SGy在x方向上延长并且与在y方向上具有共同位置的单个选择设备Qxy行的控制端子(栅极)连接。因此，根据控制栅极线SGy中的哪条控制栅极线接收将与其连接的选择设备接通的电压，选择设备Qxy一次将x方向上的一行局部位线(LBLxy)(在y方向上具有相同位置)连接至全局位线(GBLx)中的相应全局位线。剩余控制栅极线接收使其连接选择设备保持断开的电压。可以指出的是，由于仅一个选择设备(Qxy)与局部位线(LBLxy)中的每条局部位线一起使用，所以可以使在半导体衬底上的阵列在x方向和y方向两者上的间距非常小，以及因此使存储器存储元件的密度很大。In order to connect a set of local bitlines (designated as a row in this example) with corresponding global bitlines, the control gate line SGy is extended in the x-direction and rowed with a single selection device Qxy having a common position in the y-direction The control terminal (gate) connection. Therefore, depending on which of the control gate lines SGy receives the voltage to turn on the selection device connected thereto, the selection device Qxy transfers one row of local bit lines (LBLxy) in the x direction (LBLxy) in the y direction at a time. same location) to the corresponding one of the global bit lines (GBLx). The remaining control gate lines receive a voltage that keeps their connected select devices disconnected. It can be noted that since only one selection device (Qxy) is used with each of the local bitlines (LBLxy), it is possible to make the array on the semiconductor substrate in both the x-direction and the y-direction The pitch is very small, and thus the density of memory storage elements is very high.
存储器存储元件Mzxy形成于多个平面中，在衬底13上方的z方向上以不同的距离来定位所述多个平面。在图18中展示了两个平面1和2，但是通常将存在更多，比如，4个、6个或甚至更多。在距离z处的每个平面中，字线WLzy在x方向上延长并且在y方向上在局部位线(LBLxy)之间间隔开。每个平面的字线WLzy单独跨过字线的任一侧上的局部位线LBLxy中的相邻两条局部位线。单独的存储器存储元件Mzxy连接于与这些单独的交叉点相邻的一条局部位线LBLxy与一条字线WLzy之间。因此，单独的存储器元件Mzxy可通过将适当电压置于局部位线LBLxy和字线WLzy(存储器元件连接于其之间)上而寻址。对电压进行选择以便提供对使存储器元件的状态从现有状态变化为期望的新状态而言是必要的电刺激。这些电压的水平、持续时间和其他特性取决于用于存储器元件的材料。The memory storage elements Mzxy are formed in a plurality of planes positioned at different distances in the z-direction above the substrate 13 . In Figure 18 two planes 1 and 2 are shown, but typically there will be more, eg 4, 6 or even more. In each plane at distance z, word lines WLzy are elongated in the x direction and spaced between local bit lines (LBLxy) in the y direction. The word line WLzy of each plane individually spans adjacent two of the local bit lines LBLxy on either side of the word line. Individual memory storage elements Mzxy are connected between one local bit line LBLxy and one word line WLzy adjacent to these individual intersections. Thus, individual memory elements Mzxy can be addressed by placing appropriate voltages on local bit line LBLxy and word line WLzy between which the memory element is connected. The voltage is selected to provide the electrical stimulus necessary to change the state of the memory element from an existing state to a desired new state. The level, duration, and other characteristics of these voltages depend on the materials used for the memory element.
三维存储器单元结构的每个“平面”通常由至少两个层形成，导电字线WLzy被定位在其中的一个层以及由介电材料组成的将平面彼此电隔离的另一个层。例如根据存储器元件Mzxy的结构，在每个平面中还可能存在附加层。平面在半导体衬底上堆叠于彼此顶部，局部位线LBLxy与局部位线延伸穿过的每个平面的存储器元件Mzxy连接。Each "plane" of a three-dimensional memory cell structure is typically formed of at least two layers, one layer in which the conductive word lines WLzy are located and another layer composed of a dielectric material that electrically isolates the planes from each other. There may also be additional layers in each plane, eg depending on the structure of the memory elements Mzxy. The planes are stacked on top of each other on the semiconductor substrate, the local bit line LBLxy being connected to the memory element Mzxy of each plane through which the local bit line extends.
图19以剖视图示出了三维存储器的实施方式，所述三维存储器包括其之间具有存储器元件的局部位线和字线。此示例被配置成在第一次沉积时使用非导电的非易失性存储器(NVM)材料。金属氧化物或其他适当材料可能具有这种特性。可以响应于置于那些电极上的适当电压而在材料的相反侧上的电极之间形成导电长丝。这些电极是阵列中的位线和字线。由于材料是以其他方式非导电的，但是没必要将字线和位线的交叉点处的存储器元件彼此隔离。许多存储器元件可由单个连续材料层实施，在图19的情况下，所述单个连续材料层是在y方向上沿着垂直位线的相反侧垂直地取向的并且向上延伸穿过所有平面的NVM材料条。图19的结构的显著优点是所有字线以及在一组平面中在所述字线之下的绝缘条可以通过使用单个掩模来同时限定，由此在很大程度上简化制造工艺。Figure 19 shows, in cross-section, an embodiment of a three-dimensional memory including local bit lines and word lines with memory elements therebetween. This example is configured to use a non-conductive non-volatile memory (NVM) material on first deposition. Metal oxides or other suitable materials may have this property. Conductive filaments can be formed between electrodes on opposite sides of the material in response to appropriate voltages placed on those electrodes. These electrodes are the bitlines and wordlines in the array. Since the material is otherwise non-conductive, it is not necessary to isolate the memory elements at the intersection of word and bit lines from each other. Many memory elements can be implemented from a single continuous layer of material, which in the case of FIG. 19 is NVM material vertically oriented in the y-direction along opposite sides of the vertical bit lines and extending up through all planes strip. A significant advantage of the structure of Figure 19 is that all word lines and the insulating strips below them in one set of planes can be defined simultaneously by using a single mask, thereby simplifying the fabrication process considerably.
参照图19，示出了三维阵列的四个平面101、103、105和107中的一小部分。所述平面中的所有平面具有相同的水平图案的栅极、电介质和存储器存储元件(NVM)材料。在每个平面中，金属字线(WL)在x方向上延长并且在y方向上间隔开。每个平面包括将其字线与其之下的平面的(在平面101的情况下，在其之下的衬底电路部件的)字线隔离的绝缘电介质层。在垂直z方向上延长的并且在x-y方向上形成规则阵列的许多金属局部位线(LBL)“柱”延伸穿过每个平面。Referring to Figure 19, a small portion of the four planes 101, 103, 105 and 107 of the three-dimensional array are shown. All of the planes have the same horizontal pattern of gate, dielectric and memory storage element (NVM) material. In each plane, the metal word lines (WL) are elongated in the x-direction and spaced apart in the y-direction. Each plane includes an insulating dielectric layer that isolates its wordlines from the wordlines of the plane below it (in the case of plane 101 , of the substrate circuit components below it). A number of metal local bit line (LBL) "pillars" extending in the vertical z direction and forming a regular array in the x-y directions extend across each plane.
每个位线柱通过在衬底中形成的其栅极由在x方向上延长的选择栅极线(SG)驱动的选择设备(Qxy)以与柱间隔相同的间距连接至硅衬底中在y方向上延伸的一组全局位线(GBL)之一，所述选择栅极线同样形成于衬底中。切换设备Qxy可以是常规的CMOS晶体管(或垂直npn晶体管)并且可以使用与用于形成其他常规电路系统的工艺相同的工艺来制作。在使用npn晶体管而不是MOS晶体管的情况下，使用在x方向上延长的基底接触电极线来替代选择栅极(SG)线。在衬底中还制作了但是在图19中未示出读出放大器、输入-输出(I/O)电路系统、控制电路系统以及任何其他必要的外围电路系统。Each bitline pillar is connected to the silicon substrate at the same pitch as the pillar interval through a select device (Qxy) formed in the substrate whose gate is driven by a select gate line (SG) extending in the x direction. One of a set of global bit lines (GBL) extending in the y direction, the select gate lines are also formed in the substrate. Switching device Qxy may be a conventional CMOS transistor (or vertical npn transistor) and may be fabricated using the same process as used to form other conventional circuitry. Where npn transistors are used instead of MOS transistors, substrate contact electrode lines extending in the x direction are used instead of select gate (SG) lines. Also fabricated in the substrate but not shown in FIG. 19 are sense amplifiers, input-output (I/O) circuitry, control circuitry, and any other necessary peripheral circuitry.
在x方向上对于每个局部位线柱行，存在一条选择栅极线(SG)，并且对于每条单独的局部位线(LBL)，存在一个选择设备(Q)。因此，例如，SG3是控制选择设备Q13、Q23以及沿着x方向的附加选择设备(未示出)的选择栅极线。局部位线LBL13、LBL23以及沿着x方向的附加位线(未示出)以及连接至这些局部位线的存储器元件形成存储器的可分别选择的一部分。在一些情况下，存储器的不同可分别选择的部分可以具有可以通过执行某项测试来发现的不同特性。例如，在图19中可以看到，全局位线在y方向上延伸，从而使得全局位线的串联电阻随着与全局位线驱动器的距离的增大而沿着y方向增大。因此，当访问不同可分别选择的部分时，由于用于访问对应部分的全局位线的不同长度而可以观察到不同串联电阻。如果这种串联电阻超过限制，则可以修改操作参数。例如，可以增大向全局位线施加的一个或多个电压以便补偿沿着全局位线的电压降。相比更近的且具有更小全局位线电阻的可分别选择的部分，位线驱动器可以被配置成用于向更远的且具有更高的全局位线电阻的可分别选择的部分传递更高的电压。For each row of local bitline columns in the x-direction there is one select gate line (SG) and for each individual local bitline (LBL) there is one select device (Q). Thus, for example, SG3 is the select gate line controlling select devicesQ13 ,Q23 and an additional select device (not shown) along the x-direction. The local bit lines LBL13 , LBL23 and additional bit lines (not shown) along the x-direction and the memory elements connected to these local bit lines form respectively selectable parts of the memory. In some cases, different respectively selectable portions of memory may have different properties that may be discovered by performing a certain test. For example, it can be seen in FIG. 19 that the global bitlines extend in the y-direction such that the series resistance of the global bitlines increases along the y-direction with increasing distance from the global bitline driver. Thus, when accessing different separately selectable parts, different series resistances may be observed due to the different lengths of the global bit lines used to access the corresponding parts. If this series resistance exceeds limits, operating parameters can be modified. For example, one or more voltages applied to the global bit lines may be increased in order to compensate for voltage drops along the global bit lines. The bit line driver may be configured to deliver a higher value to a separately selectable portion that is further away and has a higher global bit line resistance than a separately selectable portion that is closer and has a lower global bit line resistance. high voltage.
每个垂直的非易失性存储器元件(NVM)材料条夹置在垂直局部位线(LBL)与在所有平面中垂直堆叠的多条字线(WL)之间。优选地，在x方向上在局部位线(LBL)之间存在NVM材料。存储器存储元件(M)被定位在字线(WL)与局部位线(LBL)的每个交叉点处。在存储器存储元件(M)是电阻式元件的情况下，在相交的局部位线(LBL)与字线(WL)之间的小NVM材料区域可以在导电(设置)状态与非导电(重置)状态之间通过向相交线施加的适当电压而可控地交替。Each vertical strip of non-volatile memory element (NVM) material is sandwiched between a vertical local bit line (LBL) and a plurality of word lines (WL) stacked vertically in all planes. Preferably, there is NVM material between the local bit lines (LBL) in the x-direction. A memory storage element (M) is positioned at each intersection of a word line (WL) and a local bit line (LBL). Where the memory storage element (M) is a resistive element, a small region of NVM material between the intersecting local bit line (LBL) and word line (WL) can be switched between a conductive (set) state and a non-conductive (reset) state. ) states are controllably alternated by applying appropriate voltages to the intersecting lines.
还可能存在于LBL与平面之间的电介质之间形成的寄生NVM元件。通过相比于NVM材料层的厚度而将介电条的厚度(即，局部位线与字线之间的间隔)选择为很大，可以使由相同垂直字线堆叠中的字线之间的不同电压引起的场足够小，从而使得寄生元件决不传导大量电流。类似地，在其他实施例中，如果相邻LBL之间的操作电压保持低于编程阈值，则非导电NVM材料在位置上可以在相邻局部位线之间处于左边。There may also be parasitic NVM elements formed between the LBL and the dielectric between the planes. By choosing the thickness of the dielectric strips (i.e., the spacing between local bitlines and wordlines) to be large compared to the thickness of the NVM material layer, the distance between wordlines in the same vertical wordline stack can be minimized. The fields induced by the different voltages are small enough that the parasitic elements never conduct significant current. Similarly, in other embodiments, the non-conductive NVM material may be positioned to the left between adjacent local bit lines if the operating voltage between adjacent LBLs remains below the programming threshold.
可以将各种材料用作NVM材料。用于形成电阻式存储器元件(例如，用于形成图19的阵列中的存储器元件Mzxy)的材料可以是硫族化物、金属氧化物或响应于向材料施加的外部电压或者通过材料的电流而展现出稳定可逆电阻偏移的许多材料中的任何一种材料。虽然此处描述了特定示例，但是将理解的是，可以使用任何适当材料。Various materials can be used as the NVM material. Materials used to form resistive memory elements (e.g., used to form memory elements Mzxy in the array of FIG. 19) may be chalcogenides, metal oxides, or exhibit Any of a number of materials that stabilize reversible resistive shifts. While specific examples are described herein, it will be understood that any suitable material may be used.
金属氧化物以在初始地沉积时是绝缘的来表征。一种适当的金属氧化物是钛氧化物(TiOx)。在图20的示例中，在退火工艺中对接近化学计量TiO2块材料进行变更以便在底部电极附近创建缺氧层(或氧空缺层)。具有其高功函数的顶部铂电极创建针对电子的高电位Pt/TiO2阻挡层。因此，在中等电压(低于一伏特)下，非常低的电流将流过所述结构。底部Pt/TiO2-x阻挡层由氧空缺(O+2)的存在而降低并且表现为低电阻接触(欧姆接触)。(已知TiO2中的氧空缺充当变换导电掺杂半导体中的绝缘氧化物的n型掺杂物。)所产生的复合结构处于非导电(高电阻)状态。Metal oxides are characterized as being insulating when initially deposited. One suitable metal oxide is titanium oxide (TiOx). In the example of FIG. 20, the near stoichiometric TiO2 bulk material is altered in the annealing process to create an oxygen deficient layer (or oxygen vacancy layer) near the bottom electrode. The top platinum electrode with its high work function creates a high potential Pt/TiO2 barrier for electrons. Therefore, at moderate voltages (less than one volt), very low currents will flow through the structure. The bottom Pt/TiO2-x barrier layer is reduced by the presence of oxygen vacancies (O+2) and behaves as a low resistance contact (ohmic contact). (Oxygen vacancies in TiO2 are known to act as n-type dopants for transforming the conduction of insulating oxides in doped semiconductors.) The resulting composite structure is in a non-conducting (high-resistance) state.
但是当在结构两端施加大的负电压(比如，1.5伏特)时，氧空缺朝顶部电极漂移，并且因此，电位阻挡层Pt/TiO2减小并且相对高的电流可以流过所述结构。然后，设备处于低电阻(导电)状态。其他人报告的实验已经表明在像长丝的TiO2区域(可能沿着晶界)中发生导电。But when a large negative voltage (say, 1.5 volts) is applied across the structure, oxygen vacancies drift towards the top electrode, and thus, the potential barrier Pt/TiO2 is reduced and a relatively high current can flow through the structure. The device is then in a low resistance (conducting) state. Experiments reported by others have shown that conduction occurs in filament-like TiO2 regions, possibly along grain boundaries.
通过在图20的结构两端施加大的正电压来破坏导电路径。在这种正偏压下，氧空缺移动远离顶部Pt/TiO2阻挡层附近并且“破坏”长丝。设备返回到其高电阻状态。导电状态和非导电状态两者都是非易失性的。通过施加约0.5伏特的电压来读出存储器存储元件的导电可以容易地确定存储器元件的状态。The conductive path was broken by applying a large positive voltage across the structure of FIG. 20 . Under this positive bias, oxygen vacancies move away from near the top Pt/TiO2 barrier and "break" the filament. The device returns to its high resistance state. Both the conductive state and the non-conductive state are non-volatile. The state of the memory element can be readily determined by sensing the conduction of the memory storage element by applying a voltage of about 0.5 volts.
虽然这种特定导电机构可能不适用于所有金属氧化物，但是作为整体，所述金属氧化物具有类似的行为：当施加适当电压时，发生从低导电状态到高导电状态的转变，并且这两种状态是非易失性的。其他材料的示例包括HfOx、ZrOx、WOx、NiOx、CoOx、CoalOx、MnOx、ZnMn2O4、ZnOx、TaOx、NbOx、HfSiOx、HfAlOx。适当的顶部电极包括具有与金属氧化物接触以便在触点处创建氧空缺的吸氧剂能力的具有高功函数(通常>4.5eV)的金属。一些示例是TaCN、TiCN、Ru、RuO、Pt、富Ti TiOx、TiAlN、TaAlN、TiSiN、TaSiN、IrO2。用于底部电极的适当材料为任何导电富氧材料，比如，Ti(O)N、Ta(O)N、TiN和TaN。电极的厚度通常为1nm或更大。金属氧化物的厚度通常在5nm到50nm范围内。While this particular mechanism of conduction may not apply to all metal oxides, as a whole, the metal oxides have similar behavior: when an appropriate voltage is applied, a transition from a low to a high conduction state occurs, and the two This state is non-volatile. Examples of other materials include HfOx, ZrOx, WOx, NiOx, CoOx, CoalOx, MnOx, ZnMn2O4, ZnOx, TaOx, NbOx, HfSiOx, HfAlOx. Suitable top electrodes include metals with high work function (typically >4.5eV) that have oxygen getter capabilities in contact with the metal oxide to create oxygen vacancies at the contact. Some examples are TaCN, TiCN, Ru, RuO, Pt, Ti-rich TiOx, TiAlN, TaAlN, TiSiN, TaSiN, IrO2. Suitable materials for the bottom electrode are any conductive oxygen-rich material such as Ti(O)N, Ta(O)N, TiN and TaN. The thickness of the electrodes is usually 1 nm or more. The thickness of the metal oxide is typically in the range of 5nm to 50nm.
适合存储器存储元件的另一类材料是固体电解质，但是由于它们在沉积时是导电的，所以需要形成单独的存储器元件并将其彼此隔离。固体电解质有点类似于金属氧化物，并且导电机构被假设为顶部电极与底部电极之间的金属长丝的构造。在此结构中，通过将来自一个电极(固体电解质)的离子溶化成单元的主体(可氧化电极)来形成长丝。在一个示例中，固体电解质包含银离子或铜离子，并且优选地，可氧化电极为嵌入到如Ax(MB2)1-x等过渡金属硫化物或硒化物材料中的金属，其中，A是Ag或Cu，B是S或Se，并且M是如Ta、V或Ti等过渡金属，并且x的范围为从约0.1到约0.7。这种组成使将不想要的材料氧化成固体电解质最小化。这种组成的一个示例是Agx(TaS2)1-x。替代性组成材料包括α-AgI。另一个电极(无关电极或中性电极)应当是良好的导电体，同时保持不溶于固体电解质材料。示例包括金属和化合物，比如，W、Ni、Mo、Pt、金属硅化物等。Another class of materials suitable for memory storage elements are solid electrolytes, but because they are conductive when deposited, individual memory elements need to be formed and isolated from each other. Solid electrolytes are somewhat similar to metal oxides, and the conduction mechanism is assumed to be a configuration of metal filaments between the top and bottom electrodes. In this structure, filaments are formed by melting ions from one electrode (solid electrolyte) into the bulk of the cell (oxidizable electrode). In one example, the solid electrolyte contains silver or copper ions, and preferably the oxidizable electrode is a metal embedded in a transition metal sulfide or selenide material such as Ax(MB2)1-x, where A is Ag or Cu, B is S or Se, and M is a transition metal such as Ta, V or Ti, and x ranges from about 0.1 to about 0.7. This composition minimizes oxidation of unwanted materials into the solid electrolyte. An example of such a composition is Agx(TaS2)1-x. Alternative constituent materials include α-AgI. The other electrode (the extraneous or neutral electrode) should be a good electrical conductor while remaining insoluble in the solid electrolyte material. Examples include metals and compounds such as W, Ni, Mo, Pt, metal silicides, and the like.
固体电解质材料的示例为TaO、GeSe或GeS。适合用作固体电解质单元的其他系统为：Cu/TaO/W、Ag/GeSe/W、Cu/GeSe/W、Cu/GeS/W和Ag/GeS/W，其中，第一种材料是可氧化电极，中间材料是固体电解质，并且第三种材料是无关(中性)电极。固体电解质的典型厚度在30nm与100nm之间。Examples of solid electrolyte materials are TaO, GeSe or GeS. Other systems suitable for use as solid electrolyte cells are: Cu/TaO/W, Ag/GeSe/W, Cu/GeSe/W, Cu/GeS/W and Ag/GeS/W, where the first material is oxidizable electrodes, the middle material is a solid electrolyte, and the third material is an irrelevant (neutral) electrode. Typical thicknesses for solid electrolytes are between 30 nm and 100 nm.
近年来，已经广泛地将碳作为非易失性存储器材料而进行研究。作为非易失性存储器元件，经常以两种形式使用碳：导电(或类石墨烯碳)和绝缘(或无定形碳)。这两种类型的碳材料的差异是碳化学键(所谓的sp2和sp3杂化)的内容。在sp3构型中，碳价电子保持在强共价键中，并且因此，sp3杂化是非导电的。sp3构型占主导的碳膜通常被称为四面体无定形碳或类金刚石。在sp2构型中，不是所有的碳价电子都保持在共价键中。弱紧电子(phi键)贡献导电，主要使sp2构型为导电碳材料。对碳阻式切换非易失性存储器的操作基于这样一种事实：有可能通过向碳结构施加适当的电流(或电压)脉冲来将sp3构型变换成sp2构型。例如，当在材料两端施加非常短(1至5ns)的高振幅电压脉冲时，导电性随着材料sp2变化成sp3形式(“重置”状态)而大大减小。已经推理的是，由这种脉冲生成的高局部温度引起材料无序，并且如果脉冲非常短，则碳“淬火”到无定形状态(sp3杂化)。另一方面，当处于重置状态下时，在更长时间(～300nsec)内施加更低电压使材料的一部分变成sp2形式(“设置”状态)。碳阻切换非易失性存储器元件具有像电容器的构型，其中，顶部电极和底部电极由高温熔点金属(如W、Pd、Pt和TaN)制成。In recent years, carbon has been extensively studied as a nonvolatile memory material. As non-volatile memory elements, carbon is often used in two forms: conductive (or graphene-like carbon) and insulating (or amorphous carbon). The difference between these two types of carbon materials is the content of the carbon chemical bonds (so-called sp2 and sp3 hybridization). In the sp3 configuration, the carbon valence electrons are held in strong covalent bonds, and therefore, sp3 hybridization is non-conductive. Carbon films with a dominant sp3 configuration are often referred to as tetrahedral amorphous carbon or diamond-like carbon. In the sp2 configuration, not all carbon valence electrons remain in covalent bonds. Weak tight electrons (phi bonds) contribute to conduction, mainly making the sp2 configuration a conductive carbon material. The operation of carbon resistive switching non-volatile memories is based on the fact that it is possible to switch the sp3 configuration to the sp2 configuration by applying appropriate current (or voltage) pulses to the carbon structure. For example, when very short (1 to 5 ns) high-amplitude voltage pulses are applied across the material, the conductivity is greatly reduced as the material changes from sp2 to sp3 form (the "reset" state). It has been theorized that the high local temperatures generated by such pulses induce disorder in the material, and if the pulses are very short, the carbon "quenches" to the amorphous state (sp3 hybridization). On the other hand, when in the reset state, applying a lower voltage for a longer time (~300nsec) causes a portion of the material to change to the sp2 form ("set" state). The carbon resistive switching nonvolatile memory element has a capacitor-like configuration in which top and bottom electrodes are made of high-temperature melting point metals such as W, Pd, Pt, and TaN.
最近已经显著地关注将碳纳米管(CNT)应用为非易失性存储器材料。(单壁)碳纳米管是由碳组成的中空圆柱体，通常为厚度为一个碳原子的轧制且自闭合的薄片，直径通常为1至2nm并且长度比其大几百倍。这种纳米管可以展示出非常高的导电性，并且已经作出了关于与集成电路制作的兼容性的各种提议。已经提出了将“短”CNT包封在惰性结合混合料内以便形成CNT的构造。可以使用旋涂或喷涂来将CNT沉积在硅晶片上，并且在应用时，CNT具有相对于彼此的随机取向。当在这种构造两端施加电场时，CNT倾向于自挠曲或自对准，从而使得构造的导电性改变。从低到高电阻以及相反情况的切换机构未被充分理解。像在其他基于碳的电阻式切换非易失性存储器中一样，基于CNT的存储器具有像电容器的构型，其中，顶部电极和底部电极由如以上所提及的高熔点金属等高熔点金属制成。Significant attention has recently been paid to the application of carbon nanotubes (CNTs) as non-volatile memory materials. (Single-walled) carbon nanotubes are hollow cylinders composed of carbon, typically rolled and self-closing sheets one carbon atom thick, typically 1 to 2 nm in diameter and several hundred times larger in length. Such nanotubes can exhibit very high electrical conductivity, and various proposals have been made regarding compatibility with integrated circuit fabrication. Encapsulation of "short" CNTs within an inert binding compound to form CNT configurations has been proposed. CNTs can be deposited on silicon wafers using spin coating or spray coating, and when applied, the CNTs have a random orientation relative to each other. When an electric field is applied across such a construct, the CNTs tend to self-flex, or self-align, so that the conductivity of the construct changes. The mechanism for switching from low to high resistance and vice versa is not well understood. As in other carbon-based resistive switching non-volatile memories, CNT-based memories have a capacitor-like configuration where the top and bottom electrodes are made of refractory metals such as those mentioned above to make.
适合用于存储器存储元件的仍另一类别的材料是相变材料。优选的相变材料组包括通常由组合GexSbyTez组成的硫属化合物玻璃，其中，优选地，x＝2，y＝2并且z＝5。还已经发现GeSb是有用的。其他材料包括AgInSbTe、GeTe、GaSb、BaSbTe、InSbTe以及这些基本元素的各种其他组合。厚度通常在1nm至500nm的范围内。对切换机构的普遍接受的解释是，当在非常短的时间内施加高能脉冲来使由所述材料组成的区域融化时，所述材料“淬火”到无定形状态(其是低导电状态)。当在更长时间内施加更低能脉冲，从而使得温度保持在结晶温度以上但是在融化温度以下时，材料结晶以便形成高导电性的多晶相。经常使用与加热器电极集成的亚光刻柱来制作这些设备。经常可以将经历相变的局部化区域设计成与阶跃边缘上的转变或者材料横跨在低热导率材料中蚀刻的槽的区域相对应。接触电极可以是厚度为从1nm到500nm的任何高熔点金属，比如，TiN、W、WN和TaN。Still another class of materials suitable for use in memory storage elements are phase change materials. A preferred group of phase change materials includes chalcogenide glasses generally consisting of the combination GexSbyTez, where, preferably, x=2, y=2 and z=5. GeSb has also been found to be useful. Other materials include AgInSbTe, GeTe, GaSb, BaSbTe, InSbTe, and various other combinations of these basic elements. The thickness is typically in the range of 1 nm to 500 nm. A generally accepted explanation for the switching mechanism is that the material is "quenched" to an amorphous state (which is a state of low conductivity) when a high energy pulse is applied for a very short period of time to melt a region comprised of the material. When a lower energy pulse is applied for a longer period of time such that the temperature remains above the crystallization temperature but below the melting temperature, the material crystallizes to form a highly conductive polycrystalline phase. These devices are often fabricated using sublithographic pillars integrated with heater electrodes. Often the localized region undergoing a phase transition can be designed to correspond to a transition on a step edge or a region where the material straddles a trench etched in a low thermal conductivity material. The contact electrode can be any refractory metal with a thickness from 1 nm to 500 nm, such as TiN, W, WN and TaN.
将指出的是，在大多数前述示例中的存储器材料利用其任一侧上的电极(其组成是经特别选择的)。在本文中的三维存储器阵列的实施例中(其中，字线(WL)和/或局部位线(LBL)同样通过与存储器材料的直接接触而形成这些电极)，那些线优选地由以上所描述的导电材料制成。在将附加导电段用于这两个存储器元件电极中的至少一个存储器元件电极的实施例中，那些段因此由以上所描述的用于存储器元件电极的材料制成。It will be noted that the memory material in most of the preceding examples utilizes electrodes on either side of it (the composition of which is specifically chosen). In the embodiment of the three-dimensional memory array herein (in which word lines (WL) and/or local bit lines (LBL) also form these electrodes by direct contact with the memory material), those lines are preferably formed by the above described made of conductive material. In embodiments where additional conductive segments are used for at least one of the two memory element electrodes, those segments are thus made of the materials described above for memory element electrodes.
操控元件通常结合到可控电阻型存储器存储元件中。操控元件可以是晶体管或二极管。尽管本文中所描述的三维架构的优点在于这种操控元件不是必要的，但是可以存在期望包括操控元件的特定构型。二极管可以是p-n结(不一定由硅组成)、金属/绝缘体/绝缘体/金属(MIIM)或肖特基型金属/半导体触点，但是替可替代地，可以是固体电解质元件。这种类型的二极管的特性是：对于存储器阵列中的正确操作，有必要在每个地址操作期间将其“接通”或“断开”。在寻址到存储器元件之前，二极管处于高电阻状态(“断开”状态)并且“保护”电阻式存储器元件免受干扰电压的影响。为了访问电阻式存储器元件，需要三项不同操作：a)将二极管从高电阻转换成低电阻；b)通过在二极管两端施加适当电压或施加通过二极管的电流来对存储器元件进行编程、读取或重置(擦除)；以及c)对二极管进行重置(擦除)。在一些实施例中，这些操作中的一项或多项操作可以组合到相同的步骤中。可以通过向包括二极管的存储器元件施加反向电压来实现对二极管进行重置，所述应用使二极管长丝崩溃并且使二极管返回到高电阻状态。Steering elements are often incorporated into controllable resistive memory storage elements. The control element can be a transistor or a diode. While an advantage of the three-dimensional architectures described herein is that such steering elements are not necessary, there may be certain configurations where it is desirable to include steering elements. The diodes may be p-n junctions (not necessarily composed of silicon), metal/insulator/insulator/metal (MIIM) or Schottky type metal/semiconductor contacts, but may alternatively be solid electrolyte elements. A characteristic of this type of diode is that for correct operation in a memory array it is necessary to turn it "on" or "off" during each address operation. Before the memory element is addressed, the diode is in a high resistance state ("off" state) and "protects" the resistive memory element from disturbing voltages. In order to access a resistive memory element, three distinct operations are required: a) switching the diode from high resistance to low resistance; or reset (erase); and c) reset (erase) the diode. In some embodiments, one or more of these operations may be combined into the same step. Resetting the diode can be accomplished by applying a reverse voltage to the memory element comprising the diode, which application collapses the diode filament and returns the diode to a high resistance state.
为了简单起见，以上描述已经考虑了将一个数据值存储在每个单元内的最简单情况：每个单元或者被重置或者被设置并且保持一位数据。然而，本申请的技术不限于此简单情况。通过使用接通(ON)电阻的各种值并且将读出放大器设计成能够在这种值中的许多值之间进行区别，不论什么存储器元件类型的每个存储器元件可以被配置成用于将多位数据保持在多级单元(MLC)中。For simplicity, the above description has considered the simplest case of storing one data value in each cell: each cell is either reset or set and holds one bit of data. However, the technique of the present application is not limited to this simple case. By using various values of the ON resistance and designing the sense amplifiers to be able to distinguish between many of these values, each memory element, regardless of the memory element type, can be configured to Multi-bit data is held in a multi-level cell (MLC).
图21A示出了包括在垂直方向上延伸的存储器串的ReRAM存储器的另一个视图，其中，可通过行选择线来分别选择这种串行。在图21B中示出了更详细的横截面，所述图展示了在延伸穿过多个交替的字线和电介质(在此示例中，SiO2)层的存储器孔中如何形成局部位线或垂直位线(VBL)。因为存储器孔被蚀刻穿过多个层，所以存储器孔的尺寸(以及因此垂直位线的尺寸)随着在衬底上方的高度而变化。此外，沿着存储器串的串联电阻随着在衬底上方的高度的增大而增大。图21B展示了这种安排中的层到层的串联电阻。在一些存储器中，沿着垂直位线的串联电阻可能超过存储器的某些部分的阈值。例如，在某个高度上方，串联电阻可能超过阈值。测试可以发现何时发生这种情况以及发生这种情况的程度，从而使得可以相应地调整操作参数。例如，在访问更高级的存储器元件时，可以使用更高位线电压。可以在可分别选择的部分内以及逐部分地作出调整，从而使得测试和调整不限于特定单元而可以根据在特定存储器中发现的变化而加以应用。FIG. 21A shows another view of a ReRAM memory comprising memory strings extending in the vertical direction, wherein such strings can be individually selected by row select lines. A more detailed cross-section is shown in FIG. 21B, which shows how local bitlines or vertical bit line (VBL). Because the memory hole is etched through multiple layers, the size of the memory hole (and thus the size of the vertical bit line) varies with height above the substrate. Furthermore, the series resistance along the memory string increases with increasing height above the substrate. Figure 21B demonstrates the layer-to-layer series resistance in this arrangement. In some memories, the series resistance along the vertical bit lines may exceed the threshold in some parts of the memory. For example, above a certain height, the series resistance may exceed a threshold. Testing can discover when and to what extent this occurs, allowing operating parameters to be adjusted accordingly. For example, higher bit line voltages may be used when accessing higher order memory elements. Adjustments can be made within individually selectable sections and on a section-by-section basis so that tests and adjustments are not limited to a particular unit but can be applied according to changes found in a particular memory.
可以存储适当的调整方案，其方式为使得每当访问存储器阵列的相应部分时，执行调整。例如，可以将电压偏移(与默认读取电压、写入电压、擦除电压等的偏移)存储在包括存储器阵列的不同部分的条目的表中。可以将这种表存储在非易失性存储器中，并且可以在需要时对其进行访问。在一些示例中，调整单元被定位在通过存储器总线而连接至一个或多个存储器裸片的存储器控制器中。一个或多个表可以记录要在访问块的处于不同存储器裸片中的不同部分时使用的电压偏移。可以将这种表记录在非易失性存储器中并且可以在需要时由存储器进行读取(例如，加载到RAM或其他容易访问的存储器中)。Appropriate alignment schemes may be stored in such a way that each time the corresponding portion of the memory array is accessed, the alignment is performed. For example, voltage offsets (offsets from default read voltages, write voltages, erase voltages, etc.) may be stored in a table that includes entries for different portions of the memory array. Such a table can be stored in non-volatile memory and accessed when needed. In some examples, the tuning unit is located in a memory controller connected to one or more memory dies by a memory bus. One or more tables may record voltage offsets to be used when accessing different portions of a block in different memory dies. Such a table can be recorded in non-volatile memory and can be read from memory (eg, loaded into RAM or other easily accessible memory) when needed.
除了修改用于访问存储器阵列的部分的电压以外，可以作出其他调整。例如，存储器的一些部分可以被标识为具有更高的数据丢失风险(例如，由于数据保留问题或其他问题)。当标识了这种部分时，可以作出某项调整以便减小丢失风险。例如，可以使用增强型冗余方案。通常，具有更多冗余的ECC方案允许纠正更大数量的错误并且因此提供更低数据丢失风险。然而，这种增强型冗余需要更多存储空间。在已知存储器阵列的不同部分的特性的情况下，可以在逐部分的基础上对冗余进行适配，从而使得基于给定部分中的风险而在所述部分中提供充足冗余。In addition to modifying the voltages used to access portions of the memory array, other adjustments can be made. For example, some portions of memory may be identified as having a higher risk of data loss (eg, due to data retention issues or other issues). When such parts are identified, some adjustment can be made to reduce the risk of loss. For example, an enhanced redundancy scheme can be used. In general, ECC schemes with more redundancy allow a greater number of errors to be corrected and thus provide a lower risk of data loss. However, this enhanced redundancy requires more storage space. Given the characteristics of the different sections of the memory array, redundancy can be adapted on a section-by-section basis such that sufficient redundancy is provided in a given section based on the risk in that section.
可以根据存储器阵列的包括如以上所描述的串联电阻的一部分的各种特性来作出调整。可以以静态方式来作出这种调整，从而使得一次性计算偏移并且然后在产品的寿命内使用所述偏移。可替代地，可以以动态方式来作出调整，从而使得在产品寿命期间根据需要而重新计算偏移。例如，可以基于时间、写入-擦除循环和/或其他因素以某些间隔更新偏移表。另外，可以根据环境因素或其他因素而作出调整。Adjustments may be made according to various characteristics of the memory array including a portion of the series resistance as described above. This adjustment can be made in a static manner, so that the offset is calculated once and then used over the life of the product. Alternatively, adjustments can be made in a dynamic manner such that the offset is recalculated as needed during the life of the product. For example, the offset table may be updated at certain intervals based on time, write-erase cycles, and/or other factors. Additionally, adjustments may be made for environmental or other factors.
在一个示例中，在对操作参数进行调整时，可以考虑温度。在一些存储器中，存储器特性随着温度而变化，并且可以相应地作出对操作参数的某项调整。例如，如果温度超过阈值，则可以使用不同操作参数(例如，读取电压、写入电压、擦除电压等)。可以对存储器阵列的所有部分一致地应用这种调整，其中，假设所有部分处于基本上相同的温度(例如，基于存储器裸片中、或存储器控制器裸片或其他裸片中的单次温度测量)。可替代地，多次温度测量可以允许针对存储器阵列的不同部分的不同温度调整。例如，不同存储器裸片可以具有提供它们对应裸片的温度的温度传感器。然后，可以在裸片基础上执行调整。In one example, temperature may be considered when making adjustments to operating parameters. In some memories, memory characteristics vary with temperature, and some adjustment to operating parameters may be made accordingly. For example, if the temperature exceeds a threshold, different operating parameters (eg, read voltage, write voltage, erase voltage, etc.) may be used. This adjustment can be applied consistently to all portions of the memory array, assuming all portions are at substantially the same temperature (e.g., based on a single temperature measurement in a memory die, or in a memory controller die, or other die). ). Alternatively, multiple temperature measurements may allow for different temperature adjustments for different portions of the memory array. For example, different memory dies may have temperature sensors that provide the temperature of their corresponding dies. Then, tuning can be performed on a die basis.
交叉点存储器cross point memory
虽然图21A和图21B的示例示出了在垂直位线与水平字线之间水平地延伸的存储器元件，但是可以使用其他安排。例如，在如图22A和图22B中所展示的交叉点安排中，字线和位线两者在不同水平上并且以不同取向水平地延伸。在图22A中所示出的示例中，字线沿着x方向延伸，而位线沿着y方向延伸。因此，字线和位线是正交的。字线和位线被安排交替的层中，从而使得给定字线层位于两个位线层之间，并且给定位线层位于两个字线层之间。存储器元件连接于字线与位线之间，从而使得单独的存储器元件位于特定字线与位线的交叉点处。因此，存储器元件形成于层中，单独的存储器元件层位于字线层与位线层之间。在此示例中，存储器元件垂直地延伸。存储器元件可以属于任何适当类型，例如，如之前所描述的电阻式存储器元件、相变元件、电荷存储元件、电荷俘获元件或其他适当的存储器元件。While the examples of FIGS. 21A and 21B show memory elements extending horizontally between vertical bit lines and horizontal word lines, other arrangements may be used. For example, in a cross-point arrangement as shown in Figures 22A and 22B, both word lines and bit lines extend horizontally on different levels and in different orientations. In the example shown in FIG. 22A, the word lines extend along the x direction, and the bit lines extend along the y direction. Therefore, word lines and bit lines are orthogonal. The wordlines and bitlines are arranged in alternating layers such that a given wordline layer is between two bitline layers and a given bitline layer is between two wordline layers. The memory elements are connected between the wordlines and the bitlines such that individual memory elements are located at the intersections of particular wordlines and bitlines. Thus, the memory elements are formed in layers, with a separate layer of memory elements located between the word line layer and the bit line layer. In this example, the memory elements extend vertically. The memory elements may be of any suitable type, for example, resistive memory elements as previously described, phase change elements, charge storage elements, charge trapping elements, or other suitable memory elements.
当向如图22A中所示出的安排等安排中的线施加电压时，沿着所述线存在某个电压降(在图22A中由“IR降”指示)。将理解的是，可以将等式：电压＝电流×电阻(V＝IR)应用于如字线或位线等导电线的部分，并且所有这种线具有导致根据距离(例如，离驱动器电路的距离)的电压降的某个电阻。因此，对于从驱动器电路中输出的给定电压，向存储器的部分施加的电压可能由于电压降而不一致。在一些示例中，可以对这种电压降进行测试并将其量化，例如，通过在访问存储器阵列的不同部分时测量串联电阻。如果电压降超过阈值，则可以应用一些补偿。例如，如果通过具有比阈值更大的串联电阻的线来访问存储器阵列的某些部分(例如，因为这些部分距离驱动器电路很远)，则这可以通过测试来确定(或者可以从基于设计几何结构进行的建模中找到)。作为响应，可以调整这种部分的操作参数。例如，可以相比于存储器阵列的通过具有低串联电阻的线连接的部分而增大存储器阵列的通过具有高串联电阻的线连接的部分的读取电压、写入电压和/或擦除电压。When a voltage is applied to a line in an arrangement such as that shown in Figure 22A, there is some voltage drop along the line (indicated by "IR drop" in Figure 22A). It will be appreciated that the equation: voltage=current×resistance (V=IR) can be applied to portions of conductive lines such as word lines or bit lines, and that all such lines have Some resistance of voltage drop over distance). Therefore, for a given voltage output from the driver circuit, the voltage applied to the portion of the memory may not be uniform due to the voltage drop. In some examples, this voltage drop can be tested and quantified, for example, by measuring series resistance while accessing different portions of the memory array. If the voltage drop exceeds a threshold, some compensation can be applied. For example, if some parts of the memory array are accessed through lines with a series resistance greater than the threshold (for example, because these parts are far from the driver circuit), this can be determined by testing (or can be determined from the found in the modeling performed). In response, operating parameters of such portions may be adjusted. For example, the read, write, and/or erase voltages of portions of the memory array connected by lines with high series resistance may be increased compared to portions of the memory array connected by lines with low series resistance.
可以记录不同部分的适当电压和/或其他操作参数。例如，可以将一个或多个偏移应用于不同部分，并且可以将偏移记录在表或其他记录结构中。如在先前示例中的，还可以根据如温度等环境因素来作出调整。可以根据对应部分的特性而将不同冗余应用于存储器元件的不同部分中的数据。Appropriate voltages and/or other operating parameters for the various sections may be recorded. For example, one or more offsets may be applied to different parts, and the offsets may be recorded in a table or other record structure. As in the previous example, adjustments may also be made based on environmental factors such as temperature. Different redundancies may be applied to data in different portions of a memory element according to the characteristics of the corresponding portions.
可以使用各种方法来对如以上所描述的存储器进行操作。图23展示了与图15中所展示的示例类似的示例，其中，向地址选择晶体管操作添加了步骤。在步骤301中，检查一个或多个选择晶体管的电流漂移(例如，通过测量存储器单元接通的情况下的电流以及所施加的已知电压)。作出关于电流漂移是否高于限制的确定。如果漂移未超过限制，则存储器被视为良好并且可以例如使用默认操作参数来继续进行正常操作305。如果漂移高于限制，则可以发起如之前关于图15而描述的存储器维护507。Various methods may be used to operate on the memory as described above. Figure 23 shows an example similar to that shown in Figure 15, with steps added to the address select transistor operation. In step 301, one or more select transistors are checked for current drift (eg, by measuring the current with the memory cell turned on and a known voltage applied). A determination is made as to whether the current drift is above a limit. If the drift has not exceeded the limit, the memory is considered good and normal operation can continue 305 , for example using default operating parameters. If the drift is above the limit, memory maintenance 507 as previously described with respect to FIG. 15 may be initiated.
结语epilogue
已经为了解释和说明的目的呈现了前述具体实施方式。其并不旨在穷举或限制所附权利要求书。鉴于以上教导，许多修改和变化都是可能的。The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the appended claims. Many modifications and variations are possible in light of the above teaching.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/276,635 | 2016-09-26 | ||
| US15/276,635US9691473B2 (en) | 2015-09-22 | 2016-09-26 | Adaptive operation of 3D memory |
| Publication Number | Publication Date |
|---|---|
| CN107871520Atrue CN107871520A (en) | 2018-04-03 |
| CN107871520B CN107871520B (en) | 2019-04-23 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710511496.2AActiveCN107871520B (en) | 2016-09-26 | 2017-06-28 | Adaptive operation of 3D memory |
| Country | Link |
|---|---|
| CN (1) | CN107871520B (en) |
| DE (1) | DE102017113967A1 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111540389A (en)* | 2018-12-26 | 2020-08-14 | 美光科技公司 | Write techniques for memory devices with charge transfer devices |
| CN112825252A (en)* | 2019-11-21 | 2021-05-21 | 爱思开海力士有限公司 | Memory device and operation method thereof |
| CN113169160A (en)* | 2019-10-31 | 2021-07-23 | 桑迪士克科技有限责任公司 | Methods of forming three-dimensional memory devices and driver circuits on opposite sides of a substrate |
| CN113179666A (en)* | 2019-06-28 | 2021-07-27 | 桑迪士克科技有限责任公司 | Ferroelectric memory device including word lines and channel gates and method of forming the same |
| CN114063906A (en)* | 2021-10-15 | 2022-02-18 | 北京得瑞领新科技有限公司 | Management method and device for physical blocks in NAND flash memory and SSD (solid State disk) equipment |
| TWI763343B (en)* | 2020-07-30 | 2022-05-01 | 台灣積體電路製造股份有限公司 | Memory device and method of fabricating the same |
| CN115132700A (en)* | 2021-03-26 | 2022-09-30 | 南亚科技股份有限公司 | Disposable programmable memory array and preparation method thereof |
| US11716856B2 (en) | 2021-03-05 | 2023-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
| US11985825B2 (en) | 2020-06-25 | 2024-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | 3D memory array contact structures |
| US12040006B2 (en) | 2020-06-26 | 2024-07-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array including dummy regions |
| US12087621B2 (en) | 2020-06-26 | 2024-09-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Air gaps in memory array structures |
| US12225731B2 (en) | 2020-06-25 | 2025-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array contact structures |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290802A (en)* | 2007-03-29 | 2008-10-22 | 弗拉什西利康股份有限公司 | Self-adaptive and self-calibrating multi-stage non-volatile memory |
| US20090285022A1 (en)* | 2008-05-14 | 2009-11-19 | Samsung Electronics Co., Ltd. | Memory programming method |
| CN101673580A (en)* | 2008-07-09 | 2010-03-17 | 三星电子株式会社 | Methods of detecting a shift in the threshold voltage for a nonvolatile memory cell |
| CN101677020A (en)* | 2008-09-19 | 2010-03-24 | 三星电子株式会社 | Flash memory device and systems and reading methods thereof |
| US9401216B1 (en)* | 2015-09-22 | 2016-07-26 | Sandisk Technologies Llc | Adaptive operation of 3D NAND memory |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290802A (en)* | 2007-03-29 | 2008-10-22 | 弗拉什西利康股份有限公司 | Self-adaptive and self-calibrating multi-stage non-volatile memory |
| US20090285022A1 (en)* | 2008-05-14 | 2009-11-19 | Samsung Electronics Co., Ltd. | Memory programming method |
| CN101673580A (en)* | 2008-07-09 | 2010-03-17 | 三星电子株式会社 | Methods of detecting a shift in the threshold voltage for a nonvolatile memory cell |
| CN101677020A (en)* | 2008-09-19 | 2010-03-24 | 三星电子株式会社 | Flash memory device and systems and reading methods thereof |
| US9401216B1 (en)* | 2015-09-22 | 2016-07-26 | Sandisk Technologies Llc | Adaptive operation of 3D NAND memory |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111540389A (en)* | 2018-12-26 | 2020-08-14 | 美光科技公司 | Write techniques for memory devices with charge transfer devices |
| CN113179666A (en)* | 2019-06-28 | 2021-07-27 | 桑迪士克科技有限责任公司 | Ferroelectric memory device including word lines and channel gates and method of forming the same |
| CN113169160B (en)* | 2019-10-31 | 2024-08-02 | 桑迪士克科技有限责任公司 | Method for forming device structure |
| CN113169160A (en)* | 2019-10-31 | 2021-07-23 | 桑迪士克科技有限责任公司 | Methods of forming three-dimensional memory devices and driver circuits on opposite sides of a substrate |
| CN112825252B (en)* | 2019-11-21 | 2024-01-26 | 爱思开海力士有限公司 | Memory device and method of operating the same |
| CN112825252A (en)* | 2019-11-21 | 2021-05-21 | 爱思开海力士有限公司 | Memory device and operation method thereof |
| US12225731B2 (en) | 2020-06-25 | 2025-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array contact structures |
| US11985825B2 (en) | 2020-06-25 | 2024-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | 3D memory array contact structures |
| US12087621B2 (en) | 2020-06-26 | 2024-09-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Air gaps in memory array structures |
| US12040006B2 (en) | 2020-06-26 | 2024-07-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array including dummy regions |
| TWI763343B (en)* | 2020-07-30 | 2022-05-01 | 台灣積體電路製造股份有限公司 | Memory device and method of fabricating the same |
| US12167608B2 (en) | 2020-07-30 | 2024-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming three-dimensional memory devices |
| US11495618B2 (en) | 2020-07-30 | 2022-11-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
| US12022659B2 (en) | 2020-07-30 | 2024-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
| US11716856B2 (en) | 2021-03-05 | 2023-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
| US12256550B2 (en) | 2021-03-05 | 2025-03-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
| CN115132700A (en)* | 2021-03-26 | 2022-09-30 | 南亚科技股份有限公司 | Disposable programmable memory array and preparation method thereof |
| CN114063906A (en)* | 2021-10-15 | 2022-02-18 | 北京得瑞领新科技有限公司 | Management method and device for physical blocks in NAND flash memory and SSD (solid State disk) equipment |
| Publication number | Publication date |
|---|---|
| CN107871520B (en) | 2019-04-23 |
| DE102017113967A1 (en) | 2018-03-29 |
| Publication | Publication Date | Title |
|---|---|---|
| US9691473B2 (en) | Adaptive operation of 3D memory | |
| CN107871520A (en) | The adaptive operation of 3D memories | |
| US11101326B2 (en) | Methods of forming a phase change memory with vertical cross-point structure | |
| US9922716B2 (en) | Architecture for CMOS under array | |
| US20200335144A1 (en) | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory | |
| US10026782B2 (en) | Implementation of VMCO area switching cell to VBL architecture | |
| US9136468B2 (en) | Nonvolatile semiconductor memory device | |
| CN109427969B (en) | Phase change memory electrodes with multiple thermal interfaces | |
| TWI523008B (en) | Nonvolatile semiconductor memory device including variable resistance element | |
| US9672917B1 (en) | Stacked vertical memory array architectures, systems and methods | |
| CN107924704B (en) | Adaptive operation of 3D NAND memory | |
| US20140353573A1 (en) | Methods and systems to reduce location-based variations in switching characteristics of 3d reram arrays | |
| CN113228321A (en) | Threshold switch for memory | |
| US9411669B2 (en) | Selective sampling of data stored in nonvolatile memory | |
| TW201702880A (en) | Multichip dual write | |
| US8918577B1 (en) | Three dimensional nonvolatile memory with variable block capacity | |
| US10026478B1 (en) | Biasing scheme for multi-layer cross-point ReRAM | |
| US20160232983A1 (en) | Adaptive Data Shaping in Nonvolatile Memory | |
| US12219889B2 (en) | Semiconductor storage device | |
| CN108431978A (en) | Monolithic 3D memory array formed using sacrificial polysilicon pillars | |
| US8995168B2 (en) | Semiconductor storage device |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | Effective date of registration:20250314 Address after:U.S.A. Patentee after:SANDISK TECHNOLOGIES Inc. Country or region after:U.S.A. Address before:texas Patentee before:SANDISK TECHNOLOGIES LLC Country or region before:U.S.A. | |
| TR01 | Transfer of patent right |