技术领域technical field
本发明涉及计算机存储技术领域，特别是涉及一种SSD启动控制设备以及方法。The present invention relates to the technical field of computer storage, in particular to an SSD startup control device and method.
背景技术Background technique
固态硬盘(Solid State Drives，SSD)是用固态电子存储芯片阵列而制成的硬盘，由控制单元和存储单元(FLASH芯片、DRAM芯片)组成。固态硬盘具有传统机械硬盘不具备的快速读写、质量轻、能耗低以及体积小等特点。Solid State Drives (SSD) are hard disks made of solid-state electronic storage chip arrays, consisting of a control unit and a storage unit (FLASH chip, DRAM chip). Solid-state drives have the characteristics of fast reading and writing, light weight, low energy consumption, and small size that traditional mechanical hard drives do not have.
NVMe标准是为SSD建立的新的存储规范标准，NVMe标准使SSD支持PCIe总线进行数据交互，并支持SMBus总线或I2C总线作为带外管理接口。The NVMe standard is a new storage specification standard established for SSDs. The NVMe standard enables SSDs to support PCIe bus for data interaction, and supports SMBus bus or I2C bus as an out-of-band management interface.
影响SSD启动时间的因素包括SSD电源建立时间、主控启动代码(BootLoader)加载时间及系统初始化时间。由于电源技术的发展，SSD电源建立时间已经缩短到毫秒级，而且随着主控、存储介质芯片的时钟频率不断提高，系统初始化时间也已经大幅缩短，因此，主控芯片启动代码加载时间已经成了制约SSD启动速度的主要因素。主控芯片的启动代码通常存储在EEPROM或NorFLASH等非易失性存储芯片中，电源建立之后，主控芯片通过串行总线(通常为SPI总线或I2C总线)从存储芯片中读取启动代码，SSD的功能越丰富，则启动代码的代码量越大，在串行总线的时钟频率一定的情况下，启动代码的加载时间越长，由于目前EEPROM或NorFLASH存储芯片支持的串行总线时钟频率一般只有几M到几十M，远低于主控芯片的时钟频率，因此启动代码的加载时间可能长达数秒甚至数十秒。Factors that affect SSD boot time include SSD power build-up time, master boot code (BootLoader) loading time, and system initialization time. Due to the development of power technology, the establishment time of SSD power supply has been shortened to the millisecond level, and with the continuous increase of the clock frequency of the main control and storage medium chips, the system initialization time has also been greatly shortened. Therefore, the time for loading the startup code of the main control chip has become This is the main factor restricting the boot speed of SSD. The startup code of the main control chip is usually stored in non-volatile memory chips such as EEPROM or NorFLASH. After the power supply is established, the main control chip reads the startup code from the storage chip through a serial bus (usually SPI bus or I2C bus). The richer the functions of the SSD, the larger the code volume of the startup code. When the clock frequency of the serial bus is constant, the loading time of the startup code is longer. Because the clock frequency of the serial bus supported by the current EEPROM or NorFLASH memory chip is generally Only a few M to tens of M, far lower than the clock frequency of the main control chip, so the loading time of the startup code may be as long as several seconds or even tens of seconds.
因此，如何降低SSD的启动时间是本领域技术人员亟待解决的技术问题。Therefore, how to reduce the startup time of SSD is a technical problem to be solved urgently by those skilled in the art.
发明内容Contents of the invention
本发明的目的是提供一种SSD启动控制设备及方法，以解决现有SSD启动时间较长的问题。The purpose of the present invention is to provide an SSD startup control device and method to solve the problem of long startup time of existing SSDs.
为解决上述技术问题，本发明提供一种SSD启动控制设备，包括：In order to solve the above technical problems, the present invention provides a SSD startup control device, including:
主控芯片、CPLD芯片以及多个存储芯片；Main control chip, CPLD chip and multiple memory chips;
其中，所述主控芯片与所述CPLD芯片相连，所述CPLD芯片分别与多个所述存储芯片相连；Wherein, the main control chip is connected to the CPLD chip, and the CPLD chip is connected to a plurality of the storage chips respectively;
在写入启动代码时，所述主控芯片将启动代码发送至所述CPLD芯片，所述CPLD芯片将接收到的数据分为与所述存储芯片数量相同的多个部分，并且将各个部分并行写入至多个所述存储芯片；在读取启动代码时，所述CPLD芯片并行从多个所述存储芯片中读取启动代码，并将读取到的数据发送至所述主控芯片，以实现SSD的启动。When writing the startup code, the main control chip sends the startup code to the CPLD chip, and the CPLD chip divides the received data into a plurality of parts equal to the number of the memory chips, and divides each part in parallel Write to a plurality of said storage chips; when reading the startup code, the CPLD chip reads the startup code from a plurality of the storage chips in parallel, and sends the read data to the main control chip to Realize the booting of SSD.
可选地，所述存储芯片为两片，所述CPLD芯片将所述启动代码分为两个部分，将奇数字节的数据写入到第一存储芯片，将偶数字节的数据写入到第二存储芯片。Optionally, there are two memory chips, and the CPLD chip divides the startup code into two parts, writes the data of odd bytes into the first memory chip, and writes the data of even bytes into the second memory chip.
可选地，所述主控芯片通过第一串行总线与所述CPLD芯片连接。Optionally, the main control chip is connected to the CPLD chip through a first serial bus.
可选地，所述第一串行总线为SMBus总线或I2C总线。Optionally, the first serial bus is an SMBus bus or an I2C bus.
可选地，所述CPLD芯片通过第二串行总线分别与多个所述存储芯片连接。Optionally, the CPLD chip is respectively connected to a plurality of the storage chips through a second serial bus.
可选地，所述第二串行总线为SPI总线或I2C总线。Optionally, the second serial bus is an SPI bus or an I2C bus.
可选地，所述CPLD芯片与所述主控芯片之间的串行总线时钟频率为所述CPLD芯片与所述存储芯片之间的串行总线时钟频率的两倍以上。Optionally, the clock frequency of the serial bus between the CPLD chip and the main control chip is more than twice the clock frequency of the serial bus between the CPLD chip and the memory chip.
本发明还提供了一种SSD启动控制方法，包括：The present invention also provides a SSD startup control method, including:
在写入启动代码时，主控芯片将启动代码发送至CPLD芯片，所述CPLD芯片将接收到的数据分为与存储芯片数量相同的多个部分，并且将各个部分并行写入至多个所述存储芯片；When writing the startup code, the main control chip sends the startup code to the CPLD chip, and the CPLD chip divides the received data into a plurality of parts with the same number as the memory chip, and writes each part to multiple said CPLD chips in parallel. memory chip;
在读取启动代码时，所述CPLD芯片并行从多个所述存储芯片中读取启动代码，并将读取到的数据发送至所述主控芯片，以实现SSD的启动。When reading the startup code, the CPLD chip reads the startup code from a plurality of the storage chips in parallel, and sends the read data to the main control chip, so as to realize the startup of the SSD.
可选地，所述CPLD芯片将接收到的数据分为与存储芯片数量相同的多个部分，并且将各个部分并行写入至多个所述存储芯片包括：Optionally, the CPLD chip divides the received data into a plurality of parts equal to the number of memory chips, and writing each part in parallel to a plurality of the memory chips includes:
所述存储芯片为两片，所述CPLD芯片将所述启动代码分为两个部分，将奇数字节的数据写入到第一存储芯片，将偶数字节的数据写入到第二存储芯片。The memory chip is two pieces, and the CPLD chip divides the startup code into two parts, writes the data of odd number bytes into the first memory chip, and writes the data of even number bytes into the second memory chip .
本发明所提供的SSD启动控制设备，包括：主控芯片、CPLD芯片以及多个存储芯片；其中，主控芯片与CPLD芯片相连，CPLD芯片分别与多个存储芯片相连；在写入启动代码时，主控芯片将启动代码发送至CPLD芯片，CPLD芯片将接收到的数据分为与存储芯片数量相同的多个部分，并且将各个部分并行写入至多个存储芯片；在读取启动代码时，CPLD芯片并行从多个存储芯片中读取启动代码，并将读取到的数据发送至主控芯片，以实现SSD的启动。本申请利用CPLD内部模块并行工作的特性以及CPLD与主控芯片时钟频率远高于存储芯片的特点，减少了主控芯片读取启动代码所需的时间，从而大幅降低了SSD的启动时间。此外，本申请还提供了一种具有上述技术优点的SSD启动控制方法。The SSD startup control device provided by the present invention comprises: a main control chip, a CPLD chip and a plurality of storage chips; wherein, the main control chip is connected with the CPLD chip, and the CPLD chip is connected with a plurality of storage chips respectively; when writing the startup code , the main control chip sends the startup code to the CPLD chip, and the CPLD chip divides the received data into multiple parts with the same number as the storage chips, and writes each part to multiple storage chips in parallel; when reading the startup code, The CPLD chip reads the startup codes from multiple memory chips in parallel, and sends the read data to the main control chip to realize the startup of the SSD. This application utilizes the parallel working characteristics of the internal modules of the CPLD and the fact that the clock frequency of the CPLD and the main control chip is much higher than that of the memory chip, thereby reducing the time required for the main control chip to read the startup code, thereby greatly reducing the startup time of the SSD. In addition, the present application also provides an SSD start-up control method with the above-mentioned technical advantages.
附图说明Description of drawings
为了更清楚的说明本发明实施例或现有技术的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为本发明所提供的SSD启动控制设备的一种具体实施方式的结构框图；Fig. 1 is the structural block diagram of a kind of embodiment of SSD startup control device provided by the present invention;
图2为本发明所提供的SSD启动控制设备的另一种具体实施方式的结构框图；Fig. 2 is the structural block diagram of another embodiment of the SSD start-up control device provided by the present invention;
图3为本发明实施例提供的SSD启动控制方法的流程图。FIG. 3 is a flow chart of a method for controlling startup of an SSD provided by an embodiment of the present invention.
具体实施方式Detailed ways
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明所提供的SSD启动控制设备的一种具体实施方式的结构框图如图1所示，该设备包括：A structural block diagram of a specific embodiment of the SSD startup control device provided by the present invention is shown in Figure 1, and the device includes:
主控芯片1、CPLD芯片2以及多个存储芯片3；Main control chip 1, CPLD chip 2 and multiple memory chips 3;
其中，所述主控芯片1与所述CPLD芯片2相连，所述CPLD芯片2分别与多个所述存储芯片3相连；Wherein, the main control chip 1 is connected to the CPLD chip 2, and the CPLD chip 2 is connected to a plurality of the storage chips 3 respectively;
在写入启动代码时，所述主控芯片1将启动代码发送至所述CPLD芯片2，所述CPLD芯片2将接收到的数据分为与所述存储芯片3数量相同的多个部分，并且将各个部分并行写入至多个所述存储芯片3；在读取启动代码时，所述CPLD芯片2并行从多个所述存储芯片3中读取启动代码，并将读取到的数据发送至所述主控芯片1，以实现SSD的启动。When writing the startup code, the main control chip 1 sends the startup code to the CPLD chip 2, and the CPLD chip 2 divides the received data into a plurality of parts equal to the number of the memory chips 3, and Each part is written in parallel to a plurality of said storage chips 3; when reading the startup code, said CPLD chip 2 reads the startup code from a plurality of said storage chips 3 in parallel, and sends the read data to The main control chip 1 is used to start the SSD.
需要指出的是，本申请实施例中存储芯片可以为多个，不限于其数量。作为一种具体实施方式，可以使用两片存储芯片来存储系统启动代码。It should be pointed out that there may be multiple memory chips in the embodiment of the present application, and the number is not limited. As a specific implementation manner, two memory chips can be used to store system startup codes.
本申请采用CPLD芯片作为SSD的带外管理芯片，并作为启动代码存储芯片与主控芯片之间数据传输的中转。In this application, the CPLD chip is used as the out-of-band management chip of the SSD, and as a transfer of data transmission between the startup code storage chip and the main control chip.
进一步地，可以为CPLD芯片对主控和存储芯片各配置一个串行通信总线接口，与主控通信的串行总线接口时钟频率为与存储芯片通信时钟频率的两倍。Further, a serial communication bus interface can be configured for the CPLD chip to the main control and the storage chip respectively, and the clock frequency of the serial bus interface communicating with the main control is twice the clock frequency of the communication with the storage chip.
本发明所提供的SSD启动控制设备，包括：主控芯片、CPLD芯片以及多个存储芯片；其中，主控芯片与CPLD芯片相连，CPLD芯片分别与多个存储芯片相连；在写入启动代码时，主控芯片将启动代码发送至CPLD芯片，CPLD芯片将接收到的数据分为与存储芯片数量相同的多个部分，并且将各个部分并行写入至多个存储芯片；在读取启动代码时，CPLD芯片并行从多个存储芯片中读取启动代码，并将读取到的数据发送至主控芯片，以实现SSD的启动。本申请利用CPLD内部模块并行工作的特性以及CPLD与主控芯片时钟频率远高于存储芯片的特点，减少了主控芯片读取启动代码所需的时间，从而大幅降低了SSD的启动时间。The SSD startup control device provided by the present invention comprises: a main control chip, a CPLD chip and a plurality of storage chips; wherein, the main control chip is connected with the CPLD chip, and the CPLD chip is connected with a plurality of storage chips respectively; when writing the startup code , the main control chip sends the startup code to the CPLD chip, and the CPLD chip divides the received data into multiple parts with the same number as the storage chips, and writes each part to multiple storage chips in parallel; when reading the startup code, The CPLD chip reads the startup codes from multiple memory chips in parallel, and sends the read data to the main control chip to realize the startup of the SSD. This application utilizes the parallel working characteristics of the internal modules of the CPLD and the fact that the clock frequency of the CPLD and the main control chip is much higher than that of the memory chip, thereby reducing the time required for the main control chip to read the startup code, thereby greatly reducing the startup time of the SSD.
作为一种具体实施方式，本申请中存储芯片可以具体为两片。CPLD芯片将所述启动代码分为两个部分，将奇数字节的数据写入到第一存储芯片，将偶数字节的数据写入到第二存储芯片。As a specific implementation manner, in this application, there may be specifically two memory chips. The CPLD chip divides the startup code into two parts, writes odd-numbered byte data into the first memory chip, and writes even-numbered byte data into the second memory chip.
主控芯片通过第一串行总线与所述CPLD芯片连接。主控芯片通过第一串行总线与所述CPLD芯片连接。CPLD芯片通过第二串行总线分别与多个所述存储芯片连接。所述第二串行总线为SPI总线或I2C总线。The main control chip is connected with the CPLD chip through the first serial bus. The main control chip is connected with the CPLD chip through the first serial bus. The CPLD chip is respectively connected to the multiple storage chips through the second serial bus. The second serial bus is an SPI bus or an I2C bus.
如图2本发明所提供的SSD启动控制设备的另一种具体实施方式的结构框图所示，本实施例将启动代码分为两部分分别存储到两片存储芯片中，选取的存储芯片容量可降低至原所需容量的50％，带外管理芯片选用一片CPLD芯片，除带外管理芯片通常所进行的VPD信息存储、SSD运行状态监测，以及通过SMBus总线或I2C总线与HOST(主机)进行交互等功能外，另外配置两路串行总线接口(SPI总线或I2C总线，与存储芯片串行接口保持一致)分别连接到两片存储芯片，另外配置一路串行总线接口连接到主控芯片。CPLD芯片与主控芯片之间的串行总线时钟频率可配置为CPLD芯片与存储芯片之间的串行总线时钟频率的两倍以上。As shown in the structural block diagram of another specific embodiment of the SSD startup control device provided by the present invention in Fig. 2, the startup code is divided into two parts in this embodiment and stored in two memory chips respectively, and the capacity of the selected memory chips can be Reduced to 50% of the original required capacity, a CPLD chip is selected for the out-of-band management chip, except for VPD information storage, SSD operation status monitoring, and HOST (host) through the SMBus bus or I2C bus. In addition to functions such as interaction, two serial bus interfaces (SPI bus or I2C bus, consistent with the serial interface of the memory chip) are configured to connect to two memory chips respectively, and another serial bus interface is configured to connect to the main control chip. The clock frequency of the serial bus between the CPLD chip and the main control chip can be configured to be more than twice the clock frequency of the serial bus between the CPLD chip and the memory chip.
在将启动代码写入存储芯片中时，主控芯片通过串行总线将代码发送至CPLD芯片，CPLD芯片通过串行总线将代码分别同时写入两片存储芯片，在写入的过程中，将奇数字节的数据写入第一存储芯片，将偶数字节的数据写入第二存储芯片。在主控芯片读取启动代码的过程中，CPLD芯片同时从第一存储芯片及第二存储芯片中通过串行总线读取数据，并将读取到的数据通过串行总线发送至主控，发送的过程中，从第一存储芯片中读取的数据在前，从第二存储芯片中读取的数据在后，与代码写入时的顺序保持一致。When writing the startup code into the memory chip, the main control chip sends the code to the CPLD chip through the serial bus, and the CPLD chip writes the code into the two memory chips at the same time through the serial bus. During the writing process, the The odd-numbered bytes of data are written into the first memory chip, and the even-numbered bytes of data are written into the second memory chip. In the process of the main control chip reading the startup code, the CPLD chip simultaneously reads data from the first storage chip and the second storage chip through the serial bus, and sends the read data to the main control through the serial bus, During the sending process, the data read from the first memory chip comes first, and the data read from the second memory chip follows, which is consistent with the order when the code is written.
下面对本发明实施例提供的SSD启动控制方法进行介绍，下文描述的SSD启动控制方法与上文描述的SSD启动控制设备可相互对应参照。The following is an introduction to the SSD startup control method provided by the embodiment of the present invention. The SSD startup control method described below and the SSD startup control device described above can be referred to in correspondence.
图3为本发明实施例提供的SSD启动控制方法的流程图，参照图3SSD启动控制方法可以包括：FIG. 3 is a flow chart of the SSD startup control method provided by the embodiment of the present invention. Referring to FIG. 3, the SSD startup control method may include:
步骤S101：在写入启动代码时，主控芯片将启动代码发送至CPLD芯片，所述CPLD芯片将接收到的数据分为与存储芯片数量相同的多个部分，并且将各个部分并行写入至多个所述存储芯片；Step S101: When writing the startup code, the main control chip sends the startup code to the CPLD chip, and the CPLD chip divides the received data into a plurality of parts equal to the number of memory chips, and writes each part in parallel at most a said memory chip;
步骤S102：在读取启动代码时，所述CPLD芯片并行从多个所述存储芯片中读取启动代码，并将读取到的数据发送至所述主控芯片，以实现SSD的启动。Step S102: When reading the boot code, the CPLD chip reads the boot code from multiple memory chips in parallel, and sends the read data to the main control chip, so as to start the SSD.
可选地，所述CPLD芯片将接收到的数据分为与存储芯片数量相同的多个部分，并且将各个部分并行写入至多个所述存储芯片包括：Optionally, the CPLD chip divides the received data into a plurality of parts equal to the number of memory chips, and writing each part in parallel to a plurality of the memory chips includes:
所述存储芯片为两片，所述CPLD芯片将所述启动代码分为两个部分，将奇数字节的数据写入到第一存储芯片，将偶数字节的数据写入到第二存储芯片。The memory chip is two pieces, and the CPLD chip divides the startup code into two parts, writes the data of odd number bytes into the first memory chip, and writes the data of even number bytes into the second memory chip .
本实施例的SSD启动控制方法用于前述的SSD启动控制设备，因此SSD启动控制方法中的具体实施方式可见前文中的SSD启动控制设备的实施例部分，所以，其具体实施方式可以参照相应的各个部分实施例的描述，在此不再赘述。The SSD startup control method of this embodiment is used in the aforementioned SSD startup control device, so the specific implementation manner in the SSD startup control method can be seen in the embodiment part of the SSD startup control device above, so its specific implementation method can refer to the corresponding The description of each partial embodiment will not be repeated here.
本发明所提供的SSD启动控制方法，在写入启动代码时，主控芯片将启动代码发送至CPLD芯片，CPLD芯片将接收到的数据分为与存储芯片数量相同的多个部分，并且将各个部分并行写入至多个存储芯片；在读取启动代码时，CPLD芯片并行从多个存储芯片中读取启动代码，并将读取到的数据发送至主控芯片，以实现SSD的启动。本申请利用CPLD内部模块并行工作的特性以及CPLD与主控芯片时钟频率远高于存储芯片的特点，减少了主控芯片读取启动代码所需的时间，从而大幅降低了SSD的启动时间。In the SSD start-up control method provided by the present invention, when writing the start-up code, the main control chip sends the start-up code to the CPLD chip, and the CPLD chip divides the received data into a plurality of parts with the same number as the storage chips, and divides each Part of it is written to multiple memory chips in parallel; when reading the boot code, the CPLD chip reads the boot code from multiple memory chips in parallel, and sends the read data to the main control chip to start the SSD. This application utilizes the parallel working characteristics of the internal modules of the CPLD and the fact that the clock frequency of the CPLD and the main control chip is much higher than that of the memory chip, thereby reducing the time required for the main control chip to read the startup code, thereby greatly reducing the startup time of the SSD.
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for the related part, please refer to the description of the method part.
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。Professionals can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the possible For interchangeability, in the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.
结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be directly implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known storage medium.
以上对本发明所提供的SSD启动控制设备以及方法进行了详细介绍。本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以对本发明进行若干改进和修饰，这些改进和修饰也落入本发明权利要求的保护范围内。The SSD startup control device and method provided by the present invention have been introduced in detail above. In this paper, specific examples are used to illustrate the principle and implementation of the present invention, and the descriptions of the above embodiments are only used to help understand the method and core idea of the present invention. It should be pointed out that for those skilled in the art, without departing from the principle of the present invention, some improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.
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|---|---|---|---|
| CN201711260942.3ACN107861775A (en) | 2017-12-04 | 2017-12-04 | A kind of SSD starts control device and method |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711260942.3ACN107861775A (en) | 2017-12-04 | 2017-12-04 | A kind of SSD starts control device and method |
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| CN201711260942.3APendingCN107861775A (en) | 2017-12-04 | 2017-12-04 | A kind of SSD starts control device and method |
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