技术领域technical field
本发明涉及半导体器件及其制造领域，特别涉及一种3D NAND器件及其制造方法。The invention relates to the field of semiconductor devices and manufacturing thereof, in particular to a 3D NAND device and a manufacturing method thereof.
背景技术Background technique
NAND闪存是一种比硬盘驱动器更好的存储设备，随着人们追求功耗低、质量轻和性能佳的非易失存储产品，在电子产品中得到了广泛的应用。目前，平面结构的NAND闪存已近实际扩展的极限，为了进一步的提高存储容量，降低每比特的存储成本，提出了3D结构的NAND存储器件。NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar structure NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D structure NAND memory device is proposed.
在3D NAND存储器件结构中，采用垂直堆叠多层存储单元的方式，实现堆叠式的立体存储器件。在制造3D NAND存储器件时，首先形成绝缘层和牺牲层交替层叠的堆叠层，并通过多次光刻及刻蚀工艺，在堆叠层的侧面形成阶梯形貌，使得堆叠层具有中央区域和阶梯区域；而后，在中央区域中形成沟道孔(Channel hole)，沟道孔用于形成存储层；在沟道孔中形成存储层之后，将堆叠层中的氮化硅层替换为金属层，每一层的金属层为每一层存储单元的控制栅，堆叠层阶梯区域的每一层台阶用于形成每一层控制栅的接触塞。In the 3D NAND memory device structure, a stacked three-dimensional memory device is realized by vertically stacking multi-layer memory cells. When manufacturing 3D NAND storage devices, first form a stack layer in which insulating layers and sacrificial layers are stacked alternately, and through multiple photolithography and etching processes, a stepped shape is formed on the side of the stack layer, so that the stack layer has a central area and a step region; then, form a channel hole (Channel hole) in the central region, and the channel hole is used to form a storage layer; after forming the storage layer in the channel hole, replace the silicon nitride layer in the stacked layer with a metal layer, The metal layer of each layer is the control gate of each layer of memory cells, and the steps of each layer in the step region of the stacked layers are used to form contact plugs of the control gates of each layer.
在该制造工艺中，在台阶区域上形成接触塞，而随着堆叠层数的不断增加，需要经过更多道光刻和刻蚀工艺形成阶梯形貌，使得制造成本大大提高，同时，阶梯数量越多，所需形成的堆叠层的面积也越大，不利于提高存储器件的集成度，此外，堆叠层数越多，晶圆的翘曲程度加剧，形成接触塞时与阶梯区域中台阶面的对准会更困难，影响器件的性能，不利于晶圆良率的提升。In this manufacturing process, contact plugs are formed on the step area, and as the number of stacked layers continues to increase, more photolithography and etching processes are required to form a step shape, which greatly increases the manufacturing cost. At the same time, the number of steps The more, the larger the area of the stacked layers that need to be formed, which is not conducive to improving the integration of the memory device. In addition, the more the number of stacked layers, the greater the warpage of the wafer, and the formation of the contact plug and the step surface in the stepped area. The alignment will be more difficult, which will affect the performance of the device and is not conducive to the improvement of wafer yield.
发明内容Contents of the invention
有鉴于此，本发明的目的在于提供一种3D NAND器件及其制造方法，降低了刻蚀成本，减小了器件面积，促进了器件集成度，提高了晶圆良率。In view of this, the object of the present invention is to provide a 3D NAND device and a manufacturing method thereof, which reduce etching costs, reduce device area, promote device integration, and improve wafer yield.
为实现上述目的，本申请提供了一种3D NAND存储器件的制造方法，该方法包括：In order to achieve the above purpose, the application provides a method for manufacturing a 3D NAND storage device, the method comprising:
提供衬底；provide the substrate;
在所述衬底上形成牺牲层与绝缘层交替层叠的堆叠层，所述堆叠层具有第一区域和第二区域，所述第一区域的堆叠层中形成有沟道孔以及沟道孔中的存储层；A stacked layer in which sacrificial layers and insulating layers are alternately stacked is formed on the substrate, the stacked layer has a first region and a second region, channel holes and channel holes are formed in the stacked layer in the first region storage layer;
在所述堆叠层上形成覆盖层，所述第二区域的覆盖层中形成有不同孔径的刻蚀孔；forming a cover layer on the stacked layer, and etching holes with different apertures are formed in the cover layer of the second region;
以所述刻蚀孔之外的覆盖层为遮挡，进行所述堆叠层的刻蚀，以在所述刻蚀孔下形成接触孔，不同的接触孔停止于不同层的牺牲层，孔径越大的刻蚀孔下的接触孔具有更深的孔深；Using the cover layer outside the etching hole as a shield, the stacked layer is etched to form a contact hole under the etching hole. Different contact holes stop at different layers of sacrificial layers, and the larger the hole diameter The contact hole under the etched hole has a deeper hole depth;
在所述接触孔的侧壁上形成接触绝缘层，并进行填充，形成接触塞。A contact insulating layer is formed on the sidewall of the contact hole and filled to form a contact plug.
可选地，孔径越大的刻蚀孔具有更深的孔深；则，所述进行所述堆叠层的刻蚀的步骤中，还包括：同时进行所述覆盖层的刻蚀。Optionally, the etching hole with a larger pore diameter has a deeper hole depth; then, the step of etching the stacked layers further includes: simultaneously etching the covering layer.
可选地，在形成覆盖层与进行所述堆叠层的刻蚀的步骤之间，还包括：Optionally, between the steps of forming the covering layer and etching the stacked layers, further comprising:
沉积阻挡控制层，孔径越小的刻蚀孔中的阻挡控制层具有更大的厚度；则，所述进行所述堆叠层的刻蚀的步骤中，还包括：同时进行所述阻挡控制层的刻蚀。Depositing a barrier control layer, the barrier control layer in the etching hole with a smaller aperture has a greater thickness; then, in the step of etching the stacked layers, it also includes: simultaneously performing the etching of the barrier control layer etch.
可选地，所述堆叠层为矩形堆叠，所述第一区域中的沟道孔呈阵列排布，所述第二区域位于所述第一区域的旁侧。Optionally, the stacked layer is a rectangular stack, the channel holes in the first region are arranged in an array, and the second region is located beside the first region.
可选地，所述第二区域中的刻蚀孔与其旁侧的沟道孔的排布方向一致。Optionally, the etching holes in the second region are arranged in the same direction as the channel holes beside them.
可选地，在形成接触孔之后，还包括：Optionally, after forming the contact hole, further comprising:
在所述接触孔的内壁上形成绝缘阻挡层；forming an insulating barrier layer on the inner wall of the contact hole;
利用栅线缝隙将所述牺牲层替换为金属层；则，The sacrificial layer is replaced by a metal layer by using a gate line gap; then,
在所述接触孔的侧壁上形成接触绝缘层，包括：forming a contact insulating layer on the sidewall of the contact hole, comprising:
去除所述接触孔底部的绝缘阻挡层，以所述绝缘阻挡层作为接触绝缘层。The insulating barrier layer at the bottom of the contact hole is removed, and the insulating barrier layer is used as a contact insulating layer.
本申请实施例还提供了一种3D NAND存储器件，该器件包括：The embodiment of the present application also provides a 3D NAND storage device, which includes:
衬底；Substrate;
所述衬底上的金属层与绝缘层交替层叠的堆叠层，所述堆叠层具有第一区域和第二区域，所述第一区域的堆叠层中形成有沟道孔以及沟道孔中的存储层；The metal layer and the insulating layer on the substrate are stacked alternately, the stack layer has a first region and a second region, and the stack layer in the first region is formed with a channel hole and a hole in the channel hole. storage layer;
所述第二区域的堆叠层中的接触孔，不同的接触孔具有不同的孔径且孔径越大的接触孔设置于更下层的金属层上；For the contact holes in the stacked layers in the second region, different contact holes have different apertures and the contact holes with larger apertures are disposed on the lower metal layer;
接触孔侧壁上的接触绝缘层以及接触孔中的接触塞。A contact insulating layer on the sidewall of the contact hole and a contact plug in the contact hole.
可选地，所述堆叠层为矩形堆叠，所述第一区域中的沟道孔呈阵列排布，所述第二区域位于所述第一区域的旁侧。Optionally, the stacked layer is a rectangular stack, the channel holes in the first region are arranged in an array, and the second region is located beside the first region.
可选地，所述第二区域中的接触孔与其旁侧的沟道孔的排布方向一致。Optionally, the arrangement direction of the contact holes in the second region is the same as that of the channel holes beside them.
本发明实施例提供的3D NAND存储器件的制造方法，通过在衬底上形成牺牲层与绝缘层交替堆叠的堆叠层，该堆叠层的第一区域中形成有沟道孔以及沟道孔中的存储层，在堆叠层上形成覆盖层，其中第二区域的覆盖层中形成有不同孔径的刻蚀孔，以覆盖层为遮挡，进行堆叠层的刻蚀，以在刻蚀孔下形成接触孔，不同的接触孔停止于不同层的牺牲层。由于在刻蚀过程中，刻蚀孔孔径越大，其下的堆叠层的刻蚀速率越大，使得越大刻蚀孔下的接触孔能够具有更深的孔深，实现了不同深度的接触孔的刻蚀，从而，形成对应于不同牺牲层的接触孔。对于具有较多层堆叠层的存储器件，避免了刻蚀多层台阶导致的制备工艺复杂和较高成本，降低了器件所需要的面积，提高了晶圆的良率。In the method for manufacturing a 3D NAND storage device provided by an embodiment of the present invention, a stacked layer in which sacrificial layers and insulating layers are alternately stacked is formed on a substrate, and a channel hole is formed in the first region of the stacked layer, and a channel hole in the channel hole is formed. A storage layer, forming a covering layer on the stacked layer, wherein etching holes with different apertures are formed in the covering layer of the second region, and the covering layer is used as a shield to etch the stacked layer to form a contact hole under the etching hole , different contact holes stop at different sacrificial layers. During the etching process, the larger the aperture of the etching hole, the greater the etching rate of the underlying stacked layer, so that the contact hole under the larger etching hole can have a deeper hole depth, and contact holes of different depths are realized. Etching, thereby forming contact holes corresponding to different sacrificial layers. For storage devices with multiple stacked layers, the complex manufacturing process and high cost caused by etching multi-layer steps are avoided, the area required for the device is reduced, and the yield rate of the wafer is improved.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1a和1b示出了现有技术提供的形成的3D NAND存储器件的侧向剖面图和俯视图；Figures 1a and 1b show a side sectional view and a top view of a 3D NAND storage device formed by the prior art;
图2示出了本申请实施例提供的一种3D NAND存储器件的制作方法流程图；Fig. 2 shows a flow chart of a manufacturing method of a 3D NAND storage device provided by an embodiment of the present application;
图3a-3h示出了根据本申请实施例的制造方法形成3D NAND存储器件过程中的器件剖面结构示意图；3a-3h show schematic diagrams of device cross-sectional structures in the process of forming a 3D NAND storage device according to a manufacturing method according to an embodiment of the present application;
图4示出了本申请实施例中的刻蚀孔的俯视示意图；Figure 4 shows a schematic top view of the etching hole in the embodiment of the present application;
图5示出了本申请实施例提供的另一种3D NAND存储器件的制作方法流程图；FIG. 5 shows a flow chart of another method for manufacturing a 3D NAND storage device provided by an embodiment of the present application;
图6a-6j示出了根据本申请另一实施例的制造方法形成3D NAND存储器件过程中的器件剖面结构示意图。6a-6j are diagrams illustrating a cross-sectional structure of a 3D NAND memory device during formation of a manufacturing method according to another embodiment of the present application.
具体实施方式detailed description
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.
如图1a所示，为现有技术方法形成的3D NAND垂直堆叠层存储单元中阶梯区域的侧向剖面示意图，通过将堆叠层中的氮化硅层(图未示出)替换为金属层101，形成每一层存储单元的控制栅，水平金属控制栅层101通过独立垂直金属连线102与字线103相连，其中，垂直金属连线102之间通过绝缘层(图未示出)隔开。As shown in Figure 1a, it is a schematic side cross-sectional view of the step region in the 3D NAND vertically stacked layer memory cell formed by the prior art method, by replacing the silicon nitride layer (not shown) in the stacked layer with a metal layer 101 , forming the control gate of each layer of memory cells, the horizontal metal control gate layer 101 is connected to the word line 103 through an independent vertical metal connection line 102, wherein the vertical metal connection lines 102 are separated by an insulating layer (not shown in the figure) .
如图1b所示，为现有技术方法形成的3D NAND垂直堆叠层存储单元的俯视图，左边的部分为阶梯区域104，虚线表示呈台阶结构的金属栅，水平金属栅层通过独立垂直金属连线102与字线103相连。右侧为存储区域105，其中形成有沟道孔106的阵列。在以上形成垂直堆叠层存储单元的方法中，金属栅层101为台阶状，随着堆叠层数的不断增加，制作成本也大大提高，形成堆叠层的面积也大大增加。As shown in Figure 1b, it is a top view of a 3D NAND vertically stacked layer memory cell formed by a prior art method, the left part is a step region 104, the dotted line represents a metal gate with a step structure, and the horizontal metal gate layer is connected through independent vertical metal lines 102 is connected to word line 103 . On the right is a storage area 105 in which an array of channel holes 106 is formed. In the above method for forming a vertically stacked layer memory cell, the metal gate layer 101 is stepped. As the number of stacked layers increases, the manufacturing cost is also greatly increased, and the area for forming the stacked layers is also greatly increased.
为了解决上述问题，本申请提供了一种3D NAND存储器件的制造方法，如图2所示为本申请实施例一种3D NAND存储器件的制造方法流程图，以下将结合流程图和附图3a-3h对具体的实施例进行详细的说明，为了更好地体现本方案，附图3a-3h仅示出了3D NAND存储器件的接触区域的剖面结构示意图，存储区域即本申请描述中的第一区域，接触区域也即本申请描述中的第二区域。In order to solve the above problems, the present application provides a method for manufacturing a 3D NAND storage device, as shown in FIG. 2 is a flow chart of a method for manufacturing a 3D NAND storage device according to an embodiment of the present application. The following will combine the flow chart and accompanying drawing 3a -3h is a detailed description of the specific embodiment. In order to better reflect this solution, the accompanying drawings 3a-3h only show a schematic cross-sectional structure diagram of the contact area of the 3D NAND storage device. The storage area is the first in the description of this application. One area, the contact area is also the second area in the description of this application.
步骤S201，提供衬底201，参考图3a所示。Step S201, providing a substrate 201, as shown in FIG. 3a.
在本申请实施例中，衬底201为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅，Silicon On Insulator)或GOI(绝缘体上锗，Germanium OnInsulator)等。在其他实施例中，所述半导体衬底还可以为包括其他元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以为其他外延结构，例如SGOI(绝缘体上锗硅)等。在本实施例中，所述衬底201为体硅衬底，用于支撑在其上的器件结构。In the embodiment of the present application, the substrate 201 is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator, Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator) Wait. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc. In this embodiment, the substrate 201 is a bulk silicon substrate for supporting device structures thereon.
步骤S202，在衬底201上形成牺牲层203与绝缘层202交替层叠的堆叠层，参考图4所示，所述堆叠层具有第一区域105和第二区域303，所述第一区域105的堆叠层中形成有沟道孔106以及沟道孔中的存储层(图未示出)。Step S202, forming a stacked layer in which sacrificial layers 203 and insulating layers 202 are alternately stacked on the substrate 201, as shown in FIG. A channel hole 106 and a storage layer (not shown) in the channel hole are formed in the stacked layer.
该步骤中，绝缘层202可以是氧化硅，牺牲层203可以是氮化硅，将氮化硅层和氧化硅层交替层叠来形成堆叠层，根据垂直方向所需形成的存储单元的个数来确定堆叠层的层数，堆叠层的层数例如可以为8层、32层、64层等，层数越多，越能提高集成度。可以采用化学气相沉积、原子层沉积或其他合适的沉积方法，依次交替沉积氮化硅和氧化硅，形成该堆叠层。In this step, the insulating layer 202 can be silicon oxide, and the sacrificial layer 203 can be silicon nitride, and the silicon nitride layer and the silicon oxide layer are stacked alternately to form a stacked layer, depending on the number of memory cells to be formed in the vertical direction. The number of stacked layers is determined. The number of stacked layers can be, for example, 8 layers, 32 layers, 64 layers, etc. The more the number of layers, the more the degree of integration can be improved. The stacked layers can be formed by sequentially and alternately depositing silicon nitride and silicon oxide by chemical vapor deposition, atomic layer deposition or other suitable deposition methods.
可以通过在堆叠层上旋涂光刻胶层，通过曝光显影等步骤形成图案化的光刻胶层，即在第二区域的光刻胶层中形成通孔的阵列，以该图案化的光刻胶层为掩蔽，通过对堆叠层的刻蚀形成暴露衬底的沟道孔106，参考图4所示。A patterned photoresist layer can be formed by spin-coating a photoresist layer on the stacked layer, exposure and development, etc., that is, an array of through holes is formed in the photoresist layer in the second region, and the patterned photoresist layer The resist layer is a mask, and the channel hole 106 exposing the substrate is formed by etching the stacked layers, as shown in FIG. 4 .
在沟道孔106形成之后，进行光刻胶层的去除和沟道孔106中存储层的形成，存储层包括电荷捕获层和沟道层，电荷捕获层例如可以为ONO结构，即氧化物、氮化物和氧化物的叠层，沟道层例如可以为多晶硅层，在具体的应用中，依次在沟道孔侧壁上形成ONO的电荷捕获层以及多晶硅的沟道层，而后在沟道孔中形成填充层，填充层可以为氧化硅。After the channel hole 106 is formed, the removal of the photoresist layer and the formation of the storage layer in the channel hole 106 are carried out. The storage layer includes a charge trapping layer and a channel layer. The charge trapping layer can be, for example, an ONO structure, that is, oxide, A stack of nitrides and oxides, the channel layer can be a polysilicon layer, for example, in a specific application, the charge trapping layer of ONO and the channel layer of polysilicon are formed on the sidewall of the channel hole in turn, and then the channel layer is formed on the sidewall of the channel hole A filling layer is formed in the middle, and the filling layer may be silicon oxide.
步骤S203，在所述堆叠层上形成覆盖层204，所述第二区域的覆盖层204中形成有不同孔径的刻蚀孔207。Step S203 , forming a covering layer 204 on the stacked layers, and etching holes 207 with different diameters are formed in the covering layer 204 in the second region.
覆盖层204是后续刻蚀形成接触孔时的掩膜层，是接触孔之外区域的保护层，可以根据具体的需要来选择覆盖层204的材料和厚度。在一些实施例中，覆盖层204可以是对堆叠层具有高选择比的材料形成，覆盖层204例如可以是多晶硅薄膜，其中的刻蚀孔207可以是暴露堆叠层的通孔。在本申请其他实施例中，覆盖层204也可以是其他硬掩膜材料。由于覆盖层204对堆叠层具有高选择比，因此在之后进行堆叠层的刻蚀时不会被刻蚀，且由于刻蚀孔207的孔径大小不同，越大孔径下的堆叠层的刻蚀速率越大，从而可以形成不同深度的接触孔208(参考图3d)。The cover layer 204 is a mask layer for subsequent etching to form a contact hole, and is a protective layer for areas outside the contact hole. The material and thickness of the cover layer 204 can be selected according to specific needs. In some embodiments, the covering layer 204 may be formed of a material with a high selectivity to the stacked layers. The covering layer 204 may be, for example, a polysilicon film, and the etching hole 207 therein may be a through hole exposing the stacked layers. In other embodiments of the present application, the cover layer 204 may also be other hard mask materials. Since the cover layer 204 has a high selectivity to the stacked layer, it will not be etched when the stacked layer is etched afterwards, and because the aperture size of the etching hole 207 is different, the etching rate of the stacked layer under the larger aperture The larger the , the contact holes 208 with different depths can be formed (refer to FIG. 3d ).
在另一些实施例中，覆盖层204可以为对堆叠层具有低选择比的材料，也就是在刻蚀堆叠层时，覆盖层204也会被刻蚀掉一部分，覆盖层204例如可以为无定型碳或氧化硅等，在对堆叠层进行刻蚀时，覆盖层204的厚度也在降低，因此覆盖层204的厚度需要具有合适的厚度，或者在覆盖层204下设置其他的阻挡层，避免堆叠层被过刻蚀。在该实施例中，刻蚀孔207可以是暴露堆叠层的通孔，更优地，也可以是由一定深度但未穿透该覆盖层204的孔，且孔径越大的刻蚀孔具有更深的孔深，也就是孔径越小的刻蚀孔207下保留的覆盖层204的厚度越大。由于刻蚀孔207的孔径大小不同，越大孔径下的堆叠层的刻蚀速率越大，同时，越小的刻蚀孔207下的保留的覆盖层204越厚，这样，使得越小的刻蚀孔207下的堆叠层的刻蚀开始时间越晚，便于进行刻蚀速率的控制，形成不同孔深的接触孔208。In other embodiments, the covering layer 204 can be a material with a low selectivity to the stacked layers, that is, when the stacked layers are etched, a part of the covering layer 204 will also be etched away, and the covering layer 204 can be, for example, an amorphous Carbon or silicon oxide, etc., when the stacked layer is etched, the thickness of the cover layer 204 is also reduced, so the thickness of the cover layer 204 needs to have an appropriate thickness, or other barrier layers are set under the cover layer 204 to avoid stacking layer is over-etched. In this embodiment, the etching hole 207 can be a through hole exposing the stacked layer, more preferably, it can also be a hole with a certain depth but does not penetrate the cover layer 204, and the etching hole with a larger diameter has a deeper The hole depth is smaller, that is, the thickness of the covering layer 204 remaining under the etching hole 207 is larger when the hole diameter is smaller. Due to the different aperture sizes of the etching holes 207, the etching rate of the stacked layer under the larger aperture is larger, and at the same time, the remaining cover layer 204 under the smaller etching holes 207 is thicker, so that the smaller etching holes The later the etching start time of the stacked layer under the etching hole 207 is, the easier it is to control the etching rate, and form contact holes 208 with different hole depths.
在具体的实施例中，如图3a所示，首先，可以在第二区域的堆叠层上沉积覆盖层204，并在覆盖层204上旋涂光刻胶层205，而后，形成图案化的光刻胶层205，图案化的光刻胶层205中形成有具有不同的孔径的通孔206；而后，参考图3b所示，以光刻胶层205作为掩膜进行刻蚀，在覆盖层上形成不同孔径的刻蚀孔207，再去除光刻胶205，如图3c所示。覆盖层的刻蚀方式可以是各向异性的干法刻蚀，由于光刻胶层205中通孔206的孔径大小不同，从而，越大孔径的通孔206下的覆盖层具有更快的刻蚀速率，从而，形成了深度不同的刻蚀孔207，各向异性刻蚀中形成的刻蚀孔的上部直径通常大于底部直径。In a specific embodiment, as shown in FIG. 3a, first, a cover layer 204 can be deposited on the stacked layers in the second region, and a photoresist layer 205 is spin-coated on the cover layer 204, and then, a patterned photoresist layer 205 can be formed. Resist layer 205, patterned photoresist layer 205 is formed with through holes 206 with different apertures; then, as shown in FIG. Etching holes 207 with different apertures are formed, and then the photoresist 205 is removed, as shown in FIG. 3c. The etching method of the covering layer can be anisotropic dry etching. Since the aperture sizes of the through holes 206 in the photoresist layer 205 are different, the covering layer under the through holes 206 with larger apertures has a faster etching speed. Therefore, etching holes 207 with different depths are formed, and the upper diameter of the etching holes formed in anisotropic etching is usually larger than the bottom diameter.
在矩形堆叠的堆叠层中，通常第一区域105的沟道孔106呈阵列排布，阵列排布的方式可以为行列对齐排布，如图4所示，也可以是错行排布，也就是一行的沟道孔形成在前一行的两个沟道孔间的位置处，有利于提高沟道孔的集成密度。在本发明实施例中，第二区域303可以位于第一区域105的旁侧，例如旁侧的一边，也可以是旁侧的多边，第二区域303中的刻蚀孔304可以与其旁侧的沟道孔106的排布方向一致，这样，可以有效地减小接触孔区域的面积，从而降低整个存储器的面积。In the rectangular stacked stacked layers, usually the channel holes 106 in the first region 105 are arranged in an array, and the array arrangement can be aligned in rows and columns, as shown in FIG. 4 , or arranged in staggered rows, or That is, the channel holes of one row are formed at the positions between the two channel holes of the previous row, which is beneficial to increase the integration density of the channel holes. In the embodiment of the present invention, the second region 303 can be located on the side of the first region 105, such as one side of the side, or it can be multiple sides of the side, and the etching hole 304 in the second region 303 can be The channel holes 106 are arranged in the same direction, so that the area of the contact hole region can be effectively reduced, thereby reducing the area of the entire memory.
如图4所示为本申请一种可能的实施方式，在第二区域105中的刻蚀孔106呈阵列分布，第二区域303位于第一区域的旁侧，且各个刻蚀孔304可的排布方向可与第一区域105中的沟道孔106的排布方向一致。因此，在第一区域的旁侧，第二区域的面积只需容纳多个成排的刻蚀孔即可，例如对于32层的堆叠层来说，本申请实施例中的第二区域的面积只需容纳32个刻蚀孔，相对于现有技术中需要的32个金属栅台阶来说，节省了堆叠层的面积，降低了成本。As shown in Figure 4, it is a possible implementation of the present application, the etching holes 106 in the second area 105 are distributed in an array, the second area 303 is located on the side of the first area, and each etching hole 304 can be The arrangement direction may be consistent with the arrangement direction of the channel holes 106 in the first region 105 . Therefore, on the side of the first region, the area of the second region only needs to accommodate multiple rows of etching holes. For example, for a stacked layer of 32 layers, the area of the second region in the embodiment of the present application Only 32 etching holes need to be accommodated, which saves the area of the stacked layers and reduces the cost compared with the 32 metal gate steps required in the prior art.
步骤S204，以刻蚀孔207之外的覆盖层204为遮挡，进行堆叠层的刻蚀，以在刻蚀孔207下形成接触孔208，不同的接触孔208停止于不同层的牺牲层203，孔径越大的刻蚀孔207下的接触孔208具有更深的孔深，参考图3d所示。Step S204, using the cover layer 204 outside the etching hole 207 as a shield, etch the stacked layers to form a contact hole 208 under the etching hole 207, and different contact holes 208 stop at different sacrificial layers 203, The contact hole 208 under the etching hole 207 with a larger hole diameter has a deeper hole depth, as shown in FIG. 3d.
对堆叠层的刻蚀，可以是各向异性的干法刻蚀，例如可以为RIE(反应离子刻蚀)，如图3d所示，刻蚀孔207下的堆叠层被刻蚀形成接触孔208。不同孔径的刻蚀孔207，由于其对刻蚀速率的影响，形成接触孔208的深度也不同，对于孔径较大的刻蚀孔207下的接触孔208，因为刻蚀速率较大，因此形成的接触孔208具有更深的孔深。The etching of the stacked layer may be anisotropic dry etching, such as RIE (Reactive Ion Etching), as shown in FIG. 3d, the stacked layer under the etching hole 207 is etched to form a contact hole 208 . Etched holes 207 with different apertures have different depths of contact holes 208 due to their influence on the etching rate. For the contact holes 208 under the etched holes 207 with larger apertures, because the etching rate is larger, the contact holes 208 are formed. The contact hole 208 has a deeper hole depth.
在对堆叠层的刻蚀过程中，对于对堆叠层具有高选择比的材料形成的覆盖层204，其厚度变化很小。对于对堆叠层具有低选择比的材料形成的覆盖层204，在刻蚀的过程中，该覆盖层204也逐渐被刻蚀，其厚度不断减少，因此在覆盖层204形成时，应考虑到刻蚀造成的覆盖层204损耗，初始形成的厚度可以大于在刻蚀过程中形成的损耗厚度，或者在覆盖层下增加阻挡层。During the etching process of the stacked layers, for the capping layer 204 formed of a material having a high selectivity ratio to the stacked layers, its thickness changes little. For the cover layer 204 formed of a material with a low selectivity ratio to the stacked layers, the cover layer 204 is also gradually etched during the etching process, and its thickness is continuously reduced. Therefore, when the cover layer 204 is formed, consideration should be given to etching Due to the loss of the covering layer 204 caused by etching, the initial formed thickness may be greater than the loss thickness formed during the etching process, or a barrier layer may be added under the covering layer.
由于形成的刻蚀孔207的孔径大小不一样，或者，进一步地，刻蚀孔207下的覆盖层204的保留的厚度也不一样，而孔径越大，在刻蚀过程中，其他的被刻蚀层的刻蚀速率将越快，保留的覆盖层204也会延迟对被刻蚀的堆叠层的刻蚀，通过这些控制，同时还可以结合具体刻蚀工艺的控制，刻蚀之后，孔径越大的刻蚀孔207下的接触孔208具有更深的孔深，并停止在不同的牺牲层203上。Due to the different aperture sizes of the formed etching holes 207, or further, the remaining thickness of the cover layer 204 under the etching holes 207 is also different, and the larger the aperture, the other are etched in the etching process. The faster the etching rate of the etching layer will be, the remaining cover layer 204 will also delay the etching of the etched stacked layer. Through these controls, it can also be combined with the control of the specific etching process. After etching, the aperture will be faster The contact hole 208 under the large etched hole 207 has a deeper hole depth and stops on a different sacrificial layer 203 .
在步骤S205，在接触孔208的侧壁上形成接触绝缘层211，并进行填充，形成接触塞212，参考图3g和3h。In step S205, a contact insulating layer 211 is formed on the sidewall of the contact hole 208 and filled to form a contact plug 212, referring to FIGS. 3g and 3h.
该接触绝缘层211为绝缘材料，例如可以为氧化硅或氮氧化硅等，其作为形成接触塞211后与其他金属层的隔离层。可以通过沉积接触绝缘层材料，而后进行刻蚀去除接触孔底部的接触绝缘层材料来形成。而后，在接触孔中填充金属材料，例如W，从而形成接触塞212。The contact insulating layer 211 is an insulating material, such as silicon oxide or silicon oxynitride, which serves as an isolation layer from other metal layers after the contact plug 211 is formed. It can be formed by depositing a contact insulating layer material, and then performing etching to remove the contact insulating layer material at the bottom of the contact hole. Then, a metal material, such as W, is filled in the contact hole to form a contact plug 212 .
在本发明优选的实施例中，该接触塞212在进行牺牲层203的替换之后进行，易于实现，且利于提高工艺的集成度。In a preferred embodiment of the present invention, the contact plug 212 is performed after the sacrificial layer 203 is replaced, which is easy to implement and is beneficial to improve the integration of the process.
具体的，在步骤S204之后，可以进行如下步骤：Specifically, after step S204, the following steps may be performed:
步骤S2051，在接触孔208的内壁上形成绝缘阻挡层209。In step S2051 , an insulating barrier layer 209 is formed on the inner wall of the contact hole 208 .
步骤S2052，利用栅线缝隙将牺牲层203替换为金属层210。Step S2052 , replacing the sacrificial layer 203 with the metal layer 210 by using the gate line gap.
步骤S2053，去除接触孔208底部的绝缘阻挡层，以所述绝缘阻挡层作为接触绝缘层，并在所述接触孔中形成接触塞。Step S2053 , removing the insulating barrier layer at the bottom of the contact hole 208 , using the insulating barrier layer as a contact insulating layer, and forming a contact plug in the contact hole.
如图3e所示，在接触孔侧壁形成绝缘阻挡层209。该绝缘阻挡层209在将牺牲层203替换为金属层210的工艺中，起到保持接触形貌的目的。需要说明的是，接触绝缘层211为绝缘材料，其作为形成接触塞212后与其他金属层的隔离层。作为一种优选的实施方式，绝缘阻挡层209是一种绝缘材料，例如可以为氧化硅或氮氧化硅等，即可实现形成接触塞后与其他金属层的隔离的目的，因此可以将接触孔底部的绝缘阻挡层去除，作为接触绝缘层212，从而简化制备工艺。在本申请其他实施例中，上述两种薄膜也可以由不同材料形成。As shown in FIG. 3e, an insulating barrier layer 209 is formed on the sidewall of the contact hole. The insulating barrier layer 209 serves the purpose of maintaining the contact shape during the process of replacing the sacrificial layer 203 with the metal layer 210 . It should be noted that the contact insulating layer 211 is an insulating material, which serves as an isolation layer from other metal layers after the contact plug 212 is formed. As a preferred embodiment, the insulating barrier layer 209 is an insulating material, such as silicon oxide or silicon oxynitride, which can achieve the purpose of isolation from other metal layers after the contact plug is formed, so the contact hole can be The insulating barrier layer at the bottom is removed to serve as the contact insulating layer 212, thereby simplifying the manufacturing process. In other embodiments of the present application, the above two thin films may also be formed of different materials.
在具体的实施例中，可以采用原子层沉积的方法形成氧化硅的绝缘阻挡层209，参见图3e所示，接触孔的内壁上形成有绝缘阻挡层209。In a specific embodiment, the insulating barrier layer 209 of silicon oxide may be formed by atomic layer deposition, as shown in FIG. 3 e , the insulating barrier layer 209 is formed on the inner wall of the contact hole.
而后，通过栅线缝隙(图未示出)去除所述堆叠层中的氮化硅层203，并形成替代氮化硅的金属层210。通常地，先形成栅线缝隙，而后，选择对氮化硅和氧化硅的高选择比的酸液，通过酸液进入栅线缝隙，将氮化硅层203去除，酸液例如可以为磷酸(H3PO4)。去除氮化硅203之后，填充入金属层210，金属层210可以为钨(W)。金属层210的填充可以使用气相沉积法实现，再通过对金属进行回刻去除多余的部分金属，形成金属层210，参考图3f。Then, the silicon nitride layer 203 in the stacked layers is removed through gate line gaps (not shown), and a metal layer 210 replacing silicon nitride is formed. Usually, the gate line gap is formed first, and then, an acid solution with a high selectivity ratio to silicon nitride and silicon oxide is selected, and the acid solution enters the gate line gap to remove the silicon nitride layer 203. The acid solution may be, for example, phosphoric acid ( H3 PO4 ). After the silicon nitride 203 is removed, the metal layer 210 is filled in, and the metal layer 210 may be tungsten (W). The filling of the metal layer 210 can be achieved by vapor deposition, and then the excess metal is removed by etching back the metal to form the metal layer 210 , as shown in FIG. 3 f .
之后，需要将接触孔底部绝缘阻挡层去除，形成接触绝缘层211，以便后续进行接触塞212的形成。如图3g所示，通过各向异性的干法刻蚀去除绝缘阻挡层209位于接触孔底部的部分。如图3h所示，在接触孔中形成接触塞211，接触塞211可以是用于连接字线103和金属层210的金属导体，例如可以是钨。Afterwards, the insulating barrier layer at the bottom of the contact hole needs to be removed to form a contact insulating layer 211 for subsequent formation of the contact plug 212 . As shown in FIG. 3g, the portion of the insulating barrier layer 209 at the bottom of the contact hole is removed by anisotropic dry etching. As shown in FIG. 3 h , a contact plug 211 is formed in the contact hole. The contact plug 211 may be a metal conductor for connecting the word line 103 and the metal layer 210 , such as tungsten.
本发明实施例提供的3D NAND存储器件的制造方法，通过在衬底上形成牺牲层与绝缘层交替堆叠的堆叠层，该堆叠层的第一区域中形成有沟道孔以及沟道孔中的存储层，在堆叠层上形成覆盖层，其中第二区域的覆盖层中形成有不同孔径的刻蚀孔，以覆盖层为遮挡，进行堆叠层的刻蚀，以在刻蚀孔下形成接触孔，不同的接触孔停止于不同层的牺牲层。由于在刻蚀过程中，刻蚀孔孔径越大，其下的堆叠层的刻蚀速率越大，使得越大刻蚀孔下的接触孔能够具有更深的孔深，实现了不同深度的接触孔的刻蚀，从而，形成对应于不同牺牲层的接触孔。对于具有较多层堆叠层的存储器件，避免了刻蚀多层台阶导致的制备工艺复杂和较高成本，降低了器件所需要的面积，提高了晶圆的良率。In the method for manufacturing a 3D NAND storage device provided by an embodiment of the present invention, a stacked layer in which sacrificial layers and insulating layers are alternately stacked is formed on a substrate, and a channel hole is formed in the first region of the stacked layer, and a channel hole in the channel hole is formed. A storage layer, forming a covering layer on the stacked layer, wherein etching holes with different apertures are formed in the covering layer of the second region, and the covering layer is used as a shield to etch the stacked layer to form a contact hole under the etching hole , different contact holes stop at different sacrificial layers. During the etching process, the larger the aperture of the etching hole, the greater the etching rate of the underlying stacked layer, so that the contact hole under the larger etching hole can have a deeper hole depth, and contact holes of different depths are realized. Etching, thereby forming contact holes corresponding to different sacrificial layers. For storage devices with multiple stacked layers, the complex manufacturing process and high cost caused by etching multi-layer steps are avoided, the area required for the device is reduced, and the yield rate of the wafer is improved.
基于上述实施例，本申请提供了另一种3D NAND存储器件的制造方法，与上述实施例不同的是，在覆盖层中形成不同孔径的刻蚀孔之后，可以进一步沉积阻挡控制层，以便进一步控制堆叠层的刻蚀速度，以下详细描述与上述实施例不同的部分，相同部分将不再赘述。Based on the above-mentioned embodiments, the present application provides another manufacturing method of 3D NAND memory devices. The difference from the above-mentioned embodiments is that after forming etching holes with different apertures in the cover layer, a barrier control layer can be further deposited to further Controlling the etching speed of the stacked layers, the parts that are different from the above-mentioned embodiments will be described in detail below, and the same parts will not be described again.
参考图5所示，步骤S501，提供衬底201，参考图6a所示。Referring to FIG. 5 , in step S501 , a substrate 201 is provided, as shown in FIG. 6 a .
本申请实施例中的衬底步骤S201中的相同，在此不再赘述。The substrate step S201 in the embodiment of the present application is the same and will not be repeated here.
步骤S502，在衬底201上形成牺牲层203与绝缘层202交替层叠的堆叠层，参考图4所示，堆叠层具有第一区域105和第二区域303，第一区域105的堆叠层中形成有沟道孔106以及沟道孔中的存储层(图未示出)。Step S502, forming a stacked layer in which sacrificial layers 203 and insulating layers 202 are alternately stacked on the substrate 201, as shown in FIG. There are channel holes 106 and a memory layer (not shown) in the channel holes.
上述步骤与步骤S202相同，在此不再赘述。The above steps are the same as step S202, and will not be repeated here.
步骤S503，在堆叠层上形成覆盖层202，第二区域303的覆盖层中形成有不同孔径的刻蚀孔207，参考图6b。Step S503 , forming a covering layer 202 on the stacked layers, and etching holes 207 with different diameters are formed in the covering layer of the second region 303 , as shown in FIG. 6 b .
覆盖层204是后续刻蚀形成接触孔时的掩膜层，是接触孔之外区域的保护层，可以根据具体的需要来选择覆盖层204的材料和厚度。在一些实施例中，覆盖层204可以是对堆叠层具有高选择比的材料，覆盖层204例如可以是多晶硅薄膜，其中的刻蚀孔207可以是暴露堆叠层的通孔。在另一些实施例中，覆盖层204可以为对堆叠层具有低选择比的材料，也就是在刻蚀堆叠层时，覆盖层204也会被刻蚀掉一部分，覆盖层204例如可以为无定型碳或氧化硅等，在对堆叠层进行刻蚀时，覆盖层204的厚度也在降低，因此覆盖层204的厚度需要具有合适的厚度，或者在覆盖层204下设置其他的阻挡层，避免堆叠层被过刻蚀。The cover layer 204 is a mask layer for subsequent etching to form a contact hole, and is a protective layer for areas outside the contact hole. The material and thickness of the cover layer 204 can be selected according to specific needs. In some embodiments, the covering layer 204 may be a material with a high selectivity ratio to the stacked layers. The covering layer 204 may be, for example, a polysilicon film, and the etching hole 207 therein may be a through hole exposing the stacked layers. In other embodiments, the covering layer 204 can be a material with a low selectivity to the stacked layers, that is, when the stacked layers are etched, a part of the covering layer 204 will also be etched away, and the covering layer 204 can be, for example, an amorphous Carbon or silicon oxide, etc., when the stacked layer is etched, the thickness of the cover layer 204 is also reduced, so the thickness of the cover layer 204 needs to have an appropriate thickness, or other barrier layers are set under the cover layer 204 to avoid stacking layer is over-etched.
覆盖层204的形成过程见步骤S203，在此不再赘述。The formation process of the covering layer 204 is shown in step S203, and will not be repeated here.
在矩形堆叠的堆叠层中，通常第一区域105的沟道孔106呈阵列排布，阵列排布的方式可以为行列对齐排布，如图4所示，也可以是错行排布，也就是一行的沟道孔形成在前一行的两个沟道孔间的位置处，有利于提高沟道孔的集成密度。在本发明实施例中，第二区域303可以位于第一区域105的旁侧，例如旁侧的一边，也可以是旁侧的多边，第二区域303中的刻蚀孔304可以与其旁侧的沟道孔106的排布方向一致，因此，在第一区域的旁侧，第二区域的面积只需容纳多个成排的刻蚀孔即可，这样，可以有效地减小接触孔区域的面积，从而降低整个存储器的面积，降低了成本。In the rectangular stacked stacked layers, usually the channel holes 106 in the first region 105 are arranged in an array, and the array arrangement can be aligned in rows and columns, as shown in FIG. 4 , or arranged in staggered rows, or That is, the channel holes of one row are formed at the positions between the two channel holes of the previous row, which is beneficial to increase the integration density of the channel holes. In the embodiment of the present invention, the second region 303 can be located on the side of the first region 105, such as one side of the side, or it can be multiple sides of the side, and the etching hole 304 in the second region 303 can be The channel holes 106 are arranged in the same direction, therefore, on the side of the first region, the area of the second region only needs to accommodate a plurality of etching holes in rows, so that the area of the contact hole region can be effectively reduced. area, thereby reducing the area of the entire memory and reducing the cost.
步骤S504，沉积阻挡控制层401，孔径越小的刻蚀孔中的阻挡控制层401具有更大的厚度。Step S504 , depositing the barrier control layer 401 , the barrier control layer 401 in the etching hole having a smaller aperture has a greater thickness.
阻挡控制层401可以是相对于堆叠层具有低选择比的材料形成，在刻蚀堆叠层时，该阻挡控制层401也将被刻蚀掉，作为刻蚀形成接触孔时的刻蚀速率的控制层。由于覆盖层中刻蚀孔的孔径不同，沉积时薄膜的均匀性会有所不同，越小孔径的刻蚀孔底部表面的阻挡控制层的厚度会越厚，这样，通过沉积形成阻挡控制层401，在对堆叠层进行刻蚀时，较小孔径中会先刻蚀阻挡控制层，进而才会刻蚀到堆叠层，通过不同厚度的刻蚀阻挡层，可以控制刻蚀堆叠层的起始时间，越小孔径下的堆叠层的刻蚀时间越晚，从而，进一步控制堆叠层中接触孔的深度。The barrier control layer 401 can be formed of a material with a low selectivity ratio relative to the stacked layer. When the stacked layer is etched, the barrier control layer 401 will also be etched away to control the etching rate when etching to form a contact hole. Floor. Due to the different apertures of the etched holes in the cover layer, the uniformity of the film during deposition will be different, and the thickness of the barrier control layer on the bottom surface of the etched hole with smaller apertures will be thicker. In this way, the barrier control layer 401 is formed by deposition. , when etching the stacked layer, the barrier control layer will be etched first in the smaller aperture, and then the stacked layer will be etched. Through the etching barrier layer of different thickness, the starting time of etching the stacked layer can be controlled, The etching time of the stacked layer with the smaller aperture is later, thereby further controlling the depth of the contact hole in the stacked layer.
沉积阻挡控制层401的方法可以是气相沉积法，在形成有刻蚀孔207的覆盖层204表面形成阻挡控制层401，如图6c所示，经过阻挡控制层401的沉积后，不同孔径的刻蚀孔中的阻挡控制层401薄膜的厚度不同，刻蚀孔的孔径越小，其内形成的阻挡控制层401越厚，刻蚀阻挡控制层401以暴露堆叠层所需要的时间越长。如图6d所示，在对阻挡控制层401进行刻蚀时，孔径较大的刻蚀孔207内的阻挡控制层401较薄，且刻蚀速率较快，较先完成刻蚀以暴露其下的堆叠层；而孔径较小的刻蚀孔207内的阻挡控制层401较厚，且其刻蚀速率较慢，较后完成刻蚀。通过阻挡控制层401实现了对不同刻蚀孔207下堆叠层刻蚀的顺序和速率的控制，进一步对接触孔208的深度进行控制，参考图6f所示。The method for depositing the barrier control layer 401 may be a vapor deposition method. The barrier control layer 401 is formed on the surface of the cover layer 204 with the etching holes 207 formed thereon. As shown in FIG. The film thickness of the barrier control layer 401 in the etched hole is different, the smaller the aperture of the etched hole, the thicker the barrier control layer 401 formed therein, and the longer the time required to etch the barrier control layer 401 to expose the stacked layers. As shown in Figure 6d, when the barrier control layer 401 is etched, the barrier control layer 401 in the etching hole 207 with a larger aperture is thinner, and the etching rate is faster, and the etching is completed earlier to expose the underlying layer. stacked layers; while the barrier control layer 401 in the etching hole 207 with a smaller aperture is thicker, and its etching rate is slower, and the etching is completed later. The blocking control layer 401 realizes the control of the etching sequence and rate of the stacked layers under different etching holes 207, and further controls the depth of the contact hole 208, as shown in FIG. 6f.
在本申请实施例中，步骤S504是为了控制堆叠层的刻蚀，是优选的方式，在本申请其他实施例中，也可以不进行，不影响本申请实施例的实现。In the embodiment of the present application, step S504 is to control the etching of the stacked layer, which is a preferred manner, and may not be performed in other embodiments of the present application, without affecting the implementation of the embodiment of the present application.
步骤S505，以刻蚀孔207之外的覆盖层204为遮挡，进行堆叠层208的刻蚀，以在刻蚀孔207下形成接触孔208，不同的接触孔208停止于不同层的牺牲层203，孔径越大的刻蚀孔207下的接触孔208具有更深的孔深，参考图6f所示。In step S505, the covering layer 204 outside the etching hole 207 is used as a shield to etch the stacked layer 208 to form a contact hole 208 under the etching hole 207, and different contact holes 208 stop at different sacrificial layers 203 The contact hole 208 under the etching hole 207 with a larger hole diameter has a deeper hole depth, as shown in FIG. 6f.
对堆叠层的刻蚀，可以是各向异性的干法刻蚀，例如可以为RIE(反应离子刻蚀)，刻蚀孔207下的堆叠层被刻蚀形成接触孔208。不同孔径的刻蚀孔207，由于其对刻蚀速率的影响，形成接触孔208的深度也不同，对于孔径较大的刻蚀孔207下的接触孔208，因为刻蚀速率较大且刻蚀孔中的阻挡控制层越薄，因此形成的接触孔208具有更深的孔深。The etching of the stacked layers may be anisotropic dry etching, such as RIE (Reactive Ion Etching), and the stacked layers under the etching hole 207 are etched to form a contact hole 208 . Etched holes 207 with different apertures have different depths of contact holes 208 due to their influence on the etching rate. The thinner the barrier control layer in the hole, the formed contact hole 208 has a deeper hole depth.
在对堆叠层的刻蚀过程中，同时会对阻挡控制层401进行刻蚀。由于不同孔径的刻蚀孔内形成的阻挡控制层厚度不同，且不同孔径的刻蚀孔内的阻挡控制层的刻蚀速率不同，因此，在如图6d的具体实施例中，在对堆叠层刻蚀过程中，需要对阻挡控制层进行刻蚀，孔径较大的刻蚀孔内的阻挡控制层厚度较小，率先完成刻蚀并开始堆叠层的刻蚀，因此堆叠层的刻蚀较早，孔径较小的刻蚀孔内的阻挡控制层厚度较大，需要较长时间才能完成刻蚀并暴露其下的堆叠层，因此堆叠层的刻蚀较晚，因此通过阻挡控制层401，可以实现了对不同孔径的刻蚀孔207下堆叠层刻蚀的顺序和速率的控制。During the etching process of the stacked layers, the blocking control layer 401 is simultaneously etched. Since the thickness of the barrier control layer formed in the etching holes of different apertures is different, and the etching rate of the barrier control layer in the etching holes of different apertures is different, therefore, in the specific embodiment shown in Figure 6d, in the stacked layer During the etching process, the barrier control layer needs to be etched. The thickness of the barrier control layer in the etching hole with a larger aperture is smaller. The etching is completed first and the etching of the stacked layer is started, so the etching of the stacked layer is earlier. , the thickness of the barrier control layer in the etching hole with a small aperture is relatively large, and it takes a long time to complete the etching and expose the stacked layer under it, so the etching of the stacked layer is relatively late, so through the barrier control layer 401, it can be The control of the sequence and rate of etching the stacked layers under the etching holes 207 with different apertures is realized.
如图6e所示，孔径较大的刻蚀孔207下的堆叠层刻蚀速率较快，孔径较小的刻蚀孔下的堆叠层刻蚀速率较慢，形成中间孔402，对中间孔402继续进行刻蚀，形成接触孔208，如图6f所示，其中不同孔径的接触孔208停止于不同的牺牲层203，以便在牺牲层203被替换成金属后，接触孔208内的金属介质212和金属层210连通(参考图6j)。As shown in Figure 6e, the etching rate of the stacked layer under the etching hole 207 with a larger aperture is faster, and the etching rate of the stacking layer under the etching hole with a smaller aperture is slower, forming an intermediate hole 402. Continue etching to form a contact hole 208, as shown in FIG. It communicates with the metal layer 210 (refer to FIG. 6j ).
步骤S506，在所述接触孔的内壁上形成绝缘阻挡层209(如图6g所示)；利用栅线缝隙(图未示出)将所述牺牲层203替换为金属层210(如图6h所示)；去除所述接触孔208底部的绝缘阻挡层(如图6i所示)，以所述绝缘阻挡层作为接触绝缘层211，并进行填充，形成接触塞212(如图6j所示)。Step S506, forming an insulating barrier layer 209 (as shown in FIG. 6g ) on the inner wall of the contact hole; replacing the sacrificial layer 203 with a metal layer 210 (as shown in FIG. 6h ) by using a gate line gap (not shown in the figure). shown); remove the insulating barrier layer at the bottom of the contact hole 208 (as shown in FIG. 6i ), use the insulating barrier layer as a contact insulating layer 211, and fill it to form a contact plug 212 (as shown in FIG. 6j ).
上述步骤与步骤S205类似，在此不再赘述。The above steps are similar to step S205, and will not be repeated here.
本发明实施例提供的3D NAND存储器件的制造方法，通过不同孔径的刻蚀孔来控制对堆叠层的刻蚀速率，通过阻挡控制层控制对堆叠层的刻蚀时间，形成对应于不同牺牲层的接触孔。对于具有较多层堆叠层的存储器件，提高了堆叠层刻蚀的准确性，避免了刻蚀多层台阶导致的制备工艺复杂和较高成本，降低了器件所需要的面积，提高了晶圆的良率。In the manufacturing method of the 3D NAND memory device provided by the embodiment of the present invention, the etching rate of the stacked layer is controlled through the etching holes of different apertures, and the etching time of the stacked layer is controlled through the barrier control layer, so as to form corresponding to different sacrificial layers. contact holes. For storage devices with more stacked layers, the accuracy of stack layer etching is improved, the complex preparation process and high cost caused by etching multi-layer steps are avoided, the area required for the device is reduced, and the wafer capacity is increased. yield rate.
基于以上对3D NAND存储器件的制造方法的描述，本申请还提供了一种由上述方法形成的3D NAND存储器件，参考图4和图6j所示，该器件包括：Based on the above description of the manufacturing method of the 3D NAND storage device, the present application also provides a 3D NAND storage device formed by the above method, as shown in FIG. 4 and FIG. 6j, the device includes:
衬底201；substrate 201;
所述衬底上的金属层210与绝缘层202交替层叠的堆叠层，所述堆叠层具有第一区域和第二区域，所述第一区域的堆叠层中形成有沟道孔以及沟道孔中的存储层(图未示出)；The metal layer 210 and the insulating layer 202 on the substrate are stacked alternately, the stack layer has a first region and a second region, and channel holes and channel holes are formed in the stack layer of the first region The storage layer in (figure not shown);
所述第二区域的堆叠层中的接触孔208，不同的接触孔具有不同的孔径且孔径越大的接触孔设置于更下层的金属层210上；The contact hole 208 in the stacked layer in the second region, different contact holes have different apertures and the contact hole with a larger aperture is disposed on the lower metal layer 210;
接触孔208侧壁上的接触绝缘层211以及接触孔中的接触塞212。The contact insulating layer 211 on the sidewall of the contact hole 208 and the contact plug 212 in the contact hole.
在矩形堆叠的堆叠层中，通常第一区域的沟道孔呈阵列排布，可以设定第二区域位于第一区域的旁侧，例如旁侧的一边，也可以是旁侧的多边，第二区域中的刻蚀孔可以与其旁侧的沟道孔的排布方向一致，因此，在第一区域的旁侧，第二区域的面积只需容纳多个成排的刻蚀孔即可，节省了堆叠层的面积，降低了成本。In the rectangular stacked stacked layers, usually the channel holes in the first region are arranged in an array, and the second region can be set to be located on the side of the first region, such as one side of the side, or multiple sides of the side. The etching holes in the second region can be arranged in the same direction as the channel holes beside it. Therefore, on the side of the first region, the area of the second region only needs to accommodate a plurality of rows of etching holes. The area of stacked layers is saved, and the cost is reduced.
以上所述仅是本发明的优选实施方式，虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。The above descriptions are only preferred implementations of the present invention. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent of equivalent change Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.
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| CN201711059075.7ACN107680972B (en) | 2017-11-01 | 2017-11-01 | A kind of 3D nand memory part and its manufacturing method |
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| CN201711059075.7AActiveCN107680972B (en) | 2017-11-01 | 2017-11-01 | A kind of 3D nand memory part and its manufacturing method |
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