CN107632953A - A kind of GPU casees PCIE extends interconnection topology device - Google Patents

Abstract

The invention discloses a kind of GPU casees PCIE to extend interconnection topology device, including GPU casees, and the GPU casees include the GPU of 8 groups of interconnections, and, the cpu server being connected with GPU, and, PCIE switch modules；The PCIE switch modules install interconnection cable clamp at a high speed by PCIE slot, realize the interconnection between different GPU casees；Connected between the GPU by PCIE switch modules；The cpu server is connected by PCIE links with GPU casees；The PCIE switch modules expand to PCIE links the connection that 8 groups of PCIE X16 links realize cpu server and 8 groups of GPU.The present invention realizes the independent design of standard PCIE interface GPU casees, and GPU performance guarantees maximize, and transmission delay is low, favorable expandability, can be arranged in pairs or groups and used with flexible configuration, there is provided the GPU casees design required for a kind of high-performance and artificial intelligence.

Description

Translated fromChinese

一种GPU箱PCIE扩展互连拓扑装置A GPU box PCIE extended interconnection topology device

技术领域technical field

本发明涉及服务器板卡设计技术领域，尤其是一种GPU箱PCIE扩展互连拓扑装置。The invention relates to the technical field of server board design, in particular to a GPU box PCIE extended interconnection topology device.

背景技术Background technique

随着人工智能和高性能计算的兴起，GPU(Graphics Processor Unit显示处理器单元)运算的优势在高性能计算机的体现越来越明显，相较于传统的CPU处理器，超高的出来核心，更适合更过并行运算的人工智能和高性能要求，GPU服务器已经成为服务器下个快速增长点。With the rise of artificial intelligence and high-performance computing, the advantages of GPU (Graphics Processor Unit display processor unit) computing are becoming more and more obvious in high-performance computers. Compared with traditional CPU processors, ultra-high output cores, More suitable for artificial intelligence and high-performance requirements for more parallel computing, GPU servers have become the next rapid growth point of servers.

现在的GPU设计基本上是采用通用PCIE(peripheral component interconnectexpress高速串行计算机扩展总线)插槽接口，基本上都是集成到服务器内部，和服务器本身绑定，作为GPU服务器或者高性能服务器销售。标准的PCIE接口是通用服务器常用的设计方式，但由于GPU设计需要更多的电源和结构空间，服务器本身只有单一GPU的时候，设计是没有问题的，但是应用于人工智能和高性能的的服务器现在需要使用更多的GPU处理器，多GPU设计就是会使服务器变得比较庞大，而且和其他标卡设计兼容性不好，同样这样PCIE结构就会成为GPU之间数据交换处理的瓶颈，严重影响多GPU架构下多GPU的性能发挥。The current GPU design basically adopts the universal PCIE (peripheral component interconnect express high-speed serial computer expansion bus) slot interface, which is basically integrated into the server, bound to the server itself, and sold as a GPU server or high-performance server. The standard PCIE interface is a common design method for general-purpose servers, but because GPU design requires more power and structural space, when the server itself only has a single GPU, the design is no problem, but it is applied to artificial intelligence and high-performance servers. Now more GPU processors need to be used. The multi-GPU design will make the server larger, and the compatibility with other standard card designs is not good. Similarly, the PCIE structure will become the bottleneck of data exchange processing between GPUs, which is serious. Affects the performance of multiple GPUs under the multi-GPU architecture.

GPU和CPU处理器的集成设计，绑定了GPU和CPU的应用场景，一旦应用达到GPU使用的上限时，只能通过网络做分布式互联方案，这样服务器本身的处理性能就会卡在网络带宽和延迟上，无法更高的提高服务器的性能。The integrated design of GPU and CPU processors binds the application scenarios of GPU and CPU. Once the application reaches the upper limit of GPU usage, it can only do distributed interconnection solutions through the network, so that the processing performance of the server itself will be stuck in the network bandwidth In terms of delay and delay, the performance of the server cannot be improved higher.

CPU和GPU之间的互联架构是固定的，无法根据不同的应用场景调整合适的CPU和GPU之间个互联拓扑，以达到一个浮点运算(GPU优势项)和整数运算(CPU优势项)的合理配置。The interconnection architecture between the CPU and the GPU is fixed, and it is impossible to adjust the appropriate interconnection topology between the CPU and the GPU according to different application scenarios to achieve a combination of floating-point operations (GPU advantage) and integer operations (CPU advantage). Reasonable configuration.

发明内容Contents of the invention

本发明的目的是提供一种GPU箱PCIE扩展互连拓扑装置，解决了GPU之间的互联通道宽带延迟问题，实现了GPU与CPU之间互联拓扑结构的弹性设计。The purpose of the present invention is to provide a GPU box PCIE extended interconnection topology device, which solves the problem of broadband delay of the interconnection channel between GPUs and realizes the flexible design of the interconnection topology between GPUs and CPUs.

为实现上述目的，本发明采用下述技术方案：To achieve the above object, the present invention adopts the following technical solutions:

一种GPU箱PCIE扩展互连拓扑装置，包括GPU箱，所述GPU箱包括8组互相连接的GPU，和，与GPU连接的CPU服务器，和，PCIE switch模块；所述PCIE switch模块通过PCIEslot安装高速互联线缆卡，实现不同的GPU箱之间的互联；所述GPU之间通过PCIE switch模块连接；所述CPU服务器通过PCIE链路与GPU箱连接；所述PCIE switch模块将PCIE链路扩展为8组PCIE X16链路实现CPU服务器与8组GPU的连接。A GPU box PCIE extended interconnect topology device, comprising a GPU box, the GPU box includes 8 groups of interconnected GPUs, and, a CPU server connected to the GPU, and, a PCIE switch module; the PCIE switch module is installed by PCIEslot The high-speed interconnection cable card realizes the interconnection between different GPU boxes; the GPUs are connected through a PCIE switch module; the CPU server is connected to the GPU box through a PCIE link; the PCIE switch module extends the PCIE link Realize the connection between the CPU server and 8 sets of GPUs for 8 sets of PCIE X16 links.

进一步地，所述PCIE switch模块包括第一PCIE switch芯片、第二PCIE switch芯片，所述GPU箱的上行端口配置两组PCIE X16端口与CPU服务器连接时，所述第一PCIEswitch芯片的端口S0通过PCIE slot1与第一高速互连线缆卡连接，所述第一PCIE switch芯片的端口S1通过slimline接口与CPU服务器连接，所述第二PCIE switch芯片的端口S0通过PCIE slot2与第二高速互连线缆卡连接，所述第二PCIE switch芯片的端口S1通过slimline接口与CPU服务器连接。Further, the PCIE switch module includes a first PCIE switch chip and a second PCIE switch chip, and when the uplink port of the GPU box is configured with two sets of PCIE X16 ports to connect to the CPU server, the port S0 of the first PCIE switch chip passes through PCIE slot1 is connected to the first high-speed interconnection cable card, the port S1 of the first PCIE switch chip is connected to the CPU server through the slimline interface, and the port S0 of the second PCIE switch chip is connected to the second high-speed interconnection through PCIE slot2 The cable card is connected, and the port S1 of the second PCIE switch chip is connected to the CPU server through the slimline interface.

进一步地，所述PCIE switch模块包括第一PCIE switch芯片、第二PCIE switch芯片，所述GPU箱的上行端口配置一组PCIE X16端口与CPU服务器连接时，所述第一PCIEswitch芯片的端口S0、第二PCIE switch芯片的端口S1通过PCIE转slimline转接卡与CPU服务器的slimline接口连接。Further, the PCIE switch module includes a first PCIE switch chip and a second PCIE switch chip, and when the uplink port of the GPU box is configured with a group of PCIE X16 ports to connect to the CPU server, the ports S0, S0, and The port S1 of the second PCIE switch chip is connected to the slimline interface of the CPU server through a PCIE-to-slimline adapter card.

进一步地，所述第一PCIE switch芯片的端口S2、端口S3、端口S4、端口S5分别通过PCIE X16链路与GPU0、GPU1、GPU2、GPU3连接；Further, port S2, port S3, port S4, and port S5 of the first PCIE switch chip are respectively connected to GPU0, GPU1, GPU2, and GPU3 through PCIE X16 links;

所述第二PCIE switch芯片的端口S2、端口S3、端口S4、端口S5分别通过PCIE X16链路与GPU4、GPU5、GPU6、GPU7连接。Port S2, port S3, port S4, and port S5 of the second PCIE switch chip are respectively connected to GPU4, GPU5, GPU6, and GPU7 through PCIE X16 links.

进一步地，所述第一PCIE switch芯片的电源连接端与GPU的电源连接端连接；所述第二PCIE switch芯片的电源连接端与GPU的电源连接端连接。Further, the power connection end of the first PCIE switch chip is connected to the power connection end of the GPU; the power connection end of the second PCIE switch chip is connected to the power connection end of the GPU.

进一步地，所述CPU服务器的时钟端与第一PCIE switch芯片的时钟端连接，所述第一PCIE switch芯片的时钟端分别与第二PCIE switch芯片的时钟端、第一高速互连线缆卡、第二高速互连线缆卡、GPU0、GPU1、GPU2、GPU3、GPU4、GPU5、GPU6、GPU7连接。Further, the clock end of the CPU server is connected to the clock end of the first PCIE switch chip, and the clock end of the first PCIE switch chip is respectively connected to the clock end of the second PCIE switch chip and the first high-speed interconnection cable card , the second high-speed interconnection cable card, GPU0, GPU1, GPU2, GPU3, GPU4, GPU5, GPU6, GPU7 connection.

进一步地，所述CPU服务器通过slimline接口将I2C总线分为两路，一路通过I2C开关芯片扩展8组I2C链路依次与GPU0、GPU1、GPU2、GPU3、GPU4、GPU5、GPU6、GPU7连接；另一路通过模拟侦测芯片依次与GPU0POWER、GPU1POWER、GPU2POWER、GPU3POWER、GPU4POWER、GPU5POWER、GPU6POWER、GPU7POWER连接。Further, the CPU server divides the I2C bus into two paths through the slimline interface, and one path is connected to GPU0, GPU1, GPU2, GPU3, GPU4, GPU5, GPU6, and GPU7 in turn by extending 8 groups of I2C links through the I2C switch chip; the other path The analog detection chip is connected to GPU0POWER, GPU1POWER, GPU2POWER, GPU3POWER, GPU4POWER, GPU5POWER, GPU6POWER, GPU7POWER in sequence.

发明内容中提供的效果仅仅是实施例的效果，而不是发明所有的全部效果，上述技术方案中的一个技术方案具有如下优点或有益效果：The effects provided in the summary of the invention are only the effects of the embodiments, rather than all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects:

本发明采用标准PCIE接口GPU设计，GPU型号可以根据客户需求灵活配置；GPU之间直接通过PCIE SWITCH互联访问，GPU之间速率高达16GB/s；GPU箱之间可以通过IB卡实现多机箱互联，互联速率达100Gbps，数据延迟us级别；上行端口实现标准slimline接口化，可以和不通服务器进行适配，而且上行端口可灵活配置成两组PCIE X16和一组PCIE X16。本发明实现了标准PCIE接口GPU箱的独立设计，GPU性能保证了最大化，传输延迟低，扩展性好，可以灵活配置搭配使用，提供了一种高性能和人工智能所需要的GPU箱设计。The present invention adopts the standard PCIE interface GPU design, and the GPU model can be flexibly configured according to customer needs; the GPUs are directly accessed through the PCIE SWITCH interconnection, and the rate between the GPUs is as high as 16GB/s; the GPU boxes can be connected to each other through the IB card to realize multi-chassis interconnection. The interconnection rate reaches 100Gbps, and the data delay is us level; the uplink port realizes the standard slimline interface, which can be adapted to different servers, and the uplink port can be flexibly configured into two sets of PCIE X16 and one set of PCIE X16. The invention realizes the independent design of the standard PCIE interface GPU box, the GPU performance is guaranteed to be maximized, the transmission delay is low, the scalability is good, and it can be configured and used flexibly, and a GPU box design required by high performance and artificial intelligence is provided.

附图说明Description of drawings

图1是本发明实施例一的结构示意图；Fig. 1 is a schematic structural view of Embodiment 1 of the present invention;

图2是本发明时钟隔离设计原理图；Fig. 2 is a schematic diagram of clock isolation design of the present invention;

图3是本发明I2C总线分配示意图。FIG. 3 is a schematic diagram of I2C bus distribution in the present invention.

具体实施方式detailed description

为能清楚说明本方案的技术特点，下面通过具体实施方式，并结合其附图，对本发明进行详细阐述。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。应当注意，在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。In order to clearly illustrate the technical features of this solution, the present invention will be described in detail below through specific implementation modes and in conjunction with the accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. It should be noted that components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted herein to avoid unnecessarily limiting the present invention.

实施例一Embodiment one

如图1所示，包括GPU箱，CPU服务器，第一PCIE switch芯片PEX9797、第二PCIEswitch芯片PEX9797，GPU箱包括8组互相连接的GPU，GPU箱的上行端口配置两组PCIE X16端口与CPU服务器连接时，第一PCIE switch芯片PEX9797的端口S0通过PCIE slot1与第一高速互连线缆卡连接，第一PCIE switch芯片PEX9797的端口S1通过slimline接口与CPU服务器连接，第一PCIE switch芯片PEX9797的端口S2、端口S4连接到PCIE连接端子，PCIE连接端子通过2*PCIE Gen 3X16总线与另一只PCIE连接端子连接，另一只PCIE连接端子通过两路PCIE X16总线与两只PCIE slot芯片连接，两只PCIE slot芯片分别通过PCIE X16总线与GPU0、GPU1连接，同样的，第一PCIE switch芯片PEX9797的端口S3、端口S5实现与GPU2、GPU3连接。As shown in Figure 1, it includes a GPU box, a CPU server, the first PCIE switch chip PEX9797, and the second PCIE switch chip PEX9797. The GPU box includes 8 groups of interconnected GPUs. The upstream port of the GPU box is configured with two sets of PCIE X16 ports and the CPU server. When connecting, the port S0 of the first PCIE switch chip PEX9797 is connected to the first high-speed interconnection cable card through PCIE slot1, the port S1 of the first PCIE switch chip PEX9797 is connected to the CPU server through the slimline interface, and the port S1 of the first PCIE switch chip PEX9797 is Port S2 and port S4 are connected to the PCIE connection terminal, the PCIE connection terminal is connected to another PCIE connection terminal through 2*PCIE Gen 3X16 bus, and the other PCIE connection terminal is connected to two PCIE slot chips through two PCIE X16 buses, The two PCIE slot chips are respectively connected to GPU0 and GPU1 through the PCIE X16 bus. Similarly, ports S3 and S5 of the first PCIE switch chip PEX9797 are connected to GPU2 and GPU3.

第二PCIE switch芯片PEX9797的端口S0通过PCIE slot2与第二高速互连线缆卡连接，第二PCIE switch芯片PEX9797的端口S1通过slimline接口与CPU服务器连接，第二PCIE switch芯片PEX9797的端口S2、端口S3、端口S4、端口S5分别通过PCIE X16链路与GPU4、GPU5、GPU6、GPU7连接。The port S0 of the second PCIE switch chip PEX9797 is connected to the second high-speed interconnection cable card through PCIE slot2, the port S1 of the second PCIE switch chip PEX9797 is connected to the CPU server through the slimline interface, and the ports S2, Port S3, port S4, and port S5 are respectively connected to GPU4, GPU5, GPU6, and GPU7 through PCIE X16 links.

第一PCIE switch芯片PEX9797的电源连接端与GPU的电源连接端连接；所述第二PCIE switch芯片PEX9797的电源连接端与GPU的电源连接端连接。The power connection end of the first PCIE switch chip PEX9797 is connected to the power connection end of the GPU; the power connection end of the second PCIE switch chip PEX9797 is connected to the power connection end of the GPU.

如图2所示，CPU服务器的时钟端通过时钟缓冲芯片与第一PCIE switch芯片PEX9797A的时钟端连接，所述第一PCIE switch芯片PEX9797A的时钟端分别与第二PCIEswitch芯片PEX9797的时钟端、第一高速互连线缆卡、第二高速互连线缆卡、GPU0、GPU1、GPU2、GPU3、GPU4、GPU5、GPU6、GPU7的时钟端连接。As shown in Figure 2, the clock end of the CPU server is connected to the clock end of the first PCIE switch chip PEX9797A through the clock buffer chip, and the clock end of the first PCIE switch chip PEX9797A is respectively connected to the clock end of the second PCIE switch chip PEX9797, the clock end of the second PCIE switch chip PEX9797 A high-speed interconnection cable card, a second high-speed interconnection cable card, GPU0, GPU1, GPU2, GPU3, GPU4, GPU5, GPU6, GPU7 are connected to clock terminals.

如图3所示，CPU服务器通过slimline接口将I2C总线分为两路，一路通过I2C开关芯片扩展8组I2C链路依次与GPU0、GPU1、GPU2、GPU3、GPU4、GPU5、GPU6、GPU7连接；另一路通过模拟侦测芯片依次与GPU0POWER、GPU1POWER、GPU2POWER、GPU3POWER、GPU4POWER、GPU5POWER、GPU6POWER、GPU7POWER连接。As shown in Figure 3, the CPU server divides the I2C bus into two paths through the slimline interface, and one path is connected to GPU0, GPU1, GPU2, GPU3, GPU4, GPU5, GPU6, and GPU7 in sequence through the I2C switch chip to expand 8 groups of I2C links; All the way through the analog detection chip to connect with GPU0POWER, GPU1POWER, GPU2POWER, GPU3POWER, GPU4POWER, GPU5POWER, GPU6POWER, GPU7POWER in turn.

实施例二Embodiment two

实施例二与实施例一的区别在于GPU箱上行端口配置一组PCIE X16端口与CPU服务器连接时，第一PCIE switch芯片的端口S0、第二PCIE switch芯片的端口S1通过PCIE转slimline转接卡与CPU服务器的slimline接口连接。The difference between Embodiment 2 and Embodiment 1 is that when the upstream port of the GPU box is configured with a set of PCIE X16 ports to connect to the CPU server, the port S0 of the first PCIE switch chip and the port S1 of the second PCIE switch chip are transferred through the PCIE to slimline adapter card Connect to the slimline interface of the CPU server.

上述虽然结合附图对本发明的具体实施方式进行了描述，但并非对本发明保护范围的限制，所属领域技术人员应该明白，在本发明的技术方案的基础上，本领域技术人员不需要付出创造性劳动即可做出的各种修改或变形仍在本发明的保护范围以内。Although the specific implementation of the present invention has been described above in conjunction with the accompanying drawings, it does not limit the protection scope of the present invention. Those skilled in the art should understand that on the basis of the technical solution of the present invention, those skilled in the art do not need to pay creative work Various modifications or variations that can be made are still within the protection scope of the present invention.

Claims (7)

Translated fromChinese

1.一种GPU箱PCIE扩展互连拓扑装置，其特征是，包括GPU箱，所述GPU箱包括8组互相连接的GPU，和，与GPU连接的CPU服务器，和，PCIE switch模块；所述PCIE switch模块通过PCIE slot安装高速互联线缆卡，实现不同的GPU箱之间的互联；所述GPU之间通过PCIEswitch模块连接；所述CPU服务器通过PCIE链路与GPU箱连接；所述PCIE switch模块将PCIE链路扩展为8组PCIE X16链路实现CPU服务器与8组GPU的连接。1. A GPU box PCIE extended interconnection topology device is characterized in that it comprises a GPU box, and the GPU box includes 8 groups of interconnected GPUs, and, a CPU server connected to the GPU, and, a PCIE switch module; The PCIE switch module installs a high-speed interconnection cable card through the PCIE slot to realize the interconnection between different GPU boxes; the GPUs are connected through the PCIEswitch module; the CPU server is connected to the GPU box through the PCIE link; the PCIE switch The module expands the PCIE link to 8 sets of PCIE X16 links to realize the connection between the CPU server and 8 sets of GPUs.2.如权利要求1所述的一种GPU箱PCIE扩展互连拓扑装置，其特征是，所述PCIE switch模块包括第一PCIE switch芯片、第二PCIE switch芯片，所述GPU箱的上行端口配置两组PCIE X16端口与CPU服务器连接时，所述第一PCIE switch芯片的端口S0通过PCIE slot1与第一高速互连线缆卡连接，所述第一PCIE switch芯片的端口S1通过slimline接口与CPU服务器连接，所述第二PCIE switch芯片的端口S0通过PCIE slot2与第二高速互连线缆卡连接，所述第二PCIE switch芯片的端口S1通过slimline接口与CPU服务器连接。2. a kind of GPU box PCIE expansion interconnection topology device as claimed in claim 1, is characterized in that, described PCIE switch module comprises the first PCIE switch chip, the second PCIE switch chip, the uplink port configuration of described GPU box When two sets of PCIE X16 ports are connected to the CPU server, the port S0 of the first PCIE switch chip is connected to the first high-speed interconnection cable card through PCIE slot1, and the port S1 of the first PCIE switch chip is connected to the CPU through the slimline interface Server connection, the port S0 of the second PCIE switch chip is connected to the second high-speed interconnection cable card through PCIE slot2, and the port S1 of the second PCIE switch chip is connected to the CPU server through the slimline interface.3.如权利要求1所述的一种GPU箱PCIE扩展互连拓扑装置，其特征是，所述PCIE switch模块包括第一PCIE switch芯片、第二PCIE switch芯片，所述GPU箱的上行端口配置一组PCIE X16端口与CPU服务器连接时，所述第一PCIE switch芯片的端口S0、第二PCIE switch芯片的端口S1通过PCIE转slimline转接卡与CPU服务器的slimline接口连接。3. a kind of GPU box PCIE expansion interconnection topology device as claimed in claim 1, is characterized in that, described PCIE switch module comprises the first PCIE switch chip, the second PCIE switch chip, the uplink port configuration of described GPU box When a group of PCIE X16 ports are connected to the CPU server, the port S0 of the first PCIE switch chip and the port S1 of the second PCIE switch chip are connected to the slimline interface of the CPU server through a PCIE to slimline adapter card.4.如权利要求2或3所述的一种GPU箱PCIE扩展互连拓扑装置，其特征是，所述第一PCIEswitch芯片的端口S2、端口S3、端口S4、端口S5分别通过PCIE X16链路与GPU0、GPU1、GPU2、GPU3连接；4. a kind of GPU box PCIE expansion interconnection topology device as claimed in claim 2 or 3, is characterized in that, the port S2 of described first PCIEswitch chip, port S3, port S4, port S5 pass through PCIE X16 link respectively Connect with GPU0, GPU1, GPU2, GPU3;所述第二PCIE switch芯片的端口S2、端口S3、端口S4、端口S5分别通过PCIE X16链路与GPU4、GPU5、GPU6、GPU7连接。Port S2, port S3, port S4, and port S5 of the second PCIE switch chip are respectively connected to GPU4, GPU5, GPU6, and GPU7 through PCIE X16 links.5.如权利要求2或3所述的一种GPU箱PCIE扩展互连拓扑装置，其特征是，所述第一PCIEswitch芯片的电源连接端与GPU的电源连接端连接；所述第二PCIE switch芯片的电源连接端与GPU的电源连接端连接。5. a kind of GPU box PCIE expansion interconnection topology device as claimed in claim 2 or 3, is characterized in that, the power connection end of described first PCIEswitch chip is connected with the power connection end of GPU; The second PCIE switch The power connection end of the chip is connected with the power connection end of the GPU.6.如权利要求2或3所述的一种GPU箱PCIE扩展互连拓扑装置，其特征是，所述CPU服务器的时钟端与第一PCIE switch芯片的时钟端连接，所述第一PCIE switch芯片的时钟端分别与第二PCIE switch芯片的时钟端、第一高速互连线缆卡、第二高速互连线缆卡、GPU0、GPU1、GPU2、GPU3、GPU4、GPU5、GPU6、GPU7连接。6. a kind of GPU box PCIE expansion interconnection topology device as claimed in claim 2 or 3, is characterized in that, the clock end of described CPU server is connected with the clock end of first PCIE switch chip, and described first PCIE switch The clock end of the chip is respectively connected with the clock end of the second PCIE switch chip, the first high-speed interconnection cable card, the second high-speed interconnection cable card, GPU0, GPU1, GPU2, GPU3, GPU4, GPU5, GPU6, and GPU7.7.如权利要求2或3所述的一种GPU箱PCIE扩展互连拓扑装置，其特征是，所述CPU服务器通过slimline接口将I2C总线分为两路，一路通过I2C开关芯片扩展8组I2C链路依次与GPU0、GPU1、GPU2、GPU3、GPU4、GPU5、GPU6、GPU7连接；另一路通过模拟侦测芯片依次与GPU0POWER、GPU1 POWER、GPU2 POWER、GPU3 POWER、GPU4 POWER、GPU5 POWER、GPU6 POWER、GPU7POWER连接。7. A GPU box PCIE extended interconnect topology device as claimed in claim 2 or 3, wherein the CPU server divides the I2C bus into two paths through the slimline interface, and one path expands 8 groups of I2C through the I2C switch chip The link is connected to GPU0, GPU1, GPU2, GPU3, GPU4, GPU5, GPU6, GPU7 in turn; the other link is connected to GPU0POWER, GPU1 POWER, GPU2 POWER, GPU3 POWER, GPU4 POWER, GPU5 POWER, GPU6 POWER, GPU7POWER connection.