技术领域technical field
本发明实施例涉及直流转换器技术，尤其涉及一种多相交错并联直流转换器。Embodiments of the present invention relate to DC converter technology, in particular to a multi-phase interleaved parallel DC converter.
背景技术Background technique
手机或智能终端现在大都采用多核心处理器来应对目前多功能和高性能的基本需求，这些处理器芯片具有以下特征和发展趋势：1)工艺结点不断减小2)超强的运算能力和不断攀升的核心数；3)更复杂的架构以应对多种模式的运行以及切换。以上这些处理器核心的特征给其供电的调压模块提出了极大挑战，主要表现在：1)覆盖极低的运行电压。2)大电流输出能力以及高效率，传统功率器件集成的DCDC转换器在效率和散热方面已经难以胜任，而功率器件外置的DCDC，意味着成本的增加。3)快速的负载响应性能。复杂的应用场景需要处理器在“忙”“闲”之间快速切换。为了满足上述低压低纹波，高效率，高功率密度，快速响应速度等技术指标，国内外在直流转换器领域展开了很多尝试和研究。Most mobile phones or smart terminals now use multi-core processors to meet the current basic needs of multi-function and high performance. These processor chips have the following characteristics and development trends: 1) Process nodes are continuously reduced 2) Super computing power and The number of cores keeps rising; 3) A more complex architecture to cope with the operation and switching of multiple modes. The characteristics of the above processor cores pose great challenges to the voltage regulation module powered by them, which are mainly manifested in: 1) Covering extremely low operating voltage. 2) Large current output capability and high efficiency. The DCDC converter integrated with traditional power devices is already incapable in terms of efficiency and heat dissipation, while the external DCDC of power devices means an increase in cost. 3) Fast load response performance. Complex application scenarios require the processor to quickly switch between "busy" and "idle". In order to meet the above-mentioned technical indicators such as low voltage and low ripple, high efficiency, high power density, and fast response speed, many attempts and researches have been carried out in the field of DC converters at home and abroad.
多相直流转换器技术(multiphase DCDC)是近几年来被越来越多的讨论的解决方案之一。与传统的单相同步降压控制器相比，多相控制器增加了一个或多个变换通道，每个变换器通道的相位相对间隔360度/N(N为相数)。以两相并联降压型直流转换器为例。电压反馈环路为输出VOUT通过RIN到FB端，与误差放大器正相端的参考电压VREF进行对比运算，得到输出Vc。Vc连接到两个通道，与每个通道的电流误差信号分别求和得到Vd1和Vd2。分别与错相位 的斜坡信号进行比较，得到脉宽调制的PWM信号，分别驱动两相的功率输出级。每个支路使用电阻RISEN，采样当前通道的输出电流，与平均电流求差得到电流误差信号，该误差信号与前述电压误差放大信号Vc求和，进入电压反馈环路中，实现电流的均流，保证每个通道的电流基本相等，功率能够从两相通路平均分配送出。Multiphase DC converter technology (multiphase DCDC) is one of the solutions that have been discussed more and more in recent years. Compared with the traditional single-phase synchronous buck controller, the multi-phase controller adds one or more conversion channels, and the relative phase interval of each converter channel is 360 degrees/N (N is the number of phases). Take a two-phase parallel buck DC converter as an example. The voltage feedback loop is that the output VOUT passes through RIN to the FB terminal, and is compared with the reference voltage VREF at the positive phase terminal of the error amplifier to obtain the output Vc. Vc is connected to two channels, and the current error signal of each channel is summed to obtain Vd1 and Vd2 respectively. Comparing them with the ramp signals with different phases respectively, the PWM signals of pulse width modulation are obtained, which drive the two-phase power output stages respectively. Each branch uses the resistor RISEN to sample the output current of the current channel, and calculates the difference with the average current to obtain the current error signal. The error signal is summed with the aforementioned voltage error amplification signal Vc, and enters the voltage feedback loop to realize current sharing. , to ensure that the current of each channel is basically equal, and the power can be evenly distributed and sent from the two-phase channels.
现有的多相并联计算存在的缺陷在于：为实现电流均衡要加和求平均以及多个加减运算，电路复杂；缺少相位增减机制，负载轻的同时，多相驱动多支路动态功耗占比大，多相位直流转换器效率骤降。The disadvantages of the existing multi-phase parallel calculations are: in order to achieve current balance, summing and averaging and multiple addition and subtraction operations are required, and the circuit is complicated; there is no phase increase and decrease mechanism, and the load is light. The proportion of power consumption is large, and the efficiency of the multi-phase DC converter drops sharply.
发明内容Contents of the invention
本发明提供一种多相交错并联直流转换器，以实现峰值电流均衡，节省硬件成本。The invention provides a multi-phase interleaved parallel DC converter to realize peak current balance and save hardware cost.
第一方面，本发明实施例提供了一种多相交错并联直流转换器，包括：In the first aspect, an embodiment of the present invention provides a multi-phase interleaved parallel DC converter, including:
多相时钟控制单元、外部反馈电路和至少两个相互并联的支路；a multi-phase clock control unit, an external feedback circuit and at least two branches connected in parallel with each other;
每个支路中均包括逻辑触发电路、驱动功率管电路以及比较电路；Each branch includes a logic trigger circuit, a drive power tube circuit and a comparison circuit;
所述比较电路，其采样输入端连接驱动功率管电路的峰值采样端，斜坡输入端连接驱动功率管电路的驱动输出端，PWM比较输出端连接所述逻辑触发电路的第一触发端，用于采集驱动功率管电路输出的峰值采样电流，并根据所述驱动功率管电路的驱动电流生成斜坡信号，将采样输出端的输入电流与斜坡信号相加作为斜坡比较信号，并将负端输入的电压信号与所述斜坡比较信号进行PWM比较采样；In the comparison circuit, its sampling input terminal is connected to the peak sampling terminal of the drive power tube circuit, the slope input terminal is connected to the drive output terminal of the drive power tube circuit, and the PWM comparison output terminal is connected to the first trigger terminal of the logic trigger circuit for Collect the peak sampling current output by the driving power tube circuit, and generate a ramp signal according to the driving current of the driving power tube circuit, add the input current of the sampling output terminal to the ramp signal as a ramp comparison signal, and input the voltage signal of the negative terminal Perform PWM comparison sampling with the slope comparison signal;
所述外部反馈电路，其输入端连接各支路的驱动功率管电路的电压输出端连接处，用于将各支路的驱动功率管电路的输出电压与预设基准电压比较做差， 并输出给所述比较电路的负端；The external feedback circuit, whose input end is connected to the connection of the voltage output terminals of the driving power tube circuits of each branch, is used to compare the output voltage of the driving power tube circuit of each branch with the preset reference voltage, and output to the negative terminal of the comparison circuit;
所述多相时钟控制单元，其时钟输出端连接各支路的驱动功率管电路的第二触发端，用于为开启的支路输出相位差依次相差为的时钟信号,N为开启的支路的个数，开启的支路为驱动功率管电路的电压输出端有输出电压的支路；The multi-phase clock control unit, its clock output terminal is connected to the second trigger terminal of the driving power tube circuit of each branch, and is used to output a clock signal with a phase difference of 0 for the opened branch, and N is the opened branch The number of the opened branch is the branch with output voltage at the voltage output end of the drive power tube circuit;
所述逻辑触发电路的输出端连接所述驱动功率管电路的驱动输入端，当第一触发端电压大于零且第二触发端接收时钟信号上升沿时，通过其输出端开启该支路。The output terminal of the logic trigger circuit is connected to the driving input terminal of the driving power tube circuit, and when the voltage of the first trigger terminal is greater than zero and the second trigger terminal receives a rising edge of the clock signal, the branch is opened through its output terminal.
进一步的，所述驱动功率管电路包括：栅极驱动电路、上边功率管、下边功率管以及匹配电感；所述逻辑触发电路的输出端连接所述栅极驱动电路的输入端、所述栅极驱动电路两输出端分别连接所述上边功率管的栅极和所述下边功率管的栅极，所述上边功率管的漏极与所述下边功率管的源极相连，所述栅极驱动电路第一输出端连接所述比较电路的斜坡输入端，上边功率管的源级上电，下边管的漏级接地；所述比较电路的采样输入端连接所述上边功率管以采集所述上边功率管峰值电流；所述匹配电感的一端连接上边功率管的漏极，各支路的匹配电感的另一端连接处连接外部反馈电路的输入端。Further, the drive power tube circuit includes: a gate drive circuit, an upper power tube, a lower power tube, and a matching inductor; the output end of the logic trigger circuit is connected to the input end of the gate drive circuit, the gate The two output ends of the drive circuit are respectively connected to the grid of the upper power transistor and the grid of the lower power transistor, the drain of the upper power transistor is connected to the source of the lower power transistor, and the gate drive circuit The first output end is connected to the slope input end of the comparison circuit, the source stage of the upper power transistor is powered on, and the drain stage of the lower transistor is grounded; the sampling input end of the comparison circuit is connected to the upper power transistor to collect the upper power Tube peak current; one end of the matching inductance is connected to the drain of the upper power tube, and the other end connection of the matching inductance of each branch is connected to the input end of the external feedback circuit.
进一步的，外部反馈电路包括用于采样各支路的驱动功率管电路的电压输出端连接处输出电压的比例采样电路和第一比较器，所述第一比较器的正端输入基准电压，负端连接所述比例采样电路的输出端，所述第一比较器的输入端分别连接各支路中PWM比较器的负端，所述PWM比较器的输出端连接所述逻辑触发电路的第二逻辑触发端。Further, the external feedback circuit includes a proportional sampling circuit and a first comparator for sampling the output voltage at the connection of the voltage output terminals of the driving power tube circuits of each branch, the positive terminal of the first comparator inputs the reference voltage, and the negative terminal of the first comparator inputs the reference voltage. terminal is connected to the output terminal of the proportional sampling circuit, the input terminal of the first comparator is respectively connected to the negative terminal of the PWM comparator in each branch, and the output terminal of the PWM comparator is connected to the second terminal of the logic trigger circuit. logic trigger.
进一步的，所述比较电路包括电流采样模块、斜坡电路、第一加法器以及PWM比较器；电流采样模块的采样输出端和斜坡电路的输出端均连接第一加法 器的输入端，所述第一加法器的输出端连接PWM比较器的正端，所述外部反馈电路的输出端连接PWM比较器的负端。Further, the comparison circuit includes a current sampling module, a ramp circuit, a first adder, and a PWM comparator; the sampling output of the current sampling module and the output of the ramp circuit are connected to the input of the first adder, and the first adder The output terminal of an adder is connected to the positive terminal of the PWM comparator, and the output terminal of the external feedback circuit is connected to the negative terminal of the PWM comparator.
进一步的，所述多相时钟控制单元包括相位控制单元、时钟输出端单元、峰值采样加法电路、比例电路以及ADC阈值判断电路；各支路比较电路的峰值采样输出端连接所述峰值采样加法电路的输入端，所述峰值采样加法电路的输出端连接所述比例电路的输入端，所述比例电路的输出端连接所述ADC阈值判断电路的输入端，所述ADC阈值判断电路的输出端连接所述相位控制单元，所述相位控制单元的输出端连接所述时钟输出单元的时钟生成输入端，所述时钟输出单元的输出端连接逻辑触发电路的第一触发端。Further, the multi-phase clock control unit includes a phase control unit, a clock output unit, a peak sampling addition circuit, a proportional circuit, and an ADC threshold judgment circuit; the peak sampling output terminals of each branch comparison circuit are connected to the peak sampling addition circuit The input terminal of the peak sampling addition circuit is connected to the input terminal of the proportional circuit, the output terminal of the proportional circuit is connected to the input terminal of the ADC threshold judgment circuit, and the output terminal of the ADC threshold judgment circuit is connected to In the phase control unit, the output terminal of the phase control unit is connected to the clock generation input terminal of the clock output unit, and the output terminal of the clock output unit is connected to the first trigger terminal of the logic trigger circuit.
进一步的，所述多相时钟控制单元还包括临界比较器，所述临界比较器的第一比较端连接所述比例采样电路的输出端，第二比较端连接预设使能电压临界值，所述临界比较器的输出端连接所述多相时钟控制单元的全支路使能端。Further, the multi-phase clock control unit further includes a critical comparator, the first comparison terminal of the critical comparator is connected to the output terminal of the proportional sampling circuit, and the second comparison terminal is connected to a preset enabling voltage threshold, so The output end of the critical comparator is connected to the full-branch enable end of the multi-phase clock control unit.
进一步的，所述相位控制单元，用于根据电流阈值比较结果阈值判断电路的输出信号控制各支路使能的开启状态；所述时钟输出端单元，用于根据所述相位控制单元输入的开启的支路个数N输出相位差依次相差的时钟信号给开启支路的逻辑触发电路的第一触发端。Further, the phase control unit is used to control the on-state of each branch enable according to the output signal of the current threshold comparison result threshold judgment circuit; the clock output unit is used to turn on the input according to the phase control unit The number N of branches outputs clock signals with successively different phases to the first trigger terminal of the logic trigger circuit that opens the branches.
进一步的，峰值采样加法电路包括各支路的采样保持电路和加法器，各支路比较电路的峰值采样输出端分别连接各支路的采样保持电路的输入端，所述各支路采样保持电路的输出端均连接所述加法器的输入端，所示加法器的输出端连接所述比例电路的输入端。Further, the peak sampling and adding circuit includes a sampling and holding circuit and an adder of each branch, and the peak sampling output terminals of each branch comparison circuit are respectively connected to the input terminals of the sampling and holding circuits of each branch, and each branch sampling and holding circuit The output ends of the adder are all connected to the input end of the adder, and the output ends of the adder are connected to the input end of the proportional circuit.
进一步的，所述逻辑触发电路为SR触发器，所述第一触发端为S端，所述第二触发端为R端，所述输出端为Q端。Further, the logic trigger circuit is an SR flip-flop, the first trigger terminal is an S terminal, the second trigger terminal is an R terminal, and the output terminal is a Q terminal.
进一步的，还包括电容Cout，电容Cout的一端连接各支路的驱动功率管电路的电压输出端连接处，电容Cout的另一端接地。Further, a capacitor Cout is also included, one end of the capacitor Cout is connected to the voltage output terminals of the drive power tube circuits of each branch, and the other end of the capacitor Cout is grounded.
进一步的，所述相位控制单元包括电源输入端以及N个串联分压电阻RN、N-1个电流比较器，将比例电路输出端接入各电流比较器的正端，相邻两分压电阻的连接处连接所述各电流比较器的负端,所述电流比较器的输出端均连接所述ADC阈值判断电路的输入端，所述ADC阈值判断电路的输出端连接所述时钟输出单元的输入端。Further, the phase control unit includes a power supply input terminal, N series voltage dividing resistors RN, and N-1 current comparators, and the output terminal of the proportional circuit is connected to the positive terminal of each current comparator, and two adjacent voltage dividing resistors The connection of each current comparator is connected to the negative end of each current comparator, the output end of the current comparator is connected to the input end of the ADC threshold judgment circuit, and the output end of the ADC threshold judgment circuit is connected to the clock output unit. input.
本发明通过本基于峰值电流与公共电压回路实现了各相位支路的峰值电流均衡，进而在电感感值差异可忽略的情况先实现平均电流均衡，避免了引入运算放大器，节省硬件开销。The present invention realizes the peak current balance of each phase branch based on the peak current and common voltage loop, and then realizes the average current balance first when the difference in inductance value is negligible, avoids the introduction of an operational amplifier, and saves hardware expenses.
附图说明Description of drawings
图1a是本发明实施例2中的结构框图；Fig. 1 a is a structural block diagram in Embodiment 2 of the present invention;
图1b是本发明实施例2中的电路原理图；Fig. 1 b is a circuit schematic diagram in Embodiment 2 of the present invention;
图2是本发明实施例2中的相位控制单元和ADC阈值判断电路的电路原理图(一个实现细节举例(四相)如图2所示)；Fig. 2 is a circuit schematic diagram of a phase control unit and an ADC threshold judgment circuit in Embodiment 2 of the present invention (an implementation detail example (four phases) is shown in Fig. 2);
图3是本发明实施例2中的负载分段与相位数与效率的关系示意图；Fig. 3 is a schematic diagram of the relationship between the load segment, the number of phases, and the efficiency in Embodiment 2 of the present invention;
图4是本发明实施例2中的两相工作时时钟波形；Fig. 4 is the clock waveform during two-phase operation in embodiment 2 of the present invention;
图5是本发明实施例2中的三相工作时时钟波形；Fig. 5 is a clock waveform during three-phase operation in Embodiment 2 of the present invention;
图6是本发明实施例2中的整个负载范围内的效率曲线图示意；6 is a schematic diagram of the efficiency curve in the entire load range in Embodiment 2 of the present invention;
图7是本发明实施例2中的数字滤波后的相位控制信号示意；FIG. 7 is a schematic diagram of a digitally filtered phase control signal in Embodiment 2 of the present invention;
图8是本发明实施例2中防止输出快速跌落机制示意图；Fig. 8 is a schematic diagram of the mechanism for preventing rapid output drop in Embodiment 2 of the present invention;
图9是本发明实施例2中对各支路控制的逻辑优先级关系。Fig. 9 is a logical priority relationship for each branch control in Embodiment 2 of the present invention.
具体实施方式Detailed ways
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部结构。The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.
实施例一Embodiment one
本发明实施例一提供的一种多相交错并联直流转换器具体包括：多相时钟控制单元、外部反馈电路和N个相互并联的支路，N大于等于2。A multi-phase interleaved parallel DC converter provided in Embodiment 1 of the present invention specifically includes: a multi-phase clock control unit, an external feedback circuit and N branches connected in parallel, where N is greater than or equal to 2.
每个支路中均包括逻辑触发电路、驱动功率管电路以及比较电路。驱动功率管电路用于根据逻辑触发电路的触发而产生相应的电流，并为支路储能。比较电路，其采样输入端连接驱动功率管电路的峰值采样端，斜坡输入端连接驱动功率管电路的驱动输出端，PWM比较输出端连接逻辑触发电路的第一触发端。用于采集驱动功率管电路输出的峰值采样电流，并根据驱动功率管电路的驱动电流生成斜坡信号，将采样输出端的输入电流与斜坡信号相加作为斜坡比较信号，并将负端输入的电压信号与斜坡比较信号进行PWM比较采样。Each branch includes a logic trigger circuit, a drive power tube circuit and a comparison circuit. The driving power tube circuit is used to generate corresponding current according to the triggering of the logic triggering circuit, and store energy for the branch circuit. The comparison circuit has a sampling input terminal connected to the peak sampling terminal of the drive power tube circuit, a slope input terminal connected to the drive output terminal of the drive power tube circuit, and a PWM comparison output terminal connected to the first trigger terminal of the logic trigger circuit. It is used to collect the peak sampling current output by the driving power tube circuit, and generate a ramp signal according to the driving current of the driving power tube circuit, add the input current of the sampling output terminal to the ramp signal as a ramp comparison signal, and input the voltage signal of the negative terminal PWM comparison sampling with ramp comparison signal.
外部反馈电路，其输入端连接各支路的驱动功率管电路的电压输出端连接处，用于将各支路的驱动功率管电路的输出电压与预设基准电压比较做差，并输出给比较电路的负端；The external feedback circuit, whose input terminal is connected to the connection of the voltage output terminal of the drive power tube circuit of each branch, is used to compare the output voltage of the drive power tube circuit of each branch with the preset reference voltage, and output it to the comparison the negative terminal of the circuit;
负端输入的电压信号为将各支路的驱动功率管电路的输出电压与预设基准电压比较做差得到的电压VC，与斜坡比较信号Vramp进行PWM比较采样,而电流模控制方式，借助时钟，时钟沿来临开启驱动功率管电路使驱动功率管电路的电流增加，则内部的vramp自然增加，每一支路的电感电流峰值，可以被环 路中的Vc控制，参看下面公式：The voltage signal input at the negative terminal is the voltage VC obtained by comparing the output voltage of the drive power tube circuit of each branch with the preset reference voltage, and performs PWM comparison sampling with the slope comparison signal Vramp, and the current mode control method uses the clock , the clock edge comes to turn on the drive power tube circuit to increase the current of the drive power tube circuit, then the internal vramp will naturally increase, and the peak value of the inductor current in each branch can be controlled by Vc in the loop, see the following formula:
Vc＝Vramp(peak)-----------------------------------------------------(1)Vc＝Vramp(peak) ----------------------------------------------- ---------(1)
Vramp(peak)＝(Iramp(peak)+Ip(peak))*Rramp---------------(2)Vramp(peak) ＝(Iramp(peak) +Ip(peak) )*Rramp---------------(2)
Ip(peak)为采样输入端获取的电流信号，Iramp(peak)为比较电路中生成的斜坡电流信号，当Vramp增大到Vc时，关闭上边管，完成对外供电时间段。Ip(peak) is the current signal obtained by the sampling input terminal, and Iramp(peak) is the ramp current signal generated in the comparison circuit. When Vramp increases to Vc, the upper side transistor is turned off to complete the external power supply period.
多相时钟控制单元，其时钟输出端连接各支路的驱动功率管电路的第二触发端，用于为开启的支路输出相位差依次相差为2π/N的时钟信号,N为开启的支路的个数，开启的支路为驱动功率管电路的电压输出端有输出电压的支路；The multi-phase clock control unit, whose clock output terminal is connected to the second trigger terminal of the drive power tube circuit of each branch, is used to output the clock signal with a phase difference of 2π/N for the open branch, and N is the open branch The number of roads, the opened branch is the branch with output voltage at the voltage output end of the drive power tube circuit;
逻辑触发电路的输出端连接驱动功率管电路的驱动输入端，当第一触发端电压大于零且第二触发端接收时钟信号上升沿时，通过其输出端开启该支路。The output end of the logic trigger circuit is connected to the drive input end of the driving power tube circuit, and when the voltage of the first trigger end is greater than zero and the second trigger end receives the rising edge of the clock signal, the branch is opened through its output end.
本发明在单相峰值电流模式控制的基础上，扩展为多相峰值电流模式控制，利用包含峰值电流信息的斜坡电压，以公共反馈环路信号也就是电压控制环路的误差信号作为对比基准，实现了电流均衡的目的。而不是直接采用支路电流运算，因此相比现有技术方案，实现方式更简单。On the basis of single-phase peak current mode control, the present invention expands to multi-phase peak current mode control, uses the slope voltage containing peak current information, and uses the public feedback loop signal, that is, the error signal of the voltage control loop, as a comparison reference. The purpose of current balance is achieved. Instead of directly using the branch current calculation, the implementation method is simpler than the prior art solution.
本发明引入对负载电流的分段技术，同样的，因为峰值电流信息与负载电流存在一定的线性关系，本发明利用峰值电流信息，通过模拟数字转换单元，来得到作为负载电流分段的依据。The present invention introduces the segmentation technology of the load current. Similarly, because there is a certain linear relationship between the peak current information and the load current, the present invention uses the peak current information to obtain the basis for the load current segmentation through an analog-to-digital conversion unit.
实施例二Embodiment two
图1a和图1b为本发明实施例二提供的一种多相交错并联直流转换器的电路原理图，本实施例在上述各实施例的基础上，优选是将多相时钟控制单元、外部反馈电路、逻辑触发电路、驱动功率管电路以及比较电路的支路进一步优化。Figure 1a and Figure 1b are circuit schematic diagrams of a multi-phase interleaved parallel DC converter provided by Embodiment 2 of the present invention. On the basis of the above-mentioned embodiments, this embodiment preferably uses a multi-phase clock control unit, an external feedback The circuit, the logic trigger circuit, the drive power tube circuit and the branches of the comparison circuit are further optimized.
一种多相交错并联直流转换器包括多相时钟控制单元210、外部反馈电路220、至少两个相互并联的支路230和电容Cout。A multi-phase interleaved parallel DC converter includes a multi-phase clock control unit 210, an external feedback circuit 220, at least two parallel branches 230 and a capacitor Cout.
每个支路230中均包括逻辑触发电路231、驱动功率管电路232以及比较电路233。Each branch 230 includes a logic trigger circuit 231 , a drive power transistor circuit 232 and a comparison circuit 233 .
逻辑触发电路231为SR触发器，第一触发端为S端，第二触发端为R端，输出端为Q端。The logic trigger circuit 231 is an SR flip-flop, the first trigger terminal is the S terminal, the second trigger terminal is the R terminal, and the output terminal is the Q terminal.
驱动功率管电路232包括：栅极驱动电路2321、上边功率管2322、下边功率管2323以及匹配电感Ln，n为支路编号；SR触发器的Q端(逻辑触发电路231的输出端)连接栅极驱动电路2321的输入端、栅极驱动电路两输出端分别连接上边功率管的栅极和下边功率管的栅极，上边功率管的漏极与下边功率管的源极相连，栅极驱动电路第一输出端连接比较电路的斜坡输入端，上边功率管的源级上电PVDDn，下边管的漏级接地PGNDn；电流采样模块2331的输入端(比较电路233的采样输入端)连接上边功率管以采集上边功率管峰值电流；匹配电感Ln的一端连接上边功率管的漏极，各支路的匹配电感Ln的另一端连接处连接外部反馈电路220的输入端。The driving power tube circuit 232 includes: a gate drive circuit 2321, an upper side power tube 2322, a lower side power tube 2323, and a matching inductor Ln, where n is a branch number; the Q terminal of the SR trigger (the output terminal of the logic trigger circuit 231) is connected to The input end of the pole drive circuit 2321 and the two output ends of the gate drive circuit are respectively connected to the grid of the upper power transistor and the grid of the lower power transistor, the drain of the upper power transistor is connected to the source of the lower power transistor, and the gate drive circuit The first output end is connected to the slope input end of the comparison circuit, the source stage of the upper power transistor is powered on PVDDn, and the drain stage of the lower transistor is grounded to PGNDn; the input end of the current sampling module 2331 (the sampling input end of the comparison circuit 233) is connected to the upper power transistor To collect the peak current of the upper power tube; one end of the matching inductor Ln is connected to the drain of the upper power tube, and the other end of the matching inductor Ln of each branch is connected to the input end of the external feedback circuit 220 .
比较电路233，包括电流采样模块2331、斜坡电路2332、第一加法器2333以及PWM比较器2334。The comparison circuit 233 includes a current sampling module 2331 , a ramp circuit 2332 , a first adder 2333 and a PWM comparator 2334 .
电流采样模块2331的采样输出端和斜坡电路2332的输出端均连接第一加法器2333的输入端，第一加法器2333的输出端连接PWM比较器2334的正端，外部反馈电路的输出端连接PWM比较器2334的负端。The sampling output terminal of the current sampling module 2331 and the output terminal of the ramp circuit 2332 are both connected to the input terminal of the first adder 2333, the output terminal of the first adder 2333 is connected to the positive terminal of the PWM comparator 2334, and the output terminal of the external feedback circuit is connected to Negative terminal of PWM comparator 2334.
电流采样模块2331的输入端连接上边功率管2322以采集上边功率管峰值电流(比较电路233的采样输入端连接驱动功率管电路232的峰值采样端)，斜 坡电路的输入端2332(比较电路233的斜坡输入端)连接栅极驱动电路2321的第一输出端以及栅极驱动电路2321的输入端(驱动功率管电路232的驱动输出端)，PWM比较器2334的输出端(PWM比较输出端)连接SR触发器的S端(逻辑触发电路231的第一触发端)，用于采集驱动上边功率管2322(驱动功率管电路232)输出的峰值采样电流，并根据SR触发器的驱动电流生成斜坡信号，将驱动功率管电路232的输入电流与斜坡信号相加作为斜坡比较信号，并将斜坡比较信号输入PWM比较器2334的正极，PWM比较器2334的负极输入的电压信号Vc。The input end of the current sampling module 2331 is connected to the upper power tube 2322 to collect the upper power tube peak current (the sampling input end of the comparison circuit 233 is connected to the peak sampling end of the drive power tube circuit 232), the input end 2332 of the ramp circuit (the input end of the comparison circuit 233 Slope input terminal) is connected to the first output terminal of the gate drive circuit 2321 and the input terminal of the gate drive circuit 2321 (the drive output terminal of the driving power tube circuit 232), and the output terminal of the PWM comparator 2334 (PWM comparison output terminal) is connected to The S terminal of the SR flip-flop (the first trigger end of the logic trigger circuit 231) is used to collect and drive the peak sampling current output by the upper side power tube 2322 (drive power tube circuit 232), and generate a ramp signal according to the driving current of the SR flip-flop , add the input current of the drive power tube circuit 232 to the ramp signal as a ramp comparison signal, and input the ramp comparison signal to the positive pole of the PWM comparator 2334, and the voltage signal Vc input to the negative pole of the PWM comparator 2334.
外部反馈电路220包括用于采样各支路的负载电感Ln另一端(驱动功率管电路的电压输出端连接处)的比例采样电路221和第一比较器222，第一比较器222的正端输入基准电压VREF，负端连接比例采样电路220的输出端，第一比较器222的输出端分别连接各支路中PWM比较器2334的负端，将Vc与预设基准电压VREF比较做差。The external feedback circuit 220 includes a proportional sampling circuit 221 and a first comparator 222 for sampling the other end of the load inductance Ln of each branch (connecting the voltage output end of the drive power tube circuit) and the first comparator 222, the positive terminal input of the first comparator 222 The negative end of the reference voltage VREF is connected to the output end of the proportional sampling circuit 220, and the output end of the first comparator 222 is respectively connected to the negative end of the PWM comparator 2334 in each branch, and Vc is compared with the preset reference voltage VREF.
如下对附图1b的工作过程做具体分析说明：The working process of accompanying drawing 1b is described in detail as follows:
每一支路在它的开启相位控制下的工作机理，与传统的峰值电流模式直流转换器工作机理一样。以第一支路为例，当时钟CLK1上升沿到来时，连接至RS触发器的S端使得触发器置位，Q输出高电平,经过栅极驱动电路2321输出PWMP1，打开上边功率管，给该支路的L1和Cout充电储能，同时该PWMP1信号控制斜坡电路开始产生上升斜坡，该上升沿斜坡与电流采样得到的信号加和转换为Vramp信号，该信号在PWMP1没有变化前一直为上升斜坡。电压环路将VOUT采样后连接至运算放大器的负向输入端，与基准进行比较。在PWMP1控制上边功率管打开的过程中，VOUT电压逐渐上升，至稍稍大于目标设定值，此时运算 放大器对比误差后的控制输出Vc稍稍降低。当Vramp上升斜坡从下往上刚刚穿越Vc的时刻，PWM比较器的输出由低变高，对RS触发器的R端进行复位，使得输出Q由高电平变为低电平，经过驱动电路后控制PWMP1关闭上边管，经过一个死区时间后打开下边管对电感续流，完成充电储能周期。控制上边管的PWMP1信号的脉冲宽度，与时钟周期的比值，即为占空比D。The working mechanism of each branch under its turn-on phase control is the same as that of a conventional peak current mode DC converter. Taking the first branch as an example, when the rising edge of the clock CLK1 arrives, it is connected to the S terminal of the RS flip-flop to set the flip-flop, Q outputs a high level, outputs PWMP1 through the gate drive circuit 2321, and turns on the upper power transistor. Charge and store energy to L1 and Cout of the branch, and at the same time, the PWMP1 signal controls the ramp circuit to start generating a rising ramp, and the rising ramp and the signal obtained by current sampling are summed and converted into a Vramp signal, which is always Vramp before PWMP1 does not change. Ramp up. The voltage loop samples VOUT and connects it to the negative input of the op amp for comparison with the reference. During the process of PWMP1 controlling the upper power transistor to turn on, the VOUT voltage gradually rises until it is slightly greater than the target setting value. At this time, the control output Vc of the operational amplifier is slightly lowered after the comparison error. When the rising slope of Vramp has just crossed Vc from bottom to top, the output of the PWM comparator changes from low to high, and the R terminal of the RS flip-flop is reset, so that the output Q changes from high level to low level, and passes through the driving circuit Finally, PWMP1 is controlled to turn off the upper tube, and after a dead time, the lower tube is turned on to continue the inductor to complete the charging and energy storage cycle. The ratio of the pulse width of the PWMP1 signal controlling the upper side tube to the clock period is the duty cycle D.
因此每一支路的电感电流峰值，可以被环路中的Vc控制。等式为：Therefore, the peak value of the inductor current in each branch can be controlled by Vc in the loop. The equation is:
Vc＝Vramp(peak)------------------------------------------(1)Vc＝Vramp(peak) ------------------------------------------(1 )
Vramp(peak)＝(Iramp1(peak)+Ip1(peak))*Rramp1---------------(2)Vramp(peak) ＝(Iramp1(peak) +Ip1(peak) )*Rramp1 ---------------(2)
同理支路2的电感电流峰值与Vramp关系为：Similarly, the relationship between the peak inductor current and Vramp of branch 2 is:
Vramp(peak)＝(Iramp2(peak)+Ip2(peak))*Rramp2---------------(3)Vramp(peak) ＝(Iramp2(peak) +Ip2(peak) )*Rramp2 ---------------(3)
典型的三角锯齿波的实现方式是通过电容充放电来得到，即I*t＝V*C，因此，集成电路中可以通过版图的优化匹配设计近似实现Iramp1(peak)＝Iramp2(peak)，结合(1)～(3)式，配合Rramp电阻的修调手段，可以得到两个支路的电感电流峰值Ip1和Ip2近似相等。A typical implementation of a triangular sawtooth wave is obtained by charging and discharging a capacitor, that is, I*t=V*C. Therefore, in an integrated circuit, Iramp1(peak)=Iramp2(peak) can be approximately realized by optimizing the matching design of the layout, combining (1) ~ (3), with the adjustment means of Rramp resistance, the peak value of the inductor current Ip1 and Ip2 of the two branches can be obtained approximately equal.
因此，本发明的电流均衡策略，依赖于保证电感电流的峰值相等，在忽略每条支路的电感大小差异的情况下，可以实现每支路输出的均值电流相等。Therefore, the current balancing strategy of the present invention relies on ensuring that the peak values of the inductor currents are equal, and can achieve equal output average currents of each branch while ignoring the difference in the inductance of each branch.
在以上方案的基础上，进一步的，多相时钟控制单元210，包括相位控制单元211、时钟输出单元212、峰值采样加法电路、比例电路214以及ADC阈值判断电路215。各支路的峰值电流采样电路216(比较电路的峰值采样输出端)的输出端连接峰值采样加法电路的输入端，峰值采样加法电路的输出端连接比例电路214的输入端，比例电路214的输出端连接ADC阈值判断电路215的输入端，ADC阈值判断电路215的输出端连接相位控制单元211的输入端，相位 控制单元211的输出端连接时钟输出单元212的时钟生成输入端CLK，时钟输出单元212的输出端连接各支路中RS触发器的S端。On the basis of the above solution, further, the multi-phase clock control unit 210 includes a phase control unit 211 , a clock output unit 212 , a peak sampling addition circuit, a proportional circuit 214 and an ADC threshold judgment circuit 215 . The output end of the peak current sampling circuit 216 (the peak sampling output end of the comparison circuit) of each branch is connected to the input end of the peak sampling addition circuit, and the output end of the peak sampling addition circuit is connected to the input end of the proportional circuit 214, and the output of the proportional circuit 214 is end is connected to the input end of the ADC threshold judgment circuit 215, and the output end of the ADC threshold judgment circuit 215 is connected to the input end of the phase control unit 211, and the output end of the phase control unit 211 is connected to the clock generation input terminal CLK of the clock output unit 212, and the clock output unit The output end of 212 is connected to the S end of the RS flip-flop in each branch.
相位控制单元211，用于根据电流阈值比较结果阈值判断电路的输出信号控制各支路使能的开启状态；时钟输出单元212，用于根据相位控制单元输入的开启的支路个数N输出相位差依次相差为的时钟信号给开启支路的SR触发器的S端。其时钟输出端连接各支路的SR触发器的R端，用于为开启的支路输出相位差依次相差为的时钟信号,N为开启的支路的个数，开启的支路为负载电感Ln的一端(驱动功率管电路的电压输出端)有输出电压的支路。其中匹配负载的一端连接该支路中驱动功率管电路的电压输出端，各支路的匹配电感Ln的另一端连接作为总电压输出端。The phase control unit 211 is used to control the enabled state of each branch according to the output signal of the current threshold comparison result threshold judgment circuit; the clock output unit 212 is used to output the phase according to the number N of opened branches input by the phase control unit The clock signal with a phase difference of 0 is given to the S terminal of the SR flip-flop that opens the branch. Its clock output terminal is connected to the R terminal of the SR flip-flop of each branch, which is used to output a clock signal with a phase difference of 2 for the opened branch, N is the number of opened branches, and the opened branch is the load inductance One end of Ln (the voltage output end of the drive power tube circuit) has a branch of the output voltage. One end of the matching load is connected to the voltage output end of the driving power tube circuit in the branch, and the other end of the matching inductance Ln of each branch is connected as the total voltage output end.
其中，峰值采样加法电路包括各支路的采样保持电路2131和加法器2132，各支路比较电路2131的峰值采样输出端分别连接各支路的采样保持电路2132的输入端，各支路采样保持电路2132的输出端均连接加法器2131的输入端，加法器2131的输出端连接比例电路214的输入端。Wherein, the peak sampling and adding circuit comprises the sampling and holding circuit 2131 and the adder 2132 of each branch, and the peak sampling output terminal of each branch comparing circuit 2131 is respectively connected to the input of the sampling and holding circuit 2132 of each branch, and each branch sampling and holding The output ends of the circuit 2132 are all connected to the input ends of the adder 2131 , and the output ends of the adder 2131 are connected to the input end of the proportional circuit 214 .
其中，相位控制单元211包括电源输入端,接入外部电压AVDD、N个串联分压电阻RN、N-1个电流比较器CMP1-CMPN-1，将比例电路输出端接入各电流比较器CMP1-CMPN-1的正端，相邻两分压电阻的连接处连接各电流比较器CMP1-CMPN-1的负端,电流比较器CMP1-CMPN-1的输出端均连接ADC阈值判断电路215的输入端，ADC阈值判断电路215的输出端连接时钟输出单元212的输入端。Among them, the phase control unit 211 includes a power supply input terminal, which is connected to an external voltage AVDD, N series voltage dividing resistors RN, and N-1 current comparators CMP1-CMPN-1, and connects the output terminals of the proportional circuit to each current comparator CMP1 - the positive terminal of CMPN-1, the connection of two adjacent voltage divider resistors is connected to the negative terminal of each current comparator CMP1-CMPN-1, and the output terminals of the current comparator CMP1-CMPN-1 are all connected to the ADC threshold judgment circuit 215 The input end, the output end of the ADC threshold judgment circuit 215 is connected to the input end of the clock output unit 212 .
例如：以图2中的四相为例，将负载区间分为(Iload<Ith1)，(Ith1<Iload<Ith2)，(Ith2<Iload<Ith3)，(Ith3<Iload<Iocp)，其中 Iocp为过流保护阈值，此处不就该阈值展开讨论。For example: taking the four phases in Figure 2 as an example, the load range is divided into (Iload<Ith1), (Ith1<Iload<Ith2), (Ith2<Iload<Ith3), (Ith3<Iload<Iocp), where Iocp is The overcurrent protection threshold is not discussed here.
后续连接的3个迟滞比较器以及逻辑控制部分帮助完成模拟阈值到数字控制信号的转换。根据负载电流分段后对相位数进行判断和控制。表1是以四相举例的，对应图2的接口，扩展为N相的逻辑控制表如表2所示。EN表示整个多相BUCK的使能，优先级最高，EN为0时，所有模块关闭，同时图2中的输出Phase1EN～Phase4EN输出为低电平逻辑0，表示所有支路处于关闭不工作状态。ENall表示所有支路是否处于开启工作状态，优先级高于分段比较器比较出来的结果，即ENall为高电平逻辑1时，强制打开所有支路，ENall为低电平逻辑0时，分段比较器对负载电流进行位置判断才开始生效，从而控制处于几个支路打开的状态。CMP1～CMP3分别代表比较器输出状态，Phase1EN～Phase4EN分别代表1支路到4支路的开启控制状态。The 3 hysteresis comparators and the logic control part connected subsequently help to complete the conversion of the analog threshold value to the digital control signal. The number of phases is judged and controlled according to the load current segmentation. Table 1 is an example of four phases. Corresponding to the interface in Figure 2, the logical control table expanded to N phases is shown in Table 2. EN indicates the enablement of the entire multi-phase BUCK, with the highest priority. When EN is 0, all modules are closed, and the outputs Phase1EN~Phase4EN in Figure 2 are low-level logic 0, indicating that all branches are closed and not working. ENall indicates whether all branches are in the open working state, and the priority is higher than the comparison result of the sub-section comparator, that is, when ENall is high logic 1, all branches are forced to open; when ENall is low logic 0, the division The section comparator judges the position of the load current before it becomes effective, so that the control is in the state of opening several branches. CMP1～CMP3 respectively represent the output state of the comparator, and Phase1EN～Phase4EN represent the open control states of 1 branch to 4 branches respectively.
表1四相使能逻辑控制表Table 1 Four-phase enable logic control table
当负载电流处于(Iload<Ith1)区间时，此时CMP1～CMP3输出为低电平 逻辑，对应逻辑控制输出只有Phase1EN为1，只有支路1开启工作，为传统的单相峰值电流模式直流转换器，其余的支路不工作，因此电流耗费只有一个支路，降低了动态损耗，如负载效率示意图图3中的①段，负载电流更小时进入PSM工作模式，与传统的单相峰值电流模式的直流转换器类似，这里不做赘述。When the load current is in the (Iload<Ith1) range, the output of CMP1~CMP3 is low-level logic at this time, and the corresponding logic control output is only Phase1EN is 1, and only branch 1 is turned on, which is the traditional single-phase peak current mode DC conversion The rest of the branches do not work, so the current consumption is only one branch, which reduces the dynamic loss, such as the load efficiency schematic diagram in Figure 3, paragraph ①, when the load current is smaller, it enters the PSM working mode, which is different from the traditional single-phase peak current mode The DC converter is similar and will not be described here.
当负载电流处于(Ith1<Iload<Ith2)区间时，此时CMP1对负载电流和参考设计阈值进行比较后，输出高电平逻辑1，Phase1EN和Phase2EN均为高，控制除第1支路开启外的第2支路增加开启，两个支路错相位工作，时钟波形如图4所示，每个时钟沿相差1/2个周期，即相位相差。此时负载电流如果减小到小于Ith1，仍然以两相位工作，开关功耗增大使得效率变低，相反负载电流如果增大超出Ith2，由于导通损耗占比增加，两相工作效率也会变低，如对应图3中的②段曲线所示。When the load current is in the range (Ith1<Iload<Ith2), after comparing the load current with the threshold of the reference design, CMP1 outputs a high-level logic 1, Phase1EN and Phase2EN are both high, and the control except the opening of the first branch The second branch is added to be turned on, and the two branches work out of phase. The clock waveform is shown in Figure 4. The difference between each clock edge is 1/2 period, that is, the phase difference. At this time, if the load current is reduced to be less than Ith1, the two-phase operation is still performed, and the switching power consumption increases to reduce the efficiency. On the contrary, if the load current increases beyond Ith2, the two-phase operation efficiency will increase due to the increase in the conduction loss ratio. becomes lower, as shown in the curve corresponding to paragraph ② in Figure 3.
当负载电流处于(Ith2<Iload<Ith3)区间时，CMP1和CMP2对负载电流和参考设计阈值进行比较后，输出高电平逻辑1，Phase1EN、Phase2EN和Phase3EN均为高，控制除第1支路开启外的第2支路和第3支路增加开启，三个支路错相位工作，时钟波形如图5所示，每个时钟沿相差1/3个周期，即相位相差。负载、相位以及效率图如图3中的③段曲线所示。When the load current is in the interval (Ith2<Iload<Ith3), CMP1 and CMP2 will output a high level logic 1 after comparing the load current with the threshold value of the reference design, Phase1EN, Phase2EN and Phase3EN are all high, and the control except the first branch The 2nd branch and the 3rd branch are added to be turned on, and the three branches work out of phase. The clock waveform is shown in Figure 5. The difference between each clock edge is 1/3 period, that is, the phase difference. The load, phase and efficiency diagrams are shown in the curve of section ③ in Figure 3.
当负载电流处于(Ith3<Iload<Iocp)区间时，CMP1、CMP2和CMP3对负载电流和参考设计阈值进行比较后，输出高电平逻辑1，Phase1EN、Phase2EN、Phase3EN和Phase4EN均为高，控制所有四个支路开启，四个支路错相位工作，每个时钟沿相差1/4个周期，即相位相差。负载、相位以及效率图如图3中的④段曲线所示。When the load current is in the (Ith3<Iload<Iocp) range, CMP1, CMP2 and CMP3 will output a high-level logic 1 after comparing the load current with the reference design threshold, Phase1EN, Phase2EN, Phase3EN and Phase4EN are all high, controlling all The four branches are turned on, and the four branches work in staggered phases. The difference between each clock edge is 1/4 period, that is, the phase difference. The graph of load, phase and efficiency is shown in the curve of section ④ in Figure 3.
另外，需要特别提示的是，实际的负载并不是稳定的电流，一般是动态变 化的，尤其在分段点附近，比如负载等于Ith1、Ith2、Ith3附近，在利用比较器实现上述负载分段控制相位个数的实施方案里，为防止负载的轻微动态变化引起相位数频繁切换，比较器采用迟滞比较器。同时利用时钟信号如图2所示的CLK信号，对判断中的毛刺进行滤除，经过一个或多个时钟周期稳定后，送出稳定的逻辑判断值。迟滞比较器和利用时钟周期滤除毛刺为基本模拟和数字电路的常识性技术，在此不做赘述。In addition, it needs to be specially reminded that the actual load is not a stable current, and generally changes dynamically, especially near the segmentation point, such as the load is equal to Ith1, Ith2, and Ith3, when using the comparator to realize the above load segmentation control In the implementation of the number of phases, in order to prevent frequent switching of the number of phases caused by slight dynamic changes in the load, the comparator uses a hysteresis comparator. At the same time, use the clock signal CLK signal shown in Figure 2 to filter out the burrs in the judgment, and after one or more clock cycles are stabilized, a stable logic judgment value is sent. Hysteretic comparators and glitch filtering using clock cycles are common-sense techniques for basic analog and digital circuits and will not be described here.
经过本方案实现后的多相交错并联直流转换器在整个负载范围内根据负载区间情况，自动控制相位数目的增减，来达到导通损耗和开关损耗的合理化配置，最终实现的效率图从图3变为图6，从而满足整个负载范围内的效率提升。After the implementation of this scheme, the multi-phase interleaved parallel DC converter automatically controls the increase or decrease of the number of phases according to the load interval in the entire load range to achieve a rational configuration of conduction loss and switching loss. The final efficiency diagram is shown in Fig. 3 becomes Figure 6, so as to meet the efficiency improvement in the whole load range.
表2 N相使能逻辑Table 2 N-phase enable logic
另外，在本方案列举的一个实施举例中，因为迟滞比较器的引入，以及利用时钟周期进行数字滤波，滤除负载动态变化中的毛刺，如图7所示，负载因为扰动或其他原因在某个时间内的瞬间波动，不希望相位数随之突然变化，避免了频繁切换。图7以1个时钟周期的数字滤波时间为例，在一个时钟周期内的瞬态波动，都会被作为毛刺滤除。图中在t1时刻有个负载的抖动，穿越了负载分段阈值Ith1，但随即返回正常的状态，比较器判断后得到数字滤波前的支路控制信号做出了要打开两相支路供电的逻辑信号，经过数字滤波后，(图示举例为1个CLK周期)，实际送出的支路控制信号为稳态后的值，因此，并未作出增加 第2支路开启的动作，避免的支路个数因为异常抖动的频繁切换。In addition, in an implementation example listed in this solution, due to the introduction of the hysteresis comparator and the use of clock cycles for digital filtering, the glitches in the dynamic change of the load are filtered out. Instantaneous fluctuations within a period of time, do not want the number of phases to change suddenly, avoiding frequent switching. Figure 7 takes the digital filter time of one clock cycle as an example, and the transient fluctuations within one clock cycle will be filtered out as burrs. In the figure, there is a load jitter at time t1, which crosses the load segmentation threshold Ith1, but then returns to the normal state. After the comparator judges, it obtains the branch control signal before digital filtering and makes a decision to turn on the two-phase branch power supply. After the logic signal is digitally filtered (1 CLK cycle is shown in the figure), the branch control signal actually sent is the value after the steady state. Therefore, no action is taken to increase the opening of the second branch to avoid branch The number of channels is frequently switched due to abnormal jitter.
但另一方面，由于本发明方案对异常毛刺的滤除，使得对真实的负载瞬间变化变得不敏感。比如图7中的电流毛刺是一个真实的大幅度变化，如图8所示。处理器真实工作场景负载，动态变化范围大，需要供电的直流转换器能做出快速的判断以免输出电压出现跌落。在t1时刻负载从一个较低电流突然变为一个大电流，该电流突变并非毛刺。But on the other hand, because the solution of the present invention filters out abnormal burrs, it becomes insensitive to real instantaneous load changes. For example, the current glitch in Figure 7 is a real large change, as shown in Figure 8. The real working scene load of the processor has a large dynamic range, and the DC converter that needs to be powered can make a quick judgment to avoid the output voltage from dropping. At time t1, the load suddenly changes from a low current to a high current, and the sudden change in current is not a glitch.
在以上方案的基础上，多相时钟控制单元210还包括临界比较器217，临界比较器217的第一比较端连接比例采样电路的输出端，第二比较端连接预设使能电压临界值VREF-Vav，临界比较器217的输出端连接多相控制单元211的ENall端(多相时钟控制单元的全支路使能端)。电容Cout的一端连接负载电感Ln的另一端(各支路230的驱动功率管电路的电压输出端)，电容Cout的另一端接地。On the basis of the above scheme, the multi-phase clock control unit 210 also includes a critical comparator 217, the first comparison terminal of the critical comparator 217 is connected to the output terminal of the proportional sampling circuit, and the second comparison terminal is connected to the preset enabling voltage threshold VREF - Vav, the output terminal of the critical comparator 217 is connected to the ENall terminal of the multi-phase control unit 211 (the all-branch enable terminal of the multi-phase clock control unit). One end of the capacitor Cout is connected to the other end of the load inductance Ln (the voltage output end of the driving power tube circuit of each branch 230 ), and the other end of the capacitor Cout is grounded.
图8描述了本发明方案中的另一个技术细节，快速电压判断机制。结合图1b本发明的N相交错并联直流转换器结构图，输出电压VOUT反馈采样的VFB与VREF-Vuv进行比较，低于VREF-Vuv后比较器翻转送出优先级较高的ENall信号。ENall信号相比负载分段控制相位支路个数的优先级高，前面逻辑表格已经表述，也可见图9逻辑优先级关系。对应在图8中，该Vuv的设计可以控制在VOUT跌落低于97％的VOUT预设值时，触发比较器释放ENall信号，将所有相位支路全部开启，以最大能力给负载供电，避免输出电压的进一步跌落，经过一段稳定时间B后，进入负载分段判断机制，判断C段的负载区间，决定相位支路需要关断的个数。FIG. 8 describes another technical detail in the solution of the present invention, the fast voltage judgment mechanism. Combining with the structure diagram of N-phase interleaved parallel DC converter of the present invention in Fig. 1b, the VFB of the output voltage VOUT feedback sampling is compared with VREF-Vuv, and when it is lower than VREF-Vuv, the comparator flips and sends the ENall signal with higher priority. The priority of the ENall signal is higher than that of the number of phase branches controlled by the load segment. The previous logic table has been expressed, and the logic priority relationship in Figure 9 can also be seen. Corresponding to Figure 8, the Vuv design can be controlled to trigger the comparator to release the ENall signal when VOUT drops below 97% of the VOUT preset value, and turn on all phase branches to supply power to the load with the maximum capacity and avoid output When the voltage drops further, after a period of stabilization time B, it enters the load segment judgment mechanism to judge the load range of segment C and determine the number of phase branches that need to be shut down.
综上，本发明一种多相交错并联直流转换器：基于峰值电流与公共电压回路实现了各相位支路的峰值电流均衡，进而在电感感值差异可忽略的情况先实现平均电流均衡，避免了引入运算放大器，节省硬件开销；本发明提出了利用ADC判断负载区间，利用分段技术控制自动切换相位个数，以及控制多相位时钟发生器，实现整个负载范围内保持较高效率；本发明直接采用内部上边功率管的峰值电流进行加和计算，并利用峰值电流和的信息进行负载区间分段的判断，在集成电路实现时无需额外的电流采样管脚；本发明在负载电流分段控制基础上，增加了快速电压跌落判断作为负载分段控制相位个数的补充，保证相位个数不频繁切换的基础上，同时也不降低直流转换器的快速响应能力；In summary, a multi-phase interleaved parallel DC converter of the present invention: based on the peak current and common voltage loops, the peak current balance of each phase branch is realized, and then the average current balance is realized first when the difference in inductance value is negligible, avoiding In order to introduce an operational amplifier to save hardware overhead; the present invention proposes to use the ADC to judge the load interval, use the segmentation technology to control the number of automatic switching phases, and control the multi-phase clock generator to maintain high efficiency in the entire load range; the present invention The peak current of the internal upper power tube is directly used for sum calculation, and the information of the peak current sum is used to judge the load interval segmentation, and no additional current sampling pin is required when the integrated circuit is implemented; the present invention controls the load current in segments On the basis, the rapid voltage drop judgment is added as a supplement to the number of phases controlled by the load segment to ensure that the number of phases is not switched frequently, and at the same time it does not reduce the fast response capability of the DC converter;
注意，上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的范围由所附的权利要求范围决定。Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention, and the present invention The scope is determined by the scope of the appended claims.
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| CN201610473086.9ACN107546977B (en) | 2016-06-24 | 2016-06-24 | A kind of multiphase interleaving direct current transducer |
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| CN201610473086.9ACN107546977B (en) | 2016-06-24 | 2016-06-24 | A kind of multiphase interleaving direct current transducer |
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