技术领域technical field
本发明涉及半导体制造领域，尤其涉及一种3D NAND闪存结构及其制作方法，特别是一种能简化ONO栅极绝缘堆叠结构刻蚀工艺的沟道孔的制备工艺。The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND flash memory structure and a manufacturing method thereof, in particular to a preparation process of a channel hole that can simplify the etching process of an ONO gate insulating stack structure.
背景技术Background technique
随着平面型闪存存储器的发展，半导体的生产工艺取得了巨大的进步。但是最近几年，平面型闪存的发展遇到了各种挑战：物理极限，现有显影技术极限以及存储电子密度极限等。在此背景下，为解决平面闪存遇到的困难以及最求更低的单位存储单元的生产成本，各种不同的三维(3D)闪存存储器结构应运而生，例如3D NOR(3D或非)闪存和3D NAND(3D与非)闪存。With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory.
其中，在NOR型结构的3D闪存中，存储单元在位线和地线之间并联排列，而在NAND型结构的3D闪存中，存储单元在位线和地线之间串列排列。具有串联结构的NAND型闪存具有较低的读取速度，但是却具有较高的写入速度，从而NAND型闪存适合用于存储数据，其优点在于体积小、容量大。闪存器件根据存储单元的结构可分为叠置栅极型和分离栅极型，并且根据电荷存储层的形状分为浮置栅极器件和硅-氧化物-氮化物-氧化物(SONO)器件。其中，SONO型闪存器件具有比浮置栅极型闪存器件更优的可靠性，并能够以较低的电压执行编程和擦除操作，且ONOS型闪存器件具有很薄的单元，并且便于制造。Wherein, in the 3D flash memory of the NOR structure, memory cells are arranged in parallel between the bit line and the ground line, while in the 3D flash memory of the NAND structure, the memory cells are arranged in series between the bit line and the ground line. The NAND flash memory with a serial structure has a lower reading speed but a higher writing speed, so the NAND flash memory is suitable for storing data, and has the advantages of small size and large capacity. Flash memory devices can be divided into stacked gate type and split gate type according to the structure of the memory cell, and into floating gate devices and silicon-oxide-nitride-oxide (SONO) devices according to the shape of the charge storage layer . Among them, the SONO type flash memory device has better reliability than the floating gate type flash memory device, and can perform program and erase operations at a lower voltage, and the ONOS type flash memory device has very thin cells and is easy to manufacture.
通常，采用PECVD、HDPCVD、UHVCVD、MOCVD、MBE、ALD等工艺，在深的沟道孔中依次沉积形成栅极绝缘堆叠和保护层。栅极绝缘堆叠包括多个子层，例如至少包括隧穿层、存储层、阻挡层，阻挡层直接接触沟道孔侧壁的O/N堆叠结构，隧穿层最靠近沟道孔中心轴线并接触后续沉积的保护层。其中隧穿层可以为SiO2等。存储层是具有电荷俘获能力的介质材料，例如SiN、SiON等。阻挡层可以是氧化硅、氧化铝、氧化铪等介质材料。而保护层的材质可以包括单晶硅、非晶硅、多晶硅、微晶硅、单晶锗等半导体材料，用作后续刻蚀的保护层，其厚度例如为1～10nm。并且为了更为保险的形成对于ONO栅极绝缘堆叠结构的保护，也还会再保护层的表面再沉积一层氧化物层，以强化保护的效果。Usually, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD and other processes are used to sequentially deposit gate insulating stacks and protective layers in deep trench holes. The gate insulation stack includes a plurality of sublayers, for example, at least including a tunneling layer, a storage layer, and a barrier layer. The barrier layer directly contacts the O/N stack structure of the sidewall of the channel hole, and the tunneling layer is closest to the central axis of the channel hole and contacts Subsequent deposition of protective layers. Wherein the tunneling layer may be SiO2 or the like. The storage layer is a dielectric material with charge trapping capability, such as SiN, SiON, etc. The barrier layer can be made of dielectric materials such as silicon oxide, aluminum oxide, and hafnium oxide. The material of the protective layer may include semiconductor materials such as monocrystalline silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, and single-crystalline germanium, used as a protective layer for subsequent etching, and its thickness is, for example, 1˜10 nm. And in order to form a more secure protection for the ONO gate insulation stack structure, an oxide layer will be deposited on the surface of the protection layer to strengthen the protection effect.
具体的，请参考图1a-1g，现有技术中3D NAND闪存的制作方法中ONO栅极绝缘堆叠通常采用如下工艺：Specifically, please refer to Figures 1a-1g. In the manufacturing method of 3D NAND flash memory in the prior art, the ONO gate insulation stack usually adopts the following process:
S1：沉积栅极绝缘堆叠结构，参见图1a，具体为，在O/N堆叠结构中的沟道1的侧壁及硅外延层2的表面上沉积栅极绝缘堆叠结构3，所述栅极绝缘堆叠结构3为ONO(阻挡层3-1/存储层3-2/隧穿层3-3)的堆叠结构；S1: Deposit a gate insulation stack structure, see FIG. 1a, specifically, deposit a gate insulation stack structure 3 on the sidewall of the channel 1 and the surface of the silicon epitaxial layer 2 in the O/N stack structure, and the gate The insulating stack structure 3 is a stack structure of ONO (barrier layer 3-1/storage layer 3-2/tunneling layer 3-3);
S2：沉积多晶硅保护层，参见图1b，具体为，在所述隧穿层3-3的表面进行第一次多晶硅沉积以形成多晶硅保护层4；S2: Deposit a polysilicon protection layer, see FIG. 1b, specifically, perform the first polysilicon deposition on the surface of the tunneling layer 3-3 to form a polysilicon protection layer 4;
S3：回刻多晶硅保护层，参见图1c；S3: etching back the polysilicon protection layer, see FIG. 1c;
S4：沉积氧化物保护层，参见图1d，具体为，在所述多晶硅保护层表面沉积氧化物以形成氧化物保护层5；S4: Depositing an oxide protection layer, referring to FIG. 1d, specifically, depositing oxide on the surface of the polysilicon protection layer to form an oxide protection layer 5;
S5：刻蚀栅极绝缘堆叠结构，参见图1e，具体为，通过常规刻蚀工艺刻蚀所述栅极绝缘堆叠结构的底部通至硅外延层2并形成一定深度的沟槽6；S5: Etching the gate insulation stack structure, referring to FIG. 1e, specifically, etching the bottom of the gate insulation stack structure to the silicon epitaxial layer 2 through a conventional etching process and forming a trench 6 with a certain depth;
S6：去除所述氧化物保护层5和多晶硅保护层4，参见图1f；S6: removing the oxide protection layer 5 and the polysilicon protection layer 4, see FIG. 1f;
S7：沉积多晶硅连接层，参见图1g，具体为，在所述隧穿层3-3和硅外延层的沟槽表面进行第二次多晶硅沉积以形成多晶硅连接层7，从而将硅外延层2与漏极相连通。S7: Deposit a polysilicon connection layer, see FIG. 1g, specifically, perform a second polysilicon deposition on the trench surface of the tunneling layer 3-3 and the silicon epitaxial layer to form a polysilicon connection layer 7, so that the silicon epitaxial layer 2 connected to the drain.
然而在上述常规工艺中，氧化物保护层的厚度一般在4nm左右，采用ALD的沉积工艺步骤非常难以控制；并且，在完成刻蚀栅极绝缘堆叠结构的工艺步骤后，为避免多晶硅界面的出现，优选将多晶硅保护层和氧化物保护层都去除掉，以后续顺利的进行第二次多晶硅沉积，并获得更好的多晶硅连接层，因此实际上，多晶硅保护层本身并不需要特别完美的保护，也即氧化物保护层在整个工艺过程中的作用并不多；不仅如此，氧化物保护层的沉积还往往导致晶硅保护层和氧化物保护层难以完全被清除，未被清除的残留物将会导致第二次多晶硅沉积形成的多晶硅连接层与第一次多晶硅沉积残留的多晶硅保护层之间形成界面，而影响最终的产品性能。However, in the above-mentioned conventional process, the thickness of the oxide protective layer is generally about 4nm, and the deposition process steps using ALD are very difficult to control; and, after the process step of etching the gate insulating stack structure is completed, in order to avoid the appearance of the polysilicon interface , it is preferable to remove both the polysilicon protection layer and the oxide protection layer, so that the second polysilicon deposition can be carried out smoothly, and a better polysilicon connection layer can be obtained, so in fact, the polysilicon protection layer itself does not need particularly perfect protection , that is, the oxide protection layer does not play much role in the whole process; not only that, but the deposition of the oxide protection layer often makes it difficult to completely remove the crystal silicon protection layer and the oxide protection layer, and the residues that have not been removed This will lead to the formation of an interface between the polysilicon connection layer formed by the second polysilicon deposition and the polysilicon protection layer left by the first polysilicon deposition, thereby affecting the performance of the final product.
因此，如何简化上述ONO栅极绝缘堆叠的形成工艺，避免上述问题的出现，一直为本领域技术人员所致力研究的方向。Therefore, how to simplify the formation process of the above-mentioned ONO gate insulation stack and avoid the above-mentioned problems has always been a research direction for those skilled in the art.
发明内容Contents of the invention
本发明的目的在于提供一种3D NAND闪存的制作方法，能够实现简化ONO栅极绝缘堆叠结构的刻蚀工艺，从而提高3D NAND闪存的性能。The purpose of the present invention is to provide a method for manufacturing 3D NAND flash memory, which can simplify the etching process of ONO gate insulating stack structure, thereby improving the performance of 3D NAND flash memory.
为了实现上述目的，本发明提出了3D NAND闪存沟道孔的制备工艺，其包括以下步骤：In order to achieve the above object, the present invention proposes a preparation process for channel holes of 3D NAND flash memory, which comprises the following steps:
沉积栅极绝缘堆叠结构，具体为，在O/N堆叠结构中的沟道侧壁及硅外延层的表面上沉积栅极绝缘堆叠结构；Depositing a gate insulating stack structure, specifically, depositing a gate insulating stack structure on the sidewall of the channel in the O/N stack structure and the surface of the silicon epitaxial layer;
沉积多晶硅保护层，具体为，在所述栅极绝缘堆叠结构表面进行第一次多晶硅沉积以形成多晶硅保护层，所述多晶硅保护层的厚度为12-20nm；Depositing a polysilicon protection layer, specifically, performing the first polysilicon deposition on the surface of the gate insulation stack structure to form a polysilicon protection layer, the thickness of the polysilicon protection layer is 12-20nm;
回刻多晶硅保护层；Etching back the polysilicon protection layer;
刻蚀栅极绝缘堆叠结构，具体为，通过常规刻蚀工艺刻蚀所述栅极绝缘堆叠结构的底部通至硅外延层并形成一定深度的沟槽；Etching the gate insulation stack structure, specifically, etching the bottom of the gate insulation stack structure to the silicon epitaxial layer through a conventional etching process and forming a trench with a certain depth;
沉积多晶硅连接层，具体为，在所述栅极绝缘堆叠结构表面和硅外延层的沟槽表面进行第二次多晶硅沉积以形成多晶硅连接层，从而将硅外延层与漏极相连通。Depositing a polysilicon connection layer, specifically, performing a second polysilicon deposition on the surface of the gate insulation stack structure and the trench surface of the silicon epitaxial layer to form a polysilicon connection layer, so as to connect the silicon epitaxial layer to the drain.
进一步的，所述多晶硅保护层的厚度为14-18nm。Further, the polysilicon protective layer has a thickness of 14-18nm.
进一步的，所述回刻多晶硅保护层后，所述多晶硅保护层的厚度为7-10nm。Further, after the polysilicon protection layer is etched back, the thickness of the polysilicon protection layer is 7-10 nm.
进一步的，所述栅极绝缘堆叠结构为ONO的堆叠结构；优选的，所述ONO的堆叠结构为阻挡层/存储层/隧穿层。Further, the gate insulation stack structure is an ONO stack structure; preferably, the ONO stack structure is a blocking layer/storage layer/tunneling layer.
进一步的，在所述刻蚀栅极绝缘堆叠结构的步骤后、沉积多晶硅连接层前，还包括去除所述多晶硅保护层以露出所述栅极绝缘堆叠结构表面的步骤。Further, after the step of etching the gate insulation stack structure and before depositing the polysilicon connection layer, a step of removing the polysilicon protection layer to expose the surface of the gate insulation stack structure is also included.
进一步的，所述刻蚀栅极绝缘堆叠结构，采用各向异性的刻蚀工艺，垂直向下对所述栅极绝缘堆叠结构的底部进行刻蚀；例如，采用碳氟基等离子干法刻蚀或反应离子刻蚀(RIE)。Further, the etching gate insulation stack structure adopts an anisotropic etching process to etch the bottom of the gate insulation stack structure vertically downward; for example, adopts fluorocarbon-based plasma dry etching Or Reactive Ion Etching (RIE).
本发明还提供一种3D NAND闪存结构，其沟道孔是由前述的制备工艺制备得到。The present invention also provides a 3D NAND flash memory structure, the channel hole of which is prepared by the aforementioned preparation process.
与现有技术相比，本发明的有益效果主要体现在：Compared with the prior art, the beneficial effects of the present invention are mainly reflected in:
第一，通过增加了多晶硅保护层的沉积厚度，形成了对ONO栅极绝缘堆叠结构更好的保护效果，从而可以省略以往常规工艺中的氧化物保护层的沉积步骤，节省了整个工艺流程，提高了效率；First, by increasing the deposition thickness of the polysilicon protection layer, a better protection effect is formed on the ONO gate insulation stack structure, so that the deposition step of the oxide protection layer in the conventional process can be omitted, saving the entire process flow, Improved efficiency;
第二，由于不再有氧化物保护层，从而避免了氧化物保护层去除不净而引起的氧化物残留，也将使得多晶硅保护层的去除更为容易和彻底，进而避免了可能出现的第二次多晶硅沉积界面及缺陷的风险，因此产品性能得以保证；Second, since there is no oxide protective layer anymore, oxide residues caused by unclean removal of the oxide protective layer are avoided, and the removal of the polysilicon protective layer will be easier and more thorough, thereby avoiding possible first The risk of secondary polysilicon deposition interface and defects, so product performance can be guaranteed;
第三，由于不再有氧化物保护层，将有可能获得刻蚀前沟道顶部更为开阔的开口，从而利于深沟道底部的刻蚀。Third, since there is no oxide protection layer anymore, it will be possible to obtain a wider opening at the top of the trench before etching, thereby facilitating the etching of the bottom of the deep trench.
附图说明Description of drawings
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. Also throughout the drawings, the same reference numerals are used to designate the same components. In the attached picture:
图1a-g为现有技术中3D NAND闪存沟道孔的制备工艺流程图；Fig. 1a-g is the preparation process flowchart of the channel hole of 3D NAND flash memory in the prior art;
图2a-e为本发明中3D NAND闪存沟道孔的制备工艺流程图。2a-e are the flow charts of the preparation process of channel holes of 3D NAND flash memory in the present invention.
具体实施方式detailed description
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
为了清楚，不描述实际实施例的全部特征。在下列描述中，不详细描述公知的功能和结构，因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中，必须做出大量实施细节以实现开发者的特定目标，例如按照有关系统或有关商业的限制，由一个实施例改变为另一个实施例。另外，应当认为这种开发工作可能是复杂和耗费时间的，但是对于本领域技术人员来说仅仅是常规工作。In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be recognized that such a development effort might be complex and time consuming, but would nevertheless be merely a routine undertaking for those skilled in the art.
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.
请参考图2，在本实施例中，提出了一种3D NAND闪存沟道孔的制备工艺，包括以下步骤：Please refer to FIG. 2. In this embodiment, a preparation process for channel holes of 3D NAND flash memory is proposed, including the following steps:
S100：沉积栅极绝缘堆叠结构，具体为，在O/N堆叠结构中的沟道侧壁及硅外延层的表面上沉积栅极绝缘堆叠结构；S100: Depositing a gate insulating stack structure, specifically, depositing a gate insulating stack structure on the sidewall of the channel in the O/N stack structure and the surface of the silicon epitaxial layer;
S200：沉积多晶硅保护层，具体为，在所述栅极绝缘堆叠结构表面进行第一次多晶硅沉积以形成多晶硅保护层，所述多晶硅保护层的厚度为12-20nm；S200: Depositing a polysilicon protection layer, specifically, performing the first polysilicon deposition on the surface of the gate insulation stack structure to form a polysilicon protection layer, the thickness of the polysilicon protection layer is 12-20 nm;
S300：回刻多晶硅保护层；S300: engraving back the polysilicon protection layer;
S400：刻蚀栅极绝缘堆叠结构，具体为，通过常规刻蚀工艺刻蚀所述栅极绝缘堆叠结构的底部通至硅外延层并形成一定深度的沟槽；S400: Etching the gate insulation stack structure, specifically, etching the bottom of the gate insulation stack structure to the silicon epitaxial layer through a conventional etching process and forming a trench with a certain depth;
S500：去除所述多晶硅保护层以露出所述栅极绝缘堆叠结构表面；S500: removing the polysilicon protection layer to expose the surface of the gate insulating stack structure;
S600：沉积多晶硅连接层，具体为，在所述栅极绝缘堆叠结构表面和硅外延层的沟槽表面进行第二次多晶硅沉积以形成多晶硅连接层，从而将硅外延层与漏极相连通。S600: Depositing a polysilicon connection layer, specifically, performing a second polysilicon deposition on the surface of the gate insulating stack structure and the trench surface of the silicon epitaxial layer to form a polysilicon connection layer, so as to connect the silicon epitaxial layer to the drain.
具体的，请参考图2a，在步骤S100中，在O/N堆叠结构中的沟道100侧壁及硅外延层110的表面上沉积栅极绝缘堆叠结构120，所述栅极绝缘堆叠结构120为包括多个子层的ONO堆叠结构，具体为，氧化物阻挡层121、氮化物存储层122和氧化物隧穿层123。Specifically, please refer to FIG. 2a. In step S100, a gate insulating stack structure 120 is deposited on the side walls of the channel 100 and the surface of the silicon epitaxial layer 110 in the O/N stack structure. The gate insulating stack structure 120 It is an ONO stack structure including a plurality of sublayers, specifically, an oxide barrier layer 121 , a nitride storage layer 122 and an oxide tunneling layer 123 .
请继续参考图2a，在步骤S200中，在所述栅极绝缘堆叠结构120的所述氧化物隧穿层123的表面进行第一次多晶硅沉积以形成多晶硅保护层130；一方面，为了能够有效替代氧化物保护层发挥的作用，从而对ONO堆叠结构形成足够的保护，所述多晶硅保护层130的厚度应至少为12nm，另一方面，为了后续较为容易彻底地去除多晶硅保护层，所述多晶硅保护层130的厚度应不超过20nm。优选的，所述多晶硅保护层130的厚度为12-20nm，进一步优选为14-18nm。Please continue to refer to FIG. 2a. In step S200, the first polysilicon deposition is performed on the surface of the oxide tunneling layer 123 of the gate insulating stack structure 120 to form a polysilicon protection layer 130; on the one hand, in order to effectively To replace the role played by the oxide protection layer, thereby forming sufficient protection for the ONO stack structure, the thickness of the polysilicon protection layer 130 should be at least 12nm. On the other hand, for subsequent relatively easy and thorough removal of the polysilicon protection layer, the polysilicon The thickness of the protective layer 130 should not exceed 20 nm. Preferably, the polysilicon protective layer 130 has a thickness of 12-20 nm, more preferably 14-18 nm.
请参考图2b，在步骤S300中，回刻多晶硅保护层130，以形成倒锥形的顶部开口140，以更利于后续对深沟道100底部进行刻蚀。回刻后多晶硅保护层130的厚度为7-10nm。Please refer to FIG. 2 b , in step S300 , the polysilicon protection layer 130 is etched back to form an inverted tapered top opening 140 , so as to facilitate subsequent etching of the bottom of the deep trench 100 . The polysilicon protection layer 130 has a thickness of 7-10 nm after etching back.
请参考图2c，在步骤S400中，刻蚀栅极绝缘堆叠结构120，具体为，通过常规刻蚀工艺刻蚀所述栅极绝缘堆叠结构120的底部通至硅外延层110并形成一定深度的沟槽150，其中常规的刻蚀工艺可以为各向异性的刻蚀工艺，例如，采用碳氟基等离子干法刻蚀或反应离子刻蚀(RIE)等，以便于垂直向下对所述栅极绝缘堆叠结构120的底部进行刻蚀，而少刻蚀甚至不刻蚀沟道100侧壁。Please refer to FIG. 2c. In step S400, the gate insulating stack structure 120 is etched, specifically, the bottom of the gate insulating stack structure 120 is etched to the silicon epitaxial layer 110 through a conventional etching process to form a certain depth. The trench 150, wherein the conventional etching process can be an anisotropic etching process, for example, using fluorocarbon-based plasma dry etching or reactive ion etching (RIE), etc., so as to vertically downwardly align the gate The bottom of the pole insulating stack structure 120 is etched, while the sidewalls of the trench 100 are etched less or even not etched.
请参考图2d，在步骤S500中，去除所述多晶硅保护层130以露出所述栅极绝缘堆叠结构120表面，之所以在第二次沉积多晶硅前去除第一次多晶硅沉积形成的所述多晶硅保护层130，是为了获得更好的第二次多晶硅沉积的效果，以避免两次多晶硅沉积造成的界面问题以及多晶硅保护层在刻蚀中产生的晶格损坏等可能导致第二次沉积缺陷的问题。当然，如果上述问题并不严重，亦可以省去多晶硅保护层130的去除步骤而直接进行第二次多晶硅的沉积，以将第一次沉积的多晶硅作为第二次沉积的晶核层。Please refer to FIG. 2d. In step S500, the polysilicon protection layer 130 is removed to expose the surface of the gate insulating stack structure 120. The reason why the polysilicon protection formed by the first polysilicon deposition is removed before the second polysilicon deposition is Layer 130 is to obtain a better effect of the second polysilicon deposition, so as to avoid the interface problem caused by the two polysilicon depositions and the lattice damage caused by the etching of the polysilicon protective layer, which may cause the second deposition defect. . Of course, if the above problems are not serious, the step of removing the polysilicon protection layer 130 can also be omitted and the second polysilicon deposition can be directly performed, so that the first deposited polysilicon can be used as the crystal nucleus layer for the second deposition.
请参考图2e，在步骤S600中，沉积多晶硅连接层160，具体为，在所述栅极绝缘堆叠结构120的所述氧化物隧穿层123的表面和硅外延层110的沟槽150表面进行第二次多晶硅沉积以形成多晶硅连接层160，从而将硅外延层160与漏极(未图示)相连通。Please refer to FIG. 2e. In step S600, a polysilicon connection layer 160 is deposited, specifically, on the surface of the oxide tunneling layer 123 of the gate insulating stack structure 120 and the surface of the trench 150 of the silicon epitaxial layer 110. A second polysilicon deposition is performed to form a polysilicon connection layer 160 to connect the silicon epitaxial layer 160 to the drain (not shown).
综上，通过增加了多晶硅保护层的沉积厚度，形成了对ONO栅极绝缘堆叠结构更好的保护效果，从而可以省略以往常规工艺中的氧化物保护层的沉积步骤，节省了整个工艺流程，提高了效率；同时，由于不再有氧化物保护层，从而避免了氧化物保护层去除不净而引起的氧化物残留，也将使得多晶硅保护层的去除更为容易和彻底，进而避免了可能出现的第二次多晶硅沉积界面及缺陷的风险，因此产品性能得以保证；并且，由于不再有氧化物保护层，将有可能获得刻蚀前沟道顶部更为开阔的开口，从而利于深沟道底部的刻蚀；通过本发明的上述工艺，就能够低成本、高效率的完成ONO堆叠结构的刻蚀，从而提高3D NAND闪存的整体性能。In summary, by increasing the deposition thickness of the polysilicon protection layer, a better protection effect is formed on the ONO gate insulation stack structure, so that the deposition step of the oxide protection layer in the conventional process can be omitted, saving the entire process flow. The efficiency is improved; at the same time, since there is no oxide protection layer anymore, the oxide residue caused by the oxide protection layer being removed is avoided, and the removal of the polysilicon protection layer will be easier and more thorough, thereby avoiding possible The risk of the second polysilicon deposition interface and defects appears, so the product performance can be guaranteed; and, since there is no oxide protective layer, it will be possible to obtain a wider opening on the top of the channel before etching, which is beneficial to deep trenches. The etching of the bottom of the track; through the above process of the present invention, the etching of the ONO stack structure can be completed at low cost and high efficiency, thereby improving the overall performance of the 3D NAND flash memory.
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710726116.7ACN107482017A (en) | 2017-08-22 | 2017-08-22 | A preparation process for channel holes of 3D NAND flash memory |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710726116.7ACN107482017A (en) | 2017-08-22 | 2017-08-22 | A preparation process for channel holes of 3D NAND flash memory |
| Publication Number | Publication Date |
|---|---|
| CN107482017Atrue CN107482017A (en) | 2017-12-15 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710726116.7APendingCN107482017A (en) | 2017-08-22 | 2017-08-22 | A preparation process for channel holes of 3D NAND flash memory |
| Country | Link |
|---|---|
| CN (1) | CN107482017A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108565264A (en)* | 2018-04-13 | 2018-09-21 | 长江存储科技有限责任公司 | The preparation method and semiconductor structure lithographic method of storage string |
| CN109449162A (en)* | 2018-10-16 | 2019-03-08 | 长江存储科技有限责任公司 | The manufacturing method and 3D memory device of 3D memory device |
| CN110690221A (en)* | 2019-12-11 | 2020-01-14 | 长江存储科技有限责任公司 | Method for fabricating a channel structure and storage structure |
| CN110931495A (en)* | 2019-12-11 | 2020-03-27 | 长江存储科技有限责任公司 | Manufacturing method of three-dimensional memory |
| CN111370418A (en)* | 2019-12-26 | 2020-07-03 | 长江存储科技有限责任公司 | Manufacturing method of 3D memory device |
| CN112885838A (en)* | 2020-03-16 | 2021-06-01 | 长江存储科技有限责任公司 | Memory device and method of forming a memory device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103620789A (en)* | 2011-04-11 | 2014-03-05 | 桑迪士克科技股份有限公司 | 3D vertical NAND and method of making thereof by front and back side processing |
| CN105280559A (en)* | 2014-06-04 | 2016-01-27 | 旺宏电子股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN105575909A (en)* | 2016-02-15 | 2016-05-11 | 上海格易电子有限公司 | 3D NAND flash memory and manufacturing method thereof |
| CN105580141A (en)* | 2013-07-10 | 2016-05-11 | 瓦里安半导体设备公司 | Method for Doping Polycrystalline Transistor Channels for Vertical NAND Devices |
| CN105810639A (en)* | 2014-12-31 | 2016-07-27 | 上海格易电子有限公司 | 3D NAND flash memory structure and manufacturing method therefor |
| CN106206507A (en)* | 2015-04-30 | 2016-12-07 | 旺宏电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103620789A (en)* | 2011-04-11 | 2014-03-05 | 桑迪士克科技股份有限公司 | 3D vertical NAND and method of making thereof by front and back side processing |
| CN105580141A (en)* | 2013-07-10 | 2016-05-11 | 瓦里安半导体设备公司 | Method for Doping Polycrystalline Transistor Channels for Vertical NAND Devices |
| CN105280559A (en)* | 2014-06-04 | 2016-01-27 | 旺宏电子股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN105810639A (en)* | 2014-12-31 | 2016-07-27 | 上海格易电子有限公司 | 3D NAND flash memory structure and manufacturing method therefor |
| CN106206507A (en)* | 2015-04-30 | 2016-12-07 | 旺宏电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN105575909A (en)* | 2016-02-15 | 2016-05-11 | 上海格易电子有限公司 | 3D NAND flash memory and manufacturing method thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108565264A (en)* | 2018-04-13 | 2018-09-21 | 长江存储科技有限责任公司 | The preparation method and semiconductor structure lithographic method of storage string |
| CN108565264B (en)* | 2018-04-13 | 2019-08-20 | 长江存储科技有限责任公司 | Preparation method of storage string and semiconductor structure etching method |
| CN109449162A (en)* | 2018-10-16 | 2019-03-08 | 长江存储科技有限责任公司 | The manufacturing method and 3D memory device of 3D memory device |
| CN109449162B (en)* | 2018-10-16 | 2021-02-12 | 长江存储科技有限责任公司 | Manufacturing method of 3D memory device and 3D memory device |
| CN110690221A (en)* | 2019-12-11 | 2020-01-14 | 长江存储科技有限责任公司 | Method for fabricating a channel structure and storage structure |
| CN110931495A (en)* | 2019-12-11 | 2020-03-27 | 长江存储科技有限责任公司 | Manufacturing method of three-dimensional memory |
| CN110690221B (en)* | 2019-12-11 | 2020-06-02 | 长江存储科技有限责任公司 | Method for fabricating a channel structure and storage structure |
| CN111370418A (en)* | 2019-12-26 | 2020-07-03 | 长江存储科技有限责任公司 | Manufacturing method of 3D memory device |
| CN111370418B (en)* | 2019-12-26 | 2021-09-24 | 长江存储科技有限责任公司 | Manufacturing method of 3D memory device |
| CN112885838A (en)* | 2020-03-16 | 2021-06-01 | 长江存储科技有限责任公司 | Memory device and method of forming a memory device |
| Publication | Publication Date | Title |
|---|---|---|
| US20250275142A1 (en) | Microelectronic and electronic devices with shouldered pillars or openings extending through a tiered stack, and related methods | |
| CN107482017A (en) | A preparation process for channel holes of 3D NAND flash memory | |
| US9117923B2 (en) | Three-dimensional semiconductor memory device and a method of fabricating the same | |
| CN107706191B (en) | A kind of 3D nand flash memory channel hole polysilicon articulamentum forming method | |
| CN108695332A (en) | Gate-division type flash memory and forming method thereof, control method | |
| CN107946310B (en) | A preparation method of 3D NAND flash memory using air gap as dielectric layer and flash memory | |
| US20080237680A1 (en) | Enabling flash cell scaling by shaping of the floating gate using spacers | |
| CN111785723B (en) | Manufacturing method of split gate type memory | |
| US8530950B1 (en) | Methods and structures for split gate memory | |
| CN107611130A (en) | The technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures | |
| CN109712981A (en) | Memory and forming method thereof | |
| CN107591409B (en) | The production method of channel structure in a kind of 3D nand flash memory | |
| CN108962896B (en) | Memory | |
| CN107994026A (en) | A kind of technique of the protective side wall in the etching of high-aspect-ratio raceway groove hole | |
| CN107994027B (en) | Method for reducing load effect influence in SONO etching | |
| CN107731824A (en) | A kind of preparation method of 3D nand flash memories | |
| CN111863826A (en) | Method for manufacturing patterned mask and method for manufacturing three-dimensional NAND memory | |
| CN107658222A (en) | A kind of flatening process in 3D nand flash memories raceway groove hole | |
| CN107731839A (en) | A kind of 3D NAND flash memory structures and preparation method thereof | |
| CN107731671B (en) | Process for Improving Diffusion of Ion Implanted Boron in Silicon Epitaxial Growth | |
| CN107731840A (en) | A kind of preparation technology of 3D NAND flash memory structures | |
| CN109148468A (en) | A kind of 3D nand memory | |
| CN107968040A (en) | A kind of technique for improving growing epitaxial silicon uniformity | |
| CN107946311B (en) | Method for controlling channel critical dimensions in 3D NAND flash memory structures | |
| CN107731841A (en) | A kind of method of improvement 3D nand flash memory SEG growth qualities |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | Application publication date:20171215 | |
| RJ01 | Rejection of invention patent application after publication |