技术领域technical field
本发明涉及显示技术领域，尤其涉及一种显示驱动电路及其控制方法、显示装置。The present invention relates to the field of display technology, in particular to a display driving circuit, a control method thereof, and a display device.
背景技术Background technique
显示器，例如TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)作为一种平板显示装置，因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。Displays, such as TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor-liquid crystal display), as a flat panel display device, are becoming more and more popular because of their small size, low power consumption, no radiation, and relatively low production costs. It is increasingly used in the field of high-performance display.
TFT-LCD中设置横纵交叉的栅线和数据线，该栅线和数据线交叉界定多个呈矩阵形式排列的亚像素。TFT-LCD在显示的过程中，通过逐行对栅线进行扫描，以逐行选通上述亚像素。然后通过数据线将数据电压输出至相应的亚像素，以驱动亚像素进行显示。In the TFT-LCD, gate lines and data lines intersecting horizontally and vertically are arranged, and the intersections of the gate lines and data lines define a plurality of sub-pixels arranged in a matrix. During the display process of the TFT-LCD, the gate lines are scanned row by row to gate the sub-pixels row by row. Then output the data voltage to the corresponding sub-pixels through the data lines to drive the sub-pixels for display.
然而，现有技术中，当TFT-LCD在显示过程中受到外界因素，例如噪声的影响时，会导致用于向驱动上述栅线的驱动电路提供的控制信号发生短路，使得显示面板的控制信号出现缺失，从而导致部分栅线接收到的栅极驱动信号出现异常。这样一来，在显示过程中，将出现例如亮线或者区域不亮等显示不良，从而使得用户在看到上述不良画面后造成视觉疲劳。However, in the prior art, when the TFT-LCD is affected by external factors during the display process, such as noise, it will cause a short circuit in the control signal provided to the driving circuit for driving the gate line, so that the control signal of the display panel Deletion occurs, resulting in abnormal gate drive signals received by some gate lines. In this way, during the display process, there will be display defects such as bright lines or areas that are not bright, which will cause visual fatigue to the user after seeing the above-mentioned defective pictures.
发明内容Contents of the invention
本发明的实施例提供一种显示驱动电路及其控制方法、显示装置，能够避免显示不良的画面进行显示。Embodiments of the present invention provide a display driving circuit, a control method thereof, and a display device, which can avoid displaying defective images.
为达到上述目的，本发明的实施例采用如下技术方案：In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:
本发明实施例的一方面，提供一种显示驱动电路，包括栅极驱动器，所述显示驱动电路还包括脉冲宽度调节器、时序控制器以及信号检测单元；所述信号检测单元分别与所述脉冲宽度调节器和所述时序控制器相连接；所述信号检测单元用于分别判断所述脉冲宽度调节器向所述栅极驱动器提供的第一控制信号和所述时序控制器向所述栅极驱动器提供的第二控制信号是否短路；并且当所述第一控制信号或所述第二控制信号短路时，所述信号检测单元还用于向所述脉冲宽度调节器，和/或，所述时序控制器输出反馈信号；所述脉冲宽度调节器用于根据所述反馈信号，生成控制背光模组关闭的第一使能信号；所述时序控制器用于根据所述反馈信号，生成控制显示面板显示黑色画面的第二使能信号。An aspect of the embodiments of the present invention provides a display driving circuit, including a gate driver, and the display driving circuit also includes a pulse width regulator, a timing controller, and a signal detection unit; the signal detection unit is connected to the pulse The width regulator is connected to the timing controller; the signal detection unit is used to respectively judge the first control signal provided by the pulse width regulator to the gate driver and the first control signal provided by the timing controller to the gate Whether the second control signal provided by the driver is short-circuited; and when the first control signal or the second control signal is short-circuited, the signal detection unit is also used to report to the pulse width regulator, and/or, the The timing controller outputs a feedback signal; the pulse width regulator is used to generate a first enabling signal for controlling the backlight module to be turned off according to the feedback signal; the timing controller is used to generate a first enable signal for controlling the display panel to display according to the feedback signal Second enable signal for black screen.
优选的，所述信号检测单元包括逻辑判断模块、第一非门、第二非门以及或门；所述逻辑判断模块的输入端分别与所述脉冲宽度调节器和所述时序控制器相连接；所述逻辑判断模块用于判断所述脉冲宽度调节器输出的所述第一控制信号是否短路，并将判断结果通过所述逻辑判断模块的第一输出端输出；和/或，所述逻辑判断模块用于判断所述时序控制器输出的所述第二控制信号是否短路，并将判断结果通过所述逻辑判断模块的第二输出端输出；所述逻辑判断模块的第一输出端连接所述第一非门输入端，第二输出端连接所述第二非门的输入端；所述第一非门的输出端与所述或门的第一输入端相连接，所述第二非门的输出端与所述或门的第二输入端相连接；所述或门的输出端分别与所述脉冲宽度调节器和所述时序控制器相连接。Preferably, the signal detection unit includes a logic judgment module, a first NOT gate, a second NOT gate and an OR gate; the input terminals of the logic judgment module are respectively connected to the pulse width regulator and the timing controller ; The logic judgment module is used to judge whether the first control signal output by the pulse width regulator is short-circuited, and output the judgment result through the first output terminal of the logic judgment module; and/or, the logic The judgment module is used to judge whether the second control signal output by the timing controller is short-circuited, and output the judgment result through the second output terminal of the logic judgment module; the first output terminal of the logic judgment module is connected to the The input terminal of the first NOT gate, the second output terminal is connected to the input terminal of the second NOT gate; the output terminal of the first NOT gate is connected to the first input terminal of the OR gate, and the second NOT gate is connected to the first input terminal of the OR gate. The output terminal of the gate is connected with the second input terminal of the OR gate; the output terminals of the OR gate are respectively connected with the pulse width regulator and the timing controller.
优选的，所述显示驱动电路还包括电压转换器；所述电压转换器与所述脉冲宽度调节器和所述时序控制器相连接；所述电压转换器用于对所述脉冲宽度调节器输出的所述第一控制信号和所述时序控制器输出的所述第二控制信号进行电压转换，并输出至所述栅极驱动器。Preferably, the display driving circuit further includes a voltage converter; the voltage converter is connected to the pulse width regulator and the timing controller; the voltage converter is used for the output of the pulse width regulator The first control signal and the second control signal output by the timing controller undergo voltage conversion and output to the gate driver.
进一步优选的，所述信号检测单元集成于所述电压转换器中。Further preferably, the signal detection unit is integrated in the voltage converter.
优选的，所述显示驱动电路还包括与所述时序控制器相连接的源极驱动器；所述源极驱动器用于根据所述时序控制器输出的第二使能信号，向各个亚像素输出与该第二使能信号相匹配的数据电压。Preferably, the display driving circuit further includes a source driver connected to the timing controller; the source driver is used to output a corresponding signal to each sub-pixel according to the second enable signal output by the timing controller. The second enable signal matches the data voltage.
本发明实施例的另一方面，提供一种显示装置包括如上所述的任意一种显示驱动电路。Another aspect of the embodiments of the present invention provides a display device including any display driving circuit as described above.
优选的，所述显示装置还包括背光模组，所述背光模组与所述显示驱动电路中的脉冲宽度调节器相连接。Preferably, the display device further includes a backlight module, and the backlight module is connected to the pulse width regulator in the display driving circuit.
本发明实施例提供一种用于对如上所述的任意一种显示驱动电路进行控制的方法，所述方法包括：信号检测单元判断脉冲宽度调节器向栅极驱动器提供的第一控制信号是否短路；所述信号检测单元判断时序控制器向所述栅极驱动器提供的第二控制信号是否短路；当所述第一控制信号或所述第二控制信号短路时，所述信号检测单元向所述脉冲宽度调节器，和/或，所述时序控制器输出反馈信号所述脉冲宽度调节器根据所述反馈信号，生成控制背光模组关闭的第一使能信号；所述时序控制器根据所述反馈信号，生成控制显示面板显示黑色画面的第二使能信号。An embodiment of the present invention provides a method for controlling any display driving circuit as described above, the method comprising: the signal detection unit judges whether the first control signal provided by the pulse width regulator to the gate driver is short-circuited The signal detection unit judges whether the second control signal provided by the timing controller to the gate driver is short-circuited; when the first control signal or the second control signal is short-circuited, the signal detection unit sends the signal to the A pulse width regulator, and/or, the timing controller outputs a feedback signal. The pulse width regulator generates a first enable signal for controlling the backlight module to be turned off according to the feedback signal; the timing controller outputs a first enable signal according to the feedback signal. The feedback signal is used to generate a second enabling signal for controlling the display panel to display a black picture.
优选的，当所述信号检测单元包括逻辑判断模块时，所述信号检测单元向所述脉冲宽度调节器，和/或，所述时序控制器输出反馈信号包括：所述逻辑判断模块判断所述脉冲宽度调节器输出的所述第一控制信号是否短路，并将判断结果通过所述逻辑判断模块的第一输出端输出；和/或，所述逻辑判断模块判断所述时序控制器输出的所述第二控制信号是否短路进行判断，并将判断结果通过所述逻辑判断模块的第二输出端输出。Preferably, when the signal detection unit includes a logic judgment module, the signal detection unit outputting a feedback signal to the pulse width regulator and/or, the timing controller includes: the logic judgment module judges the Whether the first control signal output by the pulse width regulator is short-circuited, and the judgment result is output through the first output terminal of the logic judgment module; and/or, the logic judgment module judges all the signals output by the timing controller judge whether the second control signal is short-circuited, and output the judgment result through the second output terminal of the logic judgment module.
优选的，当所述显示驱动电路还包括电压转换器时，所述方法还包括：电压转换器对所述脉冲宽度调节器输出的所述第一控制信号和所述时序控制器输出的所述第二控制信号进行电压转换，并将输出至所述栅极驱动器。Preferably, when the display driving circuit further includes a voltage converter, the method further includes: the voltage converter controls the first control signal output by the pulse width regulator and the first control signal output by the timing controller. The second control signal undergoes voltage conversion and is output to the gate driver.
本发明实施例提供一种显示驱动电路及其控制方法、显示装置。由上述可知该显示驱动电路中信号检测单元可以分别判断脉冲宽度调节器向栅极驱动器提供的第一控制信号和时序控制器向栅极驱动器提供的第二控制信号是否短路，当第一控制信号或所述第二控制信号短路时，信号检测单元还用于向脉冲宽度调节器和时序控制器输出反馈信号。在此情况下，当脉冲宽度调节器接收到上述反馈信号后，其可以根据该反馈信号，生成控制背光模组关闭的第一使能信号。此外，当时序控制器接收到上述反馈信号后，其根据上述反馈信号，生成控制显示面板显示黑色画面的第二使能信号。在此情况下，即使上述第一控制信号、第二控制信号中的任意一个控制信号发生短路，由于在第一使能信号的控制下显示面板会变黑，和/或，在第二使能信号控制下使得显示面板显示黑色画面，因此由于该短路导致的画面不良现象不会被用户观测到，从而能够避免该不良画面造成用户视觉疲劳的问题。Embodiments of the present invention provide a display driving circuit, a control method thereof, and a display device. From the above, it can be seen that the signal detection unit in the display driving circuit can respectively determine whether the first control signal provided by the pulse width regulator to the gate driver and the second control signal provided by the timing controller to the gate driver are short-circuited, when the first control signal Or when the second control signal is short-circuited, the signal detection unit is further configured to output a feedback signal to the pulse width regulator and the timing controller. In this case, after the pulse width regulator receives the feedback signal, it can generate the first enable signal for controlling the backlight module to turn off according to the feedback signal. In addition, after the timing controller receives the feedback signal, it generates a second enable signal for controlling the display panel to display a black picture according to the feedback signal. In this case, even if any one of the first control signal and the second control signal is short-circuited, the display panel will turn black under the control of the first enable signal, and/or, under the control of the second enable signal Under the control of the signal, the display panel displays a black picture, so the defective picture caused by the short circuit will not be observed by the user, thereby avoiding the visual fatigue of the user caused by the bad picture.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为本发明实施例提供的一种显示装置的结构示意图；FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present invention;
图2为图1中栅极驱动器的具体结构示意图；FIG. 2 is a schematic diagram of a specific structure of the gate driver in FIG. 1;
图3为本发明实施例提供的另一种显示装置的结构示意图；FIG. 3 is a schematic structural diagram of another display device provided by an embodiment of the present invention;
图4为图1或图3中信号检测单元的具体结构示意图；FIG. 4 is a schematic diagram of the specific structure of the signal detection unit in FIG. 1 or FIG. 3;
图5为本发明实施例提供的一种显示驱动电路的控制方法流程图。FIG. 5 is a flowchart of a control method of a display driving circuit provided by an embodiment of the present invention.
附图标记：Reference signs:
01-显示驱动电路；02-显示面板；03-背光模组；10-脉冲宽度调节器；20-时序控制器；30-电压转换器；301-信号检测单元；311-逻辑判断模块；321-第一非门；331-第二非门；341-或门；40-栅极驱动器；50-源极驱动器。01-display drive circuit; 02-display panel; 03-backlight module; 10-pulse width regulator; 20-sequence controller; 30-voltage converter; 301-signal detection unit; 311-logic judgment module; 321- The first NOT gate; 331-the second NOT gate; 341-OR gate; 40-gate driver; 50-source driver.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明实施例提供一种显示驱动电路01，如图1所示，包括脉冲宽度调节器(PulseWidth Modulation，PWM)10、时序控制器(Timer Control，TCON)20、信号检测单元301以及栅极驱动器(Gate on Array，GOA)40。An embodiment of the present invention provides a display driving circuit 01, as shown in FIG. 1 , including a pulse width modulator (PulseWidth Modulation, PWM) 10, a timing controller (Timer Control, TCON) 20, a signal detection unit 301 and a gate driver (Gate on Array, GOA) 40.
其中，脉冲宽度调节器10用于向栅极驱动器40提供第一控制信号。例如，该第一控制信号可以为以模拟信号(Analog Signal)的形式输出的电源电压VGH以及VGL。Wherein, the pulse width regulator 10 is used to provide the first control signal to the gate driver 40 . For example, the first control signal may be power supply voltages VGH and VGL output in the form of analog signals (Analog Signal).
此外，该时序控制器20用于向栅极驱动器40提供第二控制信号。例如，该第二控制信号可以为以数字信号(Digital Signal)的形式输出的起始信号STV(Start Vertical)以及时钟信号CLK。In addition, the timing controller 20 is used for providing the second control signal to the gate driver 40 . For example, the second control signal may be a start signal STV (Start Vertical) and a clock signal CLK output in the form of a digital signal (Digital Signal).
基于此，由于时序控制器20和脉冲宽度调节器10直接向上述栅极驱动器40提供的信号的幅值太小，不足以使得栅极驱动器40对显示面板02上的栅线进行驱动。因此需要在时序控制器20和栅极驱动器40之间，以及脉冲宽度调节器10和栅极驱动器40之间设置电压转换器(Level Shift)30。Based on this, since the amplitude of the signal directly provided by the timing controller 20 and the pulse width regulator 10 to the gate driver 40 is too small, it is not enough for the gate driver 40 to drive the gate lines on the display panel 02 . Therefore, it is necessary to provide a voltage converter (Level Shift) 30 between the timing controller 20 and the gate driver 40 and between the pulse width regulator 10 and the gate driver 40 .
在此情况下，电压转换器30与脉冲宽度调节器10相连接。电压转换器30用于对脉冲宽度调节器10输出的上述第一控制信号，即上述VGH、VGL进行转换，得到幅值提高的信号VGH’、VGL’，并输出至栅极驱动器40。In this case, voltage converter 30 is connected to pulse width regulator 10 . The voltage converter 30 is used to convert the above-mentioned first control signals output by the pulse width regulator 10 , namely the above-mentioned VGH, VGL, to obtain signals VGH', VGL' with increased amplitudes, and output them to the gate driver 40 .
此外，该电压转换器30还与时序控制器20相连接。该电压转换器30还用于对时序控制器20输出的上述第二控制信号，即上述STV、CLK进行电压转换，得到幅值提高的信号STV’、CLK’，并输出至栅极驱动器40。In addition, the voltage converter 30 is also connected to the timing controller 20 . The voltage converter 30 is also used to perform voltage conversion on the second control signals output by the timing controller 20 , namely the above STV, CLK, to obtain signals STV', CLK' with increased amplitudes, and output them to the gate driver 40 .
以下，以电压转换器30对上述脉冲宽度调节器10输出的上述第一控制信号，即上述VGH、VGL进行转换为例，对该电压转换器30的转换过程进行说明。具体的，脉冲宽度调节器10输出的上述第一控制信号中，VGH通常为3.3V，而VGL通常为0V。在此情况下，通过电压转换器30对上述第一控制信号进行转换后，得到的信号VGH’约为30V，而VGL’约为-6V。这样一来，可以增大输入至栅极驱动器40的控制信号的幅值，使得该栅极驱动器40输出的栅极驱动信号能够对栅线进行选通。Hereinafter, the conversion process of the voltage converter 30 will be described by taking the conversion of the first control signal output by the pulse width regulator 10 , ie, the VGH and VGL, by the voltage converter 30 as an example. Specifically, in the first control signal output by the pulse width regulator 10, VGH is usually 3.3V, and VGL is usually 0V. In this case, after the above-mentioned first control signal is converted by the voltage converter 30, the obtained signal VGH' is about 30V, and VGL' is about -6V. In this way, the amplitude of the control signal input to the gate driver 40 can be increased, so that the gate driving signal output by the gate driver 40 can gate the gate lines.
基于此，如图2所示，上述栅极驱动器40包括多个级联的移位寄存器单元(RS1、RS2……RSn)。Based on this, as shown in FIG. 2 , the gate driver 40 includes a plurality of cascaded shift register units ( RS1 , RS2 . . . RSn).
其中，电压转换器30向每一级移位寄存器单元提供经过电压转换后的信号VGH’、VGL’以及CLK’。从而使得每一级移位寄存器单元通过各自的信号输出端OUT，向与其相连接的栅线(G1、G2……或Gn)输出栅极扫描信号。Wherein, the voltage converter 30 provides the voltage-converted signals VGH', VGL' and CLK' to each stage of the shift register unit. Thus, the shift register units of each stage output gate scan signals to the gate lines (G1, G2...or Gn) connected thereto through their respective signal output terminals OUT.
此外，电压转换器30向第一级移位寄存器单元RS1的信号输入端INPUT提供经过电压转换后的信号STV’。当该信号STV’输出起始信号后，上述栅极驱动器40开始工作。In addition, the voltage converter 30 provides the signal STV' after voltage conversion to the signal input terminal INPUT of the first-stage shift register unit RS1. When the signal STV' outputs a start signal, the gate driver 40 starts to work.
在此基础上，上述信号检测单元301用于分别判断脉冲宽度调节器10向栅极驱动器40提供的第一控制信号(VGH、VGL)和时序控制器20向栅极驱动器40提供的第二控制信号(STV、CLK)是否短路。On this basis, the above-mentioned signal detection unit 301 is used to respectively judge the first control signal (VGH, VGL) provided by the pulse width regulator 10 to the gate driver 40 and the second control signal (VGH, VGL) provided by the timing controller 20 to the gate driver 40 Whether the signal (STV, CLK) is short circuited.
在此情况下，当第一控制信号或所述第二控制信号短路时，信号检测单元301还用于向脉冲宽度调节器10输出反馈信号FB；或者，该信号检测单元301还用于向时序控制器20输出反馈信号FB；又或者，信号检测单元301还用于向脉冲宽度调节器10和时序控制器20输出反馈信号FB。In this case, when the first control signal or the second control signal is short-circuited, the signal detection unit 301 is also used to output the feedback signal FB to the pulse width regulator 10; or, the signal detection unit 301 is also used to send the timing The controller 20 outputs the feedback signal FB; or, the signal detection unit 301 is also used to output the feedback signal FB to the pulse width regulator 10 and the timing controller 20 .
需要说明的是，第一控制信号短路(Short)是指，第一控制信号中的VGH、VGL相互短路或者分别与接地端短路。具体包括：VGH与VGL Short；VGH与GND Short；VGL与GNDShort。It should be noted that the short circuit of the first control signal (Short) means that VGH and VGL in the first control signal are shorted to each other or to the ground respectively. Specifically include: VGH and VGL Short; VGH and GND Short; VGL and GNDShort.
或者，上述第二控制信号短路是指，第二控制信号中的STV、CLK分别与接地端短路。具体包括：STV与GND Short；CLK与GND Short。Alternatively, the aforementioned short circuit of the second control signal means that STV and CLK in the second control signal are respectively shorted to the ground terminal. Specifically include: STV and GND Short; CLK and GND Short.
基于此。当脉冲宽度调节器10接收到上述反馈信号FB后，该脉冲宽度调节器10用于根据该反馈信号FB，生成控制背光模组(Backlight Module，BLM)03关闭的第一使能信号CN1。Based on. After the pulse width regulator 10 receives the feedback signal FB, the pulse width regulator 10 is used to generate the first enable signal CN1 for controlling the backlight module (BLM) 03 to turn off according to the feedback signal FB.
具体的，可以在脉冲宽度调节器10中设置特定的引脚(PIN)用于发送上述第一使能信号CN1。在此情况下，当背光模组03接收到上述第一使能信号CN1后，可以控制该背光模组03中的光源处于关闭状态，而停止发光。此时显示面板02由于没有背光而变黑。Specifically, a specific pin (PIN) may be set in the pulse width regulator 10 for sending the above-mentioned first enable signal CN1. In this case, when the backlight module 03 receives the above-mentioned first enabling signal CN1, it can control the light source in the backlight module 03 to be turned off and stop emitting light. At this time, the display panel 02 becomes black because there is no backlight.
和/或，当时序控制器20接收到上述反馈信号FB后，该时序控制器20用于根据上述反馈信号FB，生成控制显示面板02显示黑色画面的第二使能信号CN2。此时显示面板02显示黑色画面。And/or, after the timing controller 20 receives the feedback signal FB, the timing controller 20 is configured to generate a second enable signal CN2 for controlling the display panel 02 to display a black picture according to the feedback signal FB. At this moment, the display panel 02 displays a black picture.
在此情况下，即使上述第一控制信号(VGH、VGL)、第二控制信号(STV、CLK)中的任意一个控制信号发生短路，由于在第一使能信号CN1的控制下显示面板02会变黑，和/或，在第二使能信号CN2控制下使得显示面板02显示黑色画面，因此由于该短路导致的画面不良现象不会被用户观测到，从而能够避免该不良画面造成用户视觉疲劳的问题。In this case, even if any one of the first control signal (VGH, VGL) and the second control signal (STV, CLK) is short-circuited, the display panel 02 will be under the control of the first enable signal CN1 black, and/or, under the control of the second enable signal CN2, the display panel 02 displays a black picture, so the bad picture caused by the short circuit will not be observed by the user, thereby preventing the bad picture from causing visual fatigue to the user The problem.
在此基础上，为了减小上述信号检测单元301占用布线区域的面积，优选的，如图3所示，该信号检测单元301可以集成于电压转换器30中。On this basis, in order to reduce the area of the wiring area occupied by the signal detection unit 301 , preferably, as shown in FIG. 3 , the signal detection unit 301 can be integrated into the voltage converter 30 .
以下，对上述信号检测单元301的结构进行详细的说明。具体的，如图4所示，上述信号检测单元301包括逻辑判断模块311、第一非门321、第二非门331以及或门341。Hereinafter, the structure of the above-mentioned signal detection unit 301 will be described in detail. Specifically, as shown in FIG. 4 , the signal detection unit 301 includes a logic judgment module 311 , a first NOT gate 321 , a second NOT gate 331 and an OR gate 341 .
具体的，逻辑判断模块311的输入端分别与上述脉冲宽度调节器10和时序控制器20相连接，从而使得该逻辑判断模块311能够接收到脉冲宽度调节器10输出的第一控制信号(VGH、VGL)，并接收到时序控制器20输出的第二控制信号(STV、CLK)。Specifically, the input terminals of the logic judging module 311 are respectively connected to the pulse width regulator 10 and the timing controller 20, so that the logic judging module 311 can receive the first control signal (VGH, VGH, VGL), and receive the second control signal (STV, CLK) output by the timing controller 20.
在此情况下，该逻辑判断模块311用于判断脉冲宽度调节器10输出的上述第一控制信号(VGH、VGL)是否短路，并将判断结果通过该逻辑判断模块311的第一输出端A输出。In this case, the logic judging module 311 is used to judge whether the above-mentioned first control signal (VGH, VGL) output by the pulse width regulator 10 is short-circuited, and output the judging result through the first output terminal A of the logic judging module 311 .
和/或，该逻辑判断模块311用于判断时序控制器20输出的上述第二控制信号(STV、CLK)是否短路，并将判断结果通过该逻辑判断模块311的第二输出端B输出。And/or, the logic judgment module 311 is used to judge whether the above-mentioned second control signal (STV, CLK) output by the timing controller 20 is short-circuited, and output the judgment result through the second output terminal B of the logic judgment module 311 .
由上述可知，第一控制信号(VGH、VGL)为模拟信号，而第二控制信号(STV、CLK)数字信号。因此上述逻辑判断模块311可以分别对模拟信号和数字信号的短路状况进行判断，并将判断结果通过不同的输出端A或B输出。It can be known from the above that the first control signals (VGH, VGL) are analog signals, and the second control signals (STV, CLK) are digital signals. Therefore, the logic judging module 311 can judge the short-circuit status of the analog signal and the digital signal respectively, and output the judging result through different output terminals A or B.
在此基础上，上述逻辑判断模块311的第一输出端A连接第一非门321输入端，第二输出端B连接第二与非门331的输入端。On this basis, the first output terminal A of the logic judgment module 311 is connected to the input terminal of the first NOT gate 321 , and the second output terminal B is connected to the input terminal of the second NAND gate 331 .
此外，第一非门321的输出端与上述或门341的第一输入端相连接，第二非门331的输出端与该或门341的第二输入端相连接。并且，该或门341的输出端分别与脉冲宽度调节器10和时序控制器20相连接。In addition, the output terminal of the first NOT gate 321 is connected to the first input terminal of the OR gate 341 , and the output terminal of the second NOT gate 331 is connected to the second input terminal of the OR gate 341 . Moreover, the output terminals of the OR gate 341 are respectively connected with the pulse width regulator 10 and the timing controller 20 .
在此情况下，由上述第一非门321、第二非门331以及或门341构成的非加或门的真值表如表1所示。In this case, the truth table of the NOR gate composed of the first NOT gate 321 , the second NOT gate 331 and the OR gate 341 is shown in Table 1.
表1Table 1
其中，逻辑判断模块311的第一输出端A输出“0”时，表示以模拟电压形式输入至该逻辑判断模块311的第一控制信号(VGH、VGL)中的信号存在表1中所述的短路状态，例如VGH与VGL Short、VGH与GND Short或者VGL与GND Short。而当逻辑判断模块311的第一输出端A输出“1”时，表示输入至该逻辑判断模块311的第一控制信号(VGH、VGL)中的任意一个信号均未发生短路。Wherein, when the first output terminal A of the logic judging module 311 outputs "0", it means that the signal in the first control signal (VGH, VGL) input to the logic judging module 311 in the form of analog voltage exists as described in Table 1. Short circuit status, such as VGH and VGL Short, VGH and GND Short, or VGL and GND Short. When the first output terminal A of the logic judgment module 311 outputs "1", it means that none of the first control signals (VGH, VGL) input to the logic judgment module 311 is short-circuited.
此外，逻辑判断模块311的第二输出端B输出“0”时，表示以数字电压形式输入至该逻辑判断模块311的第二控制信号(STV、CLK)中的信号存在表1中所述的短路状态，例如CLK与GND Short、或者STV与GND Short。而当逻辑判断模块311的第二输出端B输出“1”时，表示输入至该逻辑判断模块311的第二控制信号(STV、CLK)中的任意一个信号均未发生短路。In addition, when the second output terminal B of the logic judging module 311 outputs "0", it means that the signal in the second control signal (STV, CLK) input to the logic judging module 311 in the form of digital voltage exists as described in Table 1. Short circuit state, such as CLK and GND Short, or STV and GND Short. When the second output terminal B of the logic judgment module 311 outputs "1", it means that none of the second control signals (STV, CLK) input to the logic judgment module 311 is short-circuited.
具体的，以VGH与VGL Short为例对上述表1进行说明，当信号VGH与信号VGL发生短路时，有上述可知逻辑判断模块311的第一输出端A输出“0”。在此情况下，无论第二控制信号(STV、CLK)中的信号是否存在短路，即该逻辑判断模块311的第二输出端B输出“0”还是输出“1”，经过上述非加或门后，或门341的输出端C输出的反馈信号FB为“1”。Specifically, take VGH and VGL Short as examples to illustrate the above Table 1. When the signal VGH and the signal VGL are short-circuited, it is known that the first output terminal A of the logic judgment module 311 outputs “0”. In this case, no matter whether there is a short circuit in the signal in the second control signal (STV, CLK), that is, the second output terminal B of the logic judgment module 311 outputs "0" or "1", through the above-mentioned NOR gate Afterwards, the feedback signal FB output from the output terminal C of the OR gate 341 is "1".
在此情况下，脉冲宽度调节器10的输入端D接收到上述为“1”的反馈信号FB，根据该反馈信号FB生成第一使能信号CN1，并输出至背光模组03，以使得背光模组03将其内部的光源关断。In this case, the input terminal D of the pulse width regulator 10 receives the above-mentioned feedback signal FB of "1", generates the first enable signal CN1 according to the feedback signal FB, and outputs it to the backlight module 03, so that the backlight Module 03 turns off its internal light source.
和/或，时序控制器20的输入端E接收到上述为“1”的反馈信号FB，根据该反馈信号FB生成第二使能信号CN2。And/or, the input terminal E of the timing controller 20 receives the above-mentioned feedback signal FB of "1", and generates the second enable signal CN2 according to the feedback signal FB.
在此情况下，当上述显示驱动电路01，如图3或4所示，还包括与该时序控制器20相连接的源极驱动器50时。该源极驱动器50可以接收到上述第二使能信号CN2，并根据该第二使能信号CN2，向各个亚像素输出与该第二使能信号CN2相匹配的数据电压。具体的，由于第二使能信号CN2能够控制显示面板02显示黑色画面。因此，上述源极驱动器50接收到该第二使能信号CN2后会向各个亚像素输出与灰阶值L0相匹配的数据电压Vdata。In this case, when the above-mentioned display driving circuit 01 , as shown in FIG. 3 or 4 , further includes a source driver 50 connected to the timing controller 20 . The source driver 50 can receive the above-mentioned second enabling signal CN2, and output a data voltage matching the second enabling signal CN2 to each sub-pixel according to the second enabling signal CN2. Specifically, the second enable signal CN2 can control the display panel 02 to display a black picture. Therefore, the source driver 50 will output the data voltage Vdata matching the gray scale value L0 to each sub-pixel after receiving the second enable signal CN2.
本发明实施例提供一种显示装置，包括如上所述的任意一种显示驱动电路01。该显示装置具有与前述实施例提供的显示驱动电路01相同的有益效果，此处不再赘述。An embodiment of the present invention provides a display device, including any display driving circuit 01 described above. The display device has the same beneficial effects as the display driving circuit 01 provided in the foregoing embodiments, which will not be repeated here.
需要说明的是，在本发明实施例中，上述显示装置具体可以包括液晶显示装置，例如该显示装置可以为显示器、电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。It should be noted that, in the embodiment of the present invention, the above-mentioned display device may specifically include a liquid crystal display device, for example, the display device may be any product or component with a display function such as a monitor, a TV, a digital photo frame, a mobile phone, or a tablet computer.
在此基础上，如图1所示，该显示装置还包括背光模组03，该背光模组03与显示驱动电路01中的脉冲宽度调节器10相连接。在此情况下，该脉冲宽度调节器10可以对背光模组03的发光亮度进行调节。此外，当脉冲宽度调节器10接收到信号检测单元301输出的反馈信号FB时，该脉冲宽度调节器10还可以通过特定的引脚，向背光模组03提供用于关断该背光模组03中光源的第一使能信号CN1。On this basis, as shown in FIG. 1 , the display device further includes a backlight module 03 , and the backlight module 03 is connected to the pulse width regulator 10 in the display driving circuit 01 . In this case, the pulse width regulator 10 can adjust the brightness of the backlight module 03 . In addition, when the pulse width regulator 10 receives the feedback signal FB output by the signal detection unit 301, the pulse width regulator 10 can also provide the backlight module 03 with a signal for turning off the backlight module 03 through a specific pin. The first enable signal CN1 of the medium light source.
本发明实施例提供一种用于对如上所述的任意一种显示驱动电路01进行控制的方法，如图5所示，上述方法包括：An embodiment of the present invention provides a method for controlling any display driving circuit 01 described above, as shown in FIG. 5 , the above method includes:
S101、如图1所示的，信号检测单元301判断脉冲宽度调节器10向栅极驱动器40提供的第一控制信号(VGH、VGL)是否短路。S101 , as shown in FIG. 1 , the signal detection unit 301 determines whether the first control signal (VGH, VGL) provided by the pulse width regulator 10 to the gate driver 40 is short-circuited.
S102、上述信号检测单元301判断时序控制器20向栅极驱动器40提供的第二控制信号(STV、CLK)是否短路。S102 , the signal detection unit 301 judges whether the second control signal (STV, CLK) provided by the timing controller 20 to the gate driver 40 is short-circuited.
需要说明的是，本发明对上述步骤S101和步骤S102的先后顺序不做限定。优选的，当输入至该信号检测单元301的第一控制信号(VGH、VGL)和第二控制信号(STV、CLK)的信号传输速度相当时，上述步骤S101和步骤S102可以同时进行。It should be noted that the present invention does not limit the order of the above steps S101 and S102. Preferably, when the signal transmission speeds of the first control signal (VGH, VGL) and the second control signal (STV, CLK) input to the signal detection unit 301 are equivalent, the above step S101 and step S102 can be performed simultaneously.
S103、当上述第一控制信号(VGH、VGL)或第二控制信号(STV、CLK)短路时，该信号检测单元301向脉冲宽度调节器10输出反馈信号FB；S103. When the first control signal (VGH, VGL) or the second control signal (STV, CLK) is short-circuited, the signal detection unit 301 outputs a feedback signal FB to the pulse width regulator 10;
或者，当上述第一控制信号(VGH、VGL)或第二控制信号(STV、CLK)短路时，信号检测单元301向时序控制器20输出上述反馈信号FB；Alternatively, when the first control signal (VGH, VGL) or the second control signal (STV, CLK) is short-circuited, the signal detection unit 301 outputs the feedback signal FB to the timing controller 20;
又或者，当上述第一控制信号(VGH、VGL)或第二控制信号(STV、CLK)短路时，信号检测单元301向脉冲宽度调节器10和时序控制器20输出上述反馈信号FB。Alternatively, when the first control signal (VGH, VGL) or the second control signal (STV, CLK) is short-circuited, the signal detection unit 301 outputs the feedback signal FB to the pulse width regulator 10 and the timing controller 20 .
S104、当该脉冲宽度调节器10接收到上述反馈信号FB时，该脉冲宽度调节器10根据反馈信号FB，生成控制背光模组03关闭的第一使能信号CN1。S104. When the pulse width regulator 10 receives the feedback signal FB, the pulse width regulator 10 generates a first enable signal CN1 for controlling the backlight module 03 to turn off according to the feedback signal FB.
S105、当该时序控制器20接收到上述反馈信号FB时，该时序控制器20根据反馈信号FB，生成控制显示面板02显示黑色画面的第二使能信号CN2。S105. When the timing controller 20 receives the feedback signal FB, the timing controller 20 generates a second enable signal CN2 for controlling the display panel 02 to display a black screen according to the feedback signal FB.
需要说明的是，当脉冲宽度调节器10和时序控制器20均接收到上述反馈信号FB时，本发明对上述步骤S104和步骤S105的先后顺序不做限定。优选的，当输入至脉冲宽度调节器10和时序控制器20的反馈信号FB的信号传输速度相当时，上述步骤S104和步骤S105可以同时进行。It should be noted that, when both the pulse width regulator 10 and the timing controller 20 receive the above-mentioned feedback signal FB, the present invention does not limit the order of the above-mentioned step S104 and step S105. Preferably, when the signal transmission speeds of the feedback signal FB input to the pulse width regulator 10 and the timing controller 20 are equivalent, the above step S104 and step S105 can be performed simultaneously.
在此基础上，当信号检测单元301如图4所示包括逻辑判断模块311时，该信号检测单元301向脉冲宽度调节器10，和/或，时序控制器20输出反馈信号FB包括：On this basis, when the signal detection unit 301 includes a logic judgment module 311 as shown in FIG.
逻辑判断模块311判断脉冲宽度调节器10输出的第一控制信号(VGH、VGL)是否短路，并将判断结果通过逻辑判断模块311的第一输出端A输出。The logic judging module 311 judges whether the first control signal (VGH, VGL) output by the pulse width regulator 10 is short-circuited, and outputs the judging result through the first output terminal A of the logic judging module 311 .
其中，逻辑判断模块311对第一控制信号(VGH、VGL)是否短路的判断过程如上所述，此处不再赘述。Wherein, the logic judging module 311 judges whether the first control signal (VGH, VGL) is short-circuited or not as described above, and will not be repeated here.
和/或，逻辑判断模块311判断时序控制器20输出的第二控制信号(STV、CLK)是否短路进行判断，并将判断结果通过所述逻辑判断模块311的第二输出端B输出。And/or, the logic judgment module 311 judges whether the second control signal (STV, CLK) output by the timing controller 20 is short-circuited, and outputs the judgment result through the second output terminal B of the logic judgment module 311 .
其中，逻辑判断模块311对第二控制信号(STV、CLK)是否短路的判断过程如上所述，此处不再赘述。Wherein, the logic judging module 311 judges whether the second control signal (STV, CLK) is short-circuited or not as described above, and will not be repeated here.
在此基础上，当显示驱动电路01如图1或如图3所示，还包括电压转换器30时，上述方法还包括：On this basis, when the display driving circuit 01 as shown in FIG. 1 or FIG. 3 further includes a voltage converter 30, the above method further includes:
电压转换器30对脉冲宽度调节器10输出的所述第一控制信号(VGH、VGL)进行转换，得到幅值提高的信号VGH’、VGL’，并输出至栅极驱动器40。The voltage converter 30 converts the first control signals (VGH, VGL) output by the pulse width regulator 10 to obtain signals VGH', VGL' with increased amplitudes, and outputs them to the gate driver 40.
电压转换器30还对时序控制器20输出的第二控制信号(STV、CLK)进行电压转换，得到幅值提高的信号STV’、CLK’，并输出至栅极驱动器40。The voltage converter 30 also performs voltage conversion on the second control signals (STV, CLK) output by the timing controller 20 to obtain signals STV', CLK' with increased amplitudes, and outputs them to the gate driver 40 .
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710800726.7ACN107481693B (en) | 2017-09-06 | 2017-09-06 | A kind of display driver circuit and its control method, display device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710800726.7ACN107481693B (en) | 2017-09-06 | 2017-09-06 | A kind of display driver circuit and its control method, display device |
| Publication Number | Publication Date |
|---|---|
| CN107481693A CN107481693A (en) | 2017-12-15 |
| CN107481693Btrue CN107481693B (en) | 2019-10-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710800726.7AExpired - Fee RelatedCN107481693B (en) | 2017-09-06 | 2017-09-06 | A kind of display driver circuit and its control method, display device |
| Country | Link |
|---|---|
| CN (1) | CN107481693B (en) |
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