技术领域technical field
本发明涉及显示领域，尤其涉及一种显示器件及其制备方法。The invention relates to the display field, in particular to a display device and a preparation method thereof.
背景技术Background technique
平面显示器件具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示器件主要包括液晶显示器件(Liquid Crystal Display，LCD)及有机发光二极管显示器件(Organic Light Emitting Display，OLED)。Flat-panel display devices have many advantages such as thin body, power saving, and no radiation, and have been widely used. Existing flat panel display devices mainly include liquid crystal display devices (Liquid Crystal Display, LCD) and organic light emitting diode display devices (Organic Light Emitting Display, OLED).
在平面显示器件中，薄膜晶体管(Thin Film Transistor，TFT)一般是用作开关元件来控制像素的作业，或是用作驱动元件来驱动像素。薄膜晶体管依其硅薄膜性质通常可分成非晶硅(a-Si)与多晶硅(poly-Si)两种。由于非晶硅本身自有的缺陷问题，如缺陷太多导致的开态电流低、迁移率低、稳定性差，使它在应用中受到限制，为了弥补非晶硅本身的缺陷，扩大其在相关领域的应用，低温多晶硅(Low Temperature Poly-Silicon，LTPS)技术应运而生。In flat panel display devices, thin film transistors (Thin Film Transistor, TFT) are generally used as switching elements to control the operation of pixels, or as driving elements to drive pixels. Thin film transistors can generally be classified into two types: amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) according to the nature of the silicon film. Due to the defects of amorphous silicon itself, such as low on-state current, low mobility, and poor stability caused by too many defects, its application is limited. In order to make up for the defects of amorphous silicon itself, expand its use in related Low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) technology emerges as the times require.
图1是现有的有机发光二极管显示器件在薄膜晶体管开关处的结构示意图，其应用了低温多晶硅技术。请参阅图1所示，有机发光二极管显示器件包括一基板100；在所述基板上设置有源层101；一栅极绝缘层102覆盖所述有源层101及基板100；栅极103设置在所述栅极绝缘层102上，并与有源层101对应设置；一钝化层104覆盖所述栅极103及栅极绝缘层102；一源极105及漏极106穿过所述钝化层104、栅极绝缘层102与所述有源层101的源极区域及漏极区域连接；一平坦化层107覆盖所述钝化层104及所述源极105和漏极106，在所述漏极106位置形成一过孔(附图中未标示)；一有机发光二极管的阳极层108穿过所述过孔与所述漏极106连接；一像素定义层109设置在所述阳极层108上；一有机发光层110设置在所述阳极层108上，且被所述像素定义层109包围。FIG. 1 is a schematic diagram of the structure of an existing organic light emitting diode display device at the switch of a thin film transistor, which uses low-temperature polysilicon technology. Please refer to FIG. 1, the organic light emitting diode display device includes a substrate 100; an active layer 101 is arranged on the substrate; a gate insulating layer 102 covers the active layer 101 and the substrate 100; the gate 103 is arranged on On the gate insulating layer 102, and corresponding to the active layer 101; a passivation layer 104 covers the gate 103 and the gate insulating layer 102; a source 105 and a drain 106 pass through the passivation layer 104, the gate insulating layer 102 are connected to the source region and the drain region of the active layer 101; a planarization layer 107 covers the passivation layer 104 and the source 105 and drain 106, in the A via hole (not marked in the drawings) is formed at the position of the drain electrode 106; an anode layer 108 of an organic light emitting diode is connected to the drain electrode 106 through the via hole; a pixel definition layer 109 is arranged on the anode layer 108 ; an organic light emitting layer 110 is disposed on the anode layer 108 and surrounded by the pixel definition layer 109 .
图1所示的有机发光二极管显示器件的制作过程中，栅极绝缘层102的材料一般采用SiOx，而栅极103的材料一般采用金属钼(Mo)，两者应力匹配不好，容易造成栅极103膜层的脱落，导致薄膜晶体管(TFT)器件的性能受到影响。In the manufacturing process of the organic light emitting diode display device shown in FIG. 1 , the material of the gate insulating layer 102 is generally SiOx , and the material of the gate 103 is generally metal molybdenum (Mo). The stress matching between the two is not good, which is easy to cause The detachment of the film layer of the gate 103 affects the performance of the thin film transistor (TFT) device.
发明内容Contents of the invention
本发明所要解决的技术问题是，提供一种显示器件及其制备方法，其能够防止栅极脱落，进而可以大幅度改善薄膜晶体管开关的性能。The technical problem to be solved by the present invention is to provide a display device and a preparation method thereof, which can prevent the grid from falling off, and further can greatly improve the performance of the thin film transistor switch.
为了解决上述问题，本发明提供了一种显示器件，在所述显示器件的薄膜晶体管开关的第一栅极绝缘层与栅极之间设置一第二栅极绝缘层，所述第二栅极绝缘层的应力介于第一栅极绝缘层的应力与栅极的应力之间。In order to solve the above problems, the present invention provides a display device, in which a second gate insulating layer is arranged between the first gate insulating layer and the gate of the thin film transistor switch of the display device, and the second gate The stress of the insulating layer is between the stress of the first gate insulating layer and the stress of the gate.
进一步，所述第一栅极绝缘层的材料为SiOx，所述栅极的材料为Mo，所述第二栅极绝缘层的材料为SiONx。Further, the material of the first gate insulating layer is SiOx, the material of the gate is Mo, and the material of the second gate insulating layer is SiONx.
进一步，所述第二栅极绝缘层覆盖所述第一栅极绝缘层的全部表面，或者所述第二栅极绝缘层覆盖所述第一栅极绝缘层与所述栅极对应的位置处的表面。Further, the second gate insulating layer covers the entire surface of the first gate insulating layer, or the second gate insulating layer covers the position of the first gate insulating layer corresponding to the gate s surface.
进一步，所述第二栅极绝缘层的厚度为100～200nm。Further, the thickness of the second gate insulating layer is 100-200 nm.
进一步，所述显示器件的薄膜晶体管开关包括一基板、设置在所述基板上的有源层、覆盖所述基板的裸露部分及所述有源层的所述第一栅极绝缘层、设置在所述第一栅极绝缘层表面的所述第二栅极绝缘层，设置在所述第二栅极绝缘层表面的所述栅极、覆盖所述栅极的钝化层及贯穿所述钝化层及第一栅极绝缘层和/或第二栅极绝缘层的源极及漏极，所述源极及漏极分别与所述有源层的源极区域及漏极区域连接。Further, the thin film transistor switch of the display device includes a substrate, an active layer disposed on the substrate, the first gate insulating layer covering the exposed part of the substrate and the active layer, disposed on The second gate insulating layer on the surface of the first gate insulating layer, the gate disposed on the surface of the second gate insulating layer, the passivation layer covering the gate and penetrating through the passivation layer layer and the source and drain of the first gate insulating layer and/or the second gate insulating layer, and the source and drain are respectively connected to the source region and the drain region of the active layer.
进一步，所述显示器件为有机发光二极管显示器件或者液晶显示器件。Further, the display device is an organic light emitting diode display device or a liquid crystal display device.
本发明还提供一种显示器件的制备方法，在制备所述显示器件的薄膜晶体管开关时，在第一栅极绝缘层上沉积一第二栅极绝缘层，在所述第二栅极绝缘层上形成栅极，所述第二栅极绝缘层的应力介于第一栅极绝缘层的应力与栅极的应力之间。The present invention also provides a method for preparing a display device. When preparing a thin film transistor switch of the display device, a second gate insulating layer is deposited on the first gate insulating layer, and a second gate insulating layer is deposited on the second gate insulating layer. A gate is formed on the top, and the stress of the second gate insulating layer is between the stress of the first gate insulating layer and the stress of the gate.
进一步，所述第一栅极绝缘层的材料为SiOx，所述栅极的材料为Mo，所述第二栅极绝缘层的形成方法为，采用等离子体化学气相沉积法沉积所述第二栅极绝缘层，其中，成膜气体为SiH4、NH3及N2O。Further, the material of the first gate insulating layer is SiOx, the material of the gate is Mo, and the method of forming the second gate insulating layer is to deposit the second gate insulating layer by plasma chemical vapor deposition. pole insulating layer, wherein the film-forming gas is SiH4 , NH3 and N2 O.
进一步，所述SiH4、NH3及N2O的流量比为1～5：8～12：20～25。Further, the flow ratio of SiH4, NH3 and N2O is 1-5:8-12:20-25.
进一步，在等离子体化学气相沉积过程中，反应温度为300℃～400℃，反应时间为30～70S。Further, during the plasma chemical vapor deposition process, the reaction temperature is 300° C. to 400° C., and the reaction time is 30 to 70 seconds.
本发明的优点在于，在所述显示器件的薄膜晶体管开关的第一栅极绝缘层与栅极之间设置一第二栅极绝缘层，所述第二栅极绝缘层的应力介于第一栅极绝缘层的应力与栅极的应力之间，所述第二栅极绝缘层能够很好地平衡所述第一栅极绝缘层与栅极之间的应力，使两者之间的应力更加匹配，防止栅极脱落，进而可以大幅度改善薄膜晶体管开关的性能。The advantage of the present invention is that a second gate insulating layer is provided between the first gate insulating layer and the gate of the thin film transistor switch of the display device, and the stress of the second gate insulating layer is between the first and second gate insulating layers. Between the stress of the gate insulating layer and the stress of the gate, the second gate insulating layer can well balance the stress between the first gate insulating layer and the gate, so that the stress between the two More matching prevents the gate from falling off, which can greatly improve the performance of the thin film transistor switch.
附图说明Description of drawings
图1是现有的有机发光二极管显示器件在薄膜晶体管开关处的结构示意图。FIG. 1 is a schematic structural view of a conventional organic light emitting diode display device at a switch of a thin film transistor.
图2是本发明显示器件在薄膜晶体管开关处的结构示意图；Fig. 2 is a schematic structural view of a display device of the present invention at a thin film transistor switch;
图3A～图3G是本发明显示器件的制备方法的一个实施例的工艺流程图。3A to 3G are process flow diagrams of an embodiment of the method for manufacturing a display device of the present invention.
具体实施方式detailed description
下面结合附图对本发明提供的显示器件及其制备方法的具体实施方式做详细说明。The specific implementation of the display device and its manufacturing method provided by the present invention will be described in detail below in conjunction with the accompanying drawings.
本发明显示器件可以为有机发光二极管显示器件(OLED)，也可以为液晶显示器件(LCD)。其中，不论是有机发光二极管显示器件还是液晶显示器件都需要薄膜晶体管(TFT)作为像素开关。本发明以有机发光二极管显示器件为例来说明本发明显示器件的技术方案。The display device of the present invention may be an organic light emitting diode display device (OLED), or a liquid crystal display device (LCD). Wherein, whether it is an organic light emitting diode display device or a liquid crystal display device, a thin film transistor (TFT) is required as a pixel switch. The present invention takes an organic light emitting diode display device as an example to illustrate the technical solution of the display device of the present invention.
图2是本发明显示器件在薄膜晶体管开关处的结构示意图。请参阅图2所示，显示器件包括一基板200。所述基板200由透光性材料制成，例如玻璃或者聚酰亚胺。其中，为了提供薄膜晶体管开关的性能，在所述基板200的表面还可以设置一缓冲层(附图中未标示)，所述缓冲层的材料可以为SiNx+SiOx。FIG. 2 is a schematic structural view of the display device of the present invention at the thin film transistor switch. Please refer to FIG. 2 , the display device includes a substrate 200 . The substrate 200 is made of light-transmitting material, such as glass or polyimide. Wherein, in order to improve the switching performance of the thin film transistor, a buffer layer (not shown in the drawings) may also be disposed on the surface of the substrate 200 , and the material of the buffer layer may be SiNx+SiOx.
在所述基板200上设置有源层201。所述有源层201由多晶硅形成。在本具体实施方式中，在所述基板200上先形成非晶硅(a-Si)，再通过背景技术中所述的低温多晶硅(LowTemperature Poly-Silicon，LTPS)技术形成多晶硅(poly-Si)。其中，所述有源层201包括源极区域(附图中未标示)、漏极区域(附图中未标示)及位于所述源极区域及漏极区域之间的沟道区域(附图中未标示)。An active layer 201 is disposed on the substrate 200 . The active layer 201 is formed of polysilicon. In this specific embodiment, amorphous silicon (a-Si) is first formed on the substrate 200, and then polysilicon (poly-Si) is formed by the low temperature polysilicon (LowTemperature Poly-Silicon, LTPS) technology described in the background art. . Wherein, the active layer 201 includes a source region (not marked in the drawings), a drain region (not marked in the drawings), and a channel region (not shown in the drawings) between the source region and the drain region. not marked).
一第一栅极绝缘层202覆盖所述有源层201及基板200。由于所述有源层201并未覆盖全部的基板200，因此，在基板200上形成有源层201后，还存在部分裸露的基板200，则所述第一栅极绝缘层202覆盖裸露的基板200及有源层201。其中，在本具体实施方式中，所述第一栅极绝缘层202的材料为SiOx。A first gate insulating layer 202 covers the active layer 201 and the substrate 200 . Since the active layer 201 does not cover the entire substrate 200, after the active layer 201 is formed on the substrate 200, there is still a partially exposed substrate 200, and the first gate insulating layer 202 covers the exposed substrate. 200 and active layer 201. Wherein, in this specific implementation manner, the material of the first gate insulating layer 202 is SiOx .
一栅极204设置在所述第一栅极绝缘层202上。所述栅极204并未全部覆盖所述第一栅极绝缘层202，而是对应所述有源层201的沟道区域设置。其中，在本具体实施方式中，所述栅极204的材料为金属钼(Mo)。A gate 204 is disposed on the first gate insulating layer 202 . The gate 204 does not entirely cover the first gate insulating layer 202 , but is disposed corresponding to the channel region of the active layer 201 . Wherein, in this specific implementation manner, the material of the gate 204 is metal molybdenum (Mo).
由于所述第一栅极绝缘层202的材料(例如，SiOx)与所述栅极204的材料(例如，金属钼，)不同，则所述栅极204与所述第一栅极绝缘层202之间会存在很大的应力差异，两者之间应力匹配不好，易造成栅极204膜层从所述第一栅极绝缘层202上脱落。鉴于此，本发明显示器件在所述第一栅极绝缘层202与栅极204之间设置一第二栅极绝缘层203。所述第二栅极绝缘层203的应力介于所述栅极204的应力与所述第一栅极绝缘层202的应力之间，例如，所述第二栅极绝缘层203的应力小于所述栅极204的应力并且大于所述第一栅极绝缘层202的应力，使所述栅极204的应力与所述第一栅极绝缘层202的应力逐渐过渡。所述第二栅极绝缘层203能够很好地平衡所述第一栅极绝缘层202与栅极204之间的应力，使两者之间的应力更加匹配，防止栅极204脱落，进而可以大幅度改善薄膜晶体管开关的性能。Since the material of the first gate insulating layer 202 (for example, SiOx ) is different from the material of the gate 204 (for example, metal molybdenum), the gate 204 and the first gate insulating layer There will be a large stress difference between the two gates 202 , and the stress matching between the two is not good, which may easily cause the film layer of the gate 204 to fall off from the first gate insulating layer 202 . In view of this, in the display device of the present invention, a second gate insulating layer 203 is disposed between the first gate insulating layer 202 and the gate 204 . The stress of the second gate insulating layer 203 is between the stress of the gate 204 and the stress of the first gate insulating layer 202, for example, the stress of the second gate insulating layer 203 is smaller than the specified stress. The stress of the gate 204 is greater than the stress of the first gate insulating layer 202 , so that the stress of the gate 204 and the stress of the first gate insulating layer 202 gradually transition. The second gate insulating layer 203 can well balance the stress between the first gate insulating layer 202 and the gate 204, so that the stress between the two can be more matched, preventing the gate 204 from falling off, and then can Significantly improve the performance of thin film transistor switches.
在本具体实施方式中，所述第一栅极绝缘层202的材料为SiOx，所述栅极204的材料为金属钼(Mo)，则所述第二栅极绝缘层203的材料为SiONx。其可采用等离子气相沉积的方法，以SiH4、NH3及N2O为成膜气体形成。优选地，所述第二栅极绝缘层203的厚度为100～200nm，例如100nm、120nm、140nm、160nm、180nm或200nm。该厚度的第二栅极绝缘层203的应力介于所述栅极204的应力与所述第一栅极绝缘层202的应力之间，能够很好地平衡所述第一栅极绝缘层202与栅极204之间的应力。In this specific embodiment, the material of the first gate insulating layer 202 isSiOx , the material of the gate 204 is metal molybdenum (Mo), and the material of the second gate insulating layer 203 is SiONx . It can be formed by plasma vapor deposition, using SiH4 , NH3 and N2 O as film-forming gases. Preferably, the thickness of the second gate insulating layer 203 is 100-200 nm, such as 100 nm, 120 nm, 140 nm, 160 nm, 180 nm or 200 nm. The stress of the second gate insulating layer 203 of this thickness is between the stress of the gate 204 and the stress of the first gate insulating layer 202, which can well balance the first gate insulating layer 202. and the stress between the gate 204 .
进一步，在本具体实施方式中，所述第二栅极绝缘层203覆盖所述第一栅极绝缘层202的全部表面。在本发明其他具体实施方式中，所述第二栅极绝缘层203覆盖所述第一栅极绝缘层202与所述栅极204对应的位置处的表面，本发明对所述第二栅极绝缘层203的设置位置及面积不进行限定，其能够隔绝第一栅极绝缘层202与栅极204即可。Further, in this specific implementation manner, the second gate insulating layer 203 covers the entire surface of the first gate insulating layer 202 . In other specific implementation manners of the present invention, the second gate insulating layer 203 covers the surface of the first gate insulating layer 202 at the position corresponding to the gate 204, and the present invention covers the second gate The location and area of the insulating layer 203 are not limited, as long as it can isolate the first gate insulating layer 202 and the gate 204 .
请再参阅图2所示，一钝化层205覆盖所述栅极204及第二栅极绝缘层203。在其他具体实施方式中，若所述第二栅极绝缘层203覆盖所述第一栅极绝缘层202与所述栅极204对应的位置处的表面，则所述钝化层205还覆盖暴露的第一栅极绝缘层202的表面。一源极206及漏极207穿过所述钝化层205及第一栅极绝缘层202与所述有源层201的源极区域及漏极区域连接。一平坦化层208覆盖所述钝化层205及所述源极206和漏极207，在所述漏极207位置形成一过孔(附图中未标示)。一有机发光二极管的阳极层209穿过所述过孔与所述漏极207连接。一像素定义层210设置在所述阳极层209上；一有机发光层211设置在所述阳极层209上，且被所述像素定义层210包围。上述结构均为本领域OLED显示器件的常规结构，本领域技术人员可从现有技术中获取其具体结构，本文不再赘述。Please refer to FIG. 2 again, a passivation layer 205 covers the gate 204 and the second gate insulating layer 203 . In other specific implementation manners, if the second gate insulating layer 203 covers the surface of the first gate insulating layer 202 corresponding to the gate 204, the passivation layer 205 also covers the exposed the surface of the first gate insulating layer 202 . A source 206 and a drain 207 are connected to the source region and the drain region of the active layer 201 through the passivation layer 205 and the first gate insulating layer 202 . A planarization layer 208 covers the passivation layer 205 and the source electrode 206 and the drain electrode 207 , and a via hole (not shown in the figure) is formed at the position of the drain electrode 207 . An anode layer 209 of an OLED is connected to the drain 207 through the via hole. A pixel definition layer 210 is disposed on the anode layer 209 ; an organic light emitting layer 211 is disposed on the anode layer 209 and surrounded by the pixel definition layer 210 . The above-mentioned structures are conventional structures of OLED display devices in the field, and those skilled in the art can obtain their specific structures from the prior art, and will not be repeated here.
本发明还提供一种显示器件的制备方法。本发明显示器件的制备方法在制备所述显示器件的薄膜晶体管开关时，在第一栅极绝缘层上沉积一第二栅极绝缘层，在所述第二栅极绝缘层上形成栅极，所述第二栅极绝缘层的应力介于第一栅极绝缘层的应力与栅极的应力之间。图3A～图3G是本发明显示器件的制备方法的一个实施例的工艺流程图，该实施例以制备有机发光二极管显示器件为例来说明本发明显示器件的制备过程。The invention also provides a preparation method of the display device. In the manufacturing method of the display device of the present invention, when preparing the thin film transistor switch of the display device, a second gate insulating layer is deposited on the first gate insulating layer, and a gate is formed on the second gate insulating layer, The stress of the second gate insulating layer is between the stress of the first gate insulating layer and the stress of the gate. 3A to 3G are process flow diagrams of an embodiment of the method for manufacturing a display device of the present invention. This embodiment takes the preparation of an organic light emitting diode display device as an example to illustrate the process of manufacturing a display device of the present invention.
请参阅图3A所示，在基板300上形成一非晶硅层(a-Si)。形成所述非晶硅层的方法可以为等离子体气相沉积法(PECVD)。再采用LTPS技术形成多晶硅，其具体为通过ELA(准分子镭射结晶)使a-Si结晶转变为多晶硅(Poly-Si)，再图形化多晶硅层，形成有源层301。所述有源层301包括源极区域(附图中未标示)、漏极区域(附图中未标示)及位于所述源极区域及漏极区域之间的沟道区域(附图中未标示)。Referring to FIG. 3A , an amorphous silicon layer (a-Si) is formed on a substrate 300 . A method of forming the amorphous silicon layer may be plasma vapor deposition (PECVD). The LTPS technology is then used to form polysilicon, which specifically converts a-Si crystals into polysilicon (Poly-Si) through ELA (excimer laser crystallization), and then patterning the polysilicon layer to form the active layer 301 . The active layer 301 includes a source region (not shown in the drawings), a drain region (not shown in the drawings) and a channel region (not shown in the drawings) between the source region and the drain region. marked).
请参阅图3B所示，在所述基板300暴露的表面及所述有源层301的表面沉积第一栅极绝缘层302。优选地，所述第一栅极绝缘层302的材料为SiOx。形成所述第一栅极绝缘层302的方法为本领域常规的方法，例如CVD。Referring to FIG. 3B , a first gate insulating layer 302 is deposited on the exposed surface of the substrate 300 and the surface of the active layer 301 . Preferably, the material of the first gate insulating layer 302 is SiOx. The method for forming the first gate insulating layer 302 is a conventional method in the field, such as CVD.
请参阅图3C所示，在所述第一栅极绝缘层302的表面形成一第二栅极绝缘层303。优选地，所述第二栅极绝缘层的材料为SiONx。在本具体实施方式中，形成所述第二栅极绝缘层303的方法为等离子体化学气相沉积法(PECVD)，其具体参数是，成膜气体为SiH4、NH3及N2O，其中，SiH4、NH3及N2O的流量比为1～5：8～12：20～25，例如2：15：22、1：10：23；反应温度为300℃～400℃，例如320℃、360℃、380℃；反应时间为30～70S，例如40S、50S、60S。进一步，在本具体实施方式中，所述第二栅极绝缘层303覆盖所述第一栅极绝缘层302的全部表面。在本发明其他具体实施方式中，所述第二栅极绝缘层303覆盖所述第一栅极绝缘层302与栅极对应的位置处的表面。Referring to FIG. 3C , a second gate insulating layer 303 is formed on the surface of the first gate insulating layer 302 . Preferably, the material of the second gate insulating layer is SiONx. In this specific embodiment, the method for forming the second gate insulating layer 303 is plasma chemical vapor deposition (PECVD), and its specific parameters are that the film-forming gas is SiH4 , NH3 and N2 O, wherein , the flow ratio of SiH4 , NH3 and N2 O is 1~5:8~12:20~25, for example 2:15:22, 1:10:23; the reaction temperature is 300℃~400℃, for example 320 ℃, 360℃, 380℃; the reaction time is 30-70S, such as 40S, 50S, 60S. Further, in this specific implementation manner, the second gate insulating layer 303 covers the entire surface of the first gate insulating layer 302 . In other specific implementation manners of the present invention, the second gate insulating layer 303 covers the surface of the first gate insulating layer 302 at the position corresponding to the gate.
请参阅图3D所示，在所述第二栅极绝缘层303上形成一栅极304。优选地，所述栅极304的材料为金属钼(Mo)。所述第二栅极绝缘层303的应力介于第一栅极绝缘层302的应力与栅极304的应力之间。例如，所述第二栅极绝缘层303的应力小于所述栅极304的应力并且大于所述第一栅极绝缘层302的应力，使所述栅极304的应力与所述第一栅极绝缘层302的应力逐渐过渡。所述第二栅极绝缘层303能够很好地平衡所述第一栅极绝缘层302与栅极304之间的应力，使两者之间的应力更加匹配，防止栅极304脱落，进而可以大幅度改善薄膜晶体管开关的性能。进一步，在形成栅极304后，以栅极304为光罩通过自对准(self-align)技术对有源层301进行B+的离子植入，形成源极区域(附图中未标示)、漏极区域(附图中未标示)及位于源极区域与漏极区域之间的沟道区域(附图中未标示)，其中，所述栅极304对应沟道区域。Referring to FIG. 3D , a gate 304 is formed on the second gate insulating layer 303 . Preferably, the material of the gate 304 is molybdenum (Mo). The stress of the second gate insulating layer 303 is between the stress of the first gate insulating layer 302 and the stress of the gate 304 . For example, the stress of the second gate insulating layer 303 is smaller than the stress of the gate 304 and greater than the stress of the first gate insulating layer 302, so that the stress of the gate 304 is the same as that of the first gate The stress of the insulating layer 302 transitions gradually. The second gate insulating layer 303 can well balance the stress between the first gate insulating layer 302 and the gate 304, so that the stress between the two can be more matched, preventing the gate 304 from falling off, and then can Significantly improve the performance of thin film transistor switches. Further, after the gate 304 is formed, the active layer 301 is implanted with B+ ions using the gate 304 as a mask by self-aligning technology to form a source region (not shown in the drawings) , a drain region (not marked in the figure) and a channel region (not marked in the figure) between the source region and the drain region, wherein the gate 304 corresponds to the channel region.
请参阅图3E所示，在所述栅极304表面及暴露的第二栅极绝缘层303表面形成钝化层305。具体地说，采用PECVD方法沉积钝化层305，材料为SiOx+SiNx，然后通过快速热退火(RTA)进行活化和氢化，其中，快速热退火(RTA)技术为本领域的常规技术。进一步，在所述钝化层305上形成源极过孔306及漏极过孔307，所述源极过孔306及漏极过孔307分别包括出有源层301的源极区域及漏极区域。Referring to FIG. 3E , a passivation layer 305 is formed on the surface of the gate 304 and the exposed surface of the second gate insulating layer 303 . Specifically, the passivation layer 305 is deposited by PECVD, and the material is SiOx+SiNx, and then activated and hydrogenated by rapid thermal annealing (RTA), wherein the rapid thermal annealing (RTA) technology is a conventional technology in the art. Further, a source via hole 306 and a drain via hole 307 are formed on the passivation layer 305, and the source via hole 306 and the drain via hole 307 respectively include the source region and the drain of the active layer 301 area.
请参阅图3F所示，沉积金属层，所述金属层的金属通过所述源极过孔306及漏极过孔307与有源层301的源极区域及漏极区域接触。图形化所述金属层形成源极308及漏极309。其中，沉积金属层的方法可以为PVD方法。所述金属层的材料可以为多层金属Mo/Al/Mo。Referring to FIG. 3F , a metal layer is deposited, and the metal of the metal layer is in contact with the source region and the drain region of the active layer 301 through the source via hole 306 and the drain via hole 307 . Patterning the metal layer forms source 308 and drain 309 . Wherein, the method of depositing the metal layer may be a PVD method. The material of the metal layer may be multilayer metal Mo/Al/Mo.
请参阅图3G所示，在所述钝化层305及源极308、漏极309的表面依次形成一平坦化层310、阳极层311、像素定义层312、有机发光层313、阴极层314。其中，所述阳极层311穿过所述平坦化层310与所述漏极309接触，所述有机发光层313设置在所述阳极层311表面并被所述像素定义层312包围。所述平坦化层310及像素定义层312的材料均可以为有机材料。上述结构均为本领域OLED显示器件的常规结构，本领域技术人员可从现有技术中获取其具体结构，本文不再赘述。Referring to FIG. 3G , a planarization layer 310 , an anode layer 311 , a pixel definition layer 312 , an organic light emitting layer 313 , and a cathode layer 314 are sequentially formed on the surfaces of the passivation layer 305 , the source electrode 308 , and the drain electrode 309 . Wherein, the anode layer 311 is in contact with the drain electrode 309 through the planarization layer 310 , and the organic light emitting layer 313 is disposed on the surface of the anode layer 311 and surrounded by the pixel definition layer 312 . Materials of the planarization layer 310 and the pixel definition layer 312 can be organic materials. The above-mentioned structures are conventional structures of OLED display devices in the field, and those skilled in the art can obtain their specific structures from the prior art, and will not be repeated here.
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be considered Be the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
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| CN201710750696.3ACN107393968A (en) | 2017-08-28 | 2017-08-28 | Display device and preparation method thereof |
| Application Number | Priority Date | Filing Date | Title |
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| CN201710750696.3ACN107393968A (en) | 2017-08-28 | 2017-08-28 | Display device and preparation method thereof |
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| CN107393968Atrue CN107393968A (en) | 2017-11-24 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201710750696.3APendingCN107393968A (en) | 2017-08-28 | 2017-08-28 | Display device and preparation method thereof |
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| CN112397562A (en)* | 2020-11-13 | 2021-02-23 | 合肥鑫晟光电科技有限公司 | Display substrate, preparation method thereof and display device |
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