CN107346786B - GGNMOS transistors, multi-finger GGNMOS devices and circuits - Google Patents

Abstract

Translated fromChinese

本发明提供一种GGNMOS晶体管、多指GGNMOS器件及电路，所述GGNMOS晶体管的漏极区中悬浮有P型离子植入区，所述P型离子植入区至少其所有侧面和底面被包裹在所述漏极区中。本发明的多指GGNMOS器件中，各个GGNMOS晶体管的漏端中均悬浮有P型离子植入区。悬浮的P型离子植入区形成漏极区与P型衬底横向的齐纳辅助击穿区域，击穿电压更低，且在漏极区与P型衬底界面的交界处无PN结，从而可以在降低ESD保护的触发电压的同时，降低传统的ESD离子注入引入的漏电，提高了ESD保护电路的可靠性。

The invention provides a GGNMOS transistor, a multi-finger GGNMOS device and a circuit. A P-type ion implantation region is suspended in the drain region of the GGNMOS transistor, and at least all sides and bottom surfaces of the P-type ion implantation region are wrapped in in the drain region. In the multi-finger GGNMOS device of the present invention, a P-type ion implantation region is suspended in the drain terminal of each GGNMOS transistor. The suspended P-type ion implantation region forms a Zener-assisted breakdown region lateral to the drain region and the P-type substrate, with a lower breakdown voltage, and there is no PN junction at the junction of the drain region and the P-type substrate interface. Therefore, while reducing the trigger voltage of the ESD protection, the leakage current introduced by the traditional ESD ion implantation can be reduced, and the reliability of the ESD protection circuit can be improved.

Description

GGNMOS transistor, multi-finger GGNMOS device and circuit

Technical Field

The invention relates to the technical field of electrostatic discharge protection design of integrated circuits, in particular to a GGNMOS (grounded-gate bipolar transistor), a multi-finger GGNMOS (grounded-gate bipolar transistor) device and an electrostatic protection circuit.

Background

In Integrated Circuits (ICs), the influence of electrostatic discharge (ESD) on the reliability of a chip is not negligible, and particularly, in the present day where deep submicron and nanometer technologies are commonly applied, the destructive influence of electrostatic discharge such as external environment, human body, machinery, radiation field, and the like on an IC chip is more significant. The industry has made a lot of research and practice on ESD protection during the design and manufacturing process of IC, and generally, the design of the ESD protection device on the chip needs to consider two issues: firstly, the ESD protection device can release large current; the other is that the ESD protection device is capable of clamping the voltage at the pin terminal of the chip at a safe low voltage level when the chip is subjected to ESD shock. In view of the above design considerations, the devices used for ESD protection are mainly diodes, GGNMOS (Gate group NMOS, i.e., grounded-Gate NMOS), Silicon Controlled Rectifier (SCR), and the like. The GGNMOS is one of devices which are most frequently selected as an ESD protection device in the CMOS process, and mainly adopts a parasitic lateral NPN triode to work to discharge ESD large current, wherein the starting voltage of the parasitic lateral NPN triode depends on the avalanche breakdown voltage of a reverse PN junction of a collector of the parasitic lateral NPN triode, namely the avalanche breakdown voltage between a Drain (Drain) of the GGNMOS and a P well (P-well) in a substrate of the GGNMOS. When a GGNMOS is used as an ESD protection device, the width of the GGNMOS needs to be designed to be large to ensure that sufficient leakage current can pass through, and due to the layout limitation and the requirement of current uniformity, a GGNMOS structure is often designed to be a multi-finger (multi-finger) structure in the prior art, which is equivalent to parallel connection of fingers of a plurality of N-type MOS structures, as shown in fig. 1A, a layout structure diagram of a typical GGNMOS structure in the prior art includes: the P-type substrate (P-well)10, the N +active region 11, thegate 16, the comb-shaped source region 14 and the comb-shaped drain region 17, wherein the comb-shaped source region 14 and the comb-shaped drain region 17 are both disposed in the N +active region 11, thegate 16 is disposed on the upper surface of the P-type substrate 10 and disposed between thesource region 14 and thedrain region 17, the source S formed on thesource region 14, the drain D formed on thedrain region 17, and an NPN junction formed between each pair of the source S and the drain D is called a finger (finger), and the source and the drain of each GGNMOS transistor are correspondingly connected through acontact hole 16 and a metal interconnection structure (not shown) and are respectively connected to a ground terminal or a static terminal, etc. Fig. 1B and fig. 1C show schematic sectional structure diagrams and schematic circuit structure diagrams of the GGNMOS structure, when the GGNMOS structure is used for ESD protection, each source S andgate 16 of the GGNMOS structure are grounded, a Pickup region (Pickup, also referred to as a connection region) 12 is also grounded, a drain D is connected to a static end, and each pair of source S and drain D and a P-type substrate 10 below the source S and drain D form a parasitic NPN transistor. As can be seen from fig. 1B, the adjacent related NMOS transistors share a drain, and the distances from thepickup region 12 to the adjacent two NMOS transistors are different, so the internal resistance R-sub of the P-type substrate 10 between the base of the adjacent parasitic NPN transistor and thepickup region 12 is also different, and therefore, the inter-finger GGNMOS structure has the largest bulk resistance, which is prior to the turn-on of other inter-fingers, and each inter-finger cannot be turned on uniformly, which results in the reduction of the electrostatic protection capability of the whole circuit, and the breakdown voltage between the drain of the NMOS of the GGNMOS structure and the P-well is relatively high, which is not favorable for ESD protection.

In the prior art, in order to optimize and reduce the turn-on voltage of a common GGNMOS ESD protection device, a common scheme is to add one ESD injection, as disclosed in U.S. patent application No. US 2003/0089951 a1 shown in fig. 1D, which is a deep submicron CMOS process ESD injection technique for a high voltage tolerant ESD protection device (ESDPD), each GGNMOS transistor is formed by its corresponding SOURCE terminal, DRAIN terminal, and GATE structure located above P-WELL, and the N + injection region of the SOURCE terminal, the P-WELL, and the N + injection region of the DRAIN terminal form a parasitic NPN transistor, the N + injection region of the SOURCE terminal is an emission region of the parasitic NPN transistor, the P-WELL is a base region of the parasitic NPN transistor, the N + injection region of the DRAIN terminal is a collector region of the parasitic NPN transistor, and the technical scheme is in the collector region of the parasitic NPN transistor (see the region marked by a dashed box in fig. 1D, i.e., the collector regions of two adjacent parasitic NPN transistors), P-type ions (see ESD IMPLANT shown in fig. 1D in detail) are implanted at the interface between the N + implanted region at the DRAIN end of the NMOS and the P-WELL, so as to introduce a zener to reduce the avalanche breakdown voltage. Although the ESD injection technology can play a role in reducing the turn-on voltage of the GGNMOS ESD protection device, a layer of photoetching and injection process is required to be added, the manufacturing cost is increased, and meanwhile, the introduction of the ESD injection brings larger PN junction leakage to the device.

Therefore, there is a need for a GGNMOS transistor, a multi-finger GGNMOS device, and an electrostatic protection circuit that can reduce the trigger voltage and also reduce the leakage introduced by ESD injection.

Disclosure of Invention

The invention aims to provide a GGNMOS transistor, a multi-finger GGNMOS device and a circuit, which can reduce trigger voltage and reduce electric leakage introduced by ESD injection.

In order to solve the above problems, the present invention provides a GGNMOS transistor, including:

a P-type substrate;

the N-type active electrode region is formed on the P-type substrate and comprises a source region, a drain region and a channel region positioned between the source region and the drain region, a P-type ion implantation region is suspended in the drain region, and at least all side surfaces and the bottom surface of the P-type ion implantation region are wrapped in the drain region;

and the grid structure covers the channel region.

Furthermore, a P-well is formed between the P-type substrate and the N-type active electrode region, and the source region, the drain region and the channel region are all formed in the P-well.

Further, all surfaces of the P-type ion implantation area are wrapped in the drain area or the upper surface of the P-type ion implantation area is flush with the upper surface of the drain area.

Further, the P-type ion implantation region is located in the center of the drain region.

Furthermore, the junction depth of the drain electrode region above the P-type ion implantation region is smaller than that of the drain electrode region of the rest region.

Furthermore, the source region and the drain region are both strip-shaped.

Furthermore, the grid electrodes in the source electrode area and the grid electrode structure are grounded, and the drain electrode area is connected with an external circuit.

The invention also provides a multi-finger GGNMOS device, which comprises:

a P-type substrate;

an N-type active electrode region formed on the P-type substrate;

at least two GGNMOS transistors formed in the N-type active region.

Furthermore, source regions of all GGNMOS transistors are connected into a whole and arranged in a comb shape; the drain regions of all GGNMOS transistors are connected into a whole and arranged in a comb-tooth shape.

Furthermore, two adjacent GGNMOS transistors are common drain region transistors; or the drain regions of two adjacent GGNMOS transistors are mutually independent, and an N-type connecting well is arranged in the P-type substrate between the drain regions of the adjacent GGNMOS transistors and is connected with the drain regions on two sides of the N-type connecting well.

Further, a pickup region is provided in the N-type active electrode region at the periphery of all GGNMOS transistors.

Furthermore, the grid electrodes and the source electrode regions of all the GGNMOS transistors are grounded, the pickup region is grounded, and the drain electrode regions of all the GGNMOS transistors are connected with an external circuit.

Furthermore, the specifications of the suspended P-type ion implantation regions in the drain regions of all GGNMOS transistors are the same.

Further, the specifications of all GGNMOS transistors are the same.

The invention also provides an electrostatic protection circuit, which comprises an input end, a grounding end and at least one GGNMOS transistor, wherein the P-type substrate, the source region and the grid structure of each GGNMOS transistor are connected to the grounding end, and the drain region of each GGNMOS transistor is connected to the input end through a corresponding parasitic resistor; or the multi-finger GGNMOS device comprises the multi-finger GGNMOS device, the grid electrodes and the source electrode regions of all GGNMOS transistors of the multi-finger GGNMOS device are connected to the grounding end, and the drain electrode regions of all GGNMOS transistors of the multi-finger GGNMOS device are connected to the input end through corresponding parasitic resistors.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

1. according to the invention, the suspended P-type ion implantation area is inserted into the drain end of the GGNMOS transistor to form the Zener auxiliary breakdown area with the drain region and the P-type substrate in the transverse direction, the breakdown voltage is lower, and the suspended P-type ion implantation area has no PN junction at the junction of the drain region and the P-type substrate interface, so that the triggering voltage of ESD protection can be reduced, the electric leakage caused by the traditional ESD ion implantation can be reduced, and the reliability of an ESD protection circuit can be improved.

2. The formation of the P-type ion implantation area with the suspended drain end of the GGNMOS transistor can be completed simultaneously with the source-drain implantation in the PMOS process, so that an ESD ion implantation photomask and process can be omitted, the manufacturing cost is low, and the GGNMOS transistor is suitable for the CMOS process with the thickness of 28nm or more.

3. In the multi-finger GGNMOS device, the drain end of each GGNMOS transistor is suspended with a P-type ion implantation area, so that the length of a leakage channel of each single-finger GGNMOS is the same, the problem of triggering consistency of the traditional multi-finger GGNMOS device is solved, meanwhile, the length of the leakage channel is increased, the parasitic resistance value of the leakage channel is improved, and the GGNMOS can be switched on by relatively small static electricity to discharge the static electricity, so that the problems of rising triggering voltage and difficulty in static electricity leakage are solved.

Drawings

FIGS. 1A to 1C are schematic structural diagrams of a conventional multi-finger GGNMOS in the prior art;

FIG. 1D is a schematic diagram of an improved multi-finger GGNMOS of the prior art;

FIGS. 2A to 2C are schematic structural diagrams of a GGNMOS transistor according to an embodiment of the invention;

fig. 3A to 3C are schematic structural diagrams of a multi-finger GGNMOS device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.

Referring to fig. 2A to 2C, the present invention provides a GGNMOS transistor for ESD protection, including a P-type substrate 20, a P-well (P well)201, an N-active region 21 and agate structure 24, wherein the P-well 20 is located on the P-type substrate 20, the N-active region 21 is located on the P-well 201, asource region 22, adrain region 23 and a channel region (not shown) located between thesource region 22 and thedrain region 23 are located on the N-active region 21, thegate structure 24 covers the channel region, a P-typeion implantation region 231 is suspended in thedrain region 23, and at least all side surfaces and bottom surfaces of the P-typeion implantation region 231 are wrapped in thedrain region 23. In this embodiment, the ions implanted In the P-typeion implantation region 231 are P + ions, such as B (boron), In (indium), etc., and are dopedAt a concentration of 10¹²/cm²～10¹³/cm². Preferably, thesource region 22 and thedrain region 23 are strip-shaped, the P-typeion implantation region 231 is located at the center of thedrain region 23, each surface of the P-typeion implantation region 231 may be wrapped in thedrain region 23, and the depth of the drain region above the P-type ion implantation region is the same as the depth of the drain region below the P-type ion implantation region. In other embodiments of the present invention, the P-typeion implantation region 231 may not be completely located at the center of thedrain region 23, for example, the depth of thedrain region 23 above the P-typeion implantation region 231 is less than the depth of thedrain region 23 below the P-typeion implantation region 231, the depths of thedrain regions 23 at the left and right of the P-typeion implantation region 231 are the same, the depths of thedrain regions 23 in front of and behind the P-typeion implantation region 231 are the same, and the junction depth of the drain region above the P-type ion implantation region is less than the junction depth of the drain regions in the other regions. In a special case, the upper surface of the P-typeion implantation region 231 is exposed at the surface of the drain region 23 (not shown), i.e. the upper surface of the P-typeion implantation region 231 is flush with the upper surface of thedrain region 23.

The P-typeion implantation region 231 of the present invention is different from the P-type ion implantation region shown in fig. 1D, the area and the depth thereof are both greatly reduced, and PN junction leakage is not generated at the boundary between thedrain region 23 of the GGNMOS transistor and the P-well 201 interface, so that the P-type ion implantation region of the present invention can greatly reduce the leakage thereof while introducing the zener diode to reduce the trigger voltage of the GGNMOS transistor, and improve the reliability and the ESD protection capability of the ESD protection device based on the GGNMOS transistor.

And further. The doping concentration, doping area and doping thickness of the N-typeactive region 21 of the GGNMOS transistor change with the requirements of the process and the device, and other doping regions change with the requirements of the device, which is not limited in the embodiment.

The GGNMOS transistor is used for ESD protection, agrid structure 24 and asource region 22 are grounded through a metal interconnection structure such as acontact hole 25, adrain region 23 is connected to an electrostatic end through a metal interconnection structure such as acontact hole 25, namely the electrostatic end of an external circuit to be protected by ESD is connected, and the specific working principle is as follows:

a parasitic NPN transistor is formed by thesource region 22, the P well 201, and thedrain region 23 of the GGNMOS transistor, thesource region 22 of the GGNMOS transistor is the emitter of the NPN transistor, the P well 201 is the base of the NPN transistor, thedrain region 23 is the collector of the NPN transistor, and a lateral zener diode is formed between the collector of the NPN transistor and an external circuit to be ESD protected by the P-typeion implantation region 231 introduced into the drain region 23 (i.e., N-type region), as shown in fig. 2C. When ESD impact occurs, ESD current flows into thedrain region 23 and the P-typeion implantation region 231 thereof through an electrostatic end of an external circuit, and then flows into the P-well 201, due to parasitic resistance in the P-well 201, ESD current generates a voltage difference in the P-well 201, and at this time, a zener diode formed by introducing the P-typeion implantation region 231 makes a higher electric field, a smaller leakage current, and a more stable voltage difference exist between thedrain region 23 and the P-well 201, and when the voltage difference exceeds a threshold voltage, a parasitic NPN triode is in a conducting state, and at this time, current flows in from thedrain region 23, and finally flows out through thesource region 22, and static electricity is discharged, thereby avoiding electrostatic damage to the circuit. Meanwhile, the P-typeion implantation area 231 has the effect similar to point discharge, so that the auxiliary breakdown of ESD is realized, and the lower excitation voltage of GGNMOS can be obtained, thereby solving the problems of increased trigger voltage and difficult electrostatic leakage, and more effectively protecting the core device of an external circuit.

Referring to fig. 2A and 2B, fig. 2A is a top view of the GGNMOS transistor of the present invention (with the metal layer omitted for clarity), fig. 2B is a perspective view of the GGNMOS transistor of the present invention (with the metal layer and contact holes omitted for clarity), and the process of manufacturing the GGNMOS transistor of the present invention includes the following steps:

step S1: providing a P-type substrate 20, wherein the P-type substrate 20 is a P-type lightly doped silicon wafer or a silicon-on-insulator substrate, and the electrical resistance, the impurity concentration and other properties of the P-type substrate meet the electrical requirements of the device. Further, P-type ion well implantation and N-type ion active region implantation are sequentially performed on the P-type substrate 20, thereby sequentially forming a P-well 201 and an N-typeactive region 21.

Step S2: agate structure 24 including a gate oxide layer and a polysilicon gate is sequentially formed on the N-typeactive region 21. Specifically, firstly, before forming a gate oxide layer, an oxide isolation region is formed in a non-active region of the P-type substrate 20 by using a device isolation method such as LOCOS or STI; then, cleaning the silicon wafer, removing the contamination and the oxide layer on the surface, and forming a layer of silicon oxide film on the N-typeactive region 21 as a gate oxide layer through an oxidation furnace process or a chemical vapor deposition process; depositing a polycrystalline silicon layer on the gate oxide layer by utilizing silane and low-pressure chemical vapor deposition equipment, and carrying out phosphorus doping or silicification on the deposited polycrystalline silicon; then, a polysilicon gate with a vertical profile is selectively etched by using a deep ultraviolet lithography technique and an anisotropic plasma etching technique, thereby obtaining agate structure 24 including a gate oxide layer and the polysilicon gate. Further, by using a deposition etching process of silicon nitride or silicon oxide, etc., a sidewall surrounding thegate structure 24 is formed on the side surface of the gate structure

Step S3: and performing LDD implantation and source/drain implantation on the N-typeactive regions 21 on two sides of thegate structure 24 by taking the gate structure as a mask, and performing source-drain ion implantation annealing to form asource region 22 and adrain region 23. The LDD implantation, i.e. lightly doped drain implantation, is to lightly dope the N-typeactive region 21 on at least one side of thegate structure 24 before forming thesource region 22 and thedrain region 23 of the GGNMOS transistor, and then perform source/drain ion implantation on the N-typeactive regions 21 on both sides of thegate structure 24, so as to effectively prevent the short channel effect and reduce the hot electron effect in the channel region between the source and the drain. In this embodiment, after the LDD implantation using thegate structure 24 as a mask, N-type ions are performed on the N-type active regions on both sides of thegate structure 24 to form thesource region 22 and thedrain region 23. The manner in which the ion implantation to formsource region 22 and drainregion 23 is performed usinggate structure 24 as a mask is thus self-aligned, with only laterally offset portions of the implanted ions overlappinggate structure 24, so that the parasitic gate-drain to gate-source coupling capacitance can be much smaller than the gate-channel capacitance. And annealing the device subjected to the source-drain ion implantation in a rapid annealing device. The rapid annealing device can rapidly reach the high temperature of about 1000 ℃ and keep the temperature at the set temperature for a plurality of seconds. This state is important for preventing the expansion of the structure and controlling the diffusion of impurities in thesource region 22 and thedrain region 23. Specifically, the annealing is implemented as follows: in the inert gas environment such as nitrogen or argon, the annealing temperature is 900-1000 ℃, and the annealing time is 10-60 s.

Step S4: the source/drain region ion implantation mask and process of the PMOS process are directly used to perform P-type ion implantation on the central region of thedrain region 23 to form the P-typeion implantation region 231 to realize ESD-assisted breakdown of thedrain region 23, so that the step can be completed simultaneously with the source/drain region ion implantation step of the PMOS process on the integrated circuit chip to be manufactured, obviously the ESD ion implantation mask and process can be omitted, the purpose of reducing the turn-on voltage of the GGNMOS ESD protection device is achieved, and excellent leakage control can be achieved. Specifically, after step S3, a photoresist is applied on the device surface, and a mask for ion implantation of the source/drain regions in the PMOS process is formed after exposure and development, in which a P-type ion implantation window is simultaneously formed at a corresponding position of thedrain region 23, for example, above the center position of the drain region 23 (i.e., the front-back and left-right symmetrical position of the drain region 23). With the photomask as a mask, B, In ions are implanted into the source/drain region of the PMOS process by using materials such as boron difluoride and indium phosphide, and simultaneously, B, In P + type impurity ions are implanted into thedrain region 23 in the P-type ion implantation window, so that a P-typeion implantation region 231 is formed, and then the photoresist is removed. The P-typeion implantation region 231 may be completely located at the center of thedrain region 23, that is, the junction depth of thedrain region 23 above the P-typeion implantation region 231 may be the same as the junction depth of thedrain region 23 below the P-type ion implantation region; the P-typeion implantation region 231 may not be completely located at the center of thedrain region 23, that is, the junction depth of thedrain region 23 above the P-typeion implantation region 231 may be smaller than that of thedrain region 23 below the P-type ion implantation region, but the width of thedrain region 23 on the left side may be the same as that of thedrain region 23 on the right side, and the width of thedrain region 23 on the front side may be the same as that of thedrain region 23 on the rear side. The GGNMOS transistor device after P-type ion implantation may be annealed in a rapid annealing apparatus. The rapid annealing device can rapidly reach the high temperature of about 1000 ℃ and keep the temperature at the set temperature for a plurality of seconds. This state is important to prevent the expansion of the structure and to control the diffusion of the source/drain impurity. Specifically, the annealing is implemented as follows: in the inert gas environment of nitrogen or argon and the like, the annealing temperature is 350-550 ℃, and the annealing time is 5-20 s. In addition, the function of adjusting the P-type ion implantation window can be achieved by changing the size of the corresponding position of the photomask, so that the area of a compressed region of the transverse Zener tube formed by implanting different P-type ions into the N +drain region 23 can be obtained, and the function of adjusting the breakdown starting voltage of the transverse Zener tube can be achieved. The depth of the formed P-type ion implantation region can be adjusted by changing the process parameters such as the P-type ion implantation dosage, the energy and the like, so that the effect of adjusting the breakdown starting voltage is achieved.

Step S5: and forming acontact hole 25 and a metal interconnection layer at a corresponding position on the surface of the device including the P-typeion implantation area 231, and the like, thereby forming the GGNMOS transistor with good ESD protection effect.

Because the P-typeion implantation region 231 can be completed simultaneously with the source-drain implantation in the PMOS process, the manufacturing method of the GGNMOS transistor can omit an ESD ion implantation photomask and process, has low manufacturing cost, and is suitable for the CMOS process with the thickness of 28nm and above.

Referring to fig. 3A and 3B, fig. 3A is a top view of the multi-finger GGNMOS device of the present invention (with metal layer omitted for clarity), fig. 3B is a perspective view of the multi-finger GGNMOS device of the present invention (with metal layer and contact hole omitted for clarity), the present invention further provides a multi-finger GGNMOS device, which comprises a P-type substrate 30, an N-typeactive region 31, and at least two of the above-mentioned GGNMOS transistors formed in the N-typeactive region 31, specifically, a plurality of sets ofstrip source regions 32 andstrip drain regions 33 are formed in the N-typeactive region 31, each set ofstrip source regions 32,strip drain regions 33 andgate structures 34 thereon form a GGNMOS transistor, and each set ofstrip source regions 32,strip drain regions 33 and P-type substrate 30 therebetween (specifically, P-well 301 on the P-type substrate) form a finger of the multi-finger GGNMOS device, and eachstrip drain region 33 is provided with a P-typeion implantation region 331 suspended therein, all sides and bottom surfaces of the P-typeion implantation region 331 are wrapped in the stripe-shapeddrain region 33, and even the upper surface is included in the stripe-shapeddrain region 33.

In addition, all the strip-shapedsource regions 32 on the N-typeactive region 31 may be independent from each other, and may be connected as a whole at the boundary position of the N-typeactive region 31, thereby forming a comb-teeth-shaped arrangement structure; similarly, all the strip-shapeddrain regions 33 on the N-typeactive region 31 may be independent of each other, and may be connected together at the boundary position of the N-typeactive region 31, thereby forming a comb-teeth-shaped arrangement structure. Therefore, in an embodiment of the present invention, a device isolation structure may be disposed between all GGNMOS transistors of the multi-finger GGNMOS device, andsource regions 32 anddrain regions 33 of all GGNMOS transistors are isolated by field isolation regions and are independent of each other, as shown in fig. 3C (fig. 3C is a cross-sectional view of the multi-finger GGNMOS device of the present invention, where metal layers and contact holes are omitted for clarity), an N-type connection well 303 is disposed in the P-type substrate 30 between thedrain regions 33 of two adjacent GGNMOS transistors, and the N-type connection well 303 is connected to thedrain regions 33 on two sides thereof for electrically connecting the two independent GGNMOS transistors. In another embodiment of the present invention, all GGNMOS transistors of a multi-finger GGNMOS device may be associated with each other, such as two adjacent GGNMOS transistors sharing onesource region 32 or two adjacent GGNMOS transistors sharing onedrain region 33 as shown in fig. 3A and 3B, and further, a pickup region (pick up)302 is disposed in the N-typeactive electrode region 31 at the periphery of all GGNMOS transistors, and the ions doped in the pickup region may be N-type ions or P-type ions.

Preferably, all the P-type ion implantation regions in the GGNMOS device have the same specification, that is, the positions, the doping ions, the doping concentrations, and the like of all the P-type ion implantation regions are the same. Further, all the GGNMOS transistors in the GGNMOS device have the same specification.

When the GGNMOS device is used for ESD protection, thegate structures 34, thesource regions 32 and thepickup regions 302 of all GGNMOS transistors are grounded, and thedrain regions 33 of all GGNMOS transistors are connected with an external circuit to be ESD protected, namely thedrain regions 33 of all GGNMOS transistors are connected to an electrostatic terminal. When electrostatic discharge (namely ESD impact) occurs, because a suspended P-type ion implantation area is arranged in a small area at the center of thedrain region 33 of each finger of the GGNMOS device, the depth of the P-typeion implantation area 331 does not generate PN junction leakage at the boundary of thedrain region 33 of each finger and the P well 301, and meanwhile, a transverse Zener auxiliary breakdown area (namely Zener diode) is still formed between thedrain region 33 of the finger NMOS (namely the GGNMOS transistor) and the P-type substrate 30, so that the starting voltage of each single-finger NMOS of the GGNMOS device is basically the same and greatly reduced, and the problems of inconsistent triggering and high triggering voltage of the traditional multi-finger GGNMOS device are solved. In addition, since thedrain regions 33 and thesource regions 32 of all the GGNMOS transistors in the GGNMOS devices shown in fig. 3A to 3C are connected together and grounded, the entire GGNMOS device is equivalent to an N-type MOS transistor with a long width, and the electrostatic discharge capacity is greatly improved compared with that of a single GGNMOS transistor shown in fig. 2A to 2C. Meanwhile, each P-type ion implantation area of the whole GGNMOS device can directly utilize a source and drain area ion implantation photomask and the same type of P-type ions in the PMOS process, namely, each P-type ion implantation area can be synchronously completed through the source and drain area ion implantation process in the PMOS process, so that any extra ESD photomask and ESD ion implantation are not needed, the process is simplified, and the cost is saved.

Referring to fig. 3A and 3B, a method for manufacturing a multi-finger GGNMOS device according to the present invention includes the following steps:

first, a P-type substrate 30 is provided, a PMOS device region (not shown) and a GGNMOS device region are provided in the P-type substrate 30, a P well 301 and an N-typeactive region 31 are sequentially formed in the GGNMOS device region, and apickup region 302 is formed in a non-active region (i.e., a periphery of the N-type active region 31) of the P-type substrate 30. Then, by means of device isolation methods such as LOCOS or STI, oxide isolation regions (not shown) are formed in appropriate positions of the non-active region, the PMOS device region, and the N-typeactive region 31 of the P-type substrate 30, so as to achieve isolation of two adjacent PMOS device regions in the PMOS device region, isolation of the PMOS device region from the GGNMOS device region, isolation of two adjacent GGNMOS device regions in the GGNMOS device region, and isolation of two adjacent GGNMOS transistors in each GGNMOS device region, and the N-typeactive region 31 defines positions of all GGNMOS transistors of the multi-finger GGNMOS device. Preferably, the layout structure of the multi-finger GGNMOS device is basically consistent with that of the existing multi-finger GGNMOS device, and is still in a square shape with uniform length and width, so that the overall layout of the ESD protection device in a chip is facilitated.

Then, a thin oxide layer and a polysilicon layer are sequentially formed on the N-typeactive region 31, and a plurality ofgate structures 34 are formed by etching. The gate structure may further include a sidewall spacer structure located on both sides of the polysilicon layer and the oxide layer, and the sidewall spacer structure may include at least one oxide layer and/or at least one nitride layer. Thegate structure 34 defines source and drain regions for each finger of the multi-finger GGNMOS device on either side. In this step, a gate structure may be formed on the PMOS device region at the same time, and the gate structure may be formed by etching the thin oxide layer and the polysilicon layer as well.

Then, using eachgate structure 34 on the N-typeactive region 31 as a mask, performing source/drain region implantation of a GGNMOS device region and annealing, thereby forming asource region 32 and adrain region 33 of each finger-strip GGNMOS transistor of the multi-finger GGNMOS device in the N-typeactive region 31 on both sides of eachgate structure 34. Two adjacent GGNMOS transistors of the multi-finger GGNMOS device may have a structure of a common source region, a structure of a common drain region, or a structure of a source/drain region separated from each other, according to the position of the oxide isolation region disposed in the N-typeactive region 31.

Then, the P-typeion implantation regions 231 are formed in eachdrain region 23 in the ion implantation process of the source/drain regions for the PMOS process, so that the ESD ion implantation mask and process can be omitted to achieve the purpose of reducing the turn-on voltage of the GGNMOS ESD protection device and achieve excellent leakage control. Specifically, a photoresist is coated on the device surface including the GGNMOS device region and the PMOS device region, an ion implantation mask of source/drain regions of the PMOS region is formed after exposure and development, and a P-type ion implantation mask is formed on the GGNMOS device region, for example, above the central position of the drain region 23 (i.e., the front-back and left-right symmetrical position of the drain region 23). The method comprises the steps of taking a photomask for ion implantation of a source/drain region of a PMOS device region and a P-type ion implantation photomask on a GGNMOS device region as masks, implanting P + type ions such as B, In into the source/drain region of the PMOS device region by adopting materials such as boron difluoride and indium phosphide, implanting P + type impurity ions such as B, In into adrain region 23 under the P-type ion implantation photomask to form a P-typeion implantation region 331, and removing photoresist. The P-typeion implantation area 331 may be completely located at the center of thedrain region 33 where the P-typeion implantation area 331 is located, that is, the junction depth of thedrain region 33 above the P-typeion implantation area 331 may be the same as the junction depth of thedrain region 33 below the P-typeion implantation area 331; the P-typeion implantation area 331 may not be located at the center of thedrain region 33, i.e. the junction depth of thedrain region 33 above the P-typeion implantation area 331 may be smaller than that of thedrain region 33 below the P-typeion implantation area 331, but the width of thedrain region 33 on the left side may be the same as that of thedrain region 33 on the right side, and the width of thedrain region 33 on the front side may be the same as that of thedrain region 33 on the rear side. The P-type ion implanted device may be annealed in a rapid annealing apparatus. To this end, all process steps performed by the method according to an exemplary embodiment of the present invention are completed to form a GGNMOS device for electrostatic discharge protection at the same time as the PMOS device is formed. Next, the fabrication of the entire semiconductor device may be completed by a subsequent process, which is identical to the conventional semiconductor device processing process. When electrostatic discharge occurs, each finger in the GGNMOS can simultaneously start the electrostatic discharge protection, and the electrostatic discharge protection level measured by a human body discharge mode (HBM) is improved.

The invention also provides an electrostatic protection circuit, which comprises an input end, a grounding end and at least one GGNMOS transistor shown in figure 2A, wherein the P-type substrate 20, thesource region 22 and thegate structure 24 of each GGNMOS transistor are all connected to the grounding end, and thedrain region 23 of each GGNMOS transistor is connected to the input end through a corresponding parasitic resistor; or comprises the multi-finger GGNMOS device shown in fig. 3AC, thegate structures 34 and thesource regions 32 of all the GGNMOS transistors of the multi-finger GGNMOS device are connected to the ground terminal, and thedrain regions 33 of all the GGNMOS transistors of the multi-finger GGNMOS device are connected to the input terminal through corresponding parasitic resistors.

Further, referring to fig. 3A and 3C, in an embodiment of the present invention, apickup region 302 is disposed in the N-typeactive electrode region 31 at the periphery of all GGNMOS transistor device regions of the multi-finger GGNMOS device of the electrostatic protection circuit, thepickup region 302 is connected to the ground terminal, and the parasitic resistance corresponding to each GGNMOS transistor is the parasitic internal resistance between the base of the parasitic NPN transistor corresponding to the GGNMOS transistor and the P-type substrate 30.

Further, referring to fig. 3A and 3B, two adjacent GGNMOS transistors of the multi-finger GGNMOS device of the electrostatic protection circuit may be in a common source region structure or a common drain region structure; alternatively, referring to fig. 3C, thesource regions 32 of two adjacent GGNMOS transistors of the multi-finger GGNMOS device of the esd protection circuit are isolated and independent from each other by thecorresponding isolation structures 36, thedrain regions 33 are isolated and independent from each other by thecorresponding isolation structures 36, and an N-type connection well is disposed in the P-well 301 under thedrain regions 33 of the two adjacent GGNMOS transistors, so as to electrically connect thedrain regions 33 of the two adjacent GGNMOS transistors.

The electrostatic protection circuit of the invention with a plurality of GGNMOS transistors shown in FIG. 2A, all GGNMOS transistors are connected in parallel; in the electrostatic protection circuit with the GGNMOS device shown in fig. 3A, the GGNMOS device has a multi-finger NMOS structure, which is equivalent to a plurality of single-finger NMOS devices connected in parallel. The floating P-type ion implantation area is arranged in the drain area of the GGNMOS, so that the trigger voltage of the electrostatic protection circuit can be reduced, and PN junction leakage cannot be generated at the junction of the drain area of the GGNMOS and the P-type substrate, so that the reliability and the ESD protection level of the electrostatic protection circuit are improved. In addition, the suspended P-type ion implantation area with the same specification can solve the problem of trigger consistency among a plurality of parallel GGNMOS transistors in the electrostatic protection circuit or a plurality of fingers of GGNMOS devices in the electrostatic protection circuit and the problems of trigger voltage rise and difficult electrostatic leakage.

It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (15)

Translated fromChinese

1.一种GGNMOS晶体管，其特征在于，包括：1. a GGNMOS transistor, is characterized in that, comprises:P型衬底；P-type substrate;N型有源极区，形成在所述P型衬底上，所述N型有源极区包括源极区、漏极区以及位于所述源极区、漏极区之间的沟道区，所述漏极区中悬浮有P型离子植入区，所述P型离子植入区至少其所有侧面和底面被包裹在所述漏极区中；An N-type active region is formed on the P-type substrate, the N-type active region includes a source region, a drain region and a channel region located between the source and drain regions , a P-type ion implantation region is suspended in the drain region, and at least all sides and bottom surfaces of the P-type ion implantation region are wrapped in the drain region;栅极结构，覆盖在所述沟道区上方；a gate structure covering the channel region;其中，所述P型衬底和N型有源极区之间还形成有P阱，所述源极区、漏极区和沟道区均形成在所述P阱中，且所述P型离子植入区的面积和深度满足以下两个条件：(1)不会在所述漏极区和所述P阱界面的交界处产生PN结漏电；(2)能在所述漏极区与所述漏极区所连接的待ESD保护的外部电路之间形成一个横向齐纳二极管。Wherein, a P well is also formed between the P-type substrate and the N-type active region, the source region, the drain region and the channel region are all formed in the P-well, and the P-type The area and depth of the ion implantation region satisfy the following two conditions: (1) PN junction leakage will not be generated at the junction of the drain region and the P-well interface; (2) the drain region and A lateral zener diode is formed between the external circuits to be ESD protected connected to the drain region.2.如权利要求1所述的GGNMOS晶体管，其特征在于，所述P型离子植入区的所有表面均被包裹在所述漏极区中或者所述P型离子植入区的上表面与所述漏极区上表面齐平。2. The GGNMOS transistor according to claim 1, wherein all surfaces of the P-type ion implantation region are wrapped in the drain region or the upper surface of the P-type ion implantation region is The upper surface of the drain region is flush.3.如权利要求1所述的GGNMOS晶体管，其特征在于，所述P型离子植入区处于所述漏极区的中心位置。3 . The GGNMOS transistor of claim 1 , wherein the P-type ion implantation region is located at the center of the drain region. 4 .4.如权利要求1所述的GGNMOS晶体管，其特征在于，所述P型离子植入区上方的漏极区结深小于其余区域的漏极区的结深。4 . The GGNMOS transistor of claim 1 , wherein the junction depth of the drain region above the P-type ion implanted region is smaller than the junction depth of the drain region of the remaining regions. 5 .5.如权利要求1所述的GGNMOS晶体管，其特征在于，所述源极区、漏极区均呈条形。5 . The GGNMOS transistor of claim 1 , wherein the source region and the drain region are both strip-shaped. 6 .6.如权利要求1所述的GGNMOS晶体管，其特征在于，所述源极区和栅极结构均接地，所述漏极区接外部电路。6 . The GGNMOS transistor of claim 1 , wherein the source region and the gate structure are both grounded, and the drain region is connected to an external circuit. 7 .7.一种多指GGNMOS器件，其特征在于，包括：7. A multi-fingered GGNMOS device, characterized in that, comprising:P型衬底；P-type substrate;N型有源极区，形成在所述P型衬底上；An N-type active region is formed on the P-type substrate;形成于N型有源极区内的至少两个权利要求1至6中任一项所述的GGNMOS晶体管。At least two GGNMOS transistors according to any one of claims 1 to 6 are formed in the N-type active region.8.如权利要求7所述的多指GGNMOS器件，其特征在于，所有GGNMOS晶体管的源极区连接为一体，并呈梳齿状排列。8 . The multi-finger GGNMOS device according to claim 7 , wherein the source regions of all GGNMOS transistors are connected as a whole and arranged in a comb-like shape. 9 .9.如权利要求7所述的多指GGNMOS器件，其特征在于，所有GGNMOS晶体管的漏极区连接为一体，并呈梳齿状排列。9 . The multi-finger GGNMOS device according to claim 7 , wherein the drain regions of all GGNMOS transistors are connected as a whole and arranged in a comb-like shape. 10 .10.如权利要求7所述的多指GGNMOS器件，其特征在于，相邻两个GGNMOS晶体管为共漏极区晶体管；或者相邻两个GGNMOS晶体管的漏极区相互独立，且位于相邻GGNMOS晶体管的漏极区之间的P型衬底内设有N型连接阱，且所述N型连接阱与其两侧的漏极区连接。10. The multi-finger GGNMOS device according to claim 7, wherein two adjacent GGNMOS transistors are transistors in a common drain region; or the drain regions of two adjacent GGNMOS transistors are independent of each other and are located in adjacent GGNMOS transistors. An N-type connection well is arranged in the P-type substrate between the drain regions of the transistor, and the N-type connection well is connected to the drain regions on both sides of the N-type connection well.11.如权利要求7所述的多指GGNMOS器件，其特征在于，在所有GGNMOS晶体管外围的所述N型有源极区中设有拾取区。11. The multi-fingered GGNMOS device according to claim 7, wherein pick-up regions are provided in the N-type active regions around all GGNMOS transistors.12.如权利要求11所述的多指GGNMOS器件，其特征在于，所有GGNMOS晶体管的栅极结构、源极区均接地，所述拾取区接地，所有GGNMOS晶体管的漏极区接外部电路。12 . The multi-finger GGNMOS device according to claim 11 , wherein the gate structures and source regions of all GGNMOS transistors are grounded, the pickup region is grounded, and the drain regions of all GGNMOS transistors are connected to external circuits. 13 .13.如权利要求7所述的多指GGNMOS器件，其特征在于，所有GGNMOS晶体管的漏极区中悬浮的P型离子植入区的规格相同。13 . The multi-finger GGNMOS device of claim 7 , wherein the specifications of the floating P-type ion implantation regions in the drain regions of all GGNMOS transistors are the same. 14 .14.如权利要求7所述的多指GGNMOS器件，其特征在于，所有GGNMOS晶体管的规格相同。14. The multi-finger GGNMOS device of claim 7, wherein all GGNMOS transistors have the same specifications.15.一种静电保护电路，其特征在于，包括输入端、接地端以及至少一个权利要求1至6中任一项所述的GGNMOS晶体管，每个GGNMOS晶体管的P型衬底、源极区、栅极结构均连接至所述接地端，每个GGNMOS晶体管的漏极区通过相应的寄生电阻连接至所述输入端；或者包括权利要求7至14中任一项所述的多指GGNMOS器件，所述多指GGNMOS器件的所有GGNMOS晶体管的栅极结构、源极区均连接至所述接地端，所述多指GGNMOS器件的所有GGNMOS晶体管的漏极区均通过相应的寄生电阻连接至所述输入端。15. An electrostatic protection circuit, characterized in that it comprises an input terminal, a ground terminal and at least one GGNMOS transistor according to any one of claims 1 to 6, wherein the P-type substrate, source region, The gate structures are all connected to the ground terminal, and the drain region of each GGNMOS transistor is connected to the input terminal through a corresponding parasitic resistance; or the multi-finger GGNMOS device according to any one of claims 7 to 14 is included, The gate structures and source regions of all GGNMOS transistors of the multi-finger GGNMOS device are connected to the ground terminal, and the drain regions of all GGNMOS transistors of the multi-finger GGNMOS device are connected to the ground through corresponding parasitic resistances. input.

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