技术领域technical field
本发明涉及一种服务器。The present invention relates to a server.
背景技术Background technique
在服务器设计中,经常会采用硬盘背板来接入到计算节点中,用于实现存储扩展,使得计算节点能够通过硬盘背板连接更多的硬盘。硬盘背板上通常设有CPLD,计算节点可以通过I2C总线访问硬盘背板的CPLD来实现读取硬盘状态或设置硬盘指示灯等功能。(如硬盘在位,硬盘错误状态等)。In server design, hard disk backplanes are often used to connect to computing nodes for storage expansion, so that computing nodes can connect more hard disks through the hard disk backplane. There is usually a CPLD on the hard disk backplane, and the computing node can access the CPLD on the hard disk backplane through the I2C bus to realize functions such as reading the hard disk status or setting the hard disk indicator. (such as hard disk in place, hard disk error status, etc.).
I2C(Inter-Integrated Circuit)总线是由PHILIPS公司开发的两线式串行总线,用于连接微控制器及其外围设备。是微电子通信控制领域广泛采用的一种总线标准。它是同步通信的一种特殊形式,具有接口线少,控制方式简单,器件封装形式小,通信速率较高等优点。I2C总线上每一个设备必须设有唯一的地址,如果地址有重复,则I2C线路异常,无法进行正常的数据通信。The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS for connecting microcontrollers and their peripherals. It is a bus standard widely used in the field of microelectronics communication control. It is a special form of synchronous communication, which has the advantages of less interface lines, simple control mode, small device package, and high communication rate. Each device on the I2C bus must have a unique address. If the address is repeated, the I2C line is abnormal and normal data communication cannot be performed.
如图1所示为现有技术一的方案框图,多个硬盘背板的CPLD通过I2C总线接到计算节点上,和计算节点进行数据交互。由于多个硬盘背板在同一I2C总线上,需要保证它们的I2C地址各不相同。因此在每个硬盘背板上,都将开关(可以使开关形式,也可以是跳帽形式)接到CPLD上,不同的硬盘背板上手动设置不同的开关值。CPLD读取这些开关值并按照预设的对应关系,根据读取到的开关值,设置CPLD的I2C地址。该技术的缺点在于,不同硬盘背板的I2C地址需要根据硬盘背板上的调帽或拨码开关来设置。这种做法的缺点是,跳帽或拨码开关需要手动调整,不仅操作复杂,批量生产的时候,操作人员也容易因为失误出现错误配置的情况。As shown in FIG. 1 , a solution block diagram of the prior art 1, CPLDs of multiple hard disk backplanes are connected to computing nodes through an I2C bus, and perform data interaction with the computing nodes. Since multiple hard disk backplanes are on the same I2C bus, it is necessary to ensure that their I2C addresses are different. Therefore, on each hard disk backplane, a switch (in the form of a switch or a jumper) is connected to the CPLD, and different switch values are manually set on different hard disk backplanes. The CPLD reads these switch values and sets the I2C address of the CPLD according to the read switch values according to the preset corresponding relationship. The disadvantage of this technology is that the I2C addresses of different hard disk backplanes need to be set according to the adjustment cap or the dial switch on the hard disk backplane. The disadvantage of this method is that the jumper cap or the DIP switch needs to be manually adjusted, which is not only complicated to operate, but also prone to misconfiguration due to mistakes by operators during mass production.
因此,如何为多个硬盘背板设置不同的I2C地址,是本领域需解决的问题。Therefore, how to set different I2C addresses for multiple hard disk backplanes is a problem to be solved in this field.
发明内容Contents of the invention
本发明为解决为服务器的硬盘背板设置自动的I2C地址分配机制,避免通过手动操作设置。为此,本发明提供一种服务器及服务器硬盘板卡分配I2C地址的方法,它具有硬盘背板CPLD自行判断、设置I2C地址的功能,无需人为的操作的优点。The present invention solves the problem of setting an automatic I2C address allocation mechanism for the hard disk backplane of the server, avoiding setting by manual operation. For this reason, the present invention provides a method for assigning I2C addresses to servers and server hard disk boards, which has the advantage of self-judging and setting I2C addresses by the CPLD on the hard disk backplane, and does not require manual operations.
为了实现上述目的,本发明采用如下技术方案。In order to achieve the above object, the present invention adopts the following technical solutions.
一种服务器,包含计算节点及多个硬盘背板,多个硬盘背板即包含硬盘背板1、硬盘背板2、…硬盘背板N;所述计算节点包含一I2C主设备;所述多个硬盘背板各包含一CPLD、一位置识别信号及电源;各硬盘背板上所述位置识别号与CPLD及计算节点连接,并通过电阻连接到电源上,所述CPLD各有一输入信号信号1及一输出信号信号2;在计算节点上将硬盘背板1的信号1端悬空,并将硬盘背板1的信号2端接到硬盘背板2的信号1端,以此类推,上一硬盘背板的信号2端连接到下一硬盘背板的信号1端,硬盘背板N的信号2端悬空。A server, comprising a computing node and a plurality of hard disk backplanes, the plurality of hard disk backplanes include a hard disk backplane 1, a hard disk backplane 2, ... hard disk backplane N; the computing node includes an I2C master device; the multiple Each hard disk backplane includes a CPLD, a position identification signal and a power supply; the position identification number on each hard disk backplane is connected to the CPLD and the computing node, and is connected to the power supply through a resistor, and each of the CPLDs has an input signal signal 1 And an output signal signal 2; on the computing node, the signal 1 end of the hard disk backplane 1 is suspended, and the signal 2 end of the hard disk backplane 1 is connected to the signal 1 end of the hard disk backplane 2, and so on, the last hard disk The signal 2 terminal of the backplane is connected to the signal 1 terminal of the next hard disk backplane, and the signal 2 terminal of the hard disk backplane N is suspended.
根据以上连接,硬盘背板1会识别到自己的位置识别信号是低电平,其他硬盘背板会识别到自己的位置识别信号为高电平。According to the above connection, the hard disk backplane 1 will recognize that its own location identification signal is at low level, and the other hard disk backplanes will recognize that its own location identification signal is at high level.
服务器硬盘板卡分配I2C地址的方法,每个硬盘背板的CPLD通过位置识别信号判断自己的位置是否是硬盘背板1。如果不是硬盘背板1,暂不做动作。如果该硬盘背板是硬盘背板1,则将其I2C地址设置为第1个备选值,并通过信号2向硬盘背板2发送第2指令;硬盘背板2收到上一硬盘背板发送的第2指令,则将其I2C地址设置为第2个备选值,并通过信号2向硬盘背板3发送第3指令;以此类推,硬盘背板N收到上一硬盘背板发送的第N指令,则将其I2C地址设置为第N个备选值。至此完成各个硬盘背板CPLD 的I2C地址的设置。保证了I2C链路上地址各不相同。The method of assigning the I2C address to the hard disk board of the server. The CPLD of each hard disk backplane judges whether its position is the hard disk backplane 1 through the position identification signal. If it is not hard disk backplane 1, do not take action for now. If the hard disk backplane is hard disk backplane 1, set its I2C address as the first alternative value, and send the second command to hard disk backplane 2 through signal 2; hard disk backplane 2 receives the previous hard disk backplane For the second instruction sent, set its I2C address as the second alternative value, and send the third instruction to the hard disk backplane 3 through signal 2; and so on, the hard disk backplane N receives the previous hard disk backplane The Nth instruction of , then set its I2C address to the Nth alternative value. So far, the setting of the I2C address of each hard disk backplane CPLD is completed. It is guaranteed that the addresses on the I2C link are different.
本发明的有益效果:本发明针对现有的服务器硬盘背板I2C地址分配方式需要人为手工操作,流程复杂且容易出错的缺点,进行改进。实现了硬盘背板CPLD自行判断、设置I2C地址的功能,无需人为的操作,避免了因为人为操作失误造成板卡功能异常的隐患。Beneficial effects of the present invention: the present invention aims at improving the existing I2C address allocation method of the hard disk backplane of the server, which requires manual operation, complicated process and error-prone. Realize the function of CPLD on the hard disk backplane to judge and set the I2C address by itself, without human operation, avoiding the hidden danger of abnormal function of the board due to human operation errors.
附图说明Description of drawings
图1是现有技术的方案连接示意图。FIG. 1 is a schematic diagram of connection schemes in the prior art.
图2是本实施例的连接示意图。Fig. 2 is a schematic connection diagram of this embodiment.
具体实施方式detailed description
下面结合附图与实施例对本发明作进一步说明。The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
如图2所示,服务器,包含计算节点及硬盘背板1-硬盘背板4。计算节点包含一I2C主设备;各硬盘背板分别包含一CPLD、一位置识别信号及电源;CPLD各有一输入信号信号1及一输出信号信号2。As shown in FIG. 2 , the server includes a computing node and a hard disk backplane 1-hard disk backplane 4 . The calculation node includes an I2C master device; each hard disk backplane includes a CPLD, a position identification signal and a power supply; each CPLD has an input signal 1 and an output signal 2 .
硬盘背板和计算节点的各个信号连接通过线缆完成,硬盘背板1-硬盘背板4是完全相同的4个板卡,只是在机器中的位置不同。The signal connections between the hard disk backplane and the computing nodes are completed through cables. The hard disk backplane 1-hard disk backplane 4 are the same four boards, but their positions in the machine are different.
每个硬盘背板中有一个CPLD,将CPLD的信号1和信号2连接到背板上,其中信号1为CPLD的输入信号,信号2为CPLD的输出信号。在计算节点上将硬盘背板1的信号1端悬空,并将硬盘背板1的信号2端接到硬盘背板2的信号1端,来支持硬盘背板1的CPLD向硬盘背板2的CPLD传输数据。同理硬盘背板2的信号2端接到硬盘背板3的信号1端,以此类推。硬盘背板4的信号2端悬空。There is a CPLD in each hard disk backplane, and signal 1 and signal 2 of the CPLD are connected to the backplane, where signal 1 is the input signal of the CPLD, and signal 2 is the output signal of the CPLD. On the computing node, the signal 1 end of the hard disk backplane 1 is suspended, and the signal 2 end of the hard disk backplane 1 is connected to the signal 1 end of the hard disk backplane 2 to support the CPLD of the hard disk backplane 1 to the hard disk backplane 2. CPLD transmits data. Similarly, the signal 2 terminal of the hard disk backplane 2 is connected to the signal 1 terminal of the hard disk backplane 3, and so on. The signal terminal 2 of the hard disk backplane 4 is suspended.
每个硬盘背板都将一个位置识别信号接到CPLD上,并通过电阻连接到电源上,这个位置识别信号也连到计算节点上。在计算节点上,将硬盘背板1的位置识别信号接地,其他硬盘背板的位置识别信号悬空。因此,硬盘背板1会识别到自己的位置识别信号是低电平,其他硬盘背板会识别到自己的位置识别信号为高电平。Each hard disk backplane connects a position identification signal to the CPLD, and connects to the power supply through a resistor, and the position identification signal is also connected to the computing node. On the computing node, ground the position identification signal of hard disk backplane 1, and suspend the position identification signals of other hard disk backplanes. Therefore, the hard disk backplane 1 will recognize that its own position identification signal is at a low level, and the other hard disk backplanes will recognize that its own position identification signal is at a high level.
下面描述系统的工作过程:The working process of the system is described below:
每个硬盘背板的CPLD通过位置识别信号判断自己的位置是否是硬盘背板1。如果不是硬盘背板1,暂不做动作。如果该硬盘背板是硬盘背板1,则将自己的I2C地址设置为第1个备选值(例如1011000),并通过信号2向硬盘背板2发送数据“2”;The CPLD of each hard disk backplane judges whether its own position is the hard disk backplane 1 through the position identification signal. If it is not hard disk backplane 1, do not take action for now. If the hard disk backplane is hard disk backplane 1, set its own I2C address to the first alternative value (for example, 1011000), and send data "2" to hard disk backplane 2 through signal 2;
硬盘背板2判断自己位置不是硬盘背板1后未做动作。硬盘背板2收到上一硬盘背板发送的数据“2”,则将自己的I2C地址设置为第2个备选值(例如1011001),并通过信号2向硬盘背板3发送数据“3”;Hard disk backplane 2 judged that its position was not that of hard disk backplane 1 and did not take any action. Hard disk backplane 2 receives the data "2" sent by the previous hard disk backplane, then sets its own I2C address to the second alternative value (for example, 1011001), and sends data "3" to hard disk backplane 3 through signal 2 ";
硬盘背板3判断自己位置不是硬盘背板1后未做动作。硬盘背板3收到上一硬盘背板发送的数据“3”,将自己的I2C地址设置为第3个备选值(例如1011010),并通过信号2向硬盘背板4发送数据“4”;Hard disk backplane 3 judges that its position is not that of hard disk backplane 1 and does not take any action. Hard disk backplane 3 receives the data "3" sent by the previous hard disk backplane, sets its own I2C address to the third alternative value (for example, 1011010), and sends data "4" to hard disk backplane 4 through signal 2 ;
硬盘背板4判断自己位置不是硬盘背板1后未做动作。硬盘背板4收到上一硬盘背板发送的数据“4”,将自己的I2C地址设置为第4个备选值(例如1011011)。The hard disk backplane 4 judges that its position is not the hard disk backplane 1 and does not take any action. Hard disk backplane 4 receives the data "4" sent by the previous hard disk backplane, and sets its own I2C address to the fourth alternative value (for example, 1011011).
至此完成各个硬盘背板CPLD 的I2C地址的设置。保证了I2C链路上地址各不相同。So far, the setting of the I2C address of each hard disk backplane CPLD is completed. It is guaranteed that the addresses on the I2C link are different.
上述虽然结合附图对本发明的具体实施方式进行了描述,但并非对本发明保护范围的限制,所属领域技术人员应该明白,在本发明的技术方案的基础上,本领域技术人员不需要付出创造性劳动即可做出的各种修改或变形仍在本发明的保护范围以内。Although the specific implementation of the present invention has been described above in conjunction with the accompanying drawings, it does not limit the protection scope of the present invention. Those skilled in the art should understand that on the basis of the technical solution of the present invention, those skilled in the art do not need to pay creative work Various modifications or variations that can be made are still within the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710381983.1ACN107256198A (en) | 2017-05-26 | 2017-05-26 | Server and the method for server hard disc board distribution I2C addresses |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710381983.1ACN107256198A (en) | 2017-05-26 | 2017-05-26 | Server and the method for server hard disc board distribution I2C addresses |
| Publication Number | Publication Date |
|---|---|
| CN107256198Atrue CN107256198A (en) | 2017-10-17 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710381983.1APendingCN107256198A (en) | 2017-05-26 | 2017-05-26 | Server and the method for server hard disc board distribution I2C addresses |
| Country | Link |
|---|---|
| CN (1) | CN107256198A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108897577A (en)* | 2018-06-20 | 2018-11-27 | 郑州云海信息技术有限公司 | A kind of server backplane CPLD state self-adaption system and method |
| CN109240869A (en)* | 2018-09-21 | 2019-01-18 | 郑州云海信息技术有限公司 | A kind of method and apparatus of determining target hard disk backboard |
| CN111176939A (en)* | 2019-12-20 | 2020-05-19 | 苏州浪潮智能科技有限公司 | Multi-node server management system and method based on CPLD |
| CN112182664A (en)* | 2020-08-28 | 2021-01-05 | 苏州浪潮智能科技有限公司 | Method, device and system for displaying hard disk label and storage medium |
| CN112596983A (en)* | 2020-12-30 | 2021-04-02 | 苏州浪潮智能科技有限公司 | A monitoring method for a connector in a server |
| CN112988635A (en)* | 2021-03-10 | 2021-06-18 | 英业达科技有限公司 | Communication system of mainboard and backplate and server that is suitable for thereof |
| CN113031702A (en)* | 2021-03-24 | 2021-06-25 | 联想(北京)有限公司 | Backplate structure and electronic equipment |
| CN113641613A (en)* | 2021-08-17 | 2021-11-12 | 西安易朴通讯技术有限公司 | Backboard, hard disk pool, server and communication method |
| CN114880269A (en)* | 2022-05-26 | 2022-08-09 | 无锡华普微电子有限公司 | Board card ID configuration and identification method, microcontroller and control system |
| CN115061976A (en)* | 2022-05-20 | 2022-09-16 | 北京百度网讯科技有限公司 | Address configuration method, device, carrier board, core board, server and medium |
| CN116541335A (en)* | 2023-07-05 | 2023-08-04 | 安擎计算机信息股份有限公司 | Method for distributing serial addresses and electronic equipment |
| TWI839210B (en)* | 2023-05-09 | 2024-04-11 | 神雲科技股份有限公司 | Address allocation circuit |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020188781A1 (en)* | 2001-06-06 | 2002-12-12 | Daniel Schoch | Apparatus and methods for initializing integrated circuit addresses |
| CN102012885A (en)* | 2010-09-15 | 2011-04-13 | 开源集成电路(苏州)有限公司 | System and method for realizing communication by adopting dynamic I2C bus |
| CN103500154A (en)* | 2013-09-11 | 2014-01-08 | 深圳市摩西尔电子有限公司 | Serial bus interface chip, serial bus transmission system and method |
| CN103703702A (en)* | 2011-03-25 | 2014-04-02 | 应美盛股份有限公司 | System, apparatus, and method for time-division multiplexed communication |
| CN105528279A (en)* | 2015-11-30 | 2016-04-27 | 英业达科技有限公司 | Backplane, and hard disk drive status display method |
| CN106502948A (en)* | 2016-10-25 | 2017-03-15 | 郑州云海信息技术有限公司 | A kind of optionally onboard FPGA design method in I2C addresses |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020188781A1 (en)* | 2001-06-06 | 2002-12-12 | Daniel Schoch | Apparatus and methods for initializing integrated circuit addresses |
| CN102012885A (en)* | 2010-09-15 | 2011-04-13 | 开源集成电路(苏州)有限公司 | System and method for realizing communication by adopting dynamic I2C bus |
| CN103703702A (en)* | 2011-03-25 | 2014-04-02 | 应美盛股份有限公司 | System, apparatus, and method for time-division multiplexed communication |
| CN103500154A (en)* | 2013-09-11 | 2014-01-08 | 深圳市摩西尔电子有限公司 | Serial bus interface chip, serial bus transmission system and method |
| CN105528279A (en)* | 2015-11-30 | 2016-04-27 | 英业达科技有限公司 | Backplane, and hard disk drive status display method |
| CN106502948A (en)* | 2016-10-25 | 2017-03-15 | 郑州云海信息技术有限公司 | A kind of optionally onboard FPGA design method in I2C addresses |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108897577A (en)* | 2018-06-20 | 2018-11-27 | 郑州云海信息技术有限公司 | A kind of server backplane CPLD state self-adaption system and method |
| CN109240869A (en)* | 2018-09-21 | 2019-01-18 | 郑州云海信息技术有限公司 | A kind of method and apparatus of determining target hard disk backboard |
| CN111176939A (en)* | 2019-12-20 | 2020-05-19 | 苏州浪潮智能科技有限公司 | Multi-node server management system and method based on CPLD |
| CN112182664B (en)* | 2020-08-28 | 2022-08-05 | 苏州浪潮智能科技有限公司 | Method, device and system for displaying hard disk label and storage medium |
| CN112182664A (en)* | 2020-08-28 | 2021-01-05 | 苏州浪潮智能科技有限公司 | Method, device and system for displaying hard disk label and storage medium |
| CN112596983A (en)* | 2020-12-30 | 2021-04-02 | 苏州浪潮智能科技有限公司 | A monitoring method for a connector in a server |
| CN112988635A (en)* | 2021-03-10 | 2021-06-18 | 英业达科技有限公司 | Communication system of mainboard and backplate and server that is suitable for thereof |
| CN113031702A (en)* | 2021-03-24 | 2021-06-25 | 联想(北京)有限公司 | Backplate structure and electronic equipment |
| CN113641613A (en)* | 2021-08-17 | 2021-11-12 | 西安易朴通讯技术有限公司 | Backboard, hard disk pool, server and communication method |
| CN115061976A (en)* | 2022-05-20 | 2022-09-16 | 北京百度网讯科技有限公司 | Address configuration method, device, carrier board, core board, server and medium |
| CN114880269A (en)* | 2022-05-26 | 2022-08-09 | 无锡华普微电子有限公司 | Board card ID configuration and identification method, microcontroller and control system |
| CN114880269B (en)* | 2022-05-26 | 2024-02-02 | 无锡华普微电子有限公司 | Board ID configuration and identification method, microcontroller and control system |
| TWI839210B (en)* | 2023-05-09 | 2024-04-11 | 神雲科技股份有限公司 | Address allocation circuit |
| CN116541335A (en)* | 2023-07-05 | 2023-08-04 | 安擎计算机信息股份有限公司 | Method for distributing serial addresses and electronic equipment |
| CN116541335B (en)* | 2023-07-05 | 2023-09-19 | 安擎计算机信息股份有限公司 | Method for distributing serial addresses and electronic equipment |
| Publication | Publication Date | Title |
|---|---|---|
| CN107256198A (en) | Server and the method for server hard disc board distribution I2C addresses | |
| US8898358B2 (en) | Multi-protocol communication on an I2C bus | |
| CN112328440B (en) | Hard disk physical position determining method and device | |
| US10268483B2 (en) | Data protocol for managing peripheral devices | |
| CN115865866B (en) | Address allocation method and device | |
| CN107357753B (en) | Method and system for realizing automatic matching of PCIE port and hard disk address | |
| CN104615572B (en) | Hot plug processing system and method | |
| CN207115097U (en) | A kind of FPGA isomeries accelerator card | |
| CN104516838B (en) | Manage determining method of path and device | |
| CN106598903A (en) | Method and device for adjusting Redriver chip parameters | |
| WO2021098485A1 (en) | Method and system for power-on and power-off control of pcie device | |
| CN107818062A (en) | A kind of hard disk backboard and its design method of compatible SAS, SATA and NVME hard disk | |
| CN111294413B (en) | Method, device and readable medium for determining Internet Protocol (IP) address | |
| CN118069562A (en) | Method, device, equipment and storage medium for managing hard disk backboard of double-node server | |
| CN114003528A (en) | OCP switching card, switching system and switching method | |
| TW201944242A (en) | Method of hot-plugging identification and server having function of hot-plugging identification | |
| CN116185505A (en) | Configuration method of hard disk backboard and computing equipment | |
| CN118643000B (en) | Method for generating configuration information table of PCIe port of server, method and device for sending configuration information table | |
| CN115904024A (en) | A multi-mode hard disk backplane structure, method and server | |
| CN115145733A (en) | A resource allocation method, device, server and system | |
| CN115129643A (en) | Method, device, equipment and storage medium for improving transmission bandwidth between BMC and CMC | |
| CN103840991A (en) | I2C bus architecture and address management method | |
| CN204945920U (en) | The IO expansion board of a kind of compatibility dissimilar computing node PCIE hot plug | |
| CN118093031A (en) | A wiring inspection method, device, equipment and machine-readable storage medium | |
| CN111723037A (en) | A PCIE interface expansion system and server |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication | Application publication date:20171017 |