技术领域technical field
本发明属于信号处理技术，具体涉及宽带数字阵雷达中多路接收通道的抽取和时延同步调整技术。The invention belongs to the signal processing technology, and in particular relates to the extraction and time delay synchronous adjustment technology of multiple receiving channels in a wideband digital array radar.
背景技术Background technique
为了获得更高的距离分辨率，提高对目标的辨识能力，宽带数字阵雷达WBDAR应运而生。它采用了宽带信号来获取目标信息，在获取更高的距离分辨率的同时，提升了对目标识别和区分的能力。但也使WBDAR需要利用实延时线TTD来进行区域范围内大角度电子扫描来取代移相器。与传统的TTD模拟方法相比较，采用数字延时滤波器的方法在降低额外的插入损耗的同时，提供了连续可变的精确时延用来保证宽带波束朝向任意方向的目标，极大的弥补了模拟时延补偿的诸多缺点。In order to obtain a higher range resolution and improve the ability to identify targets, wideband digital array radar WBDAR came into being. It uses broadband signals to obtain target information, while obtaining higher distance resolution, it improves the ability to identify and distinguish targets. But it also makes WBDAR need to use the real time delay line TTD to carry out large-angle electronic scanning in the area to replace the phase shifter. Compared with the traditional TTD analog method, the method using a digital delay filter reduces the additional insertion loss while providing a continuously variable and accurate time delay to ensure that the broadband beam is directed to the target in any direction, which greatly compensates Many shortcomings of analog delay compensation are eliminated.
近年来，随着模拟和数字芯片的高速发展，使得WADAR的实现变得可行。但高速的信号速处理速度和大量的硬件资源消耗增加了系统的复杂度和成本，从而限制了WBDAR的实现。因此如何优化系统结构和减少处理过程的复杂度仍然是研究的重点。In recent years, with the rapid development of analog and digital chips, the realization of WADAR has become feasible. However, the high-speed signal processing speed and the consumption of a large number of hardware resources increase the complexity and cost of the system, thus limiting the realization of WBDAR. Therefore, how to optimize the system structure and reduce the complexity of the processing process is still the focus of research.
在传统的WBDAR的接收通道中，主要结构通常包含微波放大器LNA、高速模数转换ADC模块、正交本振混频单元NCO、信号抽取模块(Decimation)，幅度和相位加权模块(Magnitude&Phase Weighting)、整数延时模块(Unit Delay)可变分数延时VFD滤波器，如图1所示。M倍信号抽取模块由抗混叠滤波器和抽取模块构成。信号抽取和VFD滤波器的设计成为提高系统的高效性和可重构性的关键因素。传统的通道接收结构中，天线接收信号经过微波放大器LNA输出射频信号再经ADC采样，以增加动态范围，减少接收机相位噪声，采样后的信号再经过正交本振的混频后，由抽取模块进行信号抽取，从而降低信号数据率，中间的幅度加权和相位加权是为了抑制接收波束旁瓣和补偿由多路通道射频信号到达时间差所引起的相位差。最后经过一个整数延时和分数延时VFD模块，最后输出相应的信号。VFD滤波器采用Farrow结构，如图2所示，由L+1个FIR子滤波器Gk(z)、L个延时单元、以及L个加法器级联而成，dk是分数延时因子，k＝0,1,2…,L。需要注意的是，这里的抽取和VFD滤波器模块是分开的，这样的结构一定程度上增加了系统的复杂度，降低了系统的工作效率，同时系统的可重构性差。In the traditional WBDAR receiving channel, the main structure usually includes microwave amplifier LNA, high-speed analog-to-digital conversion ADC module, quadrature local oscillator mixing unit NCO, signal extraction module (Decimation), amplitude and phase weighting module (Magnitude&Phase Weighting), Integer delay module (Unit Delay) variable fractional delay VFD filter, as shown in Figure 1. The M times signal extraction module is composed of an anti-aliasing filter and an extraction module. Signal extraction and VFD filter design become the key factors to improve the system's high efficiency and reconfigurability. In the traditional channel receiving structure, the antenna receiving signal is output by the microwave amplifier LNA and then sampled by the ADC to increase the dynamic range and reduce the phase noise of the receiver. After the sampled signal is mixed by the quadrature local oscillator, it is extracted The module performs signal extraction to reduce the signal data rate. The amplitude weighting and phase weighting in the middle are to suppress the receiving beam sidelobe and compensate the phase difference caused by the arrival time difference of multi-channel radio frequency signals. Finally, after an integer delay and fractional delay VFD module, the corresponding signal is finally output. The VFD filter adopts the Farrow structure, as shown in Figure 2, it is composed of L+1 FIR sub-filters Gk (z), L delay units, and L adders cascaded, and dk is the fractional delay Factor, k=0,1,2...,L. It should be noted that the decimation and VFD filter modules here are separated. Such a structure increases the complexity of the system to a certain extent, reduces the working efficiency of the system, and the reconfigurability of the system is poor.
一个数字信号处理系统中，乘法器和加法器数量成为了整个硬件的主要资源消耗，考虑到系统可能工作在不同的频率，我们使用乘法速率和加法速率比率来评估系统的复杂度，其中乘法速率Rm表示如下：In a digital signal processing system, the number of multipliers and adders becomes the main resource consumption of the entire hardware. Considering that the system may work at different frequencies, we use the ratio of multiplication rate and addition rate to evaluate the complexity of the system, where the multiplication rate Rm is expressed as follows:
其中，M是抽取因子，Cm是乘法器数量。同理，加法速率Ra表示如下：Among them, M is the decimation factor, and Cm is the number of multipliers. Similarly, the addition rate Ra is expressed as follows:
其中Ca是加法器数量。where Ca is the number of adders.
在传统WBDAR通道接收结构中，在一级抽取的情况下，其乘法器数量Cmo和加法器数量Cao如下：In the traditional WBDAR channel receiving structure, in the case of one-level decimation, the number of multipliers Cmo and the number of adders Cao are as follows:
Cmo＝N[N1+2+3+(L+1)(Ns+1)+2L], (3)Cmo ＝N[N1 +2+3+(L+1)(Ns +1)+2L], (3)
Cao＝N[2N1+5+2Ns(L+1)+2L]+2N-2, (4)Cao ＝N[2N1 +5+2Ns (L+1)+2L]+2N-2, (4)
其中，N1是抽取前抗混叠滤波器的阶数，Ns是VFD滤波器中子滤波器阶数，L是VFD滤波器中Farrow结构并行分支的数量，N是整个接收通道个数，这里只考虑偶数抗混叠滤波器和奇数阶子滤波器，其他阶数与此类似。Among them, N1 is the order of the anti-aliasing filter before decimation, Ns is the order of the sub-filter in the VFD filter, L is the number of parallel branches of the Farrow structure in the VFD filter, N is the number of the entire receiving channel, Only the even anti-aliasing filter and the odd-order sub-filter are considered here, and the other orders are similar.
考虑2级抽取的情况下，Rmo和Rao表示如下：Considering the case of 2-level extraction, Rmo andRao are expressed as follows:
其中，Ni，i＝1,2分别代表1级抽取前以及2级抽取前抗混叠滤波器的阶数，Mi，i＝1,2分别代表1级抽取与2级抽取中的抽取因子，整个接收通道的抽取因子M＝M1M2。Among them, Ni , i=1, 2 represent the orders of the anti-aliasing filter before the 1-stage decimation and before the 2-stage decimation, and Mi , i=1, 2 represent the decimation in the 1-stage decimation and the 2-stage decimation respectively Factor, the decimation factor of the entire receiving channel M=M1 M2 .
通过以上分析可以看出，传统的接收通道结构中，复杂度和高效性均没有达到理想状态，还有进一步优化的空间，同时它的可重构性和灵活性不足，这也是需要进一步改进的地方。From the above analysis, it can be seen that the complexity and efficiency of the traditional receiving channel structure have not reached the ideal state, and there is still room for further optimization. At the same time, its reconfigurability and flexibility are insufficient, which also needs further improvement. place.
发明内容Contents of the invention
本发明所要解决的技术问题是，在宽带数字阵雷达中提供一种高效的，灵活的，具有可重构性的接收通道结构。The technical problem to be solved by the present invention is to provide an efficient, flexible and reconfigurable receiving channel structure in wideband digital array radar.
本发明为解决上述技术问题所采用的技术方案是，宽带数字阵雷达中基于时延波束形成的高效接收通道，包括N路接收通道、2个一级加法器、2组FIR子滤波器组，N路接收通道中的N路I信号输出与1个一级加法器的输入端相连，N路接收通道中的N路Q信号与另一个1个一级加法器输入端相连，一级加法器的输出端分别与对应的1组FIR子滤波器组的输入端相连；I信号与Q信号表示互为正交的信号；每一路接收通道包括模数转换器、整数延时模块、正交本振混频单元、多相分解模块、分数时延模块、2个二级加法器、加权模块；模数转换器的输出端与整数延时模块的输入端相连，整数延时模块的输出端与正交本振混频单元的输入端相连，正交本振混频单元的I信号与Q信号经多相分解模块与分数时延模块的I信号与Q信号的输入端相连，分数时延模块的I信号输出端与1个二级加法器相连，分数时延模块的Q信号输出端与另1个二级加法器相连，2个二级加法器的输出端与加权模块输入端相连，加权模块中I信号输出为该路接收通道的I信号输出，加权模块中Q信号输出为该路接收通道的Q信号输出。The technical solution adopted by the present invention for solving the above-mentioned technical problems is that the high-efficiency receiving channel based on time-delay beamforming in the broadband digital array radar includes N receiving channels, 2 primary adders, 2 groups of FIR sub-filter banks, The N-way I signal output in the N-way receiving channel is connected to the input terminal of a first-level adder, and the N-way Q signal in the N-way receiving channel is connected to another input terminal of a first-level adder, and the first-level adder The output terminals of the corresponding FIR sub-filter banks are respectively connected to the input terminals of a group of FIR sub-filter banks; the I signal and the Q signal represent mutually orthogonal signals; each receiving channel includes an analog-to-digital converter, an integer delay module, an orthogonal vibration mixing unit, polyphase decomposition module, fractional delay module, two secondary adders, weighting module; the output of the analog-to-digital converter is connected to the input of the integer delay module, and the output of the integer delay module is connected to the The input terminal of the quadrature local oscillator mixing unit is connected, the I signal and the Q signal of the quadrature local oscillator mixing unit are connected to the input terminal of the I signal and the Q signal of the fractional time delay module through the polyphase decomposition module, and the fractional time delay module The I signal output terminal of the fractional delay module is connected to a secondary adder, the Q signal output terminal of the fractional delay module is connected to another secondary adder, the output terminals of the two secondary adders are connected to the input terminal of the weighting module, and the weighting The I signal output in the module is the I signal output of the receiving channel, and the Q signal output in the weighting module is the Q signal output of the receiving channel.
相对于传统接收通道结构中每个接收通道一组子滤波器组，本发明基于Farrow结构的通道滤波器的设计，使每个接收通道使用同样的L+1个子滤波器组，使整个结构的复杂度大幅度降低；由于多通道公用一组子滤波器，只需要修改分数时延模块中的分数延时因子就可以重构整个接收通道的频率响应特性，系统的灵活性更好。Compared with one group of sub-filter banks for each receiving channel in the traditional receiving channel structure, the present invention is based on the design of the channel filter of the Farrow structure, so that each receiving channel uses the same L+1 sub-filter banks, so that the whole structure The complexity is greatly reduced; since multiple channels share a set of sub-filters, the frequency response characteristics of the entire receiving channel can be reconstructed only by modifying the fractional delay factor in the fractional delay module, and the system has better flexibility.
本发明的有益效果是，结构复杂度更低，灵活性和可重构性更强。The beneficial effect of the invention is that the structure complexity is lower, and the flexibility and reconfigurability are stronger.
附图说明Description of drawings
图1为传统的WBDAR接收通道结构示意图；Figure 1 is a schematic diagram of a traditional WBDAR receiving channel structure;
图2为Farrow基本结构；Figure 2 shows the basic structure of Farrow;
图3为本发明设计过程中通道滤波器的结构示意图；Fig. 3 is the structural representation of channel filter in the design process of the present invention;
图4为本发明接收通道结构示意图。Fig. 4 is a schematic diagram of the receiving channel structure of the present invention.
具体实施方式detailed description
本发明中的关键部分包含了基于Farrow结构的分数时延抽取器，以及与之功能实现相匹配的通道滤波器的设计。The key part of the present invention includes the fractional time-delay decimator based on the Farrow structure, and the design of the channel filter matched with its function realization.
实施例的总体结构如图4所示，包括N路接收通道、2个一级加法器、2组FIR子滤波器，N路接收通道中的N路I信号输出与1个一级加法器的输入端相连，N路接收通道中的N路Q信号与另一个1个一级加法器输入端相连，一级加法器的输出端分别与对应的1组FIR子滤波器的输入端相连；I信号与Q信号表示互为正交的信号；The overall structure of the embodiment is shown in Figure 4, including N-way receiving channels, 2 first-level adders, 2 groups of FIR sub-filters, N-way I signal outputs in N-way receiving channels and 1 first-level adder The input terminals are connected, and the N road Q signals in the N road receiving channels are connected with another one-level adder input terminal, and the output terminals of the one-level adder are connected with the input terminals of corresponding 1 group of FIR sub-filters respectively; I The signal and the Q signal represent mutually orthogonal signals;
每一路接收通道包括模数转换器、整数延时模块、正交本振混频单元、多相分解模块、分数时延模块、2个二级加法器、加权模块；模数转换器的输出端与整数延时模块的输入端相连，整数延时模块的输出端与正交本振混频单元的输入端相连，正交本振混频单元的I信号与Q信号经多相分解模块与分数时延模块的I信号与Q信号的输入端相连，分数时延模块的I信号输出端与1个二级加法器相连，分数时延模块的Q信号输出端与另1个二级加法器相连，2个二级加法器的输出端与加权模块输入端相连，加权模块中I信号输出为该路接收通道的I信号输出，加权模块中Q信号输出为该路接收通道的Q信号输出；Each receiving channel includes an analog-to-digital converter, an integer delay module, a quadrature local oscillator mixing unit, a polyphase decomposition module, a fractional delay module, two secondary adders, and a weighting module; the output of the analog-to-digital converter It is connected to the input terminal of the integer delay module, and the output terminal of the integer delay module is connected to the input terminal of the quadrature local oscillator frequency mixing unit. The I signal and Q signal of the quadrature local oscillator frequency mixing unit are divided into fractional The I signal of the delay module is connected to the input terminal of the Q signal, the I signal output terminal of the fractional delay module is connected to a secondary adder, and the Q signal output terminal of the fractional delay module is connected to another secondary adder , the output ends of 2 secondary adders are connected with the input end of the weighting module, the I signal output in the weighting module is the I signal output of the receiving channel of the road, and the Q signal output of the weighting module is the Q signal output of the receiving channel of the road;
通道滤波器由分数时延模块、二级加法器和FIR子滤波器组组成，如图3所示；The channel filter consists of a fractional time delay module, a secondary adder and a FIR sub-filter bank, as shown in Figure 3;
M路多相分解模块用于完成一个M路多相分解，其主要作用是降低每一路信号的速率，使其降为原来的1/M；通道滤波器包含了M个分数时延加权模块，同时每一相分解因子又包含了L+1个并行乘法因子，用表示，其中m＝0,1,2…,M-1表示多相分解的M个因子，k＝0,1,2…,L表示每个分解路中并行的L+1路乘法因子。二级加法器用于把这多相分解的M路中各自的L+1路并行分支信号相加求和。The M-channel polyphase decomposition module is used to complete an M-channel polyphase decomposition, and its main function is to reduce the rate of each signal to the original 1/M; the channel filter includes M fractional delay weighting modules, At the same time, each phase decomposition factor contains L+1 parallel multiplication factors, using where m=0, 1, 2..., M-1 represents M factors of polyphase decomposition, k=0, 1, 2..., L represents parallel L+1 multiplication factors in each decomposition path. The second-stage adder is used to add and sum the respective L+1 parallel branch signals in the multi-phase decomposed M paths.
FIR子滤波器组传递函数用Gk(z)表示,k＝0,1,2…,L,其中每一个Gk(z)为一个子FIR滤波器的传递函数。通道滤波器要需要与分数时延抽取器结构相匹配，则需要设置合理的通道滤波器的分数延时因子与冲激响应。The transfer function of the FIR sub-filter bank is represented by Gk (z), k=0, 1, 2..., L, where each Gk (z) is a transfer function of a sub-FIR filter. If the channel filter needs to match the structure of the fractional delay decimator, it is necessary to set a reasonable fractional delay factor and impulse response of the channel filter.
理想情况下，通道滤波器的频率响应如下表示：Ideally, the frequency response of the channel filter is expressed as follows:
其中，Nc为整个通道滤波器的阶数，w为角频率，T为时间变量，ws为截止角频率，wsT＝π/M，M为抽取因子，d为整个通道的分数延时系数。整个通道的多相分解结构的转移公式为：Among them, Nc is the order of the entire channel filter, w is the angular frequency, T is the time variable, ws is the cut-off angular frequency, ws T = π/M, M is the decimation factor, and d is the fractional delay of the entire channel time factor. The transfer formula for the multiphase decomposition structure of the entire channel is:
其中，m为多相分解的分支变量，m＝0,1...,M-1，z为z变量，Hm(zM)是每一个分支的转移公式。这里可以通过利用一个如图2所示的Farrow结构实现多相分解，转移公式为：Wherein, m is a branch variable of multiphase decomposition, m=0,1...,M-1, z is a z variable, and Hm (zM ) is a transfer formula of each branch. Here, multiphase decomposition can be realized by using a Farrow structure as shown in Figure 2, and the transfer formula is:
其中，dk为第k条并行分支的分数延时因子，Gk(z)是子滤波器组在z变换域的传递函数；Wherein, dk is the fractional delay factor of the kth parallel branch, and Gk (z) is the transfer function of the sub-filter bank in the z transform domain;
因此，整个通道的多相分解结构转移公式(7)可以改写为：Therefore, the multiphase decomposition structure transfer formula (7) of the whole channel can be rewritten as:
其中，为多相分解第每m路第k条并行分支对应的分数延时因子，m＝0,1...,M-1，,k＝0,1,2…,L。in, is the fractional delay factor corresponding to the kth parallel branch of every m-th path in polyphase decomposition, m=0,1...,M-1, k=0,1,2...,L.
一个阶数为Ns的FIR子滤波器与多相分解分支数M以及整个通道滤波器阶数N的关系可以用以下式子表示：The relationship between a FIR sub-filter with an order of Ns and the number of polyphase decomposition branches M and the order N of the entire channel filter can be expressed by the following formula:
N＝(Ns+1)M-1 (11)N=(Ns +1)M-1 (11)
再结合公式(7)，(8)和(11)，可以得出：Combining formulas (7), (8) and (11), we can get:
再把(11)带入(12)可以得出：Substitute (11) into (12) to get:
其中，dm为多相分解第m路的分数延时因子，d是整个通道的分数延时。此时可以得出整个通道滤波器多相分解后每一分支的冲激响应为：Among them, dm is the fractional delay factor of the m-th path of polyphase decomposition, and d is the fractional delay of the entire channel. At this point, the impulse response of each branch after polyphase decomposition of the entire channel filter can be obtained as:
其中，n＝0,1…,N1，m＝0,1…,M-1，N1为Farrow结构子滤波器的阶数，gk(n)是子滤波器时域冲激响应函数。Among them, n=0,1...,N1 , m=0,1...,M-1, N1 is the order of the Farrow structure sub-filter, gk (n) is the time-domain impulse response function of the sub-filter .
本发明结构的复杂度可以用系统的乘法器和加法器的数量来表示，结果如下：The complexity of structure of the present invention can represent with the multiplier of system and the quantity of adder, and result is as follows:
Cmn＝2NLM+3N(L+1)+(Ns+1)(L+1), (15)Cmn =2NLM+3N(L+1)+(Ns +1)(L+1), (15)
Can＝2N(L+1)(M-1)+5N(L+1)+2(N-1)(L+1)+2(L+1)Ns+2L (16)Can =2N(L+1)(M-1)+5N(L+1)+2(N-1)(L+1)+2(L+1)Ns +2L (16)
可以看出，本发明设计得到的基于时延波束形成的高效接收通道结构，使传统的宽带数字阵雷达中接收通道结构的实现复杂度大大降低。当N＝8，M＝2，Ns＝5，N1＝26，N2＝0，L＝3时，由(3)(4)公式可以推出传统的接收通道结构乘法运算率和加法运算率分别为Rmo＝244，Rao＝419，而本发明的接收通道结构中，满足同样配置下，当Ns＝13时，由公式(15)(16)可以求出Rmn＝124，Ran＝195，明显优于传统结构。乘法器和加法器的使用数量降低，单位时间内需要完成的乘法运算和加法运算次数大大减少，降低了系统实现的复杂度。It can be seen that the high-efficiency receiving channel structure based on delay beamforming designed by the present invention greatly reduces the complexity of realizing the receiving channel structure in the traditional broadband digital array radar. When N = 8, M = 2, Ns = 5, N1 = 26, N2 = 0, L = 3, from (3) (4) formula can deduce the multiplication operation rate and addition operation of the traditional receiving channel structure The rates are Rmo =244,Rao =419, and in the receiving channel structure of the present invention, under the same configuration, when Ns =13, formula (15)(16) can calculate Rmn =124, Ran =195, obviously better than the traditional structure. The number of multipliers and adders used is reduced, and the number of multiplication and addition operations that need to be completed per unit time is greatly reduced, reducing the complexity of system implementation.
通过设计多相分解模块以及与之相匹配的通道滤波器，使整个接收通道结构的灵活性和可重构性大幅度增加。传统的通道接收结构需要预先配置大量的滤波器参数和分解因子以及分数延时因子，限制了整个接收结构的灵活性和可重构性。本发明的结构通过设计合适的基于多相分解和Farrow结构的通道滤波器，代替了传统的抗混叠滤波器以及VFD结构，减少了参数设置，同时灵活性更高，只需要修改通道滤波器的分数时延加权参数就可以改变通道的频率响应。By designing the polyphase decomposition module and the matching channel filter, the flexibility and reconfigurability of the entire receiving channel structure are greatly increased. The traditional channel receiving structure needs to pre-configure a large number of filter parameters, decomposition factors and fractional delay factors, which limits the flexibility and reconfigurability of the entire receiving structure. The structure of the present invention replaces the traditional anti-aliasing filter and VFD structure by designing a suitable channel filter based on polyphase decomposition and Farrow structure, which reduces parameter settings and is more flexible, only needing to modify the channel filter The fractional delay weighting parameter can change the frequency response of the channel.
整个接收通道结构具体实现步骤如下：The specific implementation steps of the entire receiving channel structure are as follows:
步骤一、设置多相分解模块与通道滤波器代替传统的抗混叠滤波器以及VFD结构的功能。首先信号通过一个M路多相分解，然后进入设计的通道滤波器。通道滤波器的理想频率响应函数由公式(7)给出，按照公式(14)的冲激响应进行设计。通道滤波器的参数设置包含三部分，一是通道滤波器中分数时延因子的设置，参照公式(13)，可以求出相应的分数延时因子dm；二是子滤波器组Gk(z)的阶数设置Ns；三是子滤波器组Gk(z)的系数设置。分数时延模块与加权模块对M组L+1路信号进行分数时延加权，再求和合并后，生成L+1路信号。Step 1. Set the polyphase decomposition module and the channel filter to replace the functions of the traditional anti-aliasing filter and the VFD structure. First, the signal is decomposed through an M-way polyphase, and then enters the designed channel filter. The ideal frequency response function of the channel filter is given by formula (7), and it is designed according to the impulse response of formula (14). The parameter setting of the channel filter includes three parts. One is the setting of the fractional delay factor in the channel filter. Referring to formula (13), the corresponding fractional delay factor dm can be obtained; the second is the sub-filter bank Gk ( z) is the order setting Ns ; the third is the coefficient setting of the sub-filter bank Gk (z). The fractional delay module and the weighting module perform fractional delay weighting on M groups of L+1 signals, and then sum and combine to generate L+1 signals.
步骤二、先配置一路接收通道结构，低噪放模块LNA、数据采集模块ADC，整数时延模块(Unit Delay D0)依次串联，然后通过一个正交本振混频单元后，到达多相分解模块。Step 2. First configure one receiving channel structure, the low noise amplifier module LNA, the data acquisition module ADC, and the integer delay module (Unit Delay D0 ) are connected in series in sequence, and then pass through a quadrature local oscillator mixing unit to reach the multiphase decomposition module.
步骤三、经过多相分解模块、分数时延模块的信号再经过幅度和相位加权(weighting Wn)后生成L+1路信号，n＝0,1...,N-1。Step 3: After the signals of the polyphase decomposition module and the fractional delay module are weighted by amplitude and phase (weighting Wn ), L+1 signals are generated, n=0,1...,N-1.
步骤四、一路接收通道设置完成后，再设置剩余的N-1路接收通道结构，每一路接收通道结构按照步骤一到步骤三设置。最后把N路接收通道的N(L+1)路信号通过第一级加法器进行求和合并，生成L+1路信号，分为I、Q两路进入各自对应的L+1子滤波器组，实现了N路通道共用一个子滤波器组。Step 4: After the setting of one receiving channel is completed, the structure of the remaining N-1 receiving channels is set, and the structure of each receiving channel is set according to steps 1 to 3. Finally, the N(L+1) signals of the N receiving channels are summed and combined by the first-stage adder to generate L+1 signals, which are divided into I and Q and enter the respective corresponding L+1 sub-filters group, realizing that N channels share one sub-filter bank.
经过上述步骤处理，即可得到符合要求的两路正交输出信号yI，yq。After the above steps, the two quadrature output signals yI , yq meeting the requirements can be obtained.
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| CN201710222859.0ACN107144821B (en) | 2017-04-07 | 2017-04-07 | Efficient receiving channel based on time delay beam forming in broadband digital array radar |
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| CN201710222859.0ACN107144821B (en) | 2017-04-07 | 2017-04-07 | Efficient receiving channel based on time delay beam forming in broadband digital array radar |
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