CN106940428B - Chip verification method, device and system - Google Patents
Chip verification method, device and systemDownload PDFInfo
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- CN106940428B CN106940428BCN201610004019.2ACN201610004019ACN106940428BCN 106940428 BCN106940428 BCN 106940428BCN 201610004019 ACN201610004019 ACN 201610004019ACN 106940428 BCN106940428 BCN 106940428B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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Abstract
Description
Technical Field
The invention relates to the field of communication, in particular to a chip verification method, a chip verification device and a chip verification system.
Background
Logic verification is a key step in the front-end design process of the digital chip, the verification platform simulates the actual operation environment of the chip, and the correctness of the functions of the chip is checked through a test case. With the rapid growth in scale and complexity of digital integrated circuits, and the rapid release requirements of a large number of functionally similar chips, higher demands are placed on the verification platform and the testing method in terms of time and cost.
The traditional verification platform is signal level verification, and a chip to be tested is verified by directly programming test stimulus. The traditional verification platform lacks abstract division of work on platform functions, and has no unified compiling standard and application interface, so that the reusability of the verification platform is poor, and the testing efficiency is low.
At present, the verification Methodology adopted is one of the trends of chip verification, and a Universal Verification Methodology (UVM) is a typical representative thereof. The UVM system architecture diagram is shown in fig. 1. The most main multiplexing unit in the UVM architecture is a bus Agent (Agent), a verifier generates a transaction-level packet (transaction) by writing a Sequence (Sequence) in a sequencer (Sequence), converts the transaction-level packet into an interface excitation signal through a Driver, and applies the interface excitation signal to a bus interface, and a Monitor (Monitor) collects a bus signal, converts the transaction-level packet back, and sends the transaction-level packet to a score board (scoreboard) for automatic comparison.
UVM provides a set of basic verification framework, and realizes basic multiplexing and automatic verification. However, for the requirement of rapid verification of a large number of data forwarding type chips at present, the UVM architecture is also deficient, firstly, the definition of the Agent in the UVM is wider, the concept of hierarchy is lacked, and the development of the high-speed bus at present makes the bus structure itself more complex, and has multiple hierarchies, and meanwhile, the modeling of the bus flow also has multiple hierarchies. More and more interface types and complex flow models can generate numerous combinations, if the functions are realized in the Agent, a multi-level sequencer is needed to realize the functions in a matching way, the Agent becomes very complex, the multiplexing of a platform is not facilitated, and meanwhile, the working efficiency of simulation tool software is influenced. The same problem exists with register validation. Secondly, it is not enough to use only the UVM architecture for the verification platform and the writing and testing of the test case.
Aiming at the problem that the reusability of a platform is low due to lack of hierarchy of a verification framework of UVM, an effective solution is not provided at present.
Disclosure of Invention
The invention provides a chip verification method, a device and a system, which are used for at least solving the problem of low reusability of a platform caused by lack of hierarchy of a verification framework of UVM.
According to an aspect of the present invention, there is provided a chip verification method, including: generating a verification platform, wherein the verification platform comprises: the system comprises a model layer and an interface layer, wherein the model layer comprises a flow model and a register model, and the interface layer comprises a data bus interface agent and a CPU bus interface agent; and verifying the chip to be tested through the verification platform.
Optionally, generating the verification platform comprises: receiving a platform configuration file, wherein the platform configuration file carries model parameters of the model layer, interface parameters of the interface layer and platform structure parameters of the verification platform; selecting components corresponding to the platform structure parameters from a platform component library, and generating a basic framework of the verification platform; generating the flow model and the register model according to the model parameters; and generating the data bus interface agent and the CPU bus interface agent according to the interface parameters.
Optionally, verifying the chip to be tested includes: receiving a test configuration for verifying a chip to be tested, wherein the test configuration carries a platform configuration, an interface test configuration, a flow test configuration and a register test configuration; selecting test cases respectively corresponding to the interface test configuration, the flow test configuration and the register test configuration from a test suite; adjusting the test case according to the platform configuration; and running the adjusted test case to generate a verification report.
Optionally, verifying the chip to be tested includes: generating a transaction-level message of forwarding surface flow required by the chip to be tested through the flow model; generating a transaction-level message of a control surface register required by the chip to be tested through the register model; converting the transaction level message received from the flow model into a bus signal level excitation sent to the chip to be tested through the data bus interface agent, and converting the bus signal level excitation received from the chip to be tested into the transaction level message sent to a reference model or a score board; and converting the transaction level message received from the register model into a bus signal level excitation sent to the chip to be tested through the CPU bus interface agent, and converting the bus signal level excitation received from the chip to be tested into the transaction level message sent to a reference model or a score board.
According to another aspect of the present invention, there is also provided a chip verification apparatus, including: a generation module configured to generate a verification platform, wherein the verification platform comprises: the system comprises a model layer and an interface layer, wherein the model layer comprises a flow model and a register model, and the interface layer comprises a data bus interface agent and a CPU bus interface agent; and the verification module is used for verifying the chip to be tested through the verification platform.
Optionally, the generating module includes: a first receiving unit, configured to receive a platform configuration file, where the platform configuration file carries a model parameter of the model layer, an interface parameter of the interface layer, and a platform structure parameter of the verification platform; the first selection unit is used for selecting components corresponding to the platform structure parameters from a platform component library and generating a basic framework of the verification platform; the first generation unit is used for generating the flow model and the register model according to the model parameters; and the second generating unit is used for generating the data bus interface agent and the CPU bus interface agent according to the interface parameters.
Optionally, the verification module comprises: the second receiving unit is used for receiving test configuration used for verifying a chip to be tested, wherein the test configuration carries platform configuration, interface test configuration, flow test configuration and register test configuration; the second selection unit is used for selecting test cases respectively corresponding to the interface test configuration, the flow test configuration and the register test configuration from the test suite; the adjusting unit is used for adjusting the test case according to the platform configuration; and the verification unit is used for running the adjusted test case and generating a verification report.
Optionally, the verification module comprises: a third generating unit, configured to generate, through the traffic model, a transaction-level message of forwarding plane traffic required by the chip to be tested; a fourth generating unit, configured to generate, through the register model, a transaction-level packet of a control plane register required by the chip to be tested; the first interface unit is used for converting the transaction level message received from the flow model into a bus signal level excitation sent to the chip to be tested through the data bus interface agent, and converting the bus signal level excitation received from the chip to be tested into the transaction level message sent to the reference model or the score board; and the second interface unit is used for converting the transaction level message received from the register model into a bus signal level excitation sent to the chip to be tested through the CPU bus interface agent, and converting the bus signal level excitation received from the chip to be tested into the transaction level message sent to the reference model or the score board.
According to an aspect of the present invention, there is provided a chip verification system including: the chip verification device, the platform component library, the test suite library and the script library are arranged, wherein the platform component library is used for providing components for constructing a basic framework of a verification platform; the test suite library is used for providing test cases; and the script library is used for providing scripts required by the automatic operation of the chip verification device.
By the invention, a generation verification platform is adopted, wherein the verification platform comprises: the system comprises a model layer and an interface layer, wherein the model layer comprises a flow model and a register model, and the interface layer comprises a data bus interface agent and a CPU bus interface agent; through the verification platform, the mode of verifying the chip to be tested solves the problem that due to the fact that the verification framework of the UVM is lack of hierarchy, the reusability of the platform is low, the reusability of the verification framework is improved, and the verification efficiency is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of the architecture of a chip verification system according to the related art;
FIG. 2 is a flow chart of a chip verification method according to an embodiment of the invention;
FIG. 3 is a block diagram of a chip verification apparatus according to an embodiment of the present invention;
FIG. 4 is a block diagram of an alternative configuration of a chip verification apparatus according to an embodiment of the present invention;
FIG. 5 is a block diagram of an alternative configuration of a chip verification device according to an embodiment of the present invention;
FIG. 6 is a block diagram of an alternative configuration of a chip verification device according to an embodiment of the present invention;
FIG. 7 is a block diagram of a chip verification system according to an embodiment of the invention;
FIG. 8 is a block diagram of an architecture for a chip verification system according to an alternative embodiment of the present invention;
FIG. 9 is a block diagram of a test case in accordance with an alternative embodiment of the present invention;
FIG. 10 is a flow diagram of a method of chip verification according to an alternative embodiment of the invention;
FIG. 11 is a schematic diagram of a chip verification system according to an alternative embodiment of the invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In this embodiment, a chip verification method is provided, and fig. 2 is a flowchart of the chip verification method according to the embodiment of the present invention, as shown in fig. 2, the flowchart includes the following steps:
step S202, generating a verification platform, wherein the verification platform comprises: the system comprises a model layer and an interface layer, wherein the model layer comprises a flow model and a register model, and the interface layer comprises a data bus interface agent and a CPU bus interface agent;
and step S204, verifying the chip to be tested through the verification platform.
Through the steps, the hierarchical verification platform is generated, the chip to be tested is verified by the hierarchical verification platform, the problem that the reusability of the platform is low due to the fact that the UVM verification framework is lack of hierarchy is solved, the reusability of the verification framework is improved, and the verification efficiency is improved.
Optionally, generating the verification platform comprises: receiving a platform configuration file, wherein the platform configuration file carries model parameters of a model layer, interface parameters of an interface layer and platform structure parameters of a verification platform; selecting components corresponding to the platform structure parameters from a platform component library to generate a basic framework of the verification platform; generating a flow model and a register model according to the model parameters; and generating a data bus interface agent and a CPU bus interface agent according to the interface parameters. Through the mode, the components used for generating the basic framework of the verification platform can be preset in the platform component library, so that the verification platform can be quickly built.
Optionally, when the chip to be tested is verified, the test configuration can be compiled and then sent to the verification platform, and the verification platform receives the test configuration for verifying the chip to be tested, wherein the test configuration carries platform configuration, interface test configuration, flow test configuration and register test configuration; the verification platform selects test cases respectively corresponding to the interface test configuration, the flow test configuration and the register test configuration from the test suite; the verification platform adjusts the test cases according to the platform configuration; and the verification platform runs the adjusted test case to generate a verification report.
Optionally, when the chip to be tested is verified, in the verification platform, the flow model generates a transaction-level message of forwarding surface flow required by the chip to be tested; the register model generates a transaction level message of a control surface register required by a chip to be tested; the data bus interface agent converts the transaction level message received from the flow model into a bus signal level excitation sent to a chip to be tested, and converts the bus signal level excitation received from the chip to be tested into the transaction level message sent to a reference model or a score board; the CPU bus interface agent converts the transaction level message received from the register model into a bus signal level excitation sent to the chip to be tested, and converts the bus signal level excitation received from the chip to be tested into the transaction level message sent to the reference model or the score board.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
In this embodiment, a chip verification apparatus is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and details are not repeated after the description is given. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 3 is a block diagram of a chip verification apparatus according to an embodiment of the present invention, and as shown in fig. 3, the apparatus includes: a generation module 32 and a verification module 34, wherein,
a generating module 32, configured to generate a verification platform, where the verification platform includes: the system comprises a model layer and an interface layer, wherein the model layer comprises a flow model and a register model, and the interface layer comprises a data bus interface agent and a CPU bus interface agent; and the verification module 34 is coupled to the generation module 32 and is used for verifying the chip to be tested through the verification platform.
Fig. 4 is a block diagram of an alternative structure of the chip verification apparatus according to the embodiment of the present invention, as shown in fig. 4, optionally, the generating module 32 includes: a first receiving unit 322, configured to receive a platform configuration file, where the platform configuration file carries a model parameter of a model layer, an interface parameter of an interface layer, and a platform structure parameter of a verification platform; a first selectingunit 324, coupled to the first receiving unit 322, for selecting a component corresponding to the platform structure parameter from the platform component library, and generating a basic framework of the verification platform; afirst generating unit 326 coupled to the first receiving unit 322, for generating a traffic model and a register model according to the model parameters; thesecond generating unit 328 is coupled to the first receiving unit 322, and is configured to generate the data bus interface agent and the CPU bus interface agent according to the interface parameters.
Fig. 5 is a block diagram of an alternative structure of the chip verification apparatus according to the embodiment of the present invention, as shown in fig. 5, optionally, the verification module 34 includes: the second receiving unit 340 is configured to receive a test configuration for verifying a chip to be tested, where the test configuration carries a platform configuration, an interface test configuration, a flow test configuration, and a register test configuration; a second selecting unit 341, coupled to the second receiving unit 340, configured to select test cases corresponding to the interface test configuration, the traffic test configuration, and the register test configuration from the test suite; an adjusting unit 342, coupled to the second selecting unit 341, for adjusting the test case according to the platform configuration; the verification unit 343, coupled to the adjusting unit 342, is configured to run the adjusted test case and generate a verification report.
Fig. 6 is a block diagram of an alternative structure of the chip verification apparatus according to the embodiment of the present invention, as shown in fig. 6, optionally, the verification module 34 includes: a third generating unit 344, configured to generate, through the traffic model, a transaction-level message of forwarding plane traffic required by the chip to be tested; a fourth generating unit 345, configured to generate, through the register model, a transaction-level message of a control plane register required by the chip to be tested; a first interface unit 346, coupled to the third generating unit 344, configured to convert, through the data bus interface agent, the transaction level message received from the traffic model into a bus signal level excitation sent to the chip to be tested, and convert the bus signal level excitation received from the chip to be tested into a transaction level message sent to the reference model or the scoreboard; the second interface unit 347 is coupled to the fourth generating unit 345, and configured to convert, through the CPU bus interface agent, the transaction level message received from the register model into a bus signal level excitation sent to the chip to be tested, and convert the bus signal level excitation received from the chip to be tested into a transaction level message sent to the reference model or the scoreboard.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in a plurality of processors.
An embodiment of the present invention further provides a chip verification system, and fig. 7 is a block diagram of a structure of the chip verification system according to the embodiment of the present invention, as shown in fig. 7, the system includes: the chip verification device 72, the platform component library 74, the test suite library 76, and the script library 78, where the platform component library 74 is coupled to the chip verification device 72 and is used to provide components for constructing a basic framework of a verification platform; a test suite library 76 coupled to the chip verification device 72 for providing test cases; and a script library 78 coupled to the chip verification device 72 for providing scripts required for the automated operation of the chip verification device.
The embodiment of the present invention also provides software for executing the technical solutions described in the above embodiments and preferred embodiments.
The embodiment of the invention also provides a storage medium. In the present embodiment, the storage medium described above may be configured to store program code for performing the steps of:
step S202, generating a verification platform, wherein the verification platform comprises: the system comprises a model layer and an interface layer, wherein the model layer comprises a flow model and a register model, and the interface layer comprises a data bus interface agent and a CPU bus interface agent;
and step S204, verifying the chip to be tested through the verification platform.
Optionally, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing program codes, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.
In order to make the description of the embodiments of the present invention clearer, the following description and illustrations are made with reference to alternative embodiments.
In the RTL front-end verification of a digital chip, the traditional verification method has a plurality of defects, and the UVM verification methodology is used, so that the defects exist in the aspects of layering, reusability and automation. Therefore, the embodiments of the present invention are directed to a new verification platform architecture and a testing method, so as to solve the problems existing in the existing verification architecture.
An optional embodiment of the present invention provides a chip verification architecture, a testing method, and a system, which are used for front-end Register Transfer Level (RTL) logic verification of a digital chip.
In order to provide a hierarchical and highly reusable verification platform structure and a standardized test case structure, and simultaneously construct a complete automatic verification process by combining a script language on the basis of the verification architecture, thereby improving the overall verification efficiency, the chip verification architecture provided by the optional embodiment of the invention adopts the following scheme:
as shown in fig. 8, the verification platform is divided into two levels, a model layer and an interface layer:
the model layer comprises a flow model and a register model, wherein:
the flow model models the flow of a forwarding plane required by the whole chip to be tested, and generates an object-level message of data flow, wherein the message is irrelevant to a specific data bus interface.
The register model models a control surface register needed by a chip to be tested, and generates an object-level message of the register, wherein the message is irrelevant to a specific CPU bus interface.
The interface layer comprises a data bus interface agent and a CPU bus interface agent:
the interface agent realizes a specific data bus protocol (comprising different data buses and a CPU bus), converts the object level message into a bus signal level excitation, monitors the bus, converts the bus interface signal into the object level message, and sends the object level message to a reference model or a scoring board. The interface agent is only associated with a specific bus protocol type, and is not associated with the type of messages carried on the bus.
In combination with the hierarchical verification architecture, the present invention provides a test case structure scheme, as shown in fig. 9, the test case structure includes:
interface configuration, which is used for describing the configuration of an interface test case corresponding to an interface agent in a platform;
the platform configuration is used for describing the working configuration parameters of all components in the platform;
message configuration, which is used for describing the working configuration of the flow model;
and the register configuration is used for describing the read-write configuration of the register model.
An alternative embodiment of the present invention further provides a method for testing a front-end RTL logic of a chip, as shown in fig. 10, including the following steps:
step S1001: compiling a platform configuration file, wherein the platform configuration file comprises platform structure configuration, flow model configuration and register model configuration, and the configuration file can be stored in an eXtensible Markup Language (eXtensible Markup Language, abbreviated as xml) format;
step S1002: and generating a verification platform, namely calling an environment building script (envBuilder), reading the platform structure configuration in the platform configuration file, selecting a corresponding interface component and other components from a component library of the software system, and generating a basic framework of the verification platform.
Secondly, calling a register model generation script (spec2reg), reading register model configuration in the platform configuration file, and generating a register model code;
thirdly, performing; calling a flow model generating script (spec2packet), reading flow model configuration in the platform configuration file, and generating a flow model code;
step S1003: compiling a reference model and a scoring board in a verification platform; supplementing a reference model and a score board module code in the generated verification platform frame according to a chip to be tested;
step S1004: writing case configuration files comprising platform configuration, interface test configuration, flow test configuration and register test configuration
Step S1005: generating a test case, calling a case generation script (testGen), selecting a case to be generated from a test suite:
firstly, selecting a corresponding interface test case from a test suite according to interface test configuration;
secondly, selecting a corresponding flow test case from the test suite according to the flow test configuration;
thirdly, selecting a corresponding register test case from the test suite according to the register test configuration;
and finally, modifying the standard use case according to different platform configurations so that the standard use case can normally run in the verification platform.
Step S1006: writing a new test case, calling a case generation script (testGen), selecting to write a new case, and generating a new test case framework, as shown in fig. 3. In the use case framework, platform configuration, interface configuration, message configuration and register configuration are compiled respectively.
Step S1007: running the test case for verification, calling a run and regression script (run & regression), selecting the required test case for running, collecting the related information of coverage rate, and generating a verification report;
in combination with the above verification platform architecture, test case structure, and test method, the present invention optionally further provides a set of verification platform software system, as shown in fig. 11, including: a platform component library, a test suite library, and a script library.
A platform component library comprising:
the basic assembly is used for storing basic modules built by the verification platform, such as a configuration module, a scoring board and the like;
the data interface assembly is used for storing a data bus agent module required by the construction of the verification platform;
the CPU interface assembly is used for storing a CPU bus agent module required by the construction of the verification platform;
the message assembly is used for storing modules required by flow model building in the verification platform;
the register component is used for storing modules required by register model building in the verification platform;
the reference model assembly is used for building a required module by using a reference model in the storage verification platform;
the macro component is used for storing macro codes required in the verification platform building and test case compiling;
and the virtual interface assembly is used for storing virtual interfaces required in the establishment of the verification platform.
A test suite library comprising:
the message use case is used for storing a typical message flow model and model configuration information;
the register use case is used for storing a typical register model and model configuration information;
and the interface protocol use case is used for storing the use case for testing the interface protocol.
A script library comprising:
an environment building script (envBuilder) is generated, and a basic framework of the verification platform and a software environment operated by the verification platform are generated according to the platform configuration file;
a register model generating script (spec2reg) generates a register model according to the register configuration file;
a flow model generating script (spec2packet) generates a flow model according to the flow configuration file;
a case generation script (testGen) extracts a case from a test suite library according to a case configuration file to generate a test case required for verification;
and running and regressing scripts (run & regressions) for controlling the running of the test cases, collecting the related information of the coverage rate and generating a verification report.
In summary, according to the above-mentioned scheme provided by the optional embodiment of the present invention, the verification platform is divided into the model layer and the interface layer, and the high-level traffic modeling and register modeling are separated from the bottom physical interface, so that the reusability of the verification platform is greatly improved. Meanwhile, a testing method and a software system are provided based on the framework, the functional definitions of a testing process and a verification module are standardized, the repeated development time of a verification platform is saved, the automation of a chip verification process is realized, and the chip verification efficiency is greatly improved.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A method of chip verification, comprising:
generating a verification platform, wherein the verification platform comprises: the system comprises a model layer and an interface layer, wherein the model layer comprises a flow model and a register model, and the interface layer comprises a data bus interface agent and a CPU bus interface agent;
verifying the chip to be tested through the verification platform;
verifying the chip to be tested comprises:
generating a transaction-level message of forwarding surface flow required by the chip to be tested through the flow model;
generating a transaction-level message of a control surface register required by the chip to be tested through the register model;
converting the transaction level message received from the flow model into a bus signal level excitation sent to the chip to be tested through the data bus interface agent, and converting the bus signal level excitation received from the chip to be tested into the transaction level message sent to a reference model or a score board;
and converting the transaction level message received from the register model into a bus signal level excitation sent to the chip to be tested through the CPU bus interface agent, and converting the bus signal level excitation received from the chip to be tested into the transaction level message sent to a reference model or a score board.
2. The method of claim 1, wherein generating the verification platform comprises:
receiving a platform configuration file, wherein the platform configuration file carries model parameters of the model layer, interface parameters of the interface layer and platform structure parameters of the verification platform;
selecting components corresponding to the platform structure parameters from a platform component library, and generating a basic framework of the verification platform;
generating the flow model and the register model according to the model parameters;
and generating the data bus interface agent and the CPU bus interface agent according to the interface parameters.
3. The method of claim 1, wherein verifying the chip under test comprises:
receiving a test configuration for verifying a chip to be tested, wherein the test configuration carries a platform configuration, an interface test configuration, a flow test configuration and a register test configuration;
selecting test cases respectively corresponding to the interface test configuration, the flow test configuration and the register test configuration from a test suite;
adjusting the test case according to the platform configuration;
and running the adjusted test case to generate a verification report.
4. A chip verification apparatus, comprising:
a generation module configured to generate a verification platform, wherein the verification platform comprises: the system comprises a model layer and an interface layer, wherein the model layer comprises a flow model and a register model, and the interface layer comprises a data bus interface agent and a CPU bus interface agent;
the verification module is used for verifying the chip to be tested through the verification platform;
the authentication module includes:
a third generating unit, configured to generate, through the traffic model, a transaction-level message of forwarding plane traffic required by the chip to be tested;
a fourth generating unit, configured to generate, through the register model, a transaction-level packet of a control plane register required by the chip to be tested;
the first interface unit is used for converting the transaction level message received from the flow model into a bus signal level excitation sent to the chip to be tested through the data bus interface agent, and converting the bus signal level excitation received from the chip to be tested into the transaction level message sent to the reference model or the score board;
and the second interface unit is used for converting the transaction level message received from the register model into a bus signal level excitation sent to the chip to be tested through the CPU bus interface agent, and converting the bus signal level excitation received from the chip to be tested into the transaction level message sent to the reference model or the score board.
5. The apparatus of claim 4, wherein the generating module comprises:
a first receiving unit, configured to receive a platform configuration file, where the platform configuration file carries a model parameter of the model layer, an interface parameter of the interface layer, and a platform structure parameter of the verification platform;
the first selection unit is used for selecting components corresponding to the platform structure parameters from a platform component library and generating a basic framework of the verification platform;
the first generation unit is used for generating the flow model and the register model according to the model parameters;
and the second generating unit is used for generating the data bus interface agent and the CPU bus interface agent according to the interface parameters.
6. The apparatus of claim 4, wherein the verification module comprises:
the second receiving unit is used for receiving test configuration used for verifying a chip to be tested, wherein the test configuration carries platform configuration, interface test configuration, flow test configuration and register test configuration;
the second selection unit is used for selecting test cases respectively corresponding to the interface test configuration, the flow test configuration and the register test configuration from the test suite;
the adjusting unit is used for adjusting the test case according to the platform configuration;
and the verification unit is used for running the adjusted test case and generating a verification report.
7. A chip verification system, comprising: the chip verification apparatus, the platform component library, the test kit library, the script library according to any one of claims 4 to 6,
the platform component library is used for providing components for constructing a basic framework of the verification platform;
the test suite library is used for providing test cases;
and the script library is used for providing scripts required by the automatic operation of the chip verification device.
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| PCT/CN2016/081331WO2016197768A1 (en) | 2016-01-04 | 2016-05-06 | Chip verification method, device, and system |
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