Background technique
Global Navigation Satellite System (Global Navigation Satellite System, GNSS) receiver it is mainTask is capture and tracking satellite signal, after signal transforms to baseband signal from radiofrequency signal, is completed by base band signal processNavigator fix resolves.
The capture of GNSS signal searches for from reception signal, captures each visible GPS satellite signal, and is therefrom defendedThe carrier frequency and C/A code phase rough estimate value of star signal.In the tracking phase of GNSS signal, what is obtained from acquisition phase is defendedStar signal(-) carrier frequency and code phase rough estimate value are set out, and multiple correlators are arranged centered on the code phase of initial estimation,And set carrier frequency to the carrier frequency of initial estimation, gradually finely two signal parameters are estimated by track loopMeter, while exporting to the various measured values of signal, then demodulate the navigation message bit in signal in passing.Track loop is generally by phaseClose device, discriminator, loop filter composition.Wherein correlator is often through hardware realization, by the integral accumulation of integer number of millisecondsIt exports and gives loop discriminator, and loop discriminator and loop filter are often by software realization.Track loop is functionally divided intoCode tracking and carrier track are respectively completed the accurate lock of ranging code phase and carrier frequency.
Frequency deviation need to be estimated using frequency discriminator by carrying out carrier track, and general there are two types of methods: utilizing arc tangentThe phase difference that function asks the correlator of adjacent time to export integrated value obtains frequency divided by time interval, and another method is to utilizeFast Fourier Transform (FFT) (Fast Fourier Transform, FFT) or discrete Fourier transform (Discrete FourierTransform, DFT) frequency spectrum then frequency discrimination is converted to the integrated value progress frequency domain of correlator continuous time point output, it is latterKind method has been widely used because bigger frequency identifies range.
It needs to find frequency spectrum maximum value within the scope of defined frequency and correlator when carrying out frequency domain identification, then in maximumNearby frequency discrimination obtains the fine values of offset estimation to value；In addition loop circuit state is monitored and is also required in some pre-determined frequencyRate and correlator range count the maximum Distribution value of frequency spectrum, that is, need to carry out multiple and different frequencies and correlator rangeMaximum Data-Statistics.Due to being modulated with navigation message in GNSS signal, coherent integration time is often limited, to improve signal-to-noise ratio,It often will do it noncoherent accumulation；In addition, also needing to calculate the mean value of frequency spectrum to the monitoring of loop.Due to the meeting when DFT is calculatedFrequency spectrum is traversed, be can be convenient and sought maximum value and mean value, calculate noncoherent accumulation value.
Calculation amount can be saved relative to DFT using FFT, the calculation amount of saving increases with frequency point number and increased, but frequency pointNumber cannot choose at random, and frequency interval is determined by frequency point number, and to increase frequency domain resolution, fft algorithm is required to input time domainData padding, this will increase calculation amount again, and when frequency point number is less, the advantage that calculation amount is saved is unobvious.It, can when using DFTWith flexible choice frequency interval and frequency point number.In view of GNSS signal tracks typical scene, required frequency point number is simultaneously little, adopts at this timeWith DFT scheme, zero padding can be avoided, calculation amount when practical application is suitable with FFT scheme, and can flexible configuration frequency intervalWith frequency point number.The present invention is to carry out frequency domain decomposition to the integrated value that correlator exports using DFT.
Currently using DFT carry out frequency domain frequency discrimination and when frequency discrimination, statistics and search for frequency spectrum maximum value by Receiver Software orFirmware realizes that DFT operation can be used software and calculate or be realized using DSP device.Software, which calculates, to be realized DFT operation that there are speed is lowDefect；DSP device realizes that arithmetic speed can be improved in DFT operation, but can not realize in large scale integrated circuit, not clever enoughIt is living.Industry needs to improve a kind of scheme, to improve GNSS signal carrier track calculating speed, to improve system processing capacity.
Summary of the invention
In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a kind of satellite navigation baseband signal track algorithmsHardware accelerator and method can be improved GNSS signal carrier track calculating speed, to improve system processing capacity, this hairThe bright technical solution for solving above-mentioned technical problem is as follows: a kind of hardware accelerator of satellite navigation baseband signal track algorithm,Including data transmission module, data cache module, access control module, operation accumulator module and statistical module, the operation is tiredAdding module includes multiple operation summing elements, and the data cache module is connected by data transmission module with base band SoC system,The operation accumulator module is connected with data cache module, and the access control module is transmitted with base band SoC system, data respectivelyModule, data cache module, operation accumulator module are connected with statistical module, by the data transmission module by DFT data andIn the NCS data write-in data cache module of last time operation, access control module generates starting DFT operation after the completion of data write-inIndication signal, operation accumulator module generate twiddle factor and carry out DFT fortune to DFT data parallel by multiple operation summing elementsIt calculates, then by the way that the cumulative of DFT operation result is obtained new NCS data and be updated to the NCS data of last time operation, countsModule obtains statistical result according to DFT operation result and updated NCS data, and data transmission module is again by updated NCSData are transmitted back to base band SoC system.
It further, further include data arbitration modules, the data cache module is passed by data arbitration modules and dataDefeated module, access control module, operation accumulator module are connected with statistical module, and data arbitration modules are used for before operation and statisticsData transmission module and the interface of data cache module carry out arbitration selection afterwards.
It further, further include interface configuration module, the access control module passes through interface configuration module and base band SoCSystem is connected.
Further, the data transmission module is connected by AHB host device interface with base band SoC system.
Further, the data cache module includes DFT data cell and NCS data cell, and DFT data cell is used forThe DFT operation result is deposited, NCS data cell is for depositing the NCS data.
A kind of hardware-accelerated method of satellite navigation baseband signal track algorithm, comprising the following steps:
1) DFT data and the NCS data of last time operation are stored in advance in base band SoC system, and hardware accelerator is being transportedThe write-in of the NCS data of DFT data and last time operation is executed before calculating；
2) after the completion of DFT data and the NCS data of last time operation are written, hardware accelerator refers to according to starting DFT operationShow that signal starts DFT operation；
3) hardware accelerator reads DFT data, and generates twiddle factor by the parameter of software configuration, passes through multiple operationsSumming elements carry out DFT operation parallel, then by obtaining updated NCS data to the cumulative of DFT operation result；
4) hardware accelerator statistics DFT operation result and updated NCS data, according to DFT operation result and updateNCS data afterwards obtain statistical result, and updated NCS data are transferred in base band SoC system；
5) after completing operation result statistics and the transmission of NCS data, hardware accelerator stops operation and counts and generate hardPart interrupts, and reads updated NCS data after base band SoC system response hardware interrupts and carries out subsequent algorithm processing.
Further, in the step 1), DFT number is written by AHB host device interface with dma mode in hardware acceleratorAccording to the NCS data with last time operation.
Further, in the step 3), the parameter of software configuration specifically include correlator number, DFT operation frequency point number,DFT operation sampling number and whether add up.
Further, in the step 4), it is equal that statistical result specifically includes energy peak, energy peak location and energyValue.
Further, in the step 4), obtain after statistical result that there are in hardware accelerator statistical result.
Beneficial effect using above-mentioned further scheme is: the present invention proposes a kind of frequency domain realized in on-chip system chipThe hardware accelerator and method of carrier track algorithm specially carry out track algorithm time-frequency domain frequency discrimination in frequency domain to GNSS signalDFT operation, while DFT operation result is counted, such as to searching for frequency spectrum maximum value within the scope of specified frequency and correlator,And circuit and performance progress height optimization for the hardware accelerator, GNSS signal carrier track calculating speed is improved, fromAnd improve system processing capacity.
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, andIt is non-to be used to limit the scope of the invention.
A kind of hardware accelerator and method of satellite navigation baseband signal track algorithm are applied to base band SoC system, i.e.,Baseband signal on-chip system chip System on Chip.Base band SoC system mainly include microcontroller, baseband processing module withAnd system RAM module, it is integrated with the base band SoC system special disposal GNSS intermediate-freuqncy signal of this hardware accelerator, it is hardware-acceleratedDevice is integrated in base band SoC system with AMBA AHB interface.This hardware accelerator external interface uses AMBA AHB interfaceAnd hardware interrupts indication signal, i.e. Advanced Microprocessor Bus Architecture Advanced Microcontroller BusStructure and Advanced High-performance Bus Advanced High-Performance Bus, interface is simple, can be straight in the form of IP moduleIt connects and is integrated in base band SoC system.AMBA AHB interface includes AHB host device interface and AHB from equipment interface, is added in this hardwareIn speed variator, data transmission module 1 is connected by AHB host device interface with base band SoC system, and interface configuration module 7 passes through AHBIt is connected from equipment interface with base band SoC system.Data are transmitted through the progress of AHB host device interface, the software of hardware acceleratorConfiguration is carried out by AHB from equipment interface.The course of work and principle of hardware-accelerated method are as follows:
The GNSS intermediate-freuqncy signal of input is after Signal Pretreatment, respectively by the trapping module of base band SoC system and tracking mouldEach correlator coherent integration results that tracking module exports can be write system by block processing, the firmware program for running on microcontrollerIn RAM module；
The source data for needing to carry out DFT operation is passed through AHB from equipment in the initial address of system RAM module by firmware programInterface configures related register inside hardware accelerator, and configures other parameters such as correlator number, DFT operation frequency pointNumber, DFT operation sampling number etc., last configuration register start DFT operation；
Hardware accelerator copies DFT operation source data from system RAM module with dma mode by AHB host device interfaceAnd DFT operation cumulative data, after starting DFT operation and adding up, statistical result is stored in data and delayed by programming count calculated resultIn storing module 2, and the resulting NCS data that will add up copy back system RAM module by AHB host device interface with dma mode, mostInterruption is generated afterwards；
After firmware program receives interruption, the resulting NCS data that add up directly are read from system RAM module, and slow from dataStoring module 2 reads statistical result, then carries out frequency domain tracking carrier wave ring algorithm, realizes and stablizes quickly tracking.
As shown in Figure 1, a kind of hardware accelerator of satellite navigation baseband signal track algorithm, including data transmission module1, data cache module 2, access control module 3, operation accumulator module 4, statistical module 5, data arbitration modules 6 and interface configurationModule 7.
Data transmission module 1 realizes that the bursting data between this hardware accelerator and base band SoC system are transmitted, and reduces numberAccording to moving the time, and realize that dma mode transmits data, i.e. the mode of Direct Memory Access directly accesses base band SoCThe system RAM module of system is not necessarily to microcontroller intervention, improves performance.Specifically, it realizes from base band SoC system and carries DFT fortuneData cache module 2 inside the evidence that counts and NCS data to hardware accelerator, and from the data inside hardware acceleratorCache module 2 reads the operation of updated NCS data writing systems RAM module.Wherein, NCS data are the energy after DFT operationMagnitude accumulation result, i.e. non-coherent integration values.
Data cache module 2 include DFT data cell and NCS data cell, be respectively used to deposit DFT operation source data andNCS data.
Access control module 3 realizes the timing control and starting control of this hardware accelerator, including single DFT operationOr energy value after DFT operation it is cumulative when to the access control of data cache module 2.
Operation accumulator module 4 includes multiple operation summing elements；Specifically, operation accumulator module 4 includes that four operations are tiredAdd unit, realize four DFT concurrent operations, and by operation result Serial output, be converted to energy value, realizes the energy that DFT is calculatedMagnitude is cumulative and data cache module 2 is written in the resulting NCS data that will add up.
Statistical module 5 realizes the statistics to DFT operation result and updated NCS data, such as to specified frequency and phaseIt closes and searches for frequency spectrum maximum value within the scope of device.
The realization of data arbitration modules 6 carries out arbitration selection to the interface of data transmission module 1 and data cache module 2.FirmlyWhen part accelerator needs to be written the NCS data of DFT data and last time operation, data arbitration modules 6 pass through data transmission module 1Data cache module 2 is written from base band SoC system in DFT data and the NCS data of last time operation；After the completion of write-in, work as hardwareWhen accelerator needs to carry out DFT operation, data arbitration modules 6 are DFT data and the NCS data of last time operation from data buffer storageOperation accumulator module 4 is written in module 2, and 4 operation of operation accumulator module obtains DFT operation result and updated NCS data and handleThe above results are stored to data cache module 2, and data arbitration modules 6 are passed updated NCS data by data transmission module 1 againReturn base band SoC system.
Interface configuration module 7 realizes configuration interface function, realize software to the register configuration of this hardware accelerator andQuery function.
As shown in Fig. 2, a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm, is mainly summarised as following stepIt is rapid:
1. the phase before hardware accelerator work, after the correlator operation of the various code phases of base band tracking module outputDry integrated value has been stored in base band as energy value accumulation result, that is, NCS data after DFT data and the operation of last time DFTDFT data and NCS data are stored in the initial address of base band SoC system by SoC system, software, are write by AHB from equipment interfaceThe interface configuration module 7 for entering this hardware accelerator is reconfigured other DFT operational parameters such as correlator number, DFT operation frequency pointNumber, DFT operation sampling number and whether cumulative etc., finally configuration starting DFT operation；
2. access control module 3 decodes configuration register, DFT operation time sequence indication signal, DFT operation to be launched are generatedWhen, control signal is issued to data transmission module 1, data transmission module 1 is automatically by AHB host device interface from base band SoC systemSystem passes sequentially through burst transfer modes and copies DFT data and NCS data with dma mode, and is written firmly by data arbitration modules 6Data cache module 2 inside part accelerator.After pending data has copied, access control module 3 is issued to operation accumulator module 4Start the indication signal of DFT operation；
After 3. operation accumulator module 4 receives starting DFT operation indication signal, from the data buffer storage inside hardware acceleratorModule 2 reads DFT data, generates twiddle factor by the parameter of software configuration, and carry out DFT operation.It is interior to accelerate DFT operationPortion realizes 4 frequency point parallel DFT arithmetic elements, can carry out the DFT operation result output of most 4 frequency points simultaneously；Operation adds up mouldFrequency point completes DFT operation to correlator to block 4 one by one one by one, and by obtaining updated NCS number to the cumulative of DFT operation resultAccording to；
4. after operation accumulator module 4 completes DFT operation and the NCS cumulative of all frequency point datas of all correlators, statisticsModule 5 starts to count DFT operation result and updated NCS data respectively, obtains statistical result.Statistical result includes energyPeak value, energy peak location and average energy value, wherein energy peak is the maximum value of all frequency point energy values of all correlators, energyMeasuring peak position is that correlator is numbered and value of frequency point, average energy value are the average value of all frequency point energy values of all correlators.Simultaneously according to software configuration, updated NCS data are automatically copied in base band SoC system by data transmission module 1；
5. being generated after statistical module 5 completes operation result statistics and NCS data are copied into base band SoC systemHardware interrupts, software directly read operation result and carry out subsequent algorithm processing.Operation result includes base band SoC internal systemThe statistical result and peak detection result that access control module 3 saves in NCS data and this hardware accelerator.
This hardware accelerator and method realize the DFT operation of signal trace algorithm by hardware accelerator form, useAMBA AHB interface can be directly integrated in base band SoC system with IP modular form, easily transplanting multiplexing, and be suitble to extensive collectionIt is realized at circuit；AHB host device interface takes out operational data from specified memory initial address automatically with dma mode, and by suddenHairdo transmission mode copies data cache module 2 to dma mode, reduces data-moving time and microprocessor intervention, improvesPerformance；When single DFT operation, each correlator can carry out the DFT operation of N number of frequency point number parallel, greatly improve technical performance, togetherWhen take into account performance and Area Balanced, wherein N is that natural number and N are greater than 2；Energy value after single DFT operation is counted, is unitedCounting result includes energy peak, energy peak location and average energy value；It, can be to the energy value after DFT operation according to software configurationIt carries out cumulative and the energy value accumulation result after DFT operation is counted, such as count cumulative average energy value, find out 3 squaresThe Peak value position of the accumulated energies value of shape window；After each DFT operation and NCS energy accumulation, when calculating statistical result,Hardware logic, which is sent, to interrupt, and software directly reads operation result and carries out subsequent algorithm processing.
Generally speaking, operation time is reduced by measure following aspects:
Energy value operation after realizing the DFT operation and DFT operation of signal trace algorithm by hardware accelerator form,It is automatic simultaneously to realize that DFT operation result is cumulative, and DFT operation result and DFT operation accumulation result are subjected to peak detectionAnd statistics, making the same operand calculating time is about the 1/200 of the software calculating time, additionally by hardware realization DFT operation knotThe statistics and peak detection of fruit more reduce the plenty of time；
Parallel to carry out DFT operation, single DFT operation can carry out the DFT operation of N number of frequency point number parallel, make DFT operation timeIt will be for the 1/N of usual serial computing time；
In the data cache module 2 by DFT data from base band SoC system copy to this hardware accelerator, or will depositWhen being placed on the DFT operation result of this hardware accelerator data cache module 2 and copying base band SoC system to, pass through AHB main equipmentInterface is carried out data transmission with dma mode, and data copy average time will be to be reduced to the 1/5 of I/O access mode.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention andWithin principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.