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CN106896710A - Scene configurable time synchronization test system and implementation method - Google Patents

Scene configurable time synchronization test system and implementation method
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Publication number
CN106896710A
CN106896710ACN201710225081.9ACN201710225081ACN106896710ACN 106896710 ACN106896710 ACN 106896710ACN 201710225081 ACN201710225081 ACN 201710225081ACN 106896710 ACN106896710 ACN 106896710A
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CN
China
Prior art keywords
test
system engine
interface
data
signal
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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CN201710225081.9A
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Chinese (zh)
Inventor
陈泽青
杨炳
王春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHENGDU FUHE POWER AUTOMATION COMPLETE EQUIPMENT Co Ltd
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CHENGDU FUHE POWER AUTOMATION COMPLETE EQUIPMENT Co Ltd
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Application filed by CHENGDU FUHE POWER AUTOMATION COMPLETE EQUIPMENT Co LtdfiledCriticalCHENGDU FUHE POWER AUTOMATION COMPLETE EQUIPMENT Co Ltd
Priority to CN201710225081.9ApriorityCriticalpatent/CN106896710A/en
Publication of CN106896710ApublicationCriticalpatent/CN106896710A/en
Pendinglegal-statusCriticalCurrent

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Abstract

The invention discloses time synchronization test system and implementation method that a kind of scene is configurable,Including general purpose interface bus,Some multifunctional signal detection cards,Embeded processor,Memory,LCD display,Man-machine interface,High precision measurement reference cell and test cell of adjusting,Multifunctional signal detection card includes fpga chip and signal conditioning circuit,System engine and bus control unit are provided with embeded processor,System engine has standard configuration script loading interface and functional unit standard dispatch interface,General purpose interface bus is manipulated by bus control unit,To respond and dispatching requirement of each functional unit to reading and writing data,Realize the management of the data exchange between functional unit,Functional unit includes test function module of adjusting,Time synchronizing signal detects functional module,Data analysis and arbitration functions module,Test result display function module and data management function module.The present invention has high flexibility and reusability, and high working efficiency is easy to safeguard.

Description

Scene configurable time synchronization test system and implementation method
Technical field
The invention belongs to technical field of electric power, and in particular to a kind of configurable time synchronization test system in scene and realizationMethod, is mainly used in the time synchronized of intelligent substation.
Background technology
With the construction and development of intelligent grid, intelligent substation proposes higher and higher wanting to clock synchronization systemAsk, the properties of product on-site evaluation, finished product factory testing, synchronous regime monitoring, diagnosing, on-the-spot test to clock synchronization system pointAnalysis etc. proposes new application requirement, i.e. time synchronous test system must possess live reconfigurable for specific test requestAbility, so as to quick changed test procedure and instrumental function at the scene, so as to conveniently and efficiently complete many using a testerPlant Site Test Analysis task.
In the prior art, such as entitled " a kind of hand-held time synchronization tester " (application number 2014103114147.8)Chinese invention patent disclose a kind of hand-held time synchronization tester, including signal preprocessing unit, stipulations receive inspectionVerification certificate unit, main control unit, measuring unit and human and machine interface unit, also including PPS/PPM/PPH pulse signals decoding unit,IRIG-B (AC/DC) TTL/422 time signals decoding unit, RS232/485 frequency time signals decoding unit, by time service equipmentWarning information decoding unit, controllable synchronous signal output and the automatic resolution unit of message.Existing tester is specific according to oneApplication scenarios and build, static system is belonged in itself:I.e. test system is pre-designed, solid after coming into operationIt is fixed constant, do not possess the ability according to different test objects and test assignment adjustment and dynamic restructuring, it is impossible to well adapt toDynamic need;In addition in traditional test system control flow, flow is single suitable according to the requirement of predefined test assignmentThe row of sequence gets off, for measurand, the requirement that test point is a lot, test parameter is complicated under, may result in testing and control flowIt is many that abnormal cumbersome and repeated work is set, it is difficult to realize structuring, modularized design, take time and effort and easily malfunction, addTest assignment demand may change at any time, and detection parameter may increase, and test scope may be adjusted, then test system controlFlow is accomplished by constantly change, and the maintenance of system is extremely difficult.
The content of the invention
The purpose of the present invention is that and provides a kind of scene configurable time synchronization test in order to solve the above problemsSystem and implementation method.
The present invention is achieved through the following technical solutions above-mentioned purpose:
A kind of configurable time synchronization test system in scene, including tester platform, general purpose interface bus and some manyFunction signal detection card;
The tester platform includes embeded processor, memory, LCD display, man-machine interface, high precision measurement baseQuasi- unit and test cell of adjusting;
The embeded processor, the memory, the LCD display, the man-machine interface, the high precision measurementReference cell, described adjust test cell and some multifunctional signals detection card is hung on the general purpose interface bus;
The multifunctional signal detection card includes fpga chip and signal conditioning circuit, the signal of the signal conditioning circuitInput is connected with input interface, and the signal output part of the signal conditioning circuit is connected with the fpga chip, the FPGAChip is hung on the general purpose interface bus.
Based on the time synchronization test implementation method that the scene that above-mentioned hardware configuration draws can configure, the embedded processingSystem engine and bus control unit are provided with device, the system engine has standard configuration script loading interface and functional unitStandard dispatch interface, the system engine manipulates general purpose interface bus by bus control unit, to respond and dispatching each work(Requirement of the energy component to reading and writing data, realizes the management of the data exchange between functional unit, and the functional unit includes adjustingTest function module, time synchronizing signal detection functional module, data analysis and arbitration functions module, test result display functionModule and data management function module, concrete methods of realizing are comprised the following steps:
1) system engine option and installment script and is delivered to by man-machine interface on an lcd display;
2) system engine is manipulated after embeded processor parsed selected configuration script, determine test object quantity, whenBetween the type of synchronizing signal, the interface level of time synchronizing signal and solution deepness;
3) system engine configuration time synchronized is adjusted testing process, reaches the ready state of detection;
4) system engine by read script parse and come configuration information, by functional unit standard dispatch interface schedulingEach functional unit, the functional unit that can work independently operationally is coupled together by bus control unit;
5) select to start detection program on an lcd display by man-machine interface and be sent to system engine;
6) embeded processor is manipulated by functional unit, drives multifunctional signal to detect card by general purpose interface busDetection configuration, and detect that the signal conditioning circuit of card carries out signaling interface level conversion by multifunctional signal, by FPGA coresThe parsing test of piece deadline synchronizing signal and test data are assembled, and the data that will be assembled are sent out by general purpose interface busReturn system engine after embeded processor is processed is given, the detection work of signal is completed;
7) system engine scheduling data analysis manipulates the analysis that embeded processor performs data with arbitration functions moduleAnd arbitration functions, and by the test data after analysis and test report file return system engine;
8) select display test data function on an lcd display by man-machine interface and send to system engine;
9) system engine returns to test data and shows on an lcd display;
10) select to preserve function on an lcd display by man-machine interface by test data and test report file storageIn background data base on to memory.
Used as a kind of technical scheme that this patent is selected, the time synchronizing signal detection functional module includes normal signalDetection functional module, network time packet check functional module and time synchronized status detection function module.
The beneficial effects of the present invention are:
The configurable clock synchronization system tester in scene proposed by the present invention and implementation method, are examined by multifunctional signalSurvey card to be connected with embeded processor by general purpose interface bus, it is ensured that the interchangeability of signal detection hardware module;SeparatelyIt is outer by all of test parameter, testing process information into configuration script, and will be with tester control, time synchronizing signalThe relevant functional module of detection is integrated into functional unit, by building general system engine, is adjusted according to existing configuration informationTest function is completed with the functional module of functional unit, when test assignment changes, as long as change by Peripheral Interface matching somebody with somebodyPutting script can allow system to adapt to new testing requirement, overcome traditional tester be difficult to realize structuring and modularized design,Take time and effort, test object and demand data may be changed, detect that parameter may increase, test scope may be adjusted at any timeIt is whole, then test system control flow be accomplished by the problem of continuous change, overcome the shortcoming of the extremely difficult maintenance of system.
Brief description of the drawings
Fig. 1 is the structural schematic block diagram of the configurable time synchronization test system in scene of the present invention;
Fig. 2 is the schematic diagram of system engine of the present invention;
Fig. 3 is the configurable time synchronization test implementation method flow chart in scene of the present invention.
Specific embodiment
The invention will be further described below in conjunction with the accompanying drawings:
As shown in figure 1, the present invention includes tester platform, general purpose interface bus and some multifunctional signals detection card;
Tester platform includes embeded processor, memory, LCD display, man-machine interface, high precision measurement benchmark listUnit and test cell of adjusting;
Embeded processor, memory, LCD display, man-machine interface, high precision measurement reference cell, test of adjusting are singleFirst and some multifunctional signal detection card is hung on general purpose interface bus;
Multifunctional signal detection card includes fpga chip and signal conditioning circuit, and the signal input part of signal conditioning circuit connectsInput interface is connected to, the signal output part of signal conditioning circuit is connected with fpga chip, and fpga chip hangs over general purpose interface busOn.
High precision measurement reference cell, for according to the satellite clock signal for receiving or outside split-second precision benchmark letterNumber, realize to local time system calibration and synchronous, the time base source of formation test system, by general purpose interface bus,The time reference signal that test is compared is provided to each component and board of the system.
Test cell of adjusting obtains standard configuration script and time base source by general purpose interface bus, according to standard configurationThe parameter of script, the characteristic value of output time signal (information), and when the time signal after adjusting (information) is transmitted into testedBetween synchronization system (device), to test response condition of the tested clock synchronization system (device) to characteristic value of adjusting.
Embeded processor standard configuration script is provided and selected by man-machine interface and is deposited in memory, standardConfiguration script need to deliver to LCD display and show by embeded processor from memory, while embeded processor enters to itRow treatment.
System engine and bus control unit, system engine tool are provided with reference to shown in Fig. 2 and Fig. 3, in embeded processorThere are standard configuration script loading interface and functional unit standard dispatch interface, system engine manipulates general connecing by bus control unitMouth bus, to respond and dispatching requirement of each functional unit to reading and writing data, realizes the data exchange between functional unitManagement.Functional unit is to follow the functional module that the standard interface specifications of system engine are write, and functional unit includes survey of adjustingExamination functional module, time synchronizing signal detection functional module, data analysis and arbitration functions module, test result display function mouldBlock and data management function module, when time synchronizing signal detection functional module includes normal signal detection functional module, networkBetween packet check functional module and time synchronized status detection function module.System engine by loading standard configuration script item,The requirement of test parameter, testing process according to standard configuration script, described data are manipulated by described bus control unitBus carries out the operation of testing process dispatching described functional unit and described background data base.
Standard configuration script is the standard configuration pin that the system engine write using the cross-platform document languages of XML can readThis, and standard configuration script one measurement procedure of correspondence, and the integrated all of test parameter of the standard configuration script, surveyThe relevant data message of examination flow and functional unit connected mode.
System engine framework is shown in Fig. 2, and the system engine shown in figure is realized matching somebody with somebody standard by the dispatch interface of standardPut the standard loading interface and the data acquisition function module to functional unit, analytical capabilities module, data conditioning work(of scriptEnergy module, the scheduling feature of data analysis Function, analytical capabilities module is XML analytical capabilities moulds in this implementation methodBlock, for parsing standard configuration script, system engine is so designed as the set of each submodule, and these modules are collectively constitutedSystem engine operation support system, the system exposes an interface to be used to support measurement task script.Under different platforms, collectionInto the test assignment of the system engine operation support system, by calling standard interface, the measurement task pin of user configuring is readThis, completes desired data acquisition and data analysis.
Control signal and the time that embeded processor is sent by general purpose interface bus are received in multifunctional signal detection clampingA reference source, when carrying out signaling interface level conversion, fpga chip completion by the signal conditioning circuit of multifunctional signal detection cardBetween synchronizing signal parsing test and test data assembling, and the test data that will be assembled is sent to by general purpose interface busEmbeded processor is processed;Data/address bus is manipulated by bus control unit by system engine, is carried out scheduling feature component and is depositedBackground data base in reservoir, each functional unit of testing results instrument platform.
Concrete methods of realizing is comprised the following steps:
1) system engine option and installment script and is delivered to by man-machine interface on an lcd display;
2) system engine is manipulated after embeded processor parsed selected configuration script, determine test object quantity, whenBetween the type of synchronizing signal, the interface level of time synchronizing signal and solution deepness;
3) system engine configuration time synchronized is adjusted testing process, reaches the ready state of detection;
4) system engine by read script parse and come configuration information, by functional unit standard dispatch interface schedulingEach functional unit, the functional unit that can work independently operationally is coupled together by bus control unit;
5) select to start detection program on an lcd display by man-machine interface and be sent to system engine;
6) embeded processor is manipulated by functional unit, drives multifunctional signal to detect card by general purpose interface busDetection configuration, and detect that the signal conditioning circuit of card carries out signaling interface level conversion by multifunctional signal, by FPGA coresThe parsing test of piece deadline synchronizing signal and test data are assembled, and the data that will be assembled are sent out by general purpose interface busReturn system engine after embeded processor is processed is given, the detection work of signal is completed;
7) system engine scheduling data analysis manipulates the analysis that embeded processor performs data with arbitration functions moduleAnd arbitration functions, and by the test data after analysis and test report file return system engine;
8) select display test data function on an lcd display by man-machine interface and send to system engine;
9) system engine returns to test data and shows on an lcd display;
10) select to preserve function on an lcd display by man-machine interface by test data and test report file storageIn background data base on to memory.
These are only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all it is of the invention spirit andAny modification, equivalent and improvement for being made within principle etc., should be included within the scope of the present invention.

Claims (3)

2. the time synchronization test implementation method that a kind of scene can configure, it is characterised in that set in the embeded processorThere are system engine and bus control unit, there is the system engine standard configuration script loading interface and functional unit standard to dispatchInterface, the system engine manipulates general purpose interface bus by bus control unit, to respond and dispatching each functional unit pairThe requirement of reading and writing data, realizes the management of the data exchange between functional unit, and the functional unit includes test function of adjustingModule, time synchronizing signal detection functional module, data analysis and arbitration functions module, test result display function module sumAccording to management function module, concrete methods of realizing is comprised the following steps:
CN201710225081.9A2017-04-072017-04-07Scene configurable time synchronization test system and implementation methodPendingCN106896710A (en)

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Applications Claiming Priority (1)

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Cited By (3)

* Cited by examiner, † Cited by third party
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CN109061448A (en)*2018-10-292018-12-21北京京航计算通讯研究所IC testing stimuli based on modularization excitation model generates system
CN109061447A (en)*2018-10-292018-12-21北京京航计算通讯研究所IC testing stimuli generation method based on modularization excitation model
CN116306591A (en)*2023-05-182023-06-23深圳市东信时代信息技术有限公司Flow form generation method, device, equipment and medium

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US5790479A (en)*1996-09-171998-08-04Xilinx, Inc.Method for characterizing interconnect timing characteristics using reference ring oscillator circuit
CN101957776A (en)*2010-09-082011-01-26西安威锐达测控系统有限公司Field configurable handheld virtual testing instrument system and implementation method
CN202421768U (en)*2011-12-162012-09-05四川省电力公司通信自动化中心Multifunctional time synchronization calibrator for electric power systems
CN104981976A (en)*2012-12-282015-10-14尤尼科斯有限公司 Response to local grid events and distributed grid events
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CN109061448A (en)*2018-10-292018-12-21北京京航计算通讯研究所IC testing stimuli based on modularization excitation model generates system
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Application publication date:20170627


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