SONOS processesTechnical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, more particularly to a kind of SONOS processes.
Background technology
As shown in figure 1, the cellular construction of SONOS devices includes storage unit tube (SONOS) and selecting pipe (SG).In unitWhen array splices, adjacent two cellular construction is placed for back-to-back mirror image, and has one between back-to-back two storage unit tubesIndividual bit line (Bit Line) or source line (Source Line) coupling part CT (contact hole).Because the gate oxide of SONOS devicesBe ONO (Oxide-Nitride-Oxide), including be formed at the first silicon oxide layer of surface of silicon, the second silicon nitride layer and3rd silicon oxide layer is constituted.There is ONO between Poly etching (Poly etch) latter two storage unit tube, to avoid using complexityCT etching technics (CT etch) and there is the risk of CT open circuits (CT OPEN), this layer of ONO needs to be removed before CT.TypicallyIt is to be removed by side wall etching technics (SPACER Etch) in SONOS techniques, i.e., in the side wall medium layer comprising logic regionSecondary (SPACER FILM) continues etching and ONO layer is removed after having carved.
But, with continuing to develop for memory process, the size of device constantly reduces, comprising Low-Voltage Logic DevicesAnd under the trend of the operating voltage reduction of SONOS, the grid oxygen of Low-Voltage Logic Devices and the thickness of ONO layer are also gradually thinning, bottomThe thickness of oxide layer is even below 20A, by side wall etching technics likely result in substrate silicon damage (silicon gauge) andThe formation of substrate silicon difference row (substrate dislocation).With prepared SONOS device bottoms in existing process methodThe thickness more and more thinner of tunneling oxide layer (tunnel oxide), removes ONO layer and encounters greatly by side wall etching technicsChallenge.
Therefore, this area needs a kind of new SONOS processes badly, and alternative use side wall etching technics removes ONO layerMethod.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of SONOS processes, by changing ONO removal sidesMethod, can avoid producing other logic regions influence and causing to reduce device electric breakdown strength BV and increase the risk of electric leakage, makeSONOS devices and SG devices can be separated and adjusted so that device optimization, can improve the reliability of device.
In order to solve the above technical problems, the unit of the SONOS devices in the manufacture method of the SONOS devices of present invention offerStructure includes a storage unit tube and a selecting pipe, and the preparation method of the cellular construction of SONOS devices comprises the following steps：
Step one, one silicon substrate of offer, ONO layer is formed in the forming region of the storage unit tube；The ONO layer by according toSecondary the first silicon oxide layer for being formed at the surface of silicon, the second silicon nitride layer and the 3rd silicon oxide layer composition；Into boiler tubeGate oxide, depositing polysilicon are grown in the forming region of the selecting pipe, and defines grid and the choosing for forming storage unit tubeSelect the grid of pipe.
Step 2, the mask plate injected using memory cell LDD carry out LDD to the storage unit tube and the selecting pipeInjection, proceeds the ONO removals beyond the grid of storage unit tube, again finally in the case of then formerly not removing photoresistRemoval photoresist.
Step 3, side wall deposition is carried out, complete side wall etching.Because the ONO layer beyond the grid of storage unit tube goesRemove, extra removal ONO is not required here, the residual oxidization layer in SONOS regions is identical with other logic regions.
Step 4, the source and drain injection that heavy doping is carried out to storage unit tube and selecting pipe.
Specifically, before the formation ONO layer of step one, being additionally included in the silicon substrate carries out deep N-well injectionAnd p-well injection.
Specifically, after carrying out the deep N-well injection and p-well injection, form the ONO layer before, also including usingThe mask plate (TUNM Mask) of tunnel injection carries out exhausting injection in the forming region of the storage unit tube, by the consumptionInjection to the greatest extent adjusts the threshold voltage window of the storage unit tube.
Specifically, after the formation ONO layer of step one, before the growth grid silicon oxide layer of step one, also wrappingInclude the ONO layer of the forming region that logic region and selecting pipe using ONO layer mask plate (ONO Mask) will be etched away.
SONOS processes of the invention, change ONO layer removal technique in existing method, have the advantages that：
1. ONO layer of the invention is removed by side wall etching technics (SPACER ETCH), but is covered not increasingUnder conditions of film version, the mask plate injected using existing LDD in SONOS techniques is proceeded with photoresist after the ldd implantationONO is removed.Because the mask plate (CELL LDD Mask) of memory cell LDD injections only opens memory cell region, it is to avoidThe influence of other logic regions is caused to reduce device electric breakdown strength and increases the risk of electric leakage.
2. because the thickness of the ONO layer of the forming region of storage unit tube wants thin very relative to side wall thicknesses (SPACER)It is many, therefore main etching (main etch) and the reduction of over etching (Over etch) time, (oxide more conducively is lost to oxide layerLoss) and silicon damage (silicon gauge) control.
3. under conditions of mask plate is not increased, it is to avoid while influence to other logic regions, moreover it is possible to preferably controlSystem and residual oxide layer loss (remain oxide loss) and silicon that reduce when ONO is removed damage (silicon damage).
4. when side wall etching is carried out, the surface class of the bit line of SONOS devices or the region of source line and other logic regionsSeemingly, residual oxide layer (remain oxide) is, side wall etching is identical with general technology, and need not take into account memory cellThe ONO etchings of the forming region of pipe, simplify side wall etching technics.
Brief description of the drawings
Fig. 1 is the cross section structure schematic diagram of the SONOS devices of generation silicon damage in existing method.
Fig. 2 is the flow chart of a specific embodiment of the inventive method.
Fig. 3 is the cross section structure schematic diagram after the step of completing the inventive method one.
Fig. 4 is the cross section structure schematic diagram after the step of completing the inventive method two.
Fig. 5 is the cross section structure schematic diagram after the step of completing the inventive method three.
Fig. 6 is the cross section structure schematic diagram after the step of completing the inventive method four.
Sign flag explanation in accompanying drawing：
1 is storage unit tube region polysilicon；2 is selecting pipe region polysilicon；3 is ONO layer；31 is the first silicaLayer；32 is the second silicon nitride layer；33 is the 3rd silicon oxide layer；4 is gate oxide；5 is TUNNEL tunnel injections area；6 is gridSide wall；7 is source-drain area；8 is low doping source drain region (LDD)；9 is p-well injection region.
Specific embodiment
Clear, complete description is carried out to technical scheme below in conjunction with accompanying drawing, it is clear that described implementationExample is a part of embodiment of the invention, rather than whole embodiments.Based on embodiments of the invention, ordinary skillThe every other embodiment that personnel are obtained on the premise of creative work is not made, belongs to the model of present invention protectionEnclose.
The manufacture method of SONOS devices of the invention, as seen in figures 3-6 the cross section structure schematic diagram of each step, its SONOSThe cellular construction of device includes a storage unit tube and a selecting pipe, and in figure, SONOS show the formation of storage unit tubeRegion, SG is the forming region of selecting pipe, and the preparation method of the cellular construction of the SONOS devices comprises the following steps：
Step one, one silicon substrate of offer, ONO layer is formed in the forming region of storage unit tube；The ONO layer is by shape successivelyFirst silicon oxide layer of surface of silicon described in Cheng Yu, the second silicon nitride layer and the 3rd silicon oxide layer composition；Into boiler tube in choosingSelect pipe forming region growth gate oxide, depositing polysilicon (including storage unit tube region polysilicon and selecting pipe region it is manyCrystal silicon), and definition forms the grid of storage unit tube and the grid of selecting pipe, obtains cross section structure schematic diagram as shown in Figure 3.
It is to be carried out using general SONOS techniques in step one.Wherein, a kind of specific embodiments possible that can be takenIt is that overall deep N-well injection and p-well injection are first carried out to SONOS devices on silicon chip；Then using the mask plate of tunnel injection(TUNM Mask) carries out exhausting injection in the forming region of the storage unit tube, is deposited described in injection regulation by described exhaustingThe threshold voltage window of storage unit pipe；Then the forming region in storage unit tube forms ONO layer, and uses ONO layer mask plate(ONO Mask) etches away the ONO layer of the forming region of logic region and selecting pipe；Finally enter back into shape of the boiler tube in selecting pipeInto region growing gate oxide, depositing polysilicon, and define the grid of the grid and selecting pipe that form storage unit tube, now itsIts logic region defines grid simultaneously.
Step 2, the mask plate injected using memory cell LDD carry out LDD to the storage unit tube and the selecting pipeInjection, proceeds the ONO removals beyond the grid of storage unit tube, again finally in the case of then formerly not removing photoresistRemoval photoresist, as shown in Figure 4.
Step 2 is after polysilicon oxidation (Poly re-oxidat ion) is completed, with memory cell LDD injectionsMask plate (CELL LDD Mask) completes LDD injections, and photoresist is not then removed first, and continuing band glue carries out ONO etchings to removeTwo ONO layers of back-to-back SONOS devices, then remove the photoresist of CELL LDD again, carry out ONO etchings and avoid to itThe influence of its logic region.
Step 3, side wall deposition is carried out, complete side wall etching, as shown in Figure 5.Side wall is deposited and side wall etching is using generalLogic process is carried out.Because the ONO layer beyond the grid of storage unit tube has been removed, extra removal ONO is not required here, is not required toSONOS regions ONO etchings are taken into account, side wall etching technics is simplified.
Step 4, the source and drain injection that heavy doping is carried out to storage unit tube and selecting pipe.Now storage unit tube and selectionPipe has been formed, as shown in Figure 6.
In sum, the various embodiments described above and accompanying drawing are only presently preferred embodiments of the present invention, are not used to limit thisThe protection domain of invention, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc., all shouldComprising within the scope of the present invention.