The content of the invention
For above-mentioned problem, the invention discloses a kind of memory compiler, the memory compiler generationMemory design data include memory macro unit and microcontroller (Micro controller Unit, MCU)；
The microcontroller is for controlling the memory read, write, selftest and self-optimization are operated.
Above-mentioned memory compiler, wherein, the memory macro unit includes memory plate, the memory plate bagInclude：
Storage array, for data storage；
Memory peripheral hardware, is connected with the storage array, for being read to the storage array, write operation.
Above-mentioned memory compiler, wherein, the memory of the memory compiler generation at least includes：
Controlling bus, for transmission of control signals；
Data/address bus, for transmitting data；
Address bus, for transmitting address；
Program entry bus, for recording program；
Bus, the expanding function for realizing the memory are expanded in outside.
Above-mentioned memory compiler, wherein, the controlling bus include：
Write-in enables bus, for transmitting write enable signal；
Read and enable bus, read to enable signal for transmitting.
Above-mentioned memory compiler, wherein, the design data of the memory of the memory compiler generation also includesCrystal oscillator and the first memory space and/or the second memory space.
Above-mentioned memory compiler, wherein, first memory space is nonvolatile memory.
Above-mentioned memory compiler, wherein, write operation when institute is carried out to the memory using the microcontrollerThe module of use includes the memory macro unit, the microcontroller, the crystal oscillator and first memory space；
The bus used when carrying out write operation to the memory using the microcontroller writes enable described in includingBus, the address bus and the data/address bus.
Above-mentioned memory compiler, wherein, said write operation is carried out to the memory using the microcontrollerThe step of include：
The write enable signal for writing enable bus transfer makes the crystal oscillator produce clock signal；
After the microcontroller receives the clock signal, the ground of data to be written in first memory space is readLocation, and the data to be written position to be stored in storage array is determined by row, column decoder；
The data to be written are write the position to be stored by memory peripheral hardware described in the microprocessor control.
Above-mentioned memory compiler, wherein, read operation when institute is carried out to the memory using the microcontrollerThe module of use includes the memory macro unit, the microcontroller and the crystal oscillator；
The bus used when carrying out read operation to the memory using the microcontroller includes that the reading is enabledBus, the address bus and the data/address bus.
Above-mentioned memory compiler, wherein, the read operation is carried out to the memory using the microcontrollerThe step of include：
The reading enable signal for reading to enable bus transfer makes the crystal oscillator produce clock signal；
After the microcontroller receives the clock signal, reading is read out the address information of data, and by row, columnDecoder is read out data position to be stored in the storage array described in determining；
Memory peripheral hardware described in the microprocessor control is read out data described in reading.
Above-mentioned memory compiler, wherein, using the microcontroller memory is carried out selftest and fromI optimizes the module used during operation includes the memory macro unit, the microcontroller, the crystal oscillator and the second storageSpace；
The bus used when selftest and self-optimization operation are carried out to the memory using the microcontrollerIncluding described program typing bus.
Above-mentioned memory compiler, wherein, the selftest is carried out to the memory using the microcontrollerThe step of being operated with self-optimization includes：
By described program typing bus by self-test, optimization program entry to second memory space；
The microcontroller performs the self testing procedure in second memory space, and selftest is carried out to memory,And obtain test result；
The microcontroller performs the self-optimizing program in second memory space, and according to the test result to instituteMemory is stated to optimize.
Above-mentioned memory compiler, wherein, first memory space and second memory space are deposited for identicalStorage space.
Above-mentioned memory compiler, wherein, second memory space is nonvolatile memory.
Above-mentioned memory compiler, wherein, the expanding function of the memory is that the microcontroller is on-chip systemIn an optional microprocessor core.
Above-mentioned memory compiler, wherein, the memory is flash memory, phase transition storage, resistance-variable storing device, magnetic storageDevice or ferroelectric memory.
Above-mentioned memory compiler, wherein, the microcontroller is the microcontroller of ARM or MIPS frameworks.
Foregoing invention has the following advantages that or beneficial effect：
The invention discloses a kind of memory compiler, the design data generated using the memory compiler is not only includedThe memory macro unit of current memory compiler generation, also at least includes a microcontroller；The microcontroller can not only be realizedTraditional reading and write operation to memory, moreover it is possible to realize to the selftest of memory, self-optimization and as oneOptional microprocessor core is used in individual on-chip system (System on Chip, SOC), so as to improve the reliability of memoryAnd performance.
Specific embodiment
The invention discloses a kind of memory compiler, the design data of the memory of memory compiler generation includesMemory macro unit and microcontroller；Wherein, microprocessor read for control memory, write, selftest and fromI optimizes operation.
In a preferred embodiment of the invention, above-mentioned memory macro unit includes memory plate, the memory plateIncluding the storage array for data storage；It is connected with storage array, operation is read and write to storage array deposits for performingReservoir peripheral hardware.
In a preferred embodiment of the invention, the memory of above-mentioned memory compiler generation is at least included for passingThe controlling bus of defeated control signal, the data/address bus for transmitting data, the address bus for transmitting address, for typing journeyThe program entry bus of sequence, the outside expansion bus for realizing expanding function.
In a preferred embodiment of the invention, above-mentioned controlling bus include that the write-in for transmitting write enable signal makesCan bus and the reading enable bus for transmitting reading enable signal.
In a preferred embodiment of the invention, the design data of the memory of memory compiler generation also includes crystalline substanceShake and the first memory space and/or the second memory space.
In a preferred embodiment of the invention, the first memory space is nonvolatile memory.
In a preferred embodiment of the invention, used when carrying out write operation to memory using microcontrollerModule includes memory macro unit, microcontroller, crystal oscillator and the first memory space；Memory is write using microcontrollerThe bus used during operation includes writing enable bus, address bus and data/address bus.
In a preferred embodiment of the invention, bag the step of carry out write operation to memory using microcontrollerInclude：
Writing the write enable signal of enable bus transfer makes crystal oscillator produce clock signal；
After microcontroller receives clock signal, read the first memory space in data to be written address, and by row,Column decoder determines the data to be written position to be stored in storage array；
Microprocessor control memory peripheral hardware is written into data and writes position to be stored.
In a preferred embodiment of the invention, used when carrying out read operation to memory using microcontrollerModule includes memory macro unit, microcontroller and crystal oscillator；Used when carrying out read operation to memory using microcontrollerBus include reading to enable bus, address bus and data/address bus.
In a preferred embodiment of the invention, bag the step of carry out read operation to memory using microcontrollerInclude：
The reading enable signal for reading to enable bus transfer makes crystal oscillator produce clock signal；
After microcontroller receives clock signal, reading is read out the address information of data, and true by row, column decoderSurely it is read out data position to be stored in storage array；
Microprocessor control memory peripheral hardware reads and is read out data.
In a preferred embodiment of the invention, selftest and self-optimization are carried out to memory using microcontrollerThe module used during operation includes memory macro unit, microcontroller, crystal oscillator and the second memory space；Using microcontroller pairThe bus that memory used when selftest and self-optimization operation includes program entry bus.
In a preferred embodiment of the invention, selftest and self-optimization are carried out to memory using microcontrollerThe step of operation, includes：
By program entry bus by self-test, optimization program entry to the second memory space；
Microcontroller performs the self testing procedure in the second memory space, selftest is carried out to memory, and obtain surveyTest result；
Microcontroller performs the self-optimizing program in the second memory space, and memory is carried out according to test result excellentChange.
In a preferred embodiment of the invention, the first memory space and the second memory space are that identical stores skyBetween.
In a preferred embodiment of the invention, the second memory space is nonvolatile memory.
In a preferred embodiment of the invention, the expanding function of memory is that microcontroller is in on-chip systemIndividual optional microprocessor core.
In a preferred embodiment of the invention, memory is flash memory, phase transition storage, resistance-variable storing device, magnetic storageDevice or ferroelectric memory.
In a preferred embodiment of the invention, microcontroller is the microcontroller of ARM or MIPS frameworks.
Memory compiler of the present invention is further described with specific embodiment with reference to figure：
The present embodiment is related to a kind of memory compiler, compared with the design data of legacy memory compiler generation, thisThe design data of the memory compiler generation that embodiment is proposed not only includes the memory macro of current memory compiler generationUnit, also at least includes the microcontroller of the frameworks such as a microcontroller, such as ARM, MIPS.Generated using the memory compilerThe flow of reservoir designs data is as shown in Figure 2：1) client proposes detailed design requirement first, specifically includes the appearance of memoryAmount, area and power consumption etc.；2) memory company/engineer obtains the design requirement of client and these requirements is input into storageIn device compiler, memory compiler is started working；3) what the generation of a period of time background storage compiler was met customer need depositsThe design data of reservoir.The structure of the memory macro unit generated using novel memory devices compiler proposed by the present invention is compared to biographyThe structure of the memory macro unit of the memory compiler generation of system not only contains all constituents of in-line memory,Also at least include a microcontroller.Using novel memory devices compiler proposed by the present invention generate memory structure at least byFollowing two parts composition：1) memory macro unit, mainly includes memory plate 2_1, mainly (is used for including storage array 2_1_1Data storage, the part of maximum area in memory) and the peripheral hardware 2_1_2 of memory (for example drive, decoder, sensitive amplificationDevice etc.), the operation such as read and write to storage array for performing, such as the ranks decoder used when reading data, sensitive putBig device etc.；2) microcontroller 2_2 (microcontroller of the framework such as such as ARM, MIPS etc.), read for control memory,Write-in, selftest, self-optimization etc. are operated.
Specifically, the microcontroller of this novel memory devices compiler generation should at least include following functions：
Write operation：Perform write operation when, as shown in figure 3, novel memory devices compiler proposed by the present invention exceptProduce outside above-mentioned basic part, crystal oscillator 2_3 (producing clock signal, make microcontroller normal work) is also produced to I haven't seen you for ages, theOne memory space 2_4 (will write the data of memory for storing), and first memory space 2_4 can be volatile memoryOr nonvolatile memory, optimal, first memory space 2_4 is nonvolatile memory.Performing write operation needsThe participation of following bus, respectively writes enable bus, data/address bus and address bus, writes enable bus and writes enable letter for transmissionNumber, data/address bus is used to transmit data, and address bus is used to transmit address.In addition, microcontroller performs memory write operationSpecific steps it is as shown in Figure 4：1) write control signal (write enable signal) makes crystal oscillator 2_3 start working, and produces clock signal；2) microcontroller 2_2 reads the address for needing to write data, by row, column decoder, determines data in storage array 2_1_1The position that will be deposited；3) the peripheral hardware 2_1_2 of microcontroller 2_2 control memories writes the data in the first memory space 2_4Enter to need the position of storage.The timing diagram of write operation is as shown in Figure 5 (assuming that now crystal oscillator is in running order), it is assumed thatEffectively, step is as follows for write enable signal high level：1) when rising edge clock arrives, microcontroller 2_2 receives write enable signal；2) when write enable signal is changed into low level from high level, microcontroller 2_2 reads the address signal ADDR_ for needing to write data1, by row, column decoder, determine the position that data will be deposited in storage array；3) microcontroller 2_2 controls peripheral hardware willData DATA_1 write-ins in first memory space 2_4 need the position of storage.
Read operation：The module carried out to memory using microcontroller 2_2 used in read operation is as shown in Figure 6.PerformRead operation needs the participation of following bus, respectively reads to enable bus, data/address bus and address bus, and reading enable bus is used forTransmission reads to enable signal, and data/address bus is used to transmit data, and address bus is used to transmit address.Microcontroller 2_2 performs reading and depositsThe specific steps of reservoir operation are as shown in fig. 7, specific as follows：1) microcontroller 2_2 receives reading and enables signal；2) microcontroller 2_2 read the address signal for needing to read data, by row, column decoder, determine that data will be deposited in storage array 2_1_1Position；3) microcontroller 2_2 control peripheral hardware 2_1_2 by the digital independent of relevant position out.The timing diagram of read operation is such asShown in Fig. 8, it is assumed that read to enable signal high level effectively, step is as follows：1) when rising edge clock arrives, microcontroller 2_2 is receivedSignal is enabled to reading；2) when read enable signal is non-be changed into low level from high level when, microcontroller 2_2 read need read dataAddress signal ADDR_2, by row, column decoder, determine position of the data in storage array；3) microcontroller 2_2 controlsPeripheral hardware 2_1_2 reads the data DATA_2 in storage array 2_1_1, is gone out to outside memory by data bus transmission.
Selftest and self-optimization：In traditional memory test, generally by ATE to storageDevice is tested, but this method of testing is larger to the degree of dependence of ATE, therefore is surveyed to reduce memoryThe degree of dependence to automatic equipment is tried, at present by built-in detecting circuit in memory, by certain testing algorithm, to depositingThe storage array of reservoir carries out a series of test, such as behaviour is written and read to memory using memory built test circuitMake, so that whether the problems such as having in finding storage array because of short circuit, open circuit, mutual interference influences asking for the functions such as reading and writing of memoryTopic.And the self-optimization of memory is the result that memory is obtained according to selftest, the parameter to memory is optimized, and is madeIt can select a kind of optimal programme of work, improve the yield of Memory Storage Unit.Novel memory devices proposed by the present inventionThe microcontroller of compiler generation can enter selftest and the self-optimization of line storage, without specific self-built testCircuit.Module used in selftest and self-optimization is carried out to memory as shown in figure 9, in figure using microcontroller 2_2The second memory space 2_5 be used to storing the code of selftest or/and self-optimization, the second memory space 2_5 is with described theOne memory space 2_4 can be same memory space, or different memory spaces, and the second memory space 2_5 can beNonvolatile memory or volatile memory, optimal, second memory space 2_5 is nonvolatile memory.Due toNeeded in download program to the second memory space 2_5 when selftest and self-optimization is carried out, it is therefore desirable to the second storageThe participation of space 2_5 and program entry bus.It is as shown in Figure 10 that memory carries out the step of selftest and self-optimization：1) lead toProgram entry bus is crossed by self-test, optimization program entry to the second memory space 2_5；2) microcontroller 2_2 performs secondSelf testing procedure in memory space 2_5, selftest is carried out to memory；3) microcontroller 2_2 performs the second memory spaceSelf-optimizing program in 2_5, according to the result that selftest is obtained, optimizes to memory.
Expand：In the memory macro unit of legacy memory compiler generation, circuit usually uses DFT (DesignFor Testability, Testability Design), will some special circuits the design phase implantation chip in (for example implantation sweepRetouch chain etc., memory self-test circuit), to be tested memory after the completion of designing.But after the completion of test, depositThe circuit as test being implanted into reservoir will become dark silicon (dark silicon, the transistor being stopped), cause coreThe waste of piece area.In the present invention, the self test program of memory is performed by microcontroller 2_2, when having testedAfter, microcontroller 2_2 can turn into an optional microprocessor core in on-chip system, without as dark silicon.StorageThe expanding function of device needs microcontroller 2_2 and outside bus of expanding to participate in.As shown in figure 11, optional microprocessor core is by outerPortion expands bus and is connected to on-chip system bus, reconnects the other parts on on-chip system, such as external memory interface 2_7(being used for external memorizer), other microprocessor cores 2_6 (the such as microprocessor of ARM, MIPS framework, and it is micro- in the present inventionProcessor 2_2 constitutes multi-core microprocessor framework, such as the big.LITTLE frameworks of ARM companies), the 3rd memory 2_8 is (such asOther memories of on-chip system), (peripheral hardware for connecting on-chip system, such as general input/output port is fixed for bridger 2_9When device, digital analog converter, analog-digital converter, USB etc.).
In order to realize function above, the memory of this memory compiler generation should at least include following bus：1) controlBus (Control Bus, CB), including storage write-in enables bus, storage reading and enables bus.2) data/address bus (DataBus, DB), carry out input, the output of data.3) the program entry bus needed for selftest, self-optimization.4) by microcontrollerBus, such as AMBA buses etc. are expanded in outside needed for device 2_2 is expanded into optional microprocessor core.Additionally, also including that address is totalLine (Address Bus, AB).As figure 12 a shows, the related bus of write operation includes：Write enable bus, address bus, dataBus；As shown in Figure 12b, the related bus of read operation includes：Read to enable bus, address bus, data/address bus；Such as Figure 12 c institutesShow, self-test, self-optimizing associated bus lines include：Program entry bus；As shown in figure 12d, expanding associated bus lines includes：Open up outsideExhibition bus.
As shown in figure 13, conventional compiler is only included for producing columns-decoders, storage core, sense amplifier, fillingThe basic module of circuit etc. and the bank modules for combining these basic modules and control logic (control_logic).In order to realize function above, memory compiler framework and legacy memory compiler frame that the present embodiment is proposedStructure is compared：1) the Arm modules for realizing Arm functions are added, selected by mode identificating circuit Arm work four kinds of patterns-Write mode, readout mode, selftest and self-optimization pattern, mode of extension.2) OSC modules are added for realizing crystal oscillatorProduce the function of clock signal.3) Code_Mem modules are added for realizing storage memory selftest and self-optimization generationThe function of code.4) Data_Mem modules are added for storing the initialization data parameter of each bank module, and self is surveyedThe Optimal Parameters produced after examination and self-optimization are as new data storage in Data_Mem.
Specifically should for novel memory devices compiler proposed by the present invention will be described in detail by a specific example belowWith.
Memory compiler proposed by the present invention is applied to the generation of all of in-line memory macroelement, such as phase transformationMemory, resistance-variable storing device, magnetic memory and ferroelectric memory etc..In the present embodiment, we come by taking phase transition storage as an exampleExplanation.Flow using New-type phase change memory compiler generation reservoir designs data is as shown in figure 14：1) client carries firstGo out detailed design requirement, specifically include capacity (128Mb), area and power consumption of memory etc.；2) memory company/engineeringTeacher obtains the design requirement of client and these requirements is input in memory compiler, and memory compiler is started working；3)The design data of the memory that the generation of a period of time background storage compiler is met customer need.Design data mainly includes128Mb embedded phase change rams macroelement and the corresponding bus of function of the present invention is realized, i.e. data/address bus, controlBus, address bus, program entry bus and expansion bus, data/address bus are used for transmitting data information, and controlling bus are used forTransmission control command, address bus be used for transmission memory address information, program entry bus be used for memory selftest,The typing of self-optimization program, bus is expanded in outside to be used to expand the optional microprocessor core in an on-chip system.
Figure 15 is the embedded phase change ram macroelement and an ARM of the 128Mb of novel memory devices compiler generationThe microcontroller of framework.It includes an embedded phase change storage array 3_1, the peripheral hardware 3_ required for storage array of 128MbThe microcontroller 3_3 of 2, ARM frameworks, crystal oscillator 3_4, the first memory space 3_6 needed for write-in data (are deposited with non-volatile hereAs a example by reservoir), the second memory space 3_7 (here by taking static RAM SRAM as an example)；Bus includes write-in dataRequired writes enable bus, data/address bus, address bus, and the reading needed for reading data enables bus, data-out bus, addressBus, program entry bus needed for selftest, self-optimization, and it is the optional microprocessor core institute on on-chip system to expandThe outside expansion bus for needing.
Novel memory devices compiler generation microcontroller proposed by the present invention has following functions：
Write operation：As shown in figure 16, write operation needs 128Mb embedded phase changes storage array 3_1, peripheral hardware 3_2,The subparticipations such as the microprocessor 3_3 of ARM frameworks, crystal oscillator 3_4, the first memory space 3_5 are, it is necessary to write enable bus, data are totalLine and address bus are participated in.Write step is as shown in figure 17, specific as follows：1) write enable signal enables crystal oscillator 3_4 and starts working,Produce clock signal；2) the microcontroller 3_3 of ARM frameworks reads the address signal for needing to write data, is decoded by row, columnDevice, determines the position that data will be deposited in phase change memory array 3_1；3) the microcontroller 3_3 of ARM frameworks believes according to clockNumber, control peripheral hardware 3_2 is by the data write-in embedded phase change ram 3_1 in the first memory space 3_5.Write operation whenSequence figure is as shown in figure 18 (assuming that crystal oscillator is in running order), it is assumed that effectively, step is as follows for write enable signal high level：1)When rising edge clock arrives, ARM microcontroller 3_3 receives write enable signal, becomes from high level for write enable signal is non-hereinIt is low level；2) when write enable signal is non-is changed into low level from high level, ARM microcontroller 3_3 reads to be needed to write dataAddress signal ADDR_1, by row, column decoder, determine the position that data will be deposited in phase change memory array；3)ARMMicrocontroller 3_3 deposits the data DATA_1 write-in needs in the first memory space 3_5 according to clock signal, control peripheral hardware 3_2The position put.
Read operation：Read operation needs 128Mb embedded phase changes storage array 3_1, peripheral hardware 3_2, ARM microcontroller 3_3, the subparticipation such as crystal oscillator 3_4 are, it is necessary to read to enable bus, data/address bus and address bus are participated in, specific as shown in figure 19, read to makeEnergy bus is used to transmit to be read to enable signal, and data/address bus is used to transmit address for transmitting data, address bus.Read operationStep is as shown in figure 20, specific as follows：1) ARM microcontroller 3_3 receives reading and enables signal；2) ARM microcontroller 3_3 reads needsThe address signal of data is read, by row, column decoder, determines that data are deposited in 128Mb embedded phase change storage arrays 3_1The position put；3) ARM microcontroller 3_3 is according to clock signal, control peripheral hardware 3_2 by the digital independent of relevant position out.ReadThe timing diagram for going out operation is as shown in figure 21, it is assumed that read to enable signal high level effectively, step is as follows：1) arrived in rising edge clockWhen, ARM microcontroller 3_3 receives reading and enables signal, and for reading is enabled, signal is non-to be changed into low level from high level herein；2) when reading makesCan signal it is non-from high level be changed into low level when, ARM microcontroller 3_3 read need read data address signal ADDR_2,By row, column decoder, position of the data in storage array 3_1 is determined；3) ARM microcontroller 3_3 is according to clock signal, controlPeripheral hardware 3_2 processed reads the data DATA_2 in 128Mb embedded phase change rams, is gone out to memory by data bus transmissionIt is outside.
3) selftest and self-optimization：Selftest and self-optimization need 128Mb embedded phase change storage arraysJoin the part such as 3_1, peripheral hardware 3_2, ARM microprocessor 3_3, crystal oscillator 3_4, second memory space 3_7 (here by taking SRAM as an example)With, needed in selftest and self-optimization download program to SRAM 3_7 when selftest and self-optimization is carried out, thisWhen need the participation of program entry bus, it is specific as shown in figure 22.In this example, using JTAG (Joint Test ActionGroup, joint test working group) interface tested memory chip, and the jtag interface of standard is 4 lines：TMS、TCK、TDI, TDO, respectively model selection, clock, data input and DOL Data Output Line, by jtag interface by program used for test typingTo in SRAM 3_7.The step of selftest and self-optimization, is as shown in figure 23, specific as follows：1) will by program entry busIn self-test, optimization program entry to SRAM 3_7；2) ARM microcontroller 3_3 performs the selftest stored in SRAM 3_7Program, carries out selftest, for example, all memory cell one writings are read with all units of checking again, and all memory cell are writeWhether " 0 " reads all units of checking again, to check short circuit, the open circuit problem of each unit, and has adjacent cells short circuitProblem；For example to first memory cell write-in " 1 ", second memory cell writes " 0 ", by that analogy, until lastMemory cell, then reads all units of checking again, then opposite data are write to each unit, then reads all units of checking,To detect that memory cell disturbs (can cause the change of state of memory cells around when reading and writing certain memory cell)；3) ARM is micro-Controller 3_3 performs the self-optimization program in SRAM 3_7, self-optimization is carried out, according to the test result of memory, to depositingThe parameter of reservoir is optimized, and can select a kind of optimal programme of work, improves the yield of Memory Storage Unit.
4) expand：Expanding function needs ARM microprocessor 3_3, it is necessary to outside expansion bus participation, uses ARM in this exampleThe AMBA buses (Advanced Micro controller Bus Architecture) of company's research and development are expanded, and 2.0Version AMBA standards define three groups of buses：(the Advanced High-performance Bus, AMBA high-performance is total for AHBLine), ASB (the Advanced System Bus, AMBA system bus) and APB (the Advanced PeripheralBus, AMBA peripheral bus).Optional microprocessor core connects the other parts on on-chip system by AMBA buses, such as passes throughAHB or ASB connections high bandwidth external memory interface 3_10, high-performance arm processor 3_7, RAM 3_8, bridge on high-performance pieceDevice 3_9 etc. is met, bridger passes through APB connection universals input/output port 3_11, USB 3_12 and timer 3_13Deng specific as shown in figure 24.
In order to realize function above, the 128Mb phase transition storages macroelement of this memory compiler generation should at least be includedFollowing bus：1) controlling bus, including storage writes enable bus, storage and reads to enable bus.2) data/address bus.3) selftest,Program entry bus (JTAG) needed for self-optimization.4) ARM microcontroller is expanded into opening up needed for optional microprocessor coreExhibition bus (AMBA).Additionally, also including address bus.As shown in Figure 25 a, the related bus of write operation includes：Write enable bus,Address bus, data/address bus；The related bus of read operation includes：As shown in figure 25b, enable bus, address bus, data are read totalLine；Shown in Figure 25 c, such as selftest, self-optimization associated bus lines include：Program entry bus；As shown in Figure 25 d, phase is expandedClosing bus includes：Bus is expanded in outside.
To sum up, the design data of memory compiler generation disclosed by the invention is not only given birth to including current memory compilerInto memory macro unit, also at least include a microcontroller.The microcontroller can not only realize traditional reading to memoryWrite operation, moreover it is possible to realize to the selftest of memory, self-optimization and as optional microprocessor in an on-chip systemDevice core is used.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and above-described embodiment can be withChange case is realized, be will not be described here.Such change case has no effect on substance of the invention, will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentionedParticular implementation, wherein the equipment and structure that do not describe in detail to the greatest extent are construed as giving reality with the common mode in this areaApply；Any those of ordinary skill in the art, in the case where technical solution of the present invention ambit is not departed from, all using the disclosure aboveMethods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.Effect embodiment, this has no effect on substance of the invention.Therefore, every content without departing from technical solution of the present invention, foundationTechnical spirit of the invention still falls within the present invention to any simple modification, equivalent variation and modification made for any of the above embodimentsIn the range of technical scheme protection.